A cache management method and system based on scalar memory automatic management strategy

Abstract

The present invention discloses a cache management method and system based on a scalar memory automated management strategy. First, a cache management strategy library is established to realize the automatic allocation, management and recovery of scalar memory cache resources. Secondly, a memory access feature model is constructed to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors. Finally, based on the memory access feature vectors, the strategy and strategy parameter deduction model is used to automatically select the optimal cache management strategy and configure the corresponding strategy parameters. This method can dynamically adapt to changes in the program's memory access behavior, improve scalar memory utilization efficiency and program memory access speed, simplify the scalar memory management process, and reduce development complexity. Compared with the prior art, the present invention provides an efficient and automated scalar memory management solution under a complex heterogeneous multi-core architecture, which has broad application prospects and significant practical value.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer architecture and parallel programming, and in particular relates to a cache management method and system based on a scalar memory automatic management strategy. Background Art

[0002] With the rapid development of fields such as scientific computing, artificial intelligence, and big data analytics, high-performance computing (HPC) plays a vital role in driving technological advancement and industrial upgrading. In HPC applications, memory access optimization is a key factor in improving performance. Efficient memory access management not only reduces data transmission latency but also improves cache hit rates, significantly enhancing overall system efficiency.

[0003] At present, domestic heterogeneous many-core architectures are in a stage of rapid development, and a variety of high-performance processors with independent intellectual property rights have emerged. These architectures have achieved efficient task allocation and parallel computing capabilities by integrating multiple types of processing units. However, as the architecture becomes increasingly complex, its storage hierarchy has also become more complex, and the difficulty of on-chip cache management has increased significantly. Taking the domestic Maichuang architecture as an example, its on-chip cache structure includes two parts: scalar memory and array memory, which are responsible for storing scalar data and vector data respectively. Its multi-domain microarchitecture and hierarchical storage design make the management of on-chip cache particularly complex. Although the hthreads parallel programming model provides an interface for managing on-chip cache, the existing method still requires manual management by the user, and there are three main problems:

[0004] First, the memory architecture is complex: The MT-3000's multi-domain microarchitecture and hierarchical storage design make manual management of scalar memory complex and error-prone.

[0005] Second, cache management is difficult: users need to write a large amount of code for cache allocation and recycling, and design complex data layout, which increases development difficulty and maintenance costs.

[0006] Third, it is difficult to optimize memory access performance: Since memory access behaviors are diverse and difficult to predict, manually optimizing cache strategies is difficult to achieve optimal performance, which limits the execution efficiency of the program.

[0007] The existing technology lacks an automated cache management policy library that can dynamically adjust cache management strategies based on the actual memory access behavior of the program. This results in low cache utilization and poor memory access performance under complex computing tasks. Therefore, an automated scalar memory management policy library and its memory access modeling method for the domestic Maichuang architecture are of great practical significance. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to address the deficiencies in the above-mentioned prior art and provide a cache management method and system based on a scalar memory automatic management strategy, so as to solve the technical problems of complex existing scalar memory management and low program memory access efficiency.

[0009] The present invention adopts the following technical solutions:

[0010] A cache management method based on a scalar memory automatic management strategy comprises the following steps:

[0011] S1. Establish a cache management policy library based on the hthreads parallel programming model interface of the Maichuang architecture to automatically allocate, manage and reclaim scalar memory cache resources;

[0012] S2. Establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors;

[0013] S3. Establish a strategy and strategy parameter deduction model, automatically select the optimal cache management strategy based on the obtained memory access feature vector, and configure the corresponding strategy parameters.

[0014] Preferably, in step S1, the cache management policy library includes:

[0015] The batch cache management strategy reads all data blocks within the access memory range into the scalar memory at one time. Subsequent access to the data blocks is taken over by the batch cache management strategy, and all calculation operations are performed in the scalar memory.

[0016] The single-buffer cache management strategy allocates a user-defined cache space in scalar memory for prefetching data from a certain data block. Memory access to this data block triggers cache hit detection logic. If a cache miss occurs, the data in the current buffer is selectively written back to main memory, and data within a certain range near the current memory access address is read into the buffer for subsequent computations.

[0017] The direct-mapped cache management strategy allocates a user-defined cache space containing several cache lines in the scalar memory for prefetching data in a certain data block. The memory access behavior of this data block will trigger the cache hit judgment logic. If it misses, the data in the current cache line will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the corresponding cache line to continue subsequent computing operations.

[0018] Preferably, the configurable parameters of the single buffer cache management strategy are , which represents the logarithm of the cache size with base 2; its cache hit judgment logic is:

[0019]

[0020] in, Indicates the address aligned according to the cache space size, Indicates the starting address of the current cache data block in the main memory, Indicates the end address of the current cache data block in the main memory, Represents a cache hit indicator.

[0021] Preferably, the configurable parameters of the direct-mapped cache management strategy are and , represents the base-2 logarithm of the cache line size, Indicates the base-2 logarithm of the number of cache groups. The cache hit judgment logic of this policy is:

[0022]

[0023] in, Indicates the cache group index, Represents a cache tag array that stores the tag value of each cache line. Represents a cache hit indicator.

[0024] Preferably, step S2 is specifically:

[0025] S201. Define relevant basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function; stream refers to a subsequence of a memory access element sequence; stride refers to the distance between any two adjacent elements;

[0026] S202, determining data block characteristics, where the characteristics of the data block are mainly defined by size boundaries;

[0027] S203, establish a flow step feature model, assuming that in a flow, the step length is a discrete random variable whose value is , ;

[0028] S204. Generate a memory access feature vector. According to the above definition, classify the memory access behavior of the key array variables in the program and generate a corresponding memory access feature vector. The memory access feature vector includes the data block size, the number of memory accesses, the memory access step length, and the proportion of high-frequency memory access step lengths.

[0029] Preferably, based on the step length feature, define:

[0030]

[0031]

[0032] in, is an arbitrarily small positive number, Represents the index of the high-frequency step, that is, the sequence number of the step with the highest frequency in the stream, Indicates the specific value of the high-frequency step size, Indicates step length Probability of occurrence; proposition Indicates that there are high-frequency non-zero steps in the stream , proposition Indicates that the step size is 1.

[0033] Preferably, according to the proposition and True or false, the flow is divided into:

[0034] Regular Sequence Flow: When When true;

[0035] Regular non-sequential flow: When When true;

[0036] Irregular flow: When When true.

[0037] Preferably, step S3 is specifically:

[0038] S301, designing a strategy selection unit to define a matching rule for a cache management strategy based on a memory access feature vector;

[0039] S302, designing a policy parameter configuration unit, configuring corresponding policy parameters according to the selected cache management policy;

[0040] S303: Automatically configure the policy and policy parameters. Through the policy selection unit and the policy parameter configuration unit, automatically select the policy and configure the policy parameters to ensure that the cache management policy can dynamically adapt to changes in the program's memory access behavior.

[0041] Preferably, the matching rules of the cache management policy are as follows:

[0042] If the data block size is smaller than the scalar memory space, select the batch cache management strategy; if the data block size is larger than the scalar memory space and the flow is a regular sequential flow, select the single buffer cache management strategy; in other cases, select the direct mapped cache management strategy;

[0043] According to the selected cache management strategy, configure the corresponding strategy parameters as follows:

[0044] When the batch cache management strategy is selected, no additional parameter configuration is required, and the data block is directly read into the scalar memory at one time; when the single buffer cache management strategy is selected, the buffer size parameter is configured. , which represents the logarithm of the cache space size with base 2; when the direct-mapped cache management strategy is selected, configure the cache line size and the number of cache groups , which represent the base-2 logarithms of the cache line size and the number of cache groups, respectively.

[0045] In a second aspect, an embodiment of the present invention provides a cache management system based on a scalar memory automatic management strategy, comprising:

[0046] The strategy module establishes a cache management strategy library based on the HThreads parallel programming model interface of the Maichuang architecture, which is used to automatically allocate, manage, and reclaim scalar memory cache resources;

[0047] The quantization module establishes a memory access feature model to quantify the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors;

[0048] The management module establishes a strategy and strategy parameter deduction model, automatically selects the optimal cache management strategy based on the obtained memory access feature vector, and configures the corresponding strategy parameters.

[0049] In a third aspect, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the cache management method based on the scalar memory automation management strategy when executing the computer program.

[0050] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, comprising a computer program, which, when executed by a processor, implements the steps of the cache management method based on the scalar memory automatic management strategy.

[0051] In a fifth aspect, a chip includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the cache management method based on the scalar memory automatic management strategy are implemented.

[0052] In a sixth aspect, an embodiment of the present invention provides an electronic device, comprising a computer program, which, when executed by the electronic device, implements the steps of the cache management method based on the scalar memory automatic management strategy.

[0053] Compared with the prior art, the present invention has at least the following beneficial effects:

[0054] A cache management method based on scalar memory automatic management strategy, firstly, establishes a cache management strategy library to realize the automatic allocation, management and recycling of scalar memory cache resources; secondly, constructs a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate the corresponding memory access feature vector; finally, based on the memory access feature vector, uses the strategy and strategy parameter deduction model to automatically select the optimal cache management strategy and configure the corresponding strategy parameters; it can dynamically adapt to the changes in the program's memory access behavior, improve the scalar memory utilization efficiency and program memory access speed, simplify the scalar memory management process, and reduce development complexity; by designing a cache management strategy for scalar memory The system eliminates the need for users to manually write complex scalar memory management code, significantly reducing the complexity and development difficulty of scalar memory management; automatic strategy selection and strategy parameter configuration based on memory access characteristics can more effectively match the actual memory access behavior of the program, improve cache hit rate and utilization, and reduce performance loss caused by cache misses; dynamic adjustment of cache management strategy can achieve optimal cache performance according to the memory access mode of different programs, significantly improving the overall execution efficiency of parallel programs; compared with the existing technology, the present invention provides an efficient and automated scalar memory management solution under complex heterogeneous many-core architecture, which has broad application prospects and significant practical value.

[0055] Furthermore, the present invention provides a dedicated scalar memory management solution for the multi-domain micro-architecture and hierarchical storage design of the domestic Maichuang architecture, which can effectively cope with the challenges brought by complex memory architecture.

[0056] Furthermore, the present invention sets configurable parameters for the proposed single buffer cache management strategy , the optimal cache size is set according to the memory access characteristics of different array variables, and a balance is achieved between memory access acceleration and scalar memory usage efficiency. At the same time, the cache hit judgment logic of this strategy uses the locality principle to achieve the reuse of data in the cache, improve the cache hit rate, and enhance the memory access speed of the program.

[0057] Furthermore, the present invention introduces configurable parameters into the direct-mapped cache management strategy. and , to adapt to the memory access characteristics of different array variables, optimize the size and number of cache lines, and achieve a balance between memory access performance and scalar memory utilization efficiency. In addition, the cache hit judgment logic of this strategy is based on the principle of locality, making full use of the data in the cache and improving the hit rate, thereby reducing memory access latency and accelerating program execution.

[0058] Furthermore, the present invention constructs a program memory access characteristic model that quantifies the memory access patterns of key array variables into key features such as data block size, number of memory accesses, memory access step length, and the proportion of high-frequency memory access step lengths, thereby accurately characterizing memory access behavior. Strategy selection and parameter configuration derived from this model can achieve optimal memory access acceleration and improve program execution efficiency.

[0059] Furthermore, the present invention constructs a cache management policy library and its policy parameter deduction model. By analyzing the memory access characteristics of key program arrays, the optimal cache management policy and corresponding optimal parameter configuration are deduced based on rules. This method can efficiently derive optimization solutions without repeatedly running the program, offering the advantages of being lightweight and efficient, effectively improving the program's memory access performance.

[0060] Furthermore, the present invention adopts cache management strategy matching rules based on memory access characteristics, which can intelligently select the optimal cache management strategy according to the data block size and memory access mode, and optimize the cache resource utilization efficiency through automatic policy parameter configuration. This method ensures that the batch cache management strategy is used first when the data block is small, thereby improving data loading efficiency; for regular sequential flows, a single buffer cache management strategy is adopted, which is dynamically adjusted. Improve cache hit rate; in other complex memory access modes, select direct mapping cache management strategy and and Fine-tune configuration to reduce cache conflicts and memory access latency. This automated policy matching and parameter optimization mechanism dynamically adjusts to memory behavior, avoiding resource waste or performance bottlenecks caused by fixed policies, improving cache utilization, and reducing the overhead caused by cache misses, significantly improving the overall memory access performance and execution efficiency of the program.

[0061] It can be understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0062] In summary, the present invention effectively improves the utilization efficiency of scalar memory and the memory access performance of programs through automated strategy selection and strategy parameter configuration, and has broad application prospects and significant practical value.

[0063] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0065] Figure 1 Schematic diagram of the MT-3000 on-chip heterogeneous many-core architecture;

[0066] Figure 2 This is a schematic diagram of the MT-3000 memory architecture;

[0067] Figure 3 This is a schematic diagram of the system architecture;

[0068] Figure 4 This is a flow chart of the single buffer cache management strategy;

[0069] Figure 5 Schematic diagram of main memory address mapping for direct-mapped cache management policy;

[0070] Figure 6 Decision flow chart for the strategy selection unit;

[0071] Figure 7 A schematic diagram of a computer device provided in accordance with an embodiment of the present invention;

[0072] Figure 8 The present invention is a block diagram of an electronic device according to an embodiment of the present invention.

[0073] Among them, 60. Computer device; 61. Processor; 62. Memory; 63. Computer program; 600. Electronic device; 610. Processing unit; 620. Storage unit; 6201. Random access memory unit; 6202. Cache memory unit; 6203. Read-only memory unit; 6204. Program / Utility; 6205. Program module; 630. Bus; 640. Display unit; 650. Input / output interface; 660. Network adapter; 700. External device. DETAILED DESCRIPTION

[0074] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0075] In the description of the present invention, it is to be understood that the terms “include” and “comprise” indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0076] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0077] It should be further understood that the term "and / or" as used in the present specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0078] It should be understood that although the terms "first," "second," and "third" may be used to describe preset ranges in embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are merely used to distinguish one preset range from another. For example, without departing from the scope of embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0079] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0080] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments disclosed herein. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0081] This paper provides a cache management method based on an automated scalar memory management strategy. By quantifying and modeling the memory access behavior of key array variables in a program, the quantified memory access characteristics are used to automatically select and configure cache management strategies, thereby optimizing the efficiency of scalar memory usage and the program's memory access performance. The cache management strategy library, developed based on the domestically produced Maichuang hthreads parallel programming model interface, is suitable for heterogeneous many-core chips with multi-domain microarchitectures and complex memory hierarchies. It effectively simplifies the cache management process, enables automated management, and improves the execution efficiency of parallel programs.

[0082] Example 1

[0083] The present invention provides a cache management method based on a scalar memory automatic management strategy, comprising the following steps:

[0084] S1. Establish a cache management policy library based on the hthreads parallel programming model interface of the Maichuang architecture to automatically allocate, manage, and reclaim scalar memory (SM) cache resources;

[0085] See also Figure 3 In the system architecture of the present invention, the cache management policy library includes three cache management policies: batch cache management policy, single buffer cache management policy, and direct-mapped cache management policy, as follows:

[0086] Batch cache management strategy: All data blocks within the access memory range are read into scalar memory at one time. Subsequent access to the data blocks is taken over by the batch cache management strategy, and all computing operations are performed in scalar memory.

[0087] Single buffer cache management strategy: A user-defined cache space is allocated in the scalar memory to prefetch data in a certain data block. The program's memory access behavior for this data block will trigger the cache hit judgment logic. If it misses, the data in the current buffer will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the buffer to continue the subsequent calculation operation. The configurable parameters of this strategy are , which represents the logarithm of the cache size with base 2. The cache hit judgment logic is:

[0088]

[0089]

[0090]

[0091] in, Indicates the address aligned according to the cache space size, Indicates the starting address of the current cache data block in the main memory, Indicates the end address of the current cache data block in the main memory, Represents the cache hit indicator, a value of 1 indicates a cache hit, and a value of 0 indicates a cache miss. The base-2 logarithm of the cache size Indicates a floor operation.

[0092] Direct-mapped cache management strategy: A user-defined cache space of a certain size containing several cache lines is allocated in the scalar memory to prefetch data in a certain data block. The program's memory access behavior for this data block will trigger the cache hit judgment logic. If it misses, the data in the current cache line will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the corresponding cache line to continue the subsequent calculation operation. The configurable parameters of this strategy are and ,in, represents the base-2 logarithm of the cache line size, Indicates the logarithm of the number of cache groups with base 2. The cache hit judgment logic of this policy is:

[0093]

[0094]

[0095]

[0096] in, Indicates the memory address currently being accessed. represents the base-2 logarithm of the cache line size, Represents the base-2 logarithm of the number of cache groups, Indicates the tag part of the memory address, used for cache hit judgment, Indicates the cache group index, Represents a cache tag array, which stores the tag value of each cache line. The initial value is Indicates invalidity. Indicates a round-down operation. Represents the cache hit indicator. A value of 1 indicates a cache hit, and a value of 0 indicates a cache miss.

[0097] S2. Establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors;

[0098] Memory access feature modeling includes four parts: defining relevant basic concepts, determining data block characteristics, establishing a stream step feature model, and generating memory access feature vectors. Specifically, it includes:

[0099] S201. Define relevant basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function; stream refers to a subsequence of a memory access element sequence; stride refers to the distance between any two adjacent elements;

[0100] S202: Determine the characteristics of the data block. The characteristics of the data block are mainly defined by the size boundary, which is specifically expressed as:

[0101]

[0102] in, Indicates the number of data blocks, Indicates the number of the data block, Indicates the The size of the data block.

[0103] The capacity of scalar memory is expressed as:

[0104]

[0105] Based on the above definition, classify different data blocks and define propositions as follows:

[0106]

[0107] Definition Proposition , indicating that the access memory area of ​​the data block is smaller than the storage space of the scalar memory.

[0108] S203, establish a flow step length feature model, specifically described as: suppose in a flow, the step length is a discrete random variable whose value is , the probability of occurrence of different step lengths is:

[0109]

[0110] in, Indicates step length No. Possible values, Indicates step length The value is The probability of , and satisfy all The sum is 1.

[0111]

[0112] Based on the step length feature, define:

[0113]

[0114]

[0115] in, is an arbitrarily small positive number, Represents the index of the high-frequency step, that is, the sequence number of the step with the highest frequency in the stream, Indicates the specific value of the high-frequency step size, Indicates step length The probability of occurrence. Indicates that there are high-frequency non-zero steps in the stream , proposition Indicates that the step length is 1. According to the proposition and The true or false situation of the flow is divided into three categories:

[0116] Regular sequence flow:

[0117] when When true;

[0118] Regular non-sequential flow:

[0119] when When true;

[0120] Irregular flow:

[0121] when When true.

[0122] S204: Generate memory access feature vectors. Based on the above definition, classify the memory access behaviors of key array variables in the program and generate corresponding memory access feature vectors. The memory access feature vectors include but are not limited to data block size, number of memory accesses, memory access step length, and the proportion of high-frequency memory access step lengths.

[0123] S3. Establish a strategy and strategy parameter deduction model, automatically select the optimal cache management strategy based on the memory access feature vector, and configure corresponding strategy parameters.

[0124] See also Figure 6 ,The strategy selection unit judges the truth values ​​of propositions T, P, and Q in turn based on the ,access feature vector and selects the corresponding cache management ,strategy, which includes the following steps:

[0125] S301. Design a strategy selection unit to define matching rules for the cache management strategy based on the aforementioned memory access feature vector. The specific rules are as follows:

[0126] S3011. If the data block size is smaller than the scalar memory space, select a batch cache management strategy;

[0127] S3012, if the data block size is larger than the scalar memory space and the flow is a regular sequential flow, select a single buffer cache management strategy;

[0128] S3013. In other cases, select the direct mapping cache management strategy.

[0129] S302, designing a policy parameter configuration unit to configure corresponding policy parameters according to the selected cache management policy;

[0130] S3021. When the batch cache management strategy is selected, no additional parameter configuration is required and the data blocks are directly read into the scalar memory at one time;

[0131] S3022: When a single buffer cache management strategy is selected, configure the buffer size parameter. , represents the logarithm of the cache size with base 2;

[0132] S3023: When selecting direct-mapped cache management strategy, configure cache line size and the number of cache groups , which represent the base-2 logarithms of the cache line size and the number of cache groups, respectively.

[0133] S303: Automatically configure the policy and policy parameters. Through the policy selection unit and the policy parameter configuration unit, automatically select the policy and configure the policy parameters to ensure that the cache management policy can dynamically adapt to changes in the program's memory access behavior.

[0134] Those skilled in the art will appreciate that various aspects of the present invention may be implemented as systems, methods, or program products. Accordingly, various aspects of the present invention may be implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as "circuits," "modules," or "platforms."

[0135] Example 2

[0136] The present invention provides a cache management system based on a scalar memory automatic management strategy, which can be used to implement the above-mentioned cache management method based on a scalar memory automatic management strategy. Specifically, the cache management system based on a scalar memory automatic management strategy includes a policy module, a quantization module and a management module.

[0137] Among them, the policy module establishes a cache management policy library, which is developed based on the hthreads parallel programming model interface of the Maichuang architecture and is used to automatically allocate, manage and reclaim cache resources of scalar memory;

[0138] The quantization module establishes a memory access feature model to quantify the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors;

[0139] The management module establishes a strategy and strategy parameter deduction model, automatically selects the optimal cache management strategy based on the obtained memory access feature vector, and configures the corresponding strategy parameters.

[0140] Example 3

[0141] The present invention provides a terminal device, which includes a processor and a memory, wherein the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or may be other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of the cache management method based on the scalar memory automatic management strategy, including:

[0142] Establish a cache management strategy library, developed based on the hthreads parallel programming model interface of the Maichuang architecture, to automatically allocate, manage, and reclaim scalar memory cache resources; establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; establish a strategy and strategy parameter deduction model to automatically select the optimal cache management strategy based on the obtained memory access feature vectors and configure the corresponding strategy parameters.

[0143] See also Figure 7The terminal device is a computer device. The computer device 60 of this embodiment includes: a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable by the processor 61. When executed by the processor 61, the computer program 63 implements the cache management method based on the scalar memory automatic management strategy of the embodiment. To avoid repetition, the details are not described here. Alternatively, when executed by the processor 61, the computer program 63 implements the functions of each model / unit in the cache management system based on the scalar memory automatic management strategy of the embodiment. To avoid repetition, the details are not described here.

[0144] The computer device 60 may be a desktop computer, a notebook computer, a PDA, a cloud server, or other computing devices. The computer device 60 may include, but is not limited to, a processor 61 and a memory 62. It will be understood by those skilled in the art that Figure 7 This is merely an example of the computer device 60 and does not constitute a limitation of the computer device 60 . The computer device 60 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the computer device may also include input and output devices, network access devices, buses, etc.

[0145] The processor 61 may be a central processing unit (CPU), or other general-purpose processors, a graphics processing unit (GPU), a tensor processing unit (TPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0146] The memory 62 may be an internal storage unit of the computer device 60, such as a hard disk or memory of the computer device 60. The memory 62 may also be an external storage device of the computer device 60, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 60.

[0147] Furthermore, the memory 62 may include both an internal storage unit of the computer device 60 and an external storage device. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 may also be used to temporarily store data that has been output or is about to be output.

[0148] See also Figure 8 The terminal device is an electronic device 600, which is implemented as a general-purpose computing device. The components of the electronic device may include, but are not limited to, at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including the storage unit 620 and the processing unit 610), and a display unit 640.

[0149] The storage unit stores program codes, which can be executed by the processing unit 610, so that the processing unit 610 performs the steps according to various exemplary embodiments of the present invention described in the above method section of this specification. For example, the processing unit 610 can perform the following steps: Figure 3 Follow the steps shown in .

[0150] The storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 6201 and / or a cache memory unit 6202 , and may further include a read-only memory unit (ROM) 6203 .

[0151] The storage unit 620 may also include a program / utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0152] Bus 630 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0153] The electronic device 600 can also communicate with one or more external devices 700 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 600, and / or any device that enables the electronic device 600 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output interface 650. Furthermore, the electronic device 600 can communicate with one or more networks (e.g., a local area network, a wide area network, and / or a public network such as the Internet) via a network adapter 660. The network adapter 660 can communicate with other modules of the electronic device 600 via the bus 630. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 600, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms.

[0154] Example 4

[0155] The present invention also provides a storage medium, specifically a computer-readable storage medium. The computer-readable storage medium is a memory device in a terminal device, used to store programs and data. It is understood that the computer-readable storage medium herein may include both the built-in storage medium in the terminal device and, of course, the extended storage medium supported by the terminal device. It may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for being loaded and executed by a processor. These instructions may be one or more computer programs (including program code). It should be noted that more specific examples of the computer-readable storage medium herein include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0156] Computer-readable storage media also include data signals propagated in baseband or as part of a carrier wave, which carry readable program code. Such propagated data signals can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than a readable storage medium, which can send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, radio frequency, etc., or any suitable combination of the above.

[0157] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network or a wide area network, or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0158] The processor may load and execute one or more instructions stored in a computer-readable storage medium to implement the corresponding steps of the cache management method based on the scalar memory automatic management strategy in the above embodiment. The processor may load and execute the following steps:

[0159] Establish a cache management strategy library, developed based on the hthreads parallel programming model interface of the Maichuang architecture, to automatically allocate, manage, and reclaim scalar memory cache resources; establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; establish a strategy and strategy parameter deduction model to automatically select the optimal cache management strategy based on the obtained memory access feature vectors and configure the corresponding strategy parameters.

[0160] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0161] See also Figure 1 , which is the on-chip heterogeneous many-core architecture of the domestic MT-3000 chip; it adopts a multi-domain micro-architecture, in which the general domain is mainly responsible for running the operating system and managing the acceleration cluster. Each acceleration cluster contains 24 acceleration arrays, and each acceleration array consists of a control core and 16 acceleration cores. The control core is responsible for the overall control flow and processing scalar calculations that are difficult to vectorize.

[0162] See also Figure 2 The hybrid memory architecture of the acceleration clusters is implemented. Each cluster has 32GB of off-chip DDR4 main memory, shared with the general domain. The on-chip memory hierarchy consists of four levels. Except for registers, all other levels must be manually managed through the hthreads programming model interface. Each core is equipped with scalar memory and array memory, which together serve as on-chip cache for storing scalar and vector data, respectively.

[0163] The solution presented in this paper is specifically designed for the scalar memory of the Maichuang platform, fully considering the unique characteristics of scalar memory in on-chip caches to improve its memory access efficiency in high-performance computing. This paper provides a scalar memory automated management policy library and memory access modeling method for the domestic Maichuang architecture. These components primarily include a scalar memory management policy library, a memory access feature model, and a policy and policy parameter derivation model. These components are developed based on the hthreads parallel programming model interface of the domestic Maichuang architecture and enable dynamic management of scalar memory cache resources at compile time or runtime.

[0164] In summary, the present invention provides a cache management method and system based on a scalar memory automatic management strategy. Through automatic strategy selection and parameter configuration, the present invention significantly improves the utilization efficiency of scalar memory and the memory access performance of the program, and has broad application prospects and significant practical value.

[0165] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0166] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0167] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0168] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, and can be electrical, mechanical, or other forms.

[0169] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0170] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0171] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0172] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0173] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0174] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0175] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A cache management method based on a scalar memory automatic management strategy, characterized in that: The following steps are involved: S1. Establish a cache management strategy library based on the HThreads parallel programming model interface of the Maichuang architecture to automatically allocate, manage, and reclaim scalar memory cache resources. The cache management strategy library includes: The batch cache management strategy reads all data blocks within the access memory range into the scalar memory at one time. Subsequent access to the data blocks is taken over by the batch cache management strategy, and all calculation operations are performed in the scalar memory. The single-buffer cache management strategy allocates a user-defined cache space in scalar memory for prefetching data from a certain data block. Memory access to this data block triggers cache hit detection logic. If a cache miss occurs, the data in the current buffer is selectively written back to main memory, and data within a certain range near the current memory access address is read into the buffer for subsequent computations. A direct-mapped cache management strategy allocates a user-defined cache space containing several cache lines in scalar memory for prefetching data from a data block. Memory accesses to this data block trigger cache hit detection logic. If a miss occurs, the data in the current cache line is selectively written back to main memory, and data within a certain range near the current access address is read into the corresponding cache line for subsequent computations. S2. Build a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors, specifically: S201. Define relevant basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function; stream refers to a subsequence of a memory access element sequence; stride refers to the distance between any two adjacent elements; S202, determining data block characteristics, where the characteristics of the data block are mainly defined by size boundaries; S203, establish a flow step feature model, assuming that in a flow, the step length is a discrete random variable whose value is , ; S204: Generate memory access feature vectors. According to the above definition, classify the memory access behaviors of key array variables in the program and generate corresponding memory access feature vectors. The memory access feature vectors include data block size, number of memory accesses, memory access step length, and proportion of high-frequency memory access step lengths. S3. Establish a strategy and strategy parameter deduction model, automatically select the optimal cache management strategy based on the obtained memory access feature vector, and configure the corresponding strategy parameters. Specifically: S301, designing a strategy selection unit to define a matching rule for a cache management strategy based on a memory access feature vector; S302, designing a policy parameter configuration unit, configuring corresponding policy parameters according to the selected cache management policy; S303: Automatically configure the policy and policy parameters. Through the policy selection unit and the policy parameter configuration unit, automatically select the policy and configure the policy parameters to ensure that the cache management policy can dynamically adapt to changes in the program's memory access behavior.

2. The cache management method based on the scalar memory automatic management strategy according to claim 1, characterized in that: The configurable parameters for the single buffer cache management strategy are , represents the logarithm of the cache size with base 2; The cache hit judgment logic is: in, Indicates the address aligned according to the cache space size, Indicates the starting address of the current cache data block in the main memory, Indicates the end address of the current cache data block in the main memory, Represents a cache hit indicator.

3. The cache management method based on scalar memory automatic management strategy according to claim 1, characterized in that: The configurable parameters for direct-mapped cache management policy are and , represents the base-2 logarithm of the cache line size, Indicates the base-2 logarithm of the number of cache groups. The cache hit judgment logic of this policy is: in, Indicates the cache group index, Represents a cache tag array that stores the tag value of each cache line. Represents a cache hit indicator.

4. The cache management method based on scalar memory automatic management strategy according to claim 1, characterized in that: Based on the step length feature, define: in, is an arbitrarily small positive number, Represents the index of the high-frequency step, that is, the sequence number of the step with the highest frequency in the stream, Indicates the specific value of the high-frequency step size, Indicates step length Probability of occurrence; proposition Indicates that there are high-frequency non-zero steps in the stream , proposition Indicates that the step size is 1.

5. The cache management method based on scalar memory automatic management strategy according to claim 4, characterized in that: According to the proposition and True or false, the flow is divided into: Regular Sequence Flow: When When true; Regular non-sequential flow: When When true; Irregular flow: When When true.

6. The cache management method based on scalar memory automatic management strategy according to claim 4, characterized in that: The matching rules for the cache management policy are as follows: If the data block size is smaller than the scalar memory space, select the batch cache management strategy; if the data block size is larger than the scalar memory space and the flow is a regular sequential flow, select the single buffer cache management strategy; in other cases, select the direct mapped cache management strategy; According to the selected cache management strategy, configure the corresponding strategy parameters as follows: When the batch cache management strategy is selected, no additional parameter configuration is required, and the data block is directly read into the scalar memory at one time; when the single buffer cache management strategy is selected, the buffer size parameter is configured. , which represents the logarithm of the cache space size with base 2; when the direct-mapped cache management strategy is selected, configure the cache line size and the number of cache groups , which represent the base-2 logarithms of the cache line size and the number of cache groups, respectively.

7. A cache management system based on a scalar memory automatic management strategy, characterized in that: include: The strategy module establishes a cache management strategy library based on the HThreads parallel programming model interface of the Maichuang architecture. It is used to automatically allocate, manage, and reclaim scalar memory cache resources. The cache management strategy library includes: The batch cache management strategy reads all data blocks within the access memory range into the scalar memory at one time. Subsequent access to the data blocks is taken over by the batch cache management strategy, and all calculation operations are performed in the scalar memory. The single-buffer cache management strategy allocates a user-defined cache space in scalar memory for prefetching data from a certain data block. Memory access to this data block triggers cache hit detection logic. If a cache miss occurs, the data in the current buffer is selectively written back to main memory, and data within a certain range near the current memory access address is read into the buffer for subsequent computations. A direct-mapped cache management strategy allocates a user-defined cache space containing several cache lines in scalar memory for prefetching data from a data block. Memory accesses to this data block trigger cache hit detection logic. If a miss occurs, the data in the current cache line is selectively written back to main memory, and data within a certain range near the current access address is read into the corresponding cache line for subsequent computations. The quantization module establishes a memory access feature model to quantify the memory access behavior of key array variables in the program and generate the corresponding memory access feature vectors, specifically: Define the relevant basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function, stream refers to a subsequence of a memory access element sequence, and step size refers to the distance between any two adjacent elements; Determine the characteristics of the data block, which are mainly defined by the size boundary; Establish a flow step feature model, assuming that in a flow, the step length is a discrete random variable whose value is , ; Generate memory access feature vectors. Based on the above definition, classify the memory access behaviors of key array variables in the program and generate corresponding memory access feature vectors. The memory access feature vectors include data block size, number of memory accesses, memory access step length, and the proportion of high-frequency memory access step lengths. The management module establishes a strategy and strategy parameter deduction model, automatically selects the optimal cache management strategy based on the obtained memory access feature vector, and configures the corresponding strategy parameters. Specifically: Design a strategy selection unit to define the matching rules of the cache management strategy based on the memory access feature vector; Design a policy parameter configuration unit to configure corresponding policy parameters according to the selected cache management policy; Automatic configuration of policies and policy parameters is achieved. Through the policy selection unit and the policy parameter configuration unit, the policy selection and policy parameter configuration are automatically achieved to ensure that the cache management policy can dynamically adapt to changes in the program's memory access behavior.

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