Test Method, System, Device, Equipment and Storage Medium for PCIE Physical Layer

Abstract

Embodiments of the present application disclose a test method, system, device, equipment and storage medium for a PCIE physical layer. In this method, on the one hand, by configuring delay parameters for each communication link, the delay difference of signals transmitted between different chips can be compensated, so as to achieve synchronous sampling of the signals transmitted in each communication link at the receiving end, and avoid the risk of signal acquisition errors or misclicks. On the other hand, by clearing the receive buffer in a timely manner when switching clocks, the risk of link establishment failure caused by receive buffer overflow can be avoided, so that the functional test of the PCIE physical layer through a third-party PCIE controller can be more accurate.

Description

Technical Field

[0001] This application relates to the technical field of PCIE physical layer testing. Specifically, it relates to a testing method, system, device, equipment, and storage medium for the PCIE physical layer. Background Art

[0002] Currently, in integrated circuit design, the design of PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is divided into a controller and a PHY (Physical Layer). Generally, the PHY and the controller are used and tested together, but in some special cases, it may be necessary to test the controller or the PHY separately.

[0003] In the related art, the function of the PHY is usually tested through a third-party PCIE controller. However, when testing the function of the PHY through a third-party PCIE controller, there are risks of incorrect parallel signal acquisition or misaligned frames, as well as the risk of PCIE link establishment failure, resulting in inaccurate function testing of the PCIE physical layer. Summary of the Invention

[0004] To solve the above technical problems, embodiments of this application provide a testing method, system, device, equipment, and storage medium for the PCIE physical layer, so as to be able to more accurately perform function testing on the PCIE physical layer.

[0005] According to one aspect of the embodiments of this application, a testing method for the PCIE physical layer is provided. The method is applied to a testing system, and the testing system includes a component under test and a testing component. The component under test includes a test chip provided with a PCIE physical layer, and the testing component includes a third-party PCIE controller for performing function testing on the PCIE physical layer. The method includes: obtaining the testing requirements of the component under test; when the testing requirements include testing the transmission function of the component under test, configuring delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end; when the testing requirements include testing the link establishment function of the component under test, performing reset control on a first data buffer corresponding to the component under test and a second data buffer corresponding to the testing component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process, where the first data buffer is used to receive the data sent by the testing component, and the second data buffer is used to receive the data sent by the component under test.

[0006] In some embodiments, the component under test further includes a first control module, which is disposed between the PCIE physical layer and the third-party PCIE controller. The test component further includes a second control module, which is connected to the third-party PCIE controller. The delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter. The first delay parameter is used to adjust the delay time of the transmission signals in each communication link. Configuring the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end includes: performing pseudo-random number training through the first control module and the second control module to obtain the first delay parameter. Among them, the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer. The first delay parameter is respectively configured into the parameter registers corresponding to each path of the transmission signals in each communication link.

[0007] In some embodiments, performing pseudo-random number training through the first control module and the second control module to obtain the first delay parameter includes: performing initial delay parameter configuration on the first control module according to a preset delay parameter sequence. Among them, the delay parameter sequence includes a plurality of preset delay times sorted in an arithmetic progression. The first control module and the second control module after configuring the delay parameters send pseudo-random numbers to each other and check the received pseudo-random numbers to obtain a data check result sequence. Among them, the data check result sequence includes the data check results corresponding to each of the preset delay times, and each data check result is arranged in the order of the preset delay times in the delay parameter sequence. Determining a first critical value and a second critical value corresponding to the effective sampling window according to the data check result sequence. Among them, the first critical value is used to represent the preset delay time configured by the first control module when the data check changes from successful to failed among the data check results in the data check result sequence. The second critical value is used to represent the preset delay time configured by the first control module when the data check changes from failed to successful. Determining the first delay parameter of each path of the transmission signals in each communication link according to the first critical value and the second critical value.

[0008] In some embodiments, the delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer further includes a second delay parameter; the second delay parameter is used to adjust the number of delay bits of the transmission signal in each communication link; the configuration of the delay parameter for each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signal in each communication link by the receiving end includes: performing constant training through the first control module and the second control module to obtain the second delay parameter; wherein, the constant training is used to determine the second delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; and configuring the second delay parameter into the parameter register corresponding to each transmission signal in each communication link.

[0009] In some embodiments, the performing constant training through the first control module and the second control module to obtain the second delay parameter includes: configuring the delay parameter for the first control module according to a preset number of delay bits; performing mutual transmission of constants through the first control module with the configured delay parameter and the second control module to obtain a data reception result; wherein, the data reception result includes the received data of each communication link at the preset number of delay bits; determining a reference data and the flag bit in the reference data from the data reception result; comparing all the received data in the data reception result with the flag bit in the reference data to obtain the relative delay difference between all the received data and the flag bit in the reference data; and determining the second delay parameter of each transmission signal in each communication link according to the relative delay difference.

[0010] In some embodiments, the test component further includes a third control module, and the third control module is connected to the third-party PCIE controller;

[0011] Performing reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process includes: sending a rate signal from the test component to the component under test and generating a second reset signal to perform reset control on the second data buffer; wherein, the rate signal is used to trigger the third control module to switch the clock frequencies of the PCIE physical layer and the third-party PCIE controller, and the second reset signal is used to restore the second data buffer to its initial state; when the component under test receives the rate signal sent by the test component, generating a first reset signal to perform reset control on the first data buffer; wherein, the first reset signal is used to restore the first data buffer to its initial state; when the component under test and the test component complete the clock frequency switching, canceling the first reset signal and the second reset signal.

[0012] In some embodiments, the method further includes: after the component under test and the test component complete the clock frequency switching, sending a clock gating signal from the component under test to the test component, so that the switched clock frequencies of the PCIE physical layer and the third-party PCIE controller can take effect simultaneously; wherein, the clock gating signal is used to indicate the clock states of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is at a first preset level, the clock state is an effective state, and when the clock gating signal is at a second preset level, the clock state is an invalid state.

[0013] According to one aspect of the embodiments of the present application, a test system for a PCIE physical layer is provided, including: a component under test, including a test chip provided with a PCIE physical layer; a test component, including a third-party PCIE controller; the test component is configured to obtain the test requirements of the component under test, and when the test requirements include the transmission function of the component under test, configure the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end; and, when the test requirements include testing the link establishment function of the component under test, performing reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein, the first data buffer is used to receive the data sent by the test component, and the second data buffer is used to receive the data sent by the component under test.

[0014] In some embodiments, the component under test further includes a first control module, which is disposed between the PCIE physical layer and the third-party PCIE controller; the test component includes a first test component, and the first test component includes the third-party PCIE controller and a second control module; the first control module and the second control module are configured to configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, so as to enable the receiving end to synchronously sample the transmission signals in each communication link.

[0015] In some embodiments, the first test component further includes a third control module, and the third control module is connected to the third-party PCIE controller; the third control module is configured to perform reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component, so as to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process.

[0016] In some embodiments, the test component further includes a second test component; the second test component is configured to obtain the test requirements of the component under test and call corresponding test cases according to the test requirements, so as to perform functional testing on the component under test.

[0017] According to one aspect of the embodiments of the present application, a test device for a PCIE physical layer is provided, which is applied to a test system. The test system includes a component under test and a test component. The component under test includes a test chip provided with a PCIE physical layer. The test component includes a third-party PCIE controller, and the third-party PCIE controller is configured to perform functional testing on the PCIE physical layer; the device includes: an acquisition module configured to acquire the test requirements of the component under test; a configuration module configured to, when the test requirements include testing the transmission function of the component under test, configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, so as to enable the receiving end to synchronously sample the transmission signals in each communication link; a control module configured to, when the test requirements include testing the link establishment function of the component under test, perform reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component, so as to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein, the first data buffer is used to receive the data sent by the test component, and the second data buffer is used to receive the data sent by the component under test.

[0018] According to one aspect of the embodiments of the present application, an electronic device is provided, including: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the test method of the PCIE physical layer as described above.

[0019] According to one aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored, which, when executed by a processor of a computer, cause the computer to execute the test method of the PCIE physical layer as described above.

[0020] In the technical solution provided by the embodiments of the present application, on the one hand, by configuring the delay parameters of each communication link, the delay difference of the transmitted signals between different chips can be compensated, so as to realize the synchronous sampling of the transmitted signals in each communication link at the receiving end, and avoid the risk of signal acquisition errors or missed beats; on the other hand, by clearing the receive buffer in time when switching the clock, the risk of link establishment failure caused by receive buffer overflow can be avoided, so that the functional test of the PCIE physical layer through a third-party PCIE controller can be more accurate.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0023] Figure 1 is a schematic structural diagram of a test system of the PCIE physical layer shown in an exemplary embodiment of the present application;

[0024] Figure 2 is a schematic structural diagram of a component under test shown in an exemplary embodiment of the present application;

[0025] Figure 3 is a schematic structural diagram of a first test component shown in an exemplary embodiment of the present application;

[0026] Figure 4 is a schematic structural diagram of a second test component shown in an exemplary embodiment of the present application;

[0027] Figure 5It is a flowchart of a test method for a PCIE physical layer shown in an exemplary embodiment of the present application;

[0028] Figure 6 is Figure 5 It is a flowchart of configuring delay parameters for step S520 in the shown embodiment in an exemplary embodiment;

[0029] Figure 7 is Figure 6 It is a flowchart of performing pseudo - random number training for step S610 in the shown embodiment in an exemplary embodiment;

[0030] Figure 8 is Figure 5 It is a flowchart of configuring delay parameters for step S520 in the shown embodiment in another exemplary embodiment;

[0031] Figure 9 is Figure 8 It is a flowchart of performing constant training for step S810 in the shown embodiment in an exemplary embodiment;

[0032] Figure 10 is Figure 5 It is a flowchart of reset control for the first data buffer and the second data buffer for step S530 in the shown embodiment in an exemplary embodiment;

[0033] Figure 11 It is a timing diagram of clock switching management shown in an exemplary embodiment of the present application;

[0034] Figure 12 It is an application schematic diagram of clock switching management shown in an exemplary embodiment of the present application;

[0035] Figure 13 It is a structural schematic diagram of a test device for a PCIE physical layer shown in an exemplary embodiment of the present application;

[0036] Figure 14 It shows a structural schematic diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application.

[0037] Reference numerals: 110: component under test; 111: test chip provided with a PCIE physical layer; 112: first control module; 113: on-chip processor; 114: on-chip PCIE controller; 120: test component; 121: first test component; 1210: IO interface; 1211: data selection module; 1212: second control module; 1213: test module; 1214: third-party PCIE controller; 1215: third-party QDMA controller; 1216: register module; 1217: data storage and test module; 1218: third control module; 1219: first serial communication controller; 1220: second serial communication controller; 122: second test component; 1221: PCIE-RC controller; 1222: third-party PCIE physical layer; 1223: test interface; 1224: test case module; 130: external debug computer. Detailed implementation manners

[0038] Here, the exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners of the present application. Instead, they are merely examples of the devices and methods that are the same as some aspects of the present application as detailed in the appended claims.

[0039] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of application programs, or implemented in one or more hardware modules or integrated circuits, or implemented in different models and / or processor devices and / or microcontroller devices.

[0040] The flowcharts shown in the drawings are only exemplary descriptions and do not necessarily include all the content and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0041] It should be noted that the term "a plurality of" as mentioned in the present application refers to two or more. The "and / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0042] Currently, in integrated circuit design, the design of PCIE (Peripheral Component Interconnect Express) is divided into a controller and a PHY (Physical Layer). Usually, the PHY and the controller are used and tested together, but in some special cases, it may be necessary to test the controller or the PHY separately.

[0043] In the related art, the function of the PHY is usually tested through a third-party PCIE controller. However, when testing the function of the PHY through a third-party PCIE controller, there are risks of parallel signal acquisition errors or wrong beats, and there is also a risk of PCIE link establishment failure, which makes the function test of the PCIE physical layer inaccurate.

[0044] Based on this, the embodiment of the present application provides a method for testing a PCIE physical layer. By configuring delay parameters for each communication link, this method can compensate for the delay differences of signals transmitted between different chips, thereby achieving synchronous sampling of the signals transmitted in each communication link at the receiving end and avoiding the risks of signal acquisition errors or wrong beats; and, by clearing the receive buffer in a timely manner when switching clocks, it can avoid the risk of link establishment failure caused by receive buffer overflow, thereby making the function test of the PCIE physical layer through a third-party PCIE controller more accurate.

[0045] To facilitate understanding of the method for testing a PCIE physical layer provided by the embodiment of the present application, the following introduces the test scenario of the PCIE physical layer in combination with Figure 1 the shown implementation environment; this implementation environment is specifically a test system for a PCIE physical layer. As Figure 1 shown, the test system for the PCIE physical layer includes a component under test 110 and a test component 120. The component under test 110 includes a test chip 111 provided with a PCIE physical layer, and the test component 120 includes a third-party PCIE controller.

[0046] In some embodiments, the test component 120 includes a first test component 121 and a second test component 122. Exemplarily, the first test component 121 can be an FPGA (Field Programmable Gate Array) test board, and the second test component 122 is used to obtain the test requirements of the component under test 110 and call the corresponding test cases according to the test requirements to perform a function test on the component under test. Exemplarily, the second test component 122 can be a computer or a server with a PCIE expansion interface, and relevant test software is installed in the second test component 122.

[0047] In some embodiments, when the test requirements include the transmission function of the component under test, the first test component 121 can configure the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmitted signals in each communication link at the receiving end.

[0048] When the test requirements include testing the link establishment function of the component under test, the first test component 121 can also perform reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein, the first data buffer is used to receive the data sent by the test component, and the second data buffer is used to receive the data sent by the component under test.

[0049] In some embodiments, the test system further includes an external debug computer 130. The external debug computer 130 includes a serial communication controller, and the external debug computer 130 initiates register read / write operations through the serial communication controller.

[0050] Combined Figure 2 as shown Figure 2 is a schematic structural diagram of the component under test shown in an exemplary embodiment of the present application. As Figure 2 shown, the component under test 110 includes a test chip 111 provided with a PCIE physical layer, a first control module 112, an on-chip processor 113, and an on-chip PCIE controller 114.

[0051] In some embodiments, the test chip 111 provided with a PCIE physical layer supports the PCIE protocol and has a maximum communication rate of Gen5. The test chip 111 provided with a PCIE physical layer can form a standard PCIE-EP (Endpoint) device with an external third-party PCIE controller, such as a graphics card, SSD (Solid-State Drive), network card, etc. inserted in a PCIe slot. However, a first control module 112 needs to be added between the test chip 111 provided with a PCIE physical layer and the third-party PCIE controller. At the same time, the test chip 111 provided with a PCIE physical layer and the on-chip PCIE controller 114 can also form a standard PCIE-EP device.

[0052] The signals between the test chip 111 with a PCIE physical layer and the third-party PCIE controller are mainly PCIE-PIPE (Physical Interface for PCI Express) signals, including signals in the direction from the third-party PCIE controller to the PCIE physical layer (TX direction) and signals in the direction from the PCIE physical layer to the third-party PCIE controller (RX direction). The test chip 111 with a PCIE physical layer is directly interconnected with the third-party PCIE physical layer in the second test component 122 to complete the communication between the PCIE-RC device and the PCIE-EP device.

[0053] In some embodiments, the first control module 112 is arranged between the test chip 111 with a PCIE physical layer and the third-party PCIE controller. The first control module 112 can control the delay of the signals in the TX direction and the transmission signals in the RX direction, as well as the generation and verification of pseudo-random numbers. Through the training process of pseudo-random numbers, it can be ensured that these signals can be correctly sampled under the 500M PIPE-PCLK (PHY Clock, the clock of the PCIE physical layer) clock, and then through the constant training process, the data alignment function is completed. In some embodiments, a first data buffer FIFO is arranged inside the first control module 112 for receiving the transmitted data from the first test component 121. The first control module 112 is interconnected with the on-chip processor 113 through the APB bus.

[0054] In some embodiments, the on-chip processor 113 is used to configure the relevant parameters of the test chip 111 with a PCIE physical layer and the on-chip PCIE controller 114, as well as the operation process after power-on. At the same time, it outputs a serial port to the first test component 121, and completes the signal pseudo-random number training process and the constant training process between the first control module 112 and the first test component 121, thereby realizing a highly reliable parallel data transmission method. The on-chip processor 113 accesses the internal registers of the first control module through the APB bus and accesses the registers related to the second control module 1212 through the serial port.

[0055] In some embodiments, the test chip 111 with a PCIE physical layer can choose to use the on-chip PCIE controller 114 or the third-party PCIE controller to form a PCIE device. In the test method and test system of the PCIE physical layer in this application, the third-party PCIE controller is used, and the on-chip PCIE controller 114 may not be used.

[0056] Combined Figure 3 shown Figure 3 is a schematic structural diagram of the first test component shown in an exemplary embodiment of this application. Figure 3Among them, the first test component 121 includes an IO (Input / Output) interface 1210, a data selection module 1211, a second control module 1212, a test module 1213, a third-party PCIE controller 1214, a third-party QDMA (Queue-based Direct Memory Access) controller 1215, a register module 1216, a data storage and test module 1217, a third control module 1218, a first serial communication controller 1219, and a second serial communication controller 1220.

[0057] The IO interface 1210 is a high-speed IO interface provided by a third party in the FPGA test board, supporting a maximum of 1.8 Gbps and the clock DDR sampling mode.

[0058] The data selection module 1211 is used to control the sending data source of the IO interface 1210 and the processing method of the received data. The sending data includes the first data from the second control module 1212, the second data from the test module 1213, and the third data from the third-party PCIE controller 1214. Among them, the first data is used to train the signal, the second data is used to test the stability of data transmission on the line after the signal training of the test system, and the third data is used to test the PCIE protocol and the stability of PCIE communication.

[0059] The second control module 1212 is used to generate pseudo-random numbers in the TX direction and verify pseudo-random numbers in the RX direction, as well as send and verify constants in the constant training, and save the verification results in the register module 1216. Finally, it is transmitted to the on-chip processor 113 in the component under test 110 through the first serial communication controller 1219 to complete the pseudo-random number training function and the constant training function, thereby implementing the high-reliability parallel data transmission method. At the same time, a second data buffer FIFO is set inside the second control module 1212 to receive the sending data from the component under test 110.

[0060] The test module 1213 is used to test the stability of signal transmission in the TX direction and the RX direction after the pseudo-random number training and the constant training are completed. The test module 1213 generates incremental data, which is then sent to the component under test 110 by the IO interface 1210. After the first control module 112 in the component under test 110 receives the incremental data, it sends the received incremental data through the sending interface. The IO interface 1210 then receives the incremental data back and completes the data comparison in the test module 1213.

[0061] A third-party PCIE controller 1214 supports the PCIE protocol and communication rates of Gen1, Gen2, Gen3, Gen4, and Gen5. The corresponding single-channel communication rates are 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, and 32 Gbps respectively. The PIPE-PCLK clock frequencies of the PIPE interface are 125 MHz, 250 MHz, 250 MHz, 500 MHz, and 500 MHz respectively. The effective data widths of the PIPE interface communication are 16 bits, 16 bits, 32 bits, 32 bits, and 64 bits respectively. In some embodiments, the third-party PCIE controller 1214 is a PCIE-EP controller.

[0062] A third-party QDMA controller 1215 is used to parse data packets from the third-party PCIE controller 1214, and after packetizing according to the protocol, send them out through the third-party PCIE controller 1214. At the same time, the third-party QDMA controller 1215 internally includes a QDMA controller, which mainly completes the DMA read and DMA write functions. The user interface mainly includes an AXI interface and an AXI-LITE interface. The AXI interface is a DMA interface, which is interconnected with the data storage and test module 1217 to complete the DMA read and DMA write tests. The AXI-LITE interface is a register read / write interface, which is interconnected with the register module 1216 and can configure the registers required by the user.

[0063] A register module 1216 is used to configure all the registers in this application. The register module 1216 includes three configuration interfaces, which are respectively connected to the third-party QDMA controller 1215, the first serial communication controller 1219, and the second serial communication controller 1220. The configuration requests of the third-party QDMA controller 1215 come from the PCIE-RC controller 1221, the configuration requests of the first serial communication controller 1219 come from the on-chip processor 113, and the configuration requests of the second serial communication controller 1220 come from the external debug computer 130. The registers in the register module 1216 include four types: data selection registers, training registers, interface test registers, and DMA test registers, which respectively correspond to the data selection module 1211, the second control module 1212, the test module 1213, and the data storage and test module 1217.

[0064] Data storage and test module 1217, the data storage and test module 1217 includes a storage module RAM, which serves as a storage carrier for DMA data. In some embodiments, the DMA test supports three modes: DMA read test mode, DMA write test mode, and DMA read / write alternating test mode; the DMA read test mode, i.e., the H2C (Host to Card) mode, where data is transferred from the memory of the PCIE-RC controller 1221 to the data storage and test module 1217, the data changes according to an increasing pattern, and then the data is compared, and the data comparison result is saved; the DMA write test mode, i.e., the C2H (Card to Host) mode, where data is transferred from the data storage and test module 1217 to the memory at the PCIE-RC controller 1221 end, the data changes according to an increasing pattern, and then the data is compared, and the data comparison result is saved; the DMA read / write alternating test mode, i.e., the alternating test of the H2C mode and the C2H mode, where the host first writes data into the storage module RAM in the data storage and test module 1217 through the H2C mode, then transfers the data back to the host through the C2H mode, and then compares the data, and loops.

[0065] The third control module 1218 is used for clock generation and clock switching. Clock generation mainly includes the clocks required for the IO interface 1210 and the third-party PCIE controller 1214. Clock switching mainly refers to the switching of the PIPE-PCLK clock among 125 MHz, 250 MHz, and 500 MHz during the PCIE link establishment process of the third-party PCIE controller 1214 from Gen1 to Gen5.

[0066] The first serial communication controller 1219 is used to implement the serial port protocol and the custom communication transmission protocol. The first serial communication controller 1219 is a serial port slave controller. The serial port master controller is on the on-chip processor 113. The on-chip processor 113 initiates register read / write operations, which are received and parsed by the first serial communication controller 1219, and then the training class registers in the register module 1216 are accessed, and finally, in cooperation with the on-chip processor 113, the pseudo-random number training function and the constant training function are completed.

[0067] The second serial communication controller 1220 has the same function as the first serial communication controller 1219 and is used to implement the serial port protocol and the custom communication transmission protocol. It is a serial port slave controller. The serial port master controller is on the external debug computer 130. The external debug computer 130 initiates register read / write operations, which are received and parsed by the second serial communication controller 1220, and then all the registers in the register module 1216 are accessed, so that the debugger can obtain the status of all the registers.

[0068] CombinedFigure 4 As shown Figure 4 It is a schematic structural diagram of a second test component shown in an exemplary embodiment of the present application. Figure 4 In it, the second test component 122 can be used to obtain the test requirements of the component under test, and call the corresponding test cases according to the test requirements to perform functional tests on the component under test. The second test component 122 includes a PCIE-RC controller 1221, a third-party PCIE physical layer 1222, a test interface 1223, and a test case module 1224.

[0069] The PCIE-RC (Root Complex) controller 1221 and the third-party PCIE physical layer form a standard PCIE-RC device, support the PCIE protocol, support communication rates of Gen1, Gen2, Gen3, Gen4, and Gen5, and can establish a link and communicate with a PCIE-EP device.

[0070] The third-party PCIE physical layer 1222 and the PCIE-RC controller 1221 form a standard PCIE-RC device and are used in cooperation to directly interconnect with the test chip 111 provided with a PCIE physical layer to complete communication between the PCIE-RC device and the PCIE-EP device.

[0071] The test interface 1223 includes interface models that can initiate various data packets on a PCIE-RC device (host device), such as a configuration write request interface, a configuration read request interface, a configuration read completion interface, a memory write request interface, a memory read request interface, a memory read completion interface, a QDMA-H2C test interface, a QDMA-C2H test interface, a vendor / device ID acquisition interface, a PCIE link establishment interface, a base address register BAR space initialization interface, etc. In some embodiments, other test interface models may also be included, such as a serial port write access interface, a serial port read access interface, a power-on initialization interface for the component under test, a training initialization interface, a TX direction pseudo-random number training interface, a TX direction constant training interface, an RX direction pseudo-random number training interface, an RX direction constant training interface, a test mode configuration interface, etc. The test interface 1223 can be called in the test case module 1224 to complete relevant test cases.

[0072] In some embodiments, the serial port write access interface and the serial port read access interface run on the on-chip processor 113 and the external debug computer 130 respectively. The power-on initialization interface for the component under test, the training initialization interface, the TX direction pseudo-random number training interface, the TX direction constant training interface, the RX direction pseudo-random number training interface, the RX direction constant training interface, and the test mode configuration interface can run on the on-chip processor 113.

[0073] The test case module 1224 is used to call test cases through the test interface 1223 according to test requirements. Exemplarily, the test cases include: training function test cases, increment number function test cases, PCIE link establishment function test cases, register read / write function test cases, QDMA transmission test cases, serial communication test cases, etc. Among them, the serial communication test is also used in the training function test cases or when the user uses the debug serial port.

[0074] In some embodiments, the training function test case is used to implement the test of inter-chip parallel data reliability transmission; the increment number function test case is used to test the stability of parallel data transmission; the PCIE link establishment function test case is used to test the basic function of PCIE to achieve successful link establishment at Gen5 rate; the register read / write function test case is used to test the basic communication function of PCIE; the QDMA transmission test case is used to test the stability of PCIE communication.

[0075] The following details the test method for the PCIE physical layer provided by the embodiments of the present application.

[0076] Please continue to refer to Figure 5 , Figure 5 which is a flowchart of the test method for the PCIE physical layer shown in an exemplary embodiment of the present application. This method can be applied to Figure 1 the test system shown, and is specifically executed by the test component 120 in this implementation environment. It should be understood that this method can also be applicable to other exemplary implementation environments and is specifically executed by the test component 120 in other implementation environments. This embodiment does not limit the implementation environment to which this method is applicable.

[0077] As Figure 5 shown, in an exemplary embodiment, the test method for the PCIE physical layer is applied to a test system. The test system includes a component under test and a test component. The component under test includes a test chip provided with a PCIE physical layer, and the test component includes a third-party PCIE controller. This method at least includes steps S510 to S530, which are introduced in detail as follows:

[0078] Step S510, obtain the test requirements of the component under test.

[0079] In the embodiments of the present application, the test component may include a first test component and a second test component. The second test component is a device such as a computer with a PCIE expansion interface, and test software is installed in the computer. When it is necessary to perform a functional test on the component under test, the corresponding test requirements can be input into the test software, and test cases can be called from the corresponding test interface to implement the functional test of the component under test. Therefore, in the embodiments of the present application, the test requirements of the component under test can be obtained through the second test component in the test component. For example, the test requirements may include one or more of testing the training function of the component under test, testing the increment function of the component under test, testing the link establishment function of the component under test, testing the register read / write function of the component under test, and testing the QDMA transmission function of the component under test.

[0080] Step S520, when the test requirements include testing the transmission function of the component under test, configure the delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer to enable the receiving end to synchronously sample the transmission signals in each communication link.

[0081] It can be understood that the design of PCIE in an integrated circuit includes a PCIE controller and a PCIE physical layer. Usually, when performing PCIE-related tests, the PCIE physical layer and the PCIE controller are tested together. However, in some cases, when testing the PCIE physical layer alone, a third-party PCIE controller is required to form a PCIE-EP device with the PCIE physical layer under test, and then cross-chip communication is performed to test the function of the PCIE physical layer.

[0082] When performing cross-chip communication, the data transmission can include two directions: from the third-party PCIE controller to the PCIE physical layer direction, that is, the TX (Transmit, send) direction; and, from the PCIE physical layer to the third-party PCIE controller direction, that is, the RX (Receive, receive) direction. When performing PCIE function tests, the third-party PCIE controller and the PCIE physical layer will send and receive data from each other. Therefore, in the TX direction, the receiving end can be the PCIE physical layer; in the RX direction, the receiving end can be the third-party PCIE controller.

[0083] In the embodiments of the present application, when it is detected that it is necessary to test the transmission function of the component under test, by configuring the delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, not only can the calibration of the sampling window be achieved, but also the offset between each communication link can be compensated, eliminating the propagation delay difference of each communication link, so that the receiving end can synchronously sample the transmission signals in each communication link.

[0084] Step S530, when the test requirement includes testing the link establishment function of the component under test, perform a reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component, so as to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process.

[0085] It should be understood that the differences in transmission rates and encoding methods among different generations result in the need for different clock frequencies to maintain the correctness and efficiency of data transmission. Therefore, different generations require different transmission rates and clock frequencies. In some embodiments, the clock switching is usually triggered by the test process of the PCIE link establishment function, and the third-party PCIE controller will automatically adjust the PIPE-PCLK frequency, that is, the clock frequency, according to the link width and the rate supported by the device. When the clock frequency is switched during the link establishment process, due to the delay in data transmission between the third-party PCIE controller and the PCIE physical layer, the clocks are generated locally respectively, and the clock switching moments may be asynchronous, which may cause buffer overflows in the local data buffers of the third-party PCIE controller and the PCIE physical layer during clock switching, resulting in the failure of PCIE link establishment and inaccurate functional test results for the PCIE physical layer.

[0086] In the embodiments of the present application, when testing the link establishment function of the PCIE physical layer, by performing a reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component, the data received by the first data buffer and the second data buffer during the clock frequency switching process can be cleared in time, thereby avoiding the risk of link establishment failure caused by buffer overflow and making the functional test of the PCIE physical layer more accurate.

[0087] In some embodiments, the PCIE physical layer in the embodiments of the present application supports a maximum communication rate of Gen5. Therefore, when testing the PCIE link establishment function, the link establishment and testing are usually performed in sequence from Gen1, Gen2, Gen3, Gen4, to Gen5.

[0088] Exemplarily, the single-channel communication rate corresponding to Gen1 is 2.5 Gbps, and the corresponding PIPE-PCLK frequency is 125 MHz; the single-channel communication rate corresponding to Gen2 is 5 Gbps, and the corresponding PIPE-PCLK frequency is 250 MHz; the single-channel communication rate corresponding to Gen3 is 8 Gbps, and the corresponding PIPE-PCLK frequency is 250 MHz; the single-channel communication rate corresponding to Gen4 is 16 Gbps, and the corresponding PIPE-PCLK frequency is 500 MHz; the single-channel communication rate corresponding to Gen5 is 32 Gbps, and the corresponding PIPE-PCLK frequency is 500 MHz.

[0089] Please refer to Figure 6 , Figure 6 which Figure 5 is a flowchart of configuring a delay parameter in step S520 in the illustrated embodiment; wherein, the component under test further includes a first control module, the first control module is disposed between the PCIE physical layer and a third-party PCIE controller, the test component further includes a second control module, and the second control module is connected to the third-party PCIE controller; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter; the first delay parameter is used to adjust the delay time of the transmitted signals in each communication link; it at least includes steps S610 to S620, which are introduced in detail as follows:

[0090] Step S610, perform pseudo-random number training through the first control module and the second control module to obtain the first delay parameter. Wherein, the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer.

[0091] In the embodiment of the present application, when testing by forming a PCIE-EP device through a third-party PCIE controller and a PCIE physical layer, high-speed parallel signal communication is performed across chips between the test chip with the PCIE physical layer and the third-party PCIE controller. Due to different parallel signal delays, there may be a risk of incorrect signal acquisition or parallel signal misalignment. By setting a first control module between the third-party PCIE controller and the PCIE physical layer, and performing pseudo-random number training through the first control module and the second control module in the test component, the sampling phase of each communication link between the third-party PCIE controller and the PCIE physical layer can be dynamically optimized, ensuring correct sampling of complex data patterns under high-speed clocks, thereby solving the problem of incorrect acquisition or misalignment caused by different transmission delays of parallel signals.

[0092] Based on the above description of the data transmission direction for cross-chip communication, it can be known that the data transmission can include two directions: from the third-party PCIE controller to the PCIE physical layer direction, that is, the TX (Transmit, send) direction; and, from the PCIE physical layer to the third-party PCIE controller direction, that is, the RX (Receive, receive) direction. Therefore, the first delay parameter in the embodiment of the present application includes the first delay parameter in the TX direction and the first delay parameter in the RX direction.

[0093] In some embodiments, the first delay parameter in the TX direction refers to the delay parameter of the first control module for receiving signals, and the first delay parameter in the RX direction refers to the delay parameter of the first control module for sending signals. On this basis, the pseudo-random number training includes pseudo-random number training in the TX direction and pseudo-random number training in the RX direction, so as to obtain the first delay parameter in the TX direction and the first delay parameter in the RX direction.

[0094] Combined with Figure 7 as shown Figure 7 is Figure 6 The flowchart of step S610 in the illustrated embodiment for performing pseudo-random number training in an exemplary embodiment; it includes at least steps S710 to S740, which are introduced in detail as follows:

[0095] Step S710, configure the initial delay parameter for the first control module according to a preset delay parameter sequence.

[0096] It can be understood that through the above description of the data transmission direction for cross-chip communication, the first delay parameter includes the first delay parameter in the TX direction and the first delay parameter in the RX direction. The first delay parameter in the TX direction refers to the delay parameter of the first control module for receiving signals, and the first delay parameter in the RX direction refers to the delay parameter of the first control module for sending signals. Therefore, when configuring the initial delay parameter for the first control module, it includes configuring the initial delay parameter of the first control module for receiving signals and configuring the initial delay parameter of the first control module for sending signals.

[0097] In some embodiments, the delay parameter sequence includes multiple preset delay times sorted in an arithmetic progression. For example: the delay parameter sequence includes an arithmetic progression with the first term being 0, the last term being Tmax, and the common difference being d.

[0098] Exemplarily, when performing pseudo-random number training in the TX direction, configuring the initial delay parameter for the first control module according to the preset delay parameter sequence includes: traversing the preset delay parameter sequence, and in ascending order, configuring the preset delay time in the delay parameter sequence as the initial delay parameter of the first control module for receiving signals.

[0099] For example, the preset delay parameter sequence is {0, 2, 4, 6}. When performing pseudo-random number training in the TX direction, first set the initial delay parameter position of the first control module for receiving signals to 0. After one round of pseudo-random number sending, receiving, and verification, then set the initial delay parameter position of the first control module for receiving signals to 2,....... Repeat the above operations until the delay sequence parameter is traversed.

[0100] Exemplarily, when performing pseudo-random number training in the RX direction, the initial delay parameter configuration of the first control module is performed according to a preset delay parameter sequence, including: configuring the initial delay parameter of the signal sent by the first control module according to the preset delay parameter sequence.

[0101] For example, the preset delay parameter sequence is {0, 2, 4, 6}. When performing pseudo-random number training in the RX direction, first set the initial delay parameter position of the signal sent by the first control module to 0. After one round of pseudo-random number transmission, reception, and verification, then set the initial delay parameter position of the signal sent by the first control module to 2,....... Repeat the above operations until the delay sequence parameters are traversed.

[0102] Step S720, the first control module and the second control module after configuring the delay parameters mutually send pseudo-random numbers, and verify the received pseudo-random numbers to obtain a data verification result sequence.

[0103] It can be understood that by having the first control module and the second control module after configuring the initial delay parameters mutually send pseudo-random numbers and verifying the received pseudo-random numbers, it is possible to realize the transmission, reception, and verification of data by the first control module under different initial delay parameters, obtain the data verification results under different initial delay parameters, so as to facilitate determining the optimal delay parameter according to the data verification results under different initial delay parameters.

[0104] In some embodiments, since the data transmission directions in the test process include the TX direction and the RX direction, it is necessary to configure the first delay parameters of each communication link in different directions. By having the first control module and the second control module after configuring the initial delay parameters mutually send pseudo-random numbers and verifying the received pseudo-random numbers, the pseudo-random number training in the TX direction and the pseudo-random number training in the RX direction are realized, and the first delay parameters of each communication link in different directions are obtained.

[0105] Exemplarily, the pseudo-random number training in the TX direction (from the third-party PCIE controller to the PCIE physical layer direction) includes: the second control module sends pseudo-random numbers to the first control module after configuring the reception signal delay parameter, and the first control module after configuring the reception signal delay parameter verifies the received pseudo-random numbers.

[0106] Exemplarily, the pseudo-random number training in the RX direction (from the PCIE physical layer to the third-party PCIE controller direction) includes: the first control module after configuring the transmission signal delay parameter sends pseudo-random numbers to the second control module, and the second control module verifies the received pseudo-random numbers.

[0107] In some embodiments, the data verification result sequence includes data verification results corresponding to respective preset delay times, and the data verification results are arranged in the order of the preset delay times in the delay parameter sequence.

[0108] For example, the preset delay parameter sequence is {0, 2, 4, 6}. For the pseudo-random number training in the TX direction, according to this delay parameter sequence, the delay parameter of the signal received by the first control module can be configured to 0 first, and then the pseudo-random number is sent through the second control module. The first control module after configuring the delay parameter 0 receives the pseudo-random number and performs verification to obtain the data verification result; then the delay parameter of the signal received by the first control module is configured to 2, and then the pseudo-random number is sent through the second control module. The first control module after configuring the delay parameter 2 receives the pseudo-random number and performs verification to obtain the data verification result; then the delay parameter of the signal received by the first control module is configured to 4,... Repeat the above operations until the delay parameter sequence is traversed, and then stop the sending, receiving, and verification of the pseudo-random number.

[0109] For example, the preset delay parameter sequence is {0, 2, 4, 6}. For the pseudo-random number training in the RX direction, according to this delay parameter sequence, the delay parameter of the signal sent by the first control module can be configured to 0 first, and then the pseudo-random number is sent through the first control module after configuring the delay parameter 0. The second control module receives the pseudo-random number and performs verification to obtain the data verification result; then the delay parameter of the signal sent by the first control module is configured to 2, and then the pseudo-random number is sent through the first control module after configuring the delay parameter 2. The second control module receives the pseudo-random number and performs verification to obtain the data verification result; then the delay parameter of the signal sent by the first control module is configured to 4,... Repeat the above operations until the delay parameter sequence is traversed, and then stop the sending, receiving, and verification of the pseudo-random number.

[0110] Step S730, determine a first critical value and a second critical value corresponding to the effective sampling window according to the data verification result sequence.

[0111] It should be understood that the first critical value and the second critical value respectively mark the boundaries of the data valid windows in the current cycle and the next cycle. The area between the two is the verification failure area, and the valid windows may be distributed in two discontinuous areas, that is, from the minimum preset delay parameter to the first critical value, and from the second critical value to the maximum preset delay parameter. Therefore, the first critical value is used to represent the preset delay time configured by the first control module when the data verification result in the data verification result sequence changes from data verification success to data verification failure; the second critical value is used to represent the preset delay time configured by the first control module when the data verification result changes from data verification failure to data verification success.

[0112] In some embodiments, the transition from successful data verification to failed data verification means that when the delay parameter increases to the first critical value, the sampling point slides out of the right edge of the data valid window, resulting in verification failure. Therefore, when transitioning from successful data verification to failed data verification, the preset delay time configured by the first control module is determined as the first critical value.

[0113] The transition from failed data verification to successful data verification means that when the delay parameter increases to the second critical value, the sampling point enters the left edge of the data valid window of the next cycle due to cycle slip, making the data verification successful again. Therefore, when transitioning from failed data verification to successful data verification, the preset delay time configured by the first control module is determined as the second critical value.

[0114] For example, if the preset delay parameter sequence includes {0, 2, 4, 6}, then the corresponding data verification result sequence includes {verification failed (0), verification successful (2), verification successful (4), verification failed (6)}. From the data verification result sequence, it can be seen that when the preset delay parameter is 4, the corresponding data verification result is verification successful, and when the preset delay parameter is 6, the verification result is failed. Thus, the first critical value is 4; when the preset delay parameter is 0, the corresponding data verification result is verification failed, and when the preset delay parameter is 2, the verification result is successful. Therefore, the second critical value is 2.

[0115] Step S740: Determine the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value.

[0116] It should be understood that when determining the first delay parameter of each transmission signal in each communication link, data transmission, reception, and verification need to be performed through each communication link to determine the first critical value and the second critical value corresponding to each communication link. Then, according to the first critical value and the second critical value corresponding to each communication link, the first delay parameter of each transmission signal in each communication link is determined. In this embodiment of the application, only the current communication link (i.e., one of the communication links) is taken as an example for illustration.

[0117] Exemplarily, determining the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value includes: comparing the first critical value with the second critical value to obtain a comparison result; when the comparison result is that the first critical value is greater than the second critical value, calculating TXBest = (X0 + X1) / 2 to obtain the first delay parameter of the current communication link; where TXBest is the first delay parameter, X0 is the first critical value, and X1 is the second critical value. In this way, when the first critical value is greater than the second critical value, it can be considered that the data valid window is continuous, and the best point can be taken as the midpoint. Therefore, the average value between the first critical value and the second critical value is determined as the best delay parameter, that is, the first delay parameter.

[0118] Exemplarily, determining the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value includes: comparing the first critical value with the second critical value to obtain a comparison result; when the comparison result is that the first critical value is less than the second critical value and the first critical value is greater than the reference delay parameter, calculating TXBest = X0 - (Tmax - X1 + X0) / 2 to obtain the first delay parameter of the current communication link; where TXBest is the first delay parameter, X0 is the first critical value, X1 is the second critical value, and Tmax is the maximum preset delay parameter. Among them, the reference delay parameter is the difference between the maximum preset delay parameter and the second critical value. In this way, when the first critical value is less than the second critical value, it can be considered that the data valid window is divided into two segments, that is, the minimum preset delay parameter to the first critical value (from 0 to X0), and the second critical value to the maximum preset delay parameter (from X1 to Tmax); then it is necessary to judge which segment is longer. The reference delay parameter is the difference between the maximum preset delay parameter and the second critical value. Therefore, the reference delay parameter can represent the length of the second segment, and X0 can represent the length of the first segment; if the first critical value is greater than the reference delay parameter, the first segment is longer. Therefore, the best point can be placed at a position slightly to the left of the center of the first segment.

[0119] Exemplarily, determining the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value includes: comparing the first critical value with the second critical value to obtain a comparison result; in the case where the comparison result is that the first critical value is less than the second critical value and the first critical value is equal to the reference delay parameter, determining the preset delay parameter as the first delay parameter of the current communication link; in some embodiments, the preset delay parameter is 0. In this way, when the first critical value is less than the second critical value, it can be considered that the data valid window is divided into two segments, that is, from the minimum preset delay parameter to the first critical value (from 0 to X0), and from the second critical value to the maximum preset delay parameter (from X1 to Tmax); then it is necessary to determine which segment is longer. If the first critical value is equal to the reference delay parameter, the lengths of the two segments are equal, so the default starting point is directly taken as the sampling point, that is, the minimum preset delay parameter.

[0120] Exemplarily, determining the first delay parameter of each transmission signal in each communication link according to the first critical value and the second critical value includes: comparing the first critical value with the second critical value to obtain a comparison result; in the case where the comparison result is that the first critical value is less than the second critical value and the first critical value is less than the reference delay parameter, obtaining the first delay parameter of the current communication link by calculating TXBest = X1 + (Tmax - X1 + X0) / 2; where TXBest is the first delay parameter, X0 is the first critical value, X1 is the second critical value, and Tmax is the maximum preset delay parameter. Among them, the reference delay parameter is the difference between the maximum preset delay parameter and the second critical value. In this way, when the first critical value is less than the second critical value, it can be considered that the data valid window is divided into two segments, that is, from the minimum preset delay parameter to the first critical value (from 0 to X0), and from the second critical value to the maximum preset delay parameter (from X1 to Tmax); then it is necessary to determine which segment is longer. If the first critical value is less than the reference delay parameter, the second segment is longer, and the best point can be placed at a position to the right of its center.

[0121] Step S620, configuring the first delay parameter into the parameter register corresponding to each transmission signal in each communication link.

[0122] In the embodiment of the present application, since the first delay parameter includes the first delay parameter in the TX direction and the first delay parameter in the RX direction, when configuring the first delay parameter, the first delay parameter in the TX direction is configured into the delay time register of each signal in the TX direction of the first control module; the first delay parameter in the RX direction is configured into the delay time register of each signal in the RX direction of the first control module.

[0123] For example, the following process can be used to perform pseudo-random number training in the TX direction (from a third-party PCIE controller to the PCIE physical layer):

[0124] Step 1: The on-chip processor in the component under test configures both the first control module and the second control module into the pseudo-random number training mode through the APB bus and the serial port respectively.

[0125] Step 2: The on-chip processor in the component under test starts the instruction to send pseudo-random numbers of the second control module through the serial port and sends them infinitely.

[0126] Step 3: The on-chip processor in the component under test configures the delay parameter for receiving signals of the first control module according to the preset delay parameter sequence through the APB bus.

[0127] Step 4: The on-chip processor in the component under test starts the pseudo-random number receiving and verification instruction of the first control module through the APB bus and verifies according to the preset fixed number of data; and returns the receiving completion status and the data verification result after the verification is completed.

[0128] Step 5: The on-chip processor in the component under test queries the receiving completion status and the data verification result of the first control module through the APB bus.

[0129] Step 6: Re-execute Step 3 to Step 5, and reconfigure the preset delay parameters in the delay parameter sequence from the minimum value to the maximum value in turn; and record the preset delay parameter when each path of signal changes from verification success to verification failure as the first critical value, and the preset delay parameter when each path of signal changes from verification failure to verification success as the second critical value. After the preset delay parameters in the delay parameter sequence are traversed and the verification is completed, execute Step 7.

[0130] Step 7: Calculate the optimal delay parameter for each path of signal, that is, the first delay parameter:

[0131] When A0 > A1; then TABest = (A0 + A1) / 2;

[0132] When A0 < A1 and A0 > (Tmax - A1); then TABest = A0 - (Tmax - A1 + A0) / 2;

[0133] When A0 < A1 and A0 = (Tmax - A1); then TABest = the minimum preset delay parameter; in some embodiments, the minimum preset delay parameter is 0;

[0134] When A0 < A1 and A0 < (Tmax - A1); then TABest = A0 + (Tmax - A1 + A0) / 2;

[0135] Wherein, A0 is the first critical value in the TX direction, A1 is the second critical value in the TX direction, TABest is the first delay parameter in the TX direction, and Tmax is the maximum preset delay parameter in the delay parameter sequence;

[0136] Step 8: Configure the first delay parameter into the delay parameter register of each signal in the TX direction of the first control module.

[0137] By adopting the TX direction pseudo-random number training method in the embodiments of the present application, it is possible to configure the delay parameter of the received signal for the first control module, so that when the component under test receives data as the receiving end, the sampling point can be adjusted to the center of the effective window, ensuring that even if there are timing jitters or path delay differences, the receiving end can still sample the data stably.

[0138] For example, the following process can be used to perform pseudo-random number training in the RX direction (from the PCIE physical layer to the third-party PCIE controller):

[0139] Step 1: The on-chip processor in the component under test configures both the first control module and the second control module into the pseudo-random number training mode through the APB bus and the serial port respectively.

[0140] Step 2: The on-chip processor in the component under test starts the instruction to send pseudo-random numbers of the first control module through the APB bus and sends them infinitely.

[0141] Step 3: The on-chip processor in the component under test configures the delay parameter of the signal sent by the first control module according to the preset delay parameter sequence through the APB bus.

[0142] Step 4: The on-chip processor in the component under test starts the pseudo-random number receiving and verification instruction of the second control module through the serial port and verifies according to the preset fixed number of data; and returns the receiving completion status and the data verification result after the verification is completed.

[0143] Step 5: The on-chip processor in the component under test queries the receiving completion status and the data verification result of the second control module through the serial port.

[0144] Step 6: Re-execute Steps 3 to 5, and re-configure the preset delay parameters in the delay parameter sequence from the minimum value to the maximum value in turn; and record the preset delay parameter when each signal changes from verification success to verification failure as the first critical value, and the preset delay parameter when each signal changes from verification failure to verification success as the second critical value. After the preset delay parameters in the delay parameter sequence are traversed and the verification is completed, execute Step 7.

[0145] Step 7: Calculate the optimal delay parameter of each signal, that is, the first delay parameter:

[0146] When B0 > B1; then TBBest = (B0 + B1) / 2;

[0147] When B0 < B1 and B0 > (Tmax - B1), then TBBest = B0 - (Tmax - B1 + B0) / 2;

[0148] When B0 < B1 and B0 = (Tmax - B1), then TBBest = the minimum preset delay parameter; in some embodiments, the minimum preset delay parameter is 0;

[0149] When B0 < B1 and B0 < (Tmax - B1), then TBBest = B0 + (Tmax - B1 + B0) / 2;

[0150] Wherein, B0 is the first critical value in the RX direction, B1 is the second critical value in the RX direction, TBBest is the first delay parameter in the RX direction, and Tmax is the maximum preset delay parameter in the delay parameter sequence;

[0151] Step 8, configure the first delay parameter into the delay parameter register of each path of signals in the RX direction of the first control module.

[0152] By adopting the RX direction pseudo-random number training method in the embodiments of the present application, the delay parameter configuration of the received signal can be configured for the first control module, so that when the test component receives data as the receiving end, the sampling point can be adjusted to the center of the effective window, ensuring that even if there is timing jitter or path delay difference, the receiving end can still stably sample the data.

[0153] Please refer to Figure 8 , Figure 8 is Figure 5 The flowchart of configuring the delay parameter in another exemplary embodiment of step S520 in the shown embodiment; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer further include the second delay parameter; the second delay parameter is used to adjust the number of delay bits of the transmitted signal in each communication link; this method at least includes step S810 to step S820, which are introduced in detail as follows:

[0154] Step S810, perform constant training through the first control module and the second control module to obtain the second delay parameter. Among them, the constant training is used to determine the second delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer.

[0155] In the embodiments of the present application, when testing a PCIE-EP device composed of a third-party PCIE controller and a PCIE physical layer, high-speed parallel signal communication is carried out across chips between the test chip with the PCIE physical layer and the third-party PCIE controller. When the parallel signals are transmitted at high speed, due to path length, impedance difference, or process deviation, the transmission delays of different signal lines are inconsistent, which may cause bit misalignment of the transmitted signals on each communication link during sampling at the receiving end. By performing constant training through the first control module and the second control module, it is possible to detect the bit position offset of each signal at the receiving end and adjust the delay parameter of the transmitting end to ensure that the data bits of each path are aligned to the same position, thereby achieving data alignment and enabling the signals to be synchronously sampled.

[0156] Based on the above description of the data transmission direction for cross-chip communication, it can be seen that the data transmission can include two directions: from the third-party PCIE controller to the PCIE physical layer direction, that is, the TX (Transmit) direction; and from the PCIE physical layer to the third-party PCIE controller direction, that is, the RX (Receive) direction. Therefore, the second delay parameter in the embodiments of the present application includes the second delay parameter in the TX direction and the second delay parameter in the RX direction.

[0157] In some embodiments, the second delay parameter in the TX direction refers to the delay parameter of the signal received by the first control module, and the second delay parameter in the RX direction refers to the delay parameter of the signal sent by the first control module. On this basis, the constant training includes constant training in the TX direction and constant training in the RX direction, so as to obtain the second delay parameter in the TX direction and the second delay parameter in the RX direction.

[0158] Combined Figure 9 shown, Figure 9 is Figure 8 The flowchart of performing constant training in step S810 in the exemplary embodiment shown; it includes at least steps S910 to S950, which are introduced in detail as follows:

[0159] Step S910, configure the delay parameter for the first control module according to the preset number of delay bits.

[0160] It can be understood that based on the above description of the data transmission direction for cross-chip communication, the second delay parameter includes the second delay parameter in the TX direction and the second delay parameter in the RX direction. The second delay parameter in the TX direction refers to the delay parameter of the signal received by the first control module, and the second delay parameter in the RX direction refers to the delay parameter of the signal sent by the first control module. Therefore, when configuring the delay parameter for the first control module, it includes configuring the number of delay bits of the signal received by the first control module and configuring the number of delay bits of the signal sent by the first control module.

[0161] In some embodiments, configuring the delay parameter for the first control module according to the number of preset delay bits includes: when performing constant training in the TX direction, configuring the number of delay bits of the signal received by the first control module as the number of preset delay bits; when performing constant training in the RX direction, configuring the number of delay bits of the signal sent by the first control module as the number of preset delay bits.

[0162] Step S920, mutually transmitting constants through the first control module and the second control module after configuring the delay parameter to obtain a data reception result. The data reception result includes received data of each communication link under the number of preset delay bits.

[0163] In some embodiments, the constant mutually transmitted by the first control module and the second control module can be 16-bit data 0x0100, which is transmitted on each communication link in a serial manner.

[0164] In some embodiments, after obtaining the data reception result, it further includes: verifying the received data to obtain a data verification result. In some embodiments, 16-bit data is received each time for verification.

[0165] Step S930, determining reference data from the data reception result, and the flag bit in the reference data.

[0166] It should be understood that the reference data is used to represent the reference signal, and the flag bit in the reference data actually represents the delay situation of this path of signal at the receiving end. In some embodiments, the flag bit in the reference data is the position of the data "1" in the reference data.

[0167] Step S940, comparing all the received data in the data reception result with the flag bit in the reference data respectively to obtain the relative delay difference between all the received data and the flag bit in the reference data.

[0168] In the embodiments of the present application, the reference data is used to represent the reference signal, and the flag bit in the reference data actually represents the delay situation of this path of signal at the receiving end. By comparing the positions of each path of signal relative to the flag bit in the reference data, the delay difference of each path of signal relative to the reference signal can be determined.

[0169] In some embodiments, comparing all the received data in the data reception result with the flag bit in the reference data respectively means comparing the positions of the flag data in all the received data with the position of the flag data in the reference data.

[0170] In some embodiments, determining reference data and a flag bit in the reference data from the data reception result includes: using the data with the flag data at the last position in the data reception result as the reference data, and determining the position of the flag data in the reference data as the flag bit.

[0171] For example, the data reception result includes 0x0100, 0x0080, and 0x0040, and the flag data is "1". The corresponding binary data of these three data are respectively: 0000 0001 0000 0000, 0000 0000 1000 0000, 0000 0000 0100 0000. It can be seen that the data with the flag data "1" at the last position is 0x0040. Then, 0x0040 is determined as the reference data. Counting from left to right, the position of the flag data "1" in 0x0040 is the 8th bit. Then, the flag data "1" at the 8th bit is determined as the flag bit. Then, compare the flag data "1" in the other two data 0x0100 and 0x0080 with the flag bit in the reference data to obtain the relative delay difference. It can be seen that the relative delay difference between the flag data "1" in 0x0080 and the flag bit is 1 bit, and the relative delay difference between the flag data "1" in 0x0100 and the flag bit is 2 bits. Therefore, the data sender sending 0x0040 does not need to do delay and can set the second delay parameter to 0, while the data sender sending 0x0080 needs to delay 1 bit, and the data sender sending 0x0100 needs to delay 2 bits.

[0172] Step S950, determining the second delay parameter of each transmission signal in each communication link according to the relative delay difference.

[0173] In some embodiments, determining the second delay parameter of each transmission signal in each communication link according to the relative delay difference includes: determining the relative delay difference as the second delay parameter of each transmission signal in each communication link.

[0174] For example, there are only three communication links, and each communication link transmits 16-bit data 0x0100. The data received by the data receiver includes 0x0100, 0x0080, and 0x0040. Then, taking 0x0040 as the reference data, the relative delay difference between 0x0080 and 0x0040 is 1 bit, and the relative delay difference between 0x0100 and 0x0040 is 2 bits. Therefore, the delay bit number configuration of the data sender corresponding to 0x0040 is 0, the delay bit number configuration of the data sender corresponding to 0x0080 is 1, and the delay bit number configuration of the data sender corresponding to 0x0100 is 2.

[0175] Step S820: Configure the second delay parameter into the parameter register corresponding to each transmission signal in each communication link respectively.

[0176] In the embodiment of the present application, since the second delay parameter includes the second delay parameter in the TX direction and the second delay parameter in the RX direction, when configuring the second delay parameter, the second delay parameter in the TX direction is configured into the delay bit number register of each signal in the TX direction of the first control module; the second delay parameter in the RX direction is configured into the delay bit number register of each signal in the RX direction of the first control module.

[0177] For example, the following process can be used for constant training in the TX direction (from a third-party PCIE controller to the PCIE physical layer):

[0178] Step 1: The on-chip processor in the device under test configures both the first control module and the second control module into the constant training mode through the APB bus and the serial port respectively; the transmission constant is set to 16-bit data 0x0100 and is transmitted serially on each communication link.

[0179] Step 2: The on-chip processor in the device under test starts the transmission constant instruction of the second control module through the serial port and transmits infinitely.

[0180] Step 3: The on-chip processor in the device under test configures the delay bit number of the received signal of the first control module into a preset bit number through the APB bus.

[0181] Step 4: The on-chip processor in the device under test starts the constant reception verification instruction of the first control module through the APB bus, and receives 16-bit data each time it starts; and returns the reception completion status and the data reception result after the verification is completed.

[0182] Step 5: The on-chip processor in the device under test queries the reception completion status and the data reception result of the first control module through the APB bus.

[0183] Step 6: Determine the reference data and the flag bit in the reference data from the data reception result, and compare all the received data in the data reception result with the flag bit in the reference data respectively to obtain the relative delay difference between all the received data and the flag bit in the reference data.

[0184] Step 7: Determine the relative delay difference as the second delay parameter, and configure the second delay parameter required for each communication link into the delay bit register of each signal in the TX direction of the first control module respectively.

[0185] By adopting the constant training method in the TX direction of the embodiments of the present application, the relative delay difference of each path of signal relative to the reference signal can be determined, and then the delay parameters of the sending end can be dynamically adjusted according to the relative delay difference to ensure that all signals can be aligned to the same clock cycle at the receiving end, thereby solving the misalignment problem between multiple paths of signals and improving the reliability and stability of data transmission.

[0186] For example, the following process can be used for the constant training in the RX direction (from the PCIE physical layer to the third-party PCIE controller):

[0187] Step 1: The on-chip processor in the device under test configures both the first control module and the second control module into the constant training mode through the APB bus and the serial port respectively; the transmission constant is set to the 16-bit data 0x0100 and is transmitted serially on each communication link.

[0188] Step 2: The on-chip processor in the device under test starts the transmission constant instruction of the first control module through the APB bus and transmits it infinitely.

[0189] Step 3: The on-chip processor in the device under test configures the delay bit number of the received signal of the first control module to the preset bit number through the APB bus.

[0190] Step 4: The on-chip processor in the device under test starts the constant reception verification instruction of the second control module through the serial port, and receives 16-bit data each time it starts; and returns the reception completion status and the data reception result after the verification is completed.

[0191] Step 5: The on-chip processor in the device under test queries the reception completion status and the data reception result of the second control module through the serial port.

[0192] Step 6: Determine the reference data and the flag bit in the reference data from the data reception result, and compare all the received data in the data reception result with the flag bit in the reference data respectively to obtain the relative delay difference between all the received data and the flag bit in the reference data.

[0193] Step 7: Determine the relative delay difference as the second delay parameter, and configure the second delay parameter required for each communication link into the delay bit register of each path of signal of the first control module in the RX direction respectively.

[0194] By adopting the constant training method in the RX direction of the embodiments of the present application, the relative delay difference of each path of signal relative to the reference signal can be determined, and then the delay parameters of the sending end can be dynamically adjusted according to the relative delay difference to ensure that all signals can be aligned to the same clock cycle at the receiving end, thereby solving the misalignment problem between multiple paths of signals and improving the reliability and stability of data transmission.

[0195] Please continue to refer to Figure 10 , Figure 10 is Figure 5 a flowchart showing the reset control of the first data buffer and the second data buffer in step S530 of the illustrated embodiment in an exemplary embodiment; wherein, the test component further includes a third control module, and the third control module is connected to a third-party PCIE controller; at least including steps S1010 to S1030, which are introduced in detail as follows:

[0196] Step S1010, sending a rate signal to the component under test through the test component, and generating a second reset signal to perform reset control on the second data buffer. Wherein, the rate signal is used to trigger the third control module to switch the clock frequencies of the PCIE physical layer and the third-party PCIE controller, and the second reset signal is used to restore the second data buffer to its initial state.

[0197] It should be understood that during the link establishment process of PCIE from Gen1 to Gen5, the PIPE-PCLK clock needs to be dynamically switched. The main reason is that different generations of link rates require matching different clock frequencies, which can optimize the bandwidth and enable the high-frequency clock to be enabled only when needed, avoiding unnecessary signal attenuation and power consumption.

[0198] Therefore, when different rate signals are received, the clock frequency will be switched to the clock frequency matching the rate. During the clock switching process, due to the delay in data transmission between the third-party PCIE controller and the PCIE physical layer, the clocks are generated locally respectively, and the clock switching moments may not be synchronized, which may cause buffer overflows in the local data buffers of the third-party PCIE controller and the PCIE physical layer during clock switching, resulting in PCIE link establishment failure and inaccurate functional test results for the PCIE physical layer.

[0199] In the embodiment of the present application, by generating a reset signal to perform reset control on the data buffer when switching the clock frequency, it is possible to timely clear the invalid data received during the clock switching process, thereby avoiding buffer overflow and avoiding link establishment failure caused by buffer overflow, and thus improving the test accuracy.

[0200] In some embodiments, the clocks of the component under test and the test component are of the same source, which can ensure that the clocks of the PCIE physical layer, the first control module, the IO interface of the test component, the second control module, and the third-party PCIE controller are of the same source.

[0201] Exemplarily, the test component sends the rate signal from the test component to the component under test through the transmission method of the IO interface and the first control module. This rate signal can be used as the clock switching trigger signal of the third-party PCIE controller. That is, after sending this rate signal, the clock of the third-party PCIE controller is switched to the clock frequency corresponding to this rate signal; and a second reset signal for the second data buffer (i.e., the local receive FIFO) is generated to restore the second data buffer to its initial state.

[0202] In some embodiments, due to the large transmission delay of the rate signal, the transmission delay of the rate signal is denoted as DT.

[0203] Step S1020, when the component under test receives the rate signal sent by the test component, a first reset signal is generated to perform reset control on the first data buffer. The first reset signal is used to restore the first data buffer to its initial state.

[0204] In the embodiments of the present application, after the component under test receives the rate signal, this rate signal can be used as the clock switching trigger signal of the PCIE physical layer. That is, after receiving this rate signal, the clock of the PCIE physical layer is switched to the clock frequency corresponding to this rate signal; and a first reset signal for the first data buffer (i.e., the local receive FIFO) is generated to restore the first data buffer to its initial state.

[0205] In this way, when switching the clock frequencies of the third-party PCIE controller and the PCIE physical layer according to the rate signal, by generating the corresponding reset signals, the receive FIFOs local to the third-party PCIE controller and the PCIE physical layer can both be restored to their initial states, so that the invalid data received during the clock switching process can be cleared.

[0206] Step S1030, when the component under test and the test component complete the clock frequency switching, the first reset signal and the second reset signal are revoked.

[0207] It should be understood that in the embodiments of the present application, the clock switching completion signal is sent through the GPIO method. This is because GPIO transmits signals by directly controlling the level (high / low) of the hardware pins, without the need for complex operations such as data packet encapsulation, verification, and timing synchronization like protocols such as SPI, I2C, and UART. This eliminates the additional delay caused by protocol parsing, and is through the hardware direct connection method, so the transmission delay of GPIO can be ignored.

[0208] In some embodiments, after the clock frequency switching is completed in the PCIE physical layer of the component under test, the component under test generates a clock switching completion signal (i.e., the SWITCH_RATE_ACK signal), cancels the first reset signal, and sends the clock switching completion signal to the test component. After receiving the clock switching completion signal, the test component cancels the second reset signal; in this way, after the clock switching is completed in the test component and the component under test, the first reset signal and the second reset signal can be cancelled, so that the first data buffer and the second data buffer start receiving data again.

[0209] In some embodiments, after the clock frequency switching is completed in the component under test and the test component, it further includes: sending a clock gating signal from the component under test to the test component, so that the clock frequencies after the switching of the PCIE physical layer and the third-party PCIE controller can take effect simultaneously. Wherein, the clock gating signal is used to indicate the clock state of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is at the first preset level, the clock state is the effective state, and when the clock gating signal is at the second preset level, the clock state is the invalid state.

[0210] In the embodiments of the present application, the component under test and the test component send the clock gating signal (CLOCK_GATE signal) by means of GPIO.

[0211] For example, when it is necessary to switch the clock, the clock gating signal can be set to a low level first, so that the clocks at both ends of the PCIE physical layer and the third-party PCIE controller stop, ensuring that no new data is generated or received. At this time, the sending end stops sending, and the receiving end stops sampling due to the clock failure, avoiding invalid data from continuing to enter the data buffer. During the period when the clock gating signal is at a low level, the first reset signal and the second reset signal are generated to reset the FIFO buffer at the receiving end, and the read and write pointers of the receiving FIFO are reset to the initial position, so that the residual data received but not processed in the receiving FIFO is cleared. After the reset, the receiving FIFO is in the "empty" state, ensuring that only new data is received after the clock is switched. Then, after the clock frequency switching is completed, the clock gating signal is set to a high level, so that the new clocks after the switching at both ends can take effect simultaneously, the sending end starts to send data, the receiving end resamples based on the new clock frequency, and the receiving FIFO has been reset to empty and only receives valid data.

[0212] Combined Figure 11 shown Figure 11 is a timing diagram of clock switching management shown in an exemplary embodiment of the present application; it includes at least steps S1110 to S1190, which are introduced in detail as follows:

[0213] Step S1110: The first test component sends a rate signal to the component under test through the IO interface and simultaneously generates a second reset signal for the second data buffer. In some embodiments, the second reset signal may be the RFIFO_RST signal, and the second reset signal is used to restore the second data buffer to its initial state.

[0214] Step S1120: The first test component switches the clock frequency of the third-party PCIE controller according to the rate signal.

[0215] Step S1130: The component under test receives the rate signal and simultaneously generates a first reset signal for the first data buffer. In some embodiments, the first reset signal may be the RFIFO_RST signal, and the first reset signal is used to restore the first data buffer to its initial state.

[0216] Step S1140: The component under test performs a clock switch according to the rate signal and generates a clock switch completion signal after the clock frequency switch is completed. In some embodiments, the clock switch completion signal may be the SWITCH_RATE_ACK signal.

[0217] Step S1150: The component under test cancels the first reset signal.

[0218] Step S1160: The component under test sends the clock switch completion signal to the first test component through GPIO.

[0219] Step S1170: After receiving the clock switch completion signal, the first test component cancels the second reset signal.

[0220] Step S1180: The component under test sends the clock gating signal to the first test component through GPIO. In some embodiments, the clock gating signal may be the CLOCK_GATE signal, which is used to indicate the clock state of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is at the first preset level (high level), the clock state is the valid state, and when the clock gating signal is at the second preset level (low level), the clock state is the invalid state.

[0221] In the embodiments of the present application, when performing a clock switch, the data buffer is controlled by setting a reset signal, and the component under test generates a clock switch completion signal and sends it to the test component to cancel the first reset signal and the second reset signal, so as to be able to timely clean up the invalid data received by the data buffer during the clock switch process; after the component under test and the test component complete the clock frequency switch, the component under test can send a high-level clock gating signal to the first test component through GPIO, so that the newly switched clock frequencies of the third-party PCIE controller and the PCIE physical layer take effect simultaneously.

[0222] In some embodiments, in combination with Figure 12 as shown, Figure 12 is an application schematic diagram of clock switching management shown in an exemplary embodiment of the present application. Figure 12 Among them, the PHY_RATE at the PCIE-EP end is used to characterize the timing of the rate signal of the third-party PCIE controller in the first test component; the RXFIFO_RST at the PCIE-EP end is used to characterize the timing of the second reset signal of the second buffer; the PHY_RATE at the PCIE-PHY end is used to characterize the timing of the rate signal received by the PCIE physical layer in the component under test; the RXFIFO_RST at the PCIE-PHY end is used to characterize the timing of the first reset signal of the first buffer; the GPIO signal SWITCH_RATE_ACK is used to characterize the timing of the clock switching completion signal generated after the component under test completes the clock frequency switching; the GPIO signal CLOCK_GATE is used to characterize the timing of indicating the clock states of the PCIE physical layer and the third-party PCIE controller.

[0223] Figure 12 Among them, the T1 moment is used to characterize the moment when the first test component sends a rate signal, the T2 moment is used to characterize the moment when the component under test receives the rate signal, and the T3 moment is used to characterize the moment when the first reset signal and the second reset signal are revoked.

[0224] From Figure 12 it can be seen that at the T1 moment, the first test component switches from Gen1 to Gen2, and then sends a rate signal to the component under test. Due to the large transmission delay of the rate signal, the transmission delay of the rate signal is denoted as DT. At the same time, the first test component will switch the clock frequency of the third-party controller. During this DT period, the first data buffer in the component under test and the second data buffer in the test component will receive invalid data. At this time, the second data buffer is reset by generating a high-level second reset signal (i.e., RXFIFO_RST at the PCIE-EP end). At the T2 moment, the component under test receives the rate signal sent by the first test component. At this time, the rate is switched from Gen1 to Gen2, and a high-level first reset signal (i.e., RXFIFO_RST at the PCIE-PHY end) is generated to reset the first data buffer. At the same time, the component under test will switch the clock frequency of the PCIE physical layer. At the same time, at the T2 moment, after the component under test receives the rate signal, a low-level clock gating signal is generated in the component under test and sent to the first test component to invalidate the clock frequencies at both ends. After the T3 moment, that is, after the clock frequency signals at both ends are switched, the clock gating signal can be set to high level to make the new clocks after the switching at both ends take effect at the same time.

[0225] Combined Figure 13 as shown Figure 13 is a test device for the PCIE physical layer shown in an exemplary embodiment of the present application. This device is applied to a test system, which includes a device under test and a test component. The device under test includes a test chip with a PCIE physical layer, and the test component includes a third-party PCIE controller, which is used to perform functional tests on the PCIE physical layer. The device includes an acquisition module 1310, a configuration module 1320, and a control module 1330. The acquisition module 1310 is configured to acquire the test requirements of the device under test. The configuration module 1320 is configured to, when the test requirements include testing the transmission function of the device under test, configure the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmitted signals in each communication link at the receiving end. The control module 1330 is configured to, when the test requirements include testing the link establishment function of the device under test, perform reset control on the first data buffer corresponding to the device under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process. Among them, the first data buffer is used to receive the data sent by the test component, and the second data buffer is used to receive the data sent by the device under test.

[0226] It should be noted that the test device for the PCIE physical layer provided in the above embodiment and the test method for the PCIE physical layer provided in the above embodiment belong to the same concept. The specific ways in which each module and unit perform operations have been described in detail in the method embodiment, and will not be repeated here. In practical applications, the test device for the PCIE physical layer provided in the above embodiment can, according to needs, allocate the above functions to different functional modules, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above. This is not limited here.

[0227] An embodiment of the present application also provides an electronic device, including: one or more processors; a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the test method for the PCIE physical layer provided in each of the above embodiments.

[0228] Figure 14 shows a schematic structural diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application. It should be noted that Figure 14 the computer system 1400 of the electronic device shown is only an example and should not bring any limitations to the functions and usage scope of the embodiments of the present application.

[0229] As Figure 14As shown, computer system 1400 includes a Central Processing Unit (CPU) 1401, which can perform various appropriate actions and processes according to a program stored in a Read-Only Memory (ROM) 1402 or a program loaded from a storage section 1408 into a Random Access Memory (RAM) 1403, such as executing the methods described in the above embodiments. In the RAM 1403, various programs and data required for system operation are also stored. The CPU 1401, ROM 1402, and RAM 1403 are connected to each other via a bus 1404. An Input / Output (I / O) interface 1405 is also connected to the bus 1404.

[0230] The following components are connected to the I / O interface 1405: an input section 1406 including a keyboard, a mouse, etc.; an output section 1407 including, for example, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc.; a storage section 1408 including a hard disk, etc.; and a communication section 1409 including a model interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1409 performs communication processing via a model such as the Internet. A drive 1410 is also connected to the I / O interface 1405 as needed. A removable medium 1411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1410 as needed so that a computer program read from it can be installed into the storage section 1408 as needed.

[0231] Specifically, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a model via the communication section 1409, and / or installed from the removable medium 1411. When the computer program is executed by a Central Processing Unit (CPU) 1401, various functions defined in the system of the present application are executed.

[0232] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0233] Another aspect of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the test method of the PCIE physical layer as described above. The computer-readable storage medium can be included in the electronic device described in the above embodiments, or can exist separately and not be assembled into the electronic device.

[0234] The above content is only a preferred exemplary embodiment of the present application and is not used to limit the implementation of the present application. Those of ordinary skill in the art can easily make corresponding adaptations or modifications according to the main concept and spirit of the present application. Therefore, the protection scope of the present application should be subject to the protection scope required by the claims.

Claims

1. A method for testing a PCIE physical layer, characterized in that: Applied to a test system, the test system includes a component under test and a test component, the component under test includes a test piece provided with a PCIE physical layer, the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer; the method includes: Obtaining the test requirements of the component under test; In the case where the test requirement includes testing the transmission function of the component under test, delay parameter configuration is performed on each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by the receiving end; In the case where the test requirement includes testing the link establishment function of the component under test, a first data buffer corresponding to the component under test and a second data buffer corresponding to the test component are reset to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test; The component under test also includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller. The test component also includes a second control module, which is connected to the third-party PCIE controller; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter; the first delay parameter is used to adjust the delay time of the transmission signal in each communication link; the delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signal in each communication link by the receiving end includes: performing pseudo-random number training through the first control module and the second control module to obtain the first delay parameter; wherein the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; and configuring the first delay parameter to the parameter register corresponding to each transmission signal in each communication link.

2. The method according to claim 1, characterized in that The performing pseudo-random number training by the first control module and the second control module to obtain the first delay parameter includes: Performing initial delay parameter configuration on the first control module according to a preset delay parameter sequence; wherein the delay parameter sequence includes a plurality of preset delay times arranged in an arithmetic progression; The first control module and the second control module after configuring the delay parameters mutually send pseudo-random numbers, and verify the received pseudo-random numbers to obtain a data verification result sequence; wherein the data verification result sequence includes data verification results corresponding to each of the preset delay times, and each data verification result is arranged in the order of the preset delay times in the delay parameter sequence; Determine a first critical value and a second critical value corresponding to a valid sampling window according to the data verification result sequence; wherein the first critical value is used to represent the preset delay time configured by the first control module from a data verification success to a data verification failure in the data verification result in the data verification result sequence; and the second critical value is used to represent the preset delay time configured by the first control module from a data verification failure to a data verification success; A first delay parameter of each transmission signal in each communication link is determined according to the first critical value and the second critical value.

3. The method according to claim 1, characterized in that The delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer further includes a second delay parameter; the second delay parameter is used to adjust the number of delay bits of the transmission signal in each communication link; The delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of transmission signals in each communication link by the receiving end includes: Performing constant training through the first control module and the second control module to obtain the second delay parameter; wherein the constant training is used to determine the second delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; The second delay parameter is respectively configured in the parameter register corresponding to each transmission signal in each communication link.

4. The method according to claim 3, characterized in that The performing constant training by the first control module and the second control module to obtain the second delay parameter includes: Performing delay parameter configuration on the first control module according to a preset number of delay bits; The first control module and the second control module after configuring the delay parameter mutually send constants to obtain a data reception result; wherein the data reception result includes the reception data of each communication link under the preset number of delay bits; Determining reference data and a flag bit in the reference data from the data receiving result; Compare all received data in the data reception result with the flag bits in the reference data respectively to obtain the relative delay difference between all received data and the flag bits in the reference data; A second delay parameter of each transmission signal in each communication link is determined according to the relative delay difference.

5. The method according to claim 1, characterized in that The test component further includes a third control module, and the third control module is connected to the third-party PCIE controller; The resetting control of the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process includes: Sending a rate signal to the component under test through the test component, and generating a second reset signal to reset the second data buffer; wherein the rate signal is used to trigger the third control module to switch the clock frequency of the PCIE physical layer and the third-party PCIE controller, and the second reset signal is used to restore the second data buffer to an initial state; When the component under test receives the rate signal sent by the test component, a first reset signal is generated to reset the first data buffer; wherein the first reset signal is used to restore the first data buffer to an initial state; When the component under test and the testing component complete the clock frequency switching, the first reset signal and the second reset signal are cancelled.

6. The method according to claim 1, characterized in that The method further comprises: After the tested component and the test component complete the clock frequency switching, the tested component sends a clock gating signal to the test component, so that the switched clock frequencies of the PCIE physical layer and the third-party PCIE controller can take effect at the same time; Wherein, the clock gating signal is used to indicate the clock state of the PCIE physical layer and the third-party PCIE controller; when the clock gating signal is a first preset level, the clock state is a valid state, and when the clock gating signal is a second preset level, the clock state is an invalid state.

7. A PCIE physical layer test system applied to the method of claim 1, characterized in that: include: The component under test includes a test piece provided with a PCIE physical layer; Test components, including third-party PCIE controllers; The test component is used to obtain the test requirements of the component under test, and when the test requirements include the transmission function of the component under test, the delay parameter configuration is performed on each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signals in each communication link by the receiving end; And, in the case where the test requirement includes testing the link building function of the component under test, the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component are reset to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test.

8. The system according to claim 7, characterized in that The component under test further includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller; the test component includes a first test component, which includes the third-party PCIE controller and a second control module; The first control module and the second control module are used to configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, so as to achieve synchronous sampling of transmission signals in each communication link by the receiving end.

9. The system according to claim 8, characterized in that The first test component also includes a third control module, and the third control module is connected to the third-party PCIE controller; The third control module is used to perform reset control on the first data buffer corresponding to the component under test and the second data buffer corresponding to the test component to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process.

10. The system according to claim 7, characterized in that The test assembly also includes a second test assembly; The second test component is used to obtain the test requirements of the component under test, and call the corresponding test case according to the test requirements to perform functional testing on the component under test.

11. A PCIE physical layer testing device, characterized in that: Applied to a test system, the test system includes a component under test and a test component, the component under test includes a test piece provided with a PCIE physical layer, the test component includes a third-party PCIE controller, and the third-party PCIE controller is used to perform a functional test on the PCIE physical layer; the device includes: An acquisition module, configured to acquire the test requirements of the component under test; A configuration module, configured to, when the test requirement includes testing the transmission function of the component under test, configure delay parameters for each communication link between the third-party PCIE controller and the PCIE physical layer, so as to achieve synchronous sampling of transmission signals in each communication link by a receiving end; A control module, configured to, when the test requirement includes testing the link establishment function of the component under test, reset a first data buffer corresponding to the component under test and a second data buffer corresponding to the test component, so as to clear the data received by the first data buffer and the second data buffer during the clock frequency switching process; wherein the first data buffer is used to receive data sent by the test component, and the second data buffer is used to receive data sent by the component under test; The component under test also includes a first control module, which is arranged between the PCIE physical layer and the third-party PCIE controller. The test component also includes a second control module, which is connected to the third-party PCIE controller; the delay parameters of each communication link between the third-party PCIE controller and the PCIE physical layer include a first delay parameter; the first delay parameter is used to adjust the delay time of the transmission signal in each communication link; the delay parameter configuration of each communication link between the third-party PCIE controller and the PCIE physical layer to achieve synchronous sampling of the transmission signal in each communication link by the receiving end includes: performing pseudo-random number training through the first control module and the second control module to obtain the first delay parameter; wherein the pseudo-random number training is used to determine the first delay parameter of each communication link between the third-party PCIE controller and the PCIE physical layer; and configuring the first delay parameter to the parameter register corresponding to each transmission signal in each communication link.

12. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the PCIE physical layer testing method as described in any one of claims 1 to 6.

13. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is enabled to execute the PCIE physical layer testing method according to any one of claims 1 to 6.

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