A layout processing method for reducing parasitic RC through a cascode structure

Abstract

The present invention discloses a layout processing method for reducing parasitic RC through a cascode structure, which relates to the technical field of integrated circuit design. The present invention reduces parasitic RC through a cascode structure, improves the performance of high-frequency modules of the chip, extracts MOS transistor and metal wire parameters by parsing the layout file, generates a report using a parasitic parameter extraction tool, and maps and generates a distribution map to identify high-parasitic regions. Then, based on the distribution map, an optimizable MOS transistor combination is identified, a cascode structure diagram is designed to guide the re-layout and wiring of MOS transistors in the layout software, the source and drain ends are merged, the connection path is optimized, and then layout verification and circuit simulation are carried out. By comparing the parasitic parameters and operating frequencies before and after optimization, a simulation report is generated; it can accurately quantify the parasitic effect, optimize the layout to reduce parasitic parameters, effectively improve the operating frequency of the module, and meet the design requirements of high-performance chips.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and specifically to a layout processing method for reducing parasitic RC through a cascode structure. Background Art

[0002] With the continuous development of the electronics industry, the requirements for the frequency of chip design are getting higher and higher. In high-speed modules, the parasitic resistance and parasitic capacitance of devices and wires have a particularly significant impact on the module performance. These parasitic parameters will increase the load, resulting in a decrease in the operating frequency of the module, thereby affecting the overall performance of the IP module. Especially in some scenarios that are sensitive to high-frequency signals, the existence of unnecessary parasitic resistance and parasitic capacitance makes it difficult for the module to reach the required operating frequency, restricting the performance improvement of the chip. Summary of the Invention

[0003] The purpose of the present invention is to provide a layout processing method for reducing parasitic RC through a cascode structure, which optimizes the layout design through the cascode structure to reduce parasitic resistance and parasitic capacitance, thereby improving the operating frequency of the module.

[0004] The purpose of the present invention can be achieved by the following technical solutions:

[0005] The present application provides a layout processing method for reducing parasitic RC through a cascode structure, including the following steps:

[0006] Parse the original layout file, extract the parameters of MOS transistors, and store them in the layout parameter list;

[0007] Use a parasitic parameter extraction tool, input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS transistor and metal line segment, and then generate a parasitic parameter report;

[0008] Among them, according to the parasitic parameter report, map the parasitic parameter values to the layout to generate a parasitic parameter distribution map. In the distribution map, mark the high-parasitic regions with different colors or marks;

[0009] According to the parasitic parameter distribution map, identify the MOS transistor combinations optimized through the cascode structure, determine the merging method of the source and drain ends of the MOS transistors, and generate a design diagram of the cascode structure;

[0010] In the layout design software, according to the cascode structure design diagram, re-layout and re-wire the MOS transistors, and merge and optimize the connection paths of the source and drain ends between the same-group devices;

[0011] According to the optimized connection route, perform layout verification and circuit simulation, and compare the changes in parasitic parameters before and after the application of the cascode structure.

[0012] Furthermore, parse the original layout file, extract the parameters of the MOS transistors, and store them in the layout parameter list, specifically including:

[0013] Read the original layout file to obtain the graphic element information in the layout, including the parameters of MOS transistors, metal wires, and polysilicon graphic elements;

[0014] Based on the graphic element information of the MOS transistors, determine the types of the MOS transistors, and determine the position coordinates of the source, drain, gate, and substrate of the MOS transistors, and determine the layer of the metal wire, and determine the starting and ending coordinates of the metal wire, as well as the width and length parameters of the metal wire;

[0015] Based on the graphic element information of the polysilicon, determine the type of the polysilicon, and determine the position coordinates, width, and length parameters of the polysilicon. Then, based on the position coordinates of the source, drain, gate, and substrate of the MOS transistors, and the position coordinates of the metal wire and polysilicon, determine the connection relationship between the MOS transistors and the metal wire and polysilicon, and store the connection relationship parameters in the layout parameter list;

[0016] Based on the starting and ending coordinates of the metal wire, as well as the width and length parameters of the metal wire, extract the routing information in the layout, and store the routing information parameters in the layout parameter list. Store the extracted MOS transistor layout positions, connection relationships, and routing information in the layout parameter list according to the preset data format.

[0017] Furthermore, use the parasitic parameter extraction tool, input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS transistor and metal segment, and then generate a parasitic parameter report, specifically including:

[0018] Based on the input layout parameter list, obtain the geometric parameter information of each MOS transistor and metal segment;

[0019] Based on the geometric parameter information, use the pre-established parasitic resistance and parasitic capacitance calculation models to calculate the parasitic resistance value and parasitic capacitance value of each MOS transistor; then use the pre-established parasitic resistance and parasitic capacitance calculation models to calculate its parasitic resistance value and parasitic capacitance value;

[0020] Associate the parasitic resistance value and parasitic capacitance value of each MOS transistor with its corresponding layout parameter information to obtain the parasitic parameter information of each MOS transistor. Then, associate the parasitic resistance value and parasitic capacitance value of each metal segment with its corresponding layout parameter information to obtain the parasitic parameter information of each metal segment;

[0021] Generate a data table containing the parasitic parameters of all MOS transistors and metal line segments based on the parasitic parameter information of each MOS transistor and each metal line segment, and generate a final parasitic parameter report file according to the preset report template and format requirements.

[0022] Furthermore, according to the parasitic parameter report, map the parasitic parameter values onto the layout to generate a parasitic parameter distribution map. In the distribution map, mark the high parasitic regions with different colors or markings, specifically including:

[0023] Obtain the parasitic parameter report, extract the parasitic parameter values and the corresponding layout position information in the report, and determine different colors or marking methods according to the magnitude of the parasitic parameter values to represent different degrees of parasitic parameters in the layout.

[0024] Use layout design software to load the layout file to be analyzed, overlay the parasitic parameter values at the corresponding positions according to the layout position information in the parasitic parameter report, and map the parasitic parameter values into different colors or markings through a data visualization tool to generate a parasitic parameter distribution map on the layout.

[0025] Judge whether the parasitic parameter value exceeds a preset threshold. When it exceeds, mark the region as a high parasitic region and highlight it.

[0026] Traverse all regions on the layout, generate a complete parasitic parameter distribution map based on the parasitic parameter values, and obtain a visualization result including the marking of high parasitic regions.

[0027] Furthermore, according to the parasitic parameter distribution map, identify the MOS transistor combinations optimized by the cascode structure, determine the merging method of the source and drain terminals of the MOS transistors, and generate a design diagram of the cascode structure, specifically including:

[0028] Obtain the parasitic parameter distribution map of the MOS transistors, group the MOS transistors using a clustering algorithm according to the parasitic parameter characteristics of the MOS transistors in the distribution map, and obtain MOS transistor combinations with similar parasitic parameters.

[0029] By analyzing the distribution characteristics of the parasitic parameters of each MOS transistor combination, judge whether it is suitable for optimization using the cascode structure. When it is suitable, mark the MOS transistor combination as an optimizable combination.

[0030] Then, for each optimizable MOS transistor combination, determine whether to merge the source and drain terminals of the MOS transistors in series or in parallel according to the positional relationship and parasitic parameter distribution of the MOS transistors therein.

[0031] According to the determined MOS transistor merging method, generate the corresponding cascode structure design diagram, and clearly mark the connection relationship of the merged MOS transistors in the design diagram, including the connections between gate, source, and drain.

[0032] Furthermore, in the layout design software, according to the cascode structure design diagram, re-layout and route the MOS transistors, and merge and optimize the connection paths of the source and drain ends between the same group of devices. Specifically, it includes:

[0033] Obtain the layout information of the position, direction, and connection relationship of the MOS transistors according to the given cascode circuit structure diagram; judge whether the source and drain electrodes of the same group of MOS transistors meet the merging conditions, and if they do, merge them into one node;

[0034] Through the graphic recognition algorithm, determine the positions of the source and drain electrodes of the merged MOS transistors, and update the layout information. According to the updated layout information, adopt the minimum spanning tree algorithm to optimize the wiring scheme of the metal interconnect lines;

[0035] Conduct a design rule check on the optimized wiring scheme to judge whether it meets the process requirements. If it does not meet, return for re-routing;

[0036] According to the wiring scheme passed by the DRC, generate a new layout file, and update the device parameters and interconnection information; import the new layout file into the layout design software, and layout and route the MOS transistors and metal interconnect lines to complete the optimized design of the cascode circuit.

[0037] Furthermore, after merging the source and drain ends between the same group of devices, it also includes: according to the preset device grouping information, determine the same group of devices that need to merge the source and drain electrodes, and then obtain the layout positions and pin information of the same group of devices, and judge the position relationship between the source and drain ports; when the source and drain ports are adjacent in position, directly merge them in the layout to form a shared port structure; when the source and drain ports are not adjacent in position, introduce an additional interconnection structure in the layout;

[0038] According to the signal integrity and parasitic parameter characteristics of the merged circuit, optimize the wiring topology of the interconnection structure; adopt the method of parasitic parameter extraction and post-simulation verification to evaluate the optimized wiring topology to ensure that it meets the design index requirements; after layout and routing, perform layout extraction on the device unit after merging the source and drain electrodes.

[0039] Furthermore, perform layout verification, specifically including:

[0040] According to the optimized connection route, obtain the preset electrical rules and physical rules, and perform rule checks on the optimized layout. When electrical rule errors are found during the check, correct the circuit design according to the electrical rules to obtain a corrected circuit design scheme;

[0041] When physical rule errors are found during the check, correct the physical design according to the physical rules to obtain a corrected physical design scheme, and fuse the corrected circuit design scheme and the physical design scheme to obtain a corrected layout design scheme;

[0042] According to the corrected layout design scheme, use the simulated annealing algorithm to optimize the connection route again to obtain an optimized connection route again;

[0043] According to the optimized connection route again, re-verify the corrected layout design scheme to determine whether there are still electrical rule errors or physical rule errors. When the re-verification passes, determine the final layout design scheme; when the re-verification fails, continue with rule checks and corrections until the verification passes.

[0044] Furthermore, compare the changes in parasitic parameters before and after the application of the cascode structure, specifically including:

[0045] Obtain the original circuit diagram of the circuit to be analyzed, determine the target module therein, and perform circuit simulation analysis on the target module;

[0046] In the circuit simulation environment, build the simulation circuit diagram of the original circuit, set the circuit parameters, and perform simulation to obtain the performance index data of the parasitic parameters and operating frequency when the cascode structure is not applied;

[0047] Use the cascode structure to perform circuit optimization design on the target module of the original circuit to obtain an optimized circuit diagram;

[0048] By building the optimized circuit simulation diagram, setting the same circuit parameters as the original circuit, and performing simulation, obtain the performance index data of the parasitic parameters and operating frequency after the application of the cascode structure;

[0049] Then compare and analyze the changes in parasitic parameters before and after the application of the cascode structure, and visually display the influence of the cascode structure on the parasitic parameters through data curves and values; compare and analyze the changes in operating frequency before and after the application of the cascode structure, and visually display the influence of the cascode structure on the operating frequency through data curves and values;

[0050] According to the comparative analysis results of the parasitic parameters and operating frequency, judge the overall influence of the cascode structure on the performance of the circuit module, and generate a complete circuit simulation analysis report.

[0051] It further includes: according to the simulation report, when it is found that the effect of reducing parasitic RC cannot meet the expected performance requirements, the design and layout of the cascode structure are iteratively optimized until the performance requirements are met.

[0052] The beneficial effects of the present invention are as follows:

[0053] By parsing the original layout file and using a parasitic parameter extraction tool, this method can accurately extract the parameters of MOS transistors and metal line segments, and generate a detailed parasitic parameter report, solving the problem of difficult accurate identification and quantification of parasitic effects in complex layouts, enabling designers to visually identify high-parasitic regions and providing accurate data support for subsequent optimizations; furthermore, by reading the layout file, extracting graphic element information, calculating parasitic parameters and generating a distribution map, the parasitic resistance and parasitic capacitance values of each MOS transistor and metal line segment can be clearly seen, thus locating the region with the greatest impact on the module performance;

[0054] Based on the parasitic parameter distribution map, by optimizing the layout design with the cascode structure, the parasitic resistance and parasitic capacitance are significantly reduced. Then, by identifying suitable MOS transistor combinations, determining the merging method of the source and drain ends, and generating a cascode structure design diagram, designers can perform precise re-layout and wiring in the layout design software, solving the problem of difficult control of parasitic effects in traditional layout design. By merging the source and drain ends of the same group of devices, the use of metal wires is reduced, the connection path is optimized, thereby effectively reducing the parasitic effect and improving the operating frequency and overall performance of the module;

[0055] Through layout verification and circuit simulation, this method ensures that the optimized layout design not only complies with electrical and physical rules, but also actually improves the performance of the module. By comparing the changes in parasitic parameters and operating frequency before and after the application of the cascode structure and generating a detailed simulation report, designers can visually evaluate the optimization effect. When it is found that the effect of reducing parasitic RC cannot meet the expected performance requirements, iterative optimization can be carried out until the performance requirements are met; solving the problem of uncertain effects after optimization design, and ensuring that the final layout design scheme meets the expected goals in terms of performance through repeated verification and correction, providing a reliable guarantee for high-performance chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] For better understanding and implementation, the technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0057] Figure 1 It is a schematic flow diagram of a layout processing method for reducing parasitic RC through a cascode structure provided by the present application;

[0058] Figure 2 A schematic flow chart for extracting MOS transistor parameters by a layout processing method for reducing parasitic RC through a cascode structure provided for this application;

[0059] Figure 3 A schematic flow chart for generating a parasitic parameter report by a layout processing method for reducing parasitic RC through a cascode structure provided for this application. Detailed implementation manners

[0060] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the exemplary embodiments will be described in detail herein, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are merely examples of methods and systems consistent with some aspects of this application as detailed in the appended claims.

[0061] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0062] The following will, in conjunction with the accompanying drawings and preferred embodiments, elaborate in detail on the specific implementation manners, features, and effects of the present invention.

[0063] Please refer to Figures 1 - 3 , this embodiment provides a layout processing method for reducing parasitic RC through a cascode structure, including the following steps:

[0064] S1. Analyze the original layout file, extract parameters such as the layout position, connection relationship, and routing information of the MOS transistors, and store them in the layout parameter list;

[0065] Further, analyzing the original layout file, extracting parameters such as the layout position, connection relationship, and routing information of the MOS transistors, and storing them in the layout parameter list specifically includes:

[0066] S11. Read the original layout file, obtain the graphic element information in the layout, including parameters such as the position coordinates and shape dimensions of graphic elements such as MOS transistors, metal wires, and polysilicon.

[0067] S12. Determine the type of the MOS transistor (NMOS or PMOS) based on the graphic element information of the MOS transistor, and determine the position coordinates of the source, drain, gate, and substrate of the MOS transistor. Also, determine the layer of the metal wire (Metal1, Metal2, etc.), and determine the start and end coordinates of the metal wire, as well as parameters such as the width and length of the metal wire;

[0068] S13. Determine the type of the polysilicon (n-type polysilicon or p-type polysilicon) based on the graphic element information of the polysilicon, and determine parameters such as the position coordinates, width, and length of the polysilicon. Then, based on the position coordinates of the source, drain, gate, and substrate of the MOS transistor, as well as the position coordinates of the metal wire and the polysilicon, determine the connection relationship between the MOS transistor and the metal wire and the polysilicon, and store the connection relationship parameters in the layout parameter list;

[0069] S14. Extract the routing information in the layout based on the start and end coordinates of the metal wire, as well as parameters such as the width and length of the metal wire, and store the routing information parameters in the layout parameter list. Store the parameters such as the MOS transistor layout position, connection relationship, and routing information obtained in a preset data format in the layout parameter list for subsequent layout analysis and optimization.

[0070] Specifically, by analyzing the original layout file in detail, the parameters of the MOS transistor, metal wire, and polysilicon and their connection relationships are extracted and stored, providing an accurate data basis for subsequent layout analysis and optimization. This solves the problem of unclear component positions, types, and connection information during the layout optimization process, enabling designers to accurately identify and locate areas with high parasitic parameters, and thus optimize them targeted to reduce parasitic effects and improve the operating frequency and overall performance of the module.

[0071] S2. Use a parasitic parameter extraction tool, input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS transistor and metal segment, and then generate a parasitic parameter report containing the parasitic resistance and parasitic capacitance values of each MOS transistor and metal segment;

[0072] Among them, based on the parasitic parameter report, use a layout design software or data visualization tool to map the parasitic parameter values onto the layout to generate a parasitic parameter distribution map. In the distribution map, mark the high-parasitic regions with different colors or markings to visually identify the key regions that need to be optimized. This step helps us determine the regions that have the greatest impact on the module's operating frequency, thereby identifying the key regions that need to be optimized.

[0073] Furthermore, use a parasitic parameter extraction tool, input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS transistor and metal segment, and then generate a parasitic parameter report, specifically including:

[0074] S21. Obtain the geometric parameter information of each MOS transistor and metal wire segment according to the input layout parameter list, including length, width, thickness, etc.;

[0075] S22. According to its geometric parameter information, use the pre-established parasitic resistance and parasitic capacitance calculation models to calculate the parasitic resistance value and parasitic capacitance value of each MOS transistor; then use the pre-established parasitic resistance and parasitic capacitance calculation models to calculate its parasitic resistance value and parasitic capacitance value;

[0076] S23. Associate the parasitic resistance value and parasitic capacitance value of each MOS transistor with its corresponding layout parameter information to obtain the parasitic parameter information of each MOS transistor, and then associate the parasitic resistance value and parasitic capacitance value of each metal wire segment with its corresponding layout parameter information to obtain the parasitic parameter information of each metal wire segment;

[0077] S24. Generate a data table containing the parasitic parameters of all MOS transistors and metal wire segments according to the parasitic parameter information of each MOS transistor and the parasitic parameter information of each metal wire segment, and generate a final parasitic parameter report file according to the preset report template and format requirements.

[0078] Specifically, by accurately calculating and visualizing the parasitic parameters, this method enables designers to intuitively identify and locate high-parasitic regions in the layout, thereby optimizing them targeted, effectively reducing the parasitic effects, and significantly improving the operating frequency and performance of the module.

[0079] Furthermore, according to the parasitic parameter report, use layout design software or data visualization tools to map the parasitic parameter values onto the layout to generate a parasitic parameter distribution map. In the distribution map, mark the high-parasitic regions with different colors or marks, specifically including:

[0080] Obtain the parasitic parameter report, extract the parasitic parameter values and the corresponding layout position information in the report, and determine different color or marking methods according to the magnitude of the parasitic parameter values for representing different degrees of parasitic parameters in the layout;

[0081] Use layout design software to load the layout file to be analyzed, and according to the layout position information in the parasitic parameter report, superimpose the parasitic parameter values at the corresponding positions. Through data visualization tools, map the parasitic parameter values into different colors or marks to generate a parasitic parameter distribution map on the layout;

[0082] Judge whether the parasitic parameter value exceeds a preset threshold. If it exceeds, mark this region as a high-parasitic region and highlight it;

[0083] Traverse all regions on the layout, generate a complete parasitic parameter distribution map based on the parasitic parameter values, and obtain a visualization result with high parasitic regions marked.

[0084] Specifically, by mapping the parasitic parameter values onto the layout and generating a parasitic parameter distribution map, the intuitive visualization of the parasitic parameters in the layout is achieved, solving the problem of difficult intuitive identification and positioning of high parasitic regions in complex layouts, enabling designers to quickly and accurately identify the regions that have the greatest impact on the module performance. Through the highlighting display with different colors or marks, designers can optimize targeted, thereby effectively reducing the parasitic effect, improving the operating frequency and overall performance of the module, and ensuring that the chip design meets the high-performance requirements.

[0085] S3. According to the parasitic parameter distribution map, identify the MOS transistor combinations optimized by the cascode structure, design an algorithm to determine the merging method of the source and drain ends of the MOS transistors, generate a design diagram of the cascode structure, and clearly mark the connection relationship of the merged MOS transistors. This step is the core of achieving parasitic parameter reduction. Through a reasonable design diagram of the cascode structure, the parasitic effect can be significantly reduced;

[0086] Furthermore, according to the parasitic parameter distribution map, identify the MOS transistor combinations optimized by the cascode structure, design an algorithm to determine the merging method of the source and drain ends of the MOS transistors, generate a design diagram of the cascode structure, and clearly mark the connection relationship of the merged MOS transistors, specifically including:

[0087] Obtain the parasitic parameter distribution map of the MOS transistors. According to the parasitic parameter characteristics of the MOS transistors in the distribution map, use a clustering algorithm to group the MOS transistors to obtain MOS transistor combinations with similar parasitic parameters;

[0088] By analyzing the distribution characteristics of the parasitic parameters of each MOS transistor combination, judge whether it is suitable for optimization by the cascode structure. If it is suitable, mark the MOS transistor combination as an optimizable combination;

[0089] Then, for each optimizable MOS transistor combination, determine whether to merge the source and drain ends of the MOS transistors in series or in parallel according to the positional relationship and parasitic parameter distribution of the MOS transistors in it;

[0090] According to the determined MOS transistor merging method, generate the corresponding design diagram of the cascode structure, and clearly mark the connection relationship of the merged MOS transistors in the design diagram, including the connections between gate, source, and drain.

[0091] Specifically, by analyzing the parasitic parameter distribution map and using a clustering algorithm to identify combinations of MOS transistors with similar parasitic parameters, and then determining whether they are suitable for optimization using a cascode structure. For suitable combinations, determine the merging method of the source and drain terminals of the MOS transistors, and generate a detailed cascode structure design diagram, which solves the problem of accurately screening out MOS transistors that can be optimized by a specific structure to reduce parasitic effects from numerous MOS transistors, achieving the effect of significantly reducing parasitic parameters and improving module performance, and is a key method for realizing the core step of reducing parasitic parameters.

[0092] S4. In the layout design software, according to the cascode structure design diagram, re-layout and wire the MOS transistors, merge the source and drain terminals between devices in the same group, reduce the use of metal wires, and at the same time, optimize the connection path after merging to ensure the efficiency and reliability of signal transmission; this step converts the design diagram into an actual layout, preparing for subsequent optimization and verification.

[0093] Furthermore, in the layout design software, according to the cascode structure design diagram, re-layout and wire the MOS transistors, merge the source and drain terminals between devices in the same group, reduce the use of metal wires, specifically including:

[0094] Obtain layout information such as the position, orientation, and connection relationship of the MOS transistors according to the given cascode circuit structure diagram; judge whether the source and drain electrodes of the MOS transistors in the same group meet the merging conditions, and if so, merge them into one node;

[0095] Through a graphic recognition algorithm, determine the positions of the source and drain electrodes of the merged MOS transistors, update the layout information, and according to the updated layout information, use the minimum spanning tree algorithm to optimize the wiring scheme of the metal interconnects, reducing the line length and crossings;

[0096] Conduct a design rule check (DRC) on the optimized wiring scheme to judge whether it meets the process requirements, and if not, return for re-wiring;

[0097] Generate a new layout file according to the wiring scheme that passes the DRC check, and update the device parameters and interconnect information; import the new layout file into the layout design software, layout and wire the MOS transistors and metal interconnects to complete the optimized design of the cascode circuit.

[0098] Specifically, by precisely re - arranging and routing MOS transistors in the layout design software according to the cascode structure design diagram, and by means of graphic recognition algorithms and minimum spanning tree algorithms, etc., the problem of parasitic parameters caused by excessive metal wires in traditional layouts is solved; specifically, by merging the source and drain terminals between devices in the same group, the use of metal wires is reduced, and the connection path is optimized to reduce signal transmission delay and distortion. This process not only reduces parasitic effects but also ensures the efficiency and reliability of signal transmission, ultimately transforming the theoretical design into a practical and feasible layout, effectively improving the performance and stability of the circuit.

[0099] Furthermore, after merging the source and drain terminals between devices in the same group, it also includes: optimizing the connection path after merging;

[0100] Among them, according to the preset device grouping information, determine the devices in the same group that need to merge the source and drain, then obtain the layout positions and pin information of the devices in the same group, and judge the positional relationship between the source and drain ports; when the source and drain ports are adjacent, directly merge them in the layout to form a shared port structure; when the source and drain ports are not adjacent, introduce an additional interconnection structure in the layout to achieve their electrical connection;

[0101] According to the signal integrity and parasitic parameter characteristics of the circuit after merging, optimize the wiring topology of the interconnection structure; use the method of parasitic parameter extraction and post - simulation verification to evaluate the optimized wiring topology to ensure that it meets the design index requirements; after layout and routing, perform layout extraction on the device unit after merging the source and drain for subsequent chip - level integrated design.

[0102] Specifically, by optimizing the connection path after merging, this method effectively solves the influence of the positional relationship between the source and drain on the circuit performance. When the port positions are adjacent, directly merge them to form a shared port structure, simplifying the layout and reducing parasitic effects; when the port positions are not adjacent, introduce an additional interconnection structure to ensure the integrity of the electrical connection. Furthermore, by optimizing the wiring topology of the interconnection structure and using parasitic parameter extraction and post - simulation verification, it is ensured that the optimized wiring topology meets the design index requirements, thereby improving signal integrity and circuit performance.

[0103] S5. According to the optimized connection route, perform layout verification again to check for electrical rule errors or physical rule errors. Through circuit simulation, compare the changes in parasitic parameters before and after the application of the cascode structure, as well as the impact on performance indicators such as the operating frequency of the module; and generate a simulation report, including key indicators such as the percentage reduction in parasitic parameters and the improvement in the operating frequency of the module. This step is an important link to verify the optimization effect and ensure that our design has achieved the expected performance improvement.

[0104] Further, according to the optimized connection route, perform layout verification again to check for electrical rule errors or physical rule errors, specifically including:

[0105] According to the optimized connection route, obtain the preset electrical rules and physical rules, and perform rule checking on the optimized layout. When electrical rule errors are found during the check, correct the circuit design according to the electrical rules to obtain a corrected circuit design scheme;

[0106] When physical rule errors are found during the check, correct the physical design according to the physical rules to obtain a corrected physical design scheme, and fuse the corrected circuit design scheme and the physical design scheme to obtain a corrected layout design scheme;

[0107] According to the corrected layout design scheme, use the simulated annealing algorithm to optimize the connection route again to obtain an optimized connection route again;

[0108] According to the optimized connection route again, perform verification on the corrected layout design scheme again to determine whether there are still electrical rule errors or physical rule errors. When the verification passes again, determine the final layout design scheme; when the verification fails again, continue with rule checking and correction until the verification passes.

[0109] Specifically, through layout verification and circuit simulation, it is ensured that the optimized connection route not only complies with electrical and physical rules, but also actually improves the performance of the module; effectively identifies and corrects potential design errors, further optimizes the connection route through the simulated annealing algorithm, and finally determines a layout design scheme that has no rule errors and meets the performance improvement requirements, thus ensuring the reliability and efficiency of the chip design.

[0110] Further, through circuit simulation, compare the changes in parasitic parameters before and after the application of the cascode structure, as well as the impact on performance indicators such as the operating frequency of the module; and generate a simulation report, specifically including:

[0111] Obtain the original circuit diagram of the circuit to be analyzed, determine the target module therein, and perform circuit simulation analysis on the target module;

[0112] In a circuit simulation environment, build a simulation circuit diagram of the original circuit, set the circuit parameters, and perform simulations to obtain performance index data such as parasitic parameters and operating frequencies when the cascode structure is not applied;

[0113] Use the cascode structure to perform circuit optimization design on the target module of the original circuit to obtain the optimized circuit diagram;

[0114] By building the optimized circuit simulation diagram, setting the same circuit parameters as the original circuit, and performing simulations, obtain performance index data such as parasitic parameters and operating frequencies after applying the cascode structure;

[0115] Then, compare and analyze the changes in parasitic parameters before and after applying the cascode structure, and visually display the impact of the cascode structure on parasitic parameters through data curves and values; compare and analyze the changes in operating frequencies before and after applying the cascode structure, and visually display the impact of the cascode structure on operating frequencies through data curves and values;

[0116] Based on the comparative analysis results of parasitic parameters and operating frequencies, judge the overall impact of the cascode structure on the performance of the circuit module, and generate a complete circuit simulation analysis report.

[0117] Specifically, by comparing the circuit simulation results before and after applying the cascode structure, this method visually displays the changes in parasitic parameters and operating frequencies, thereby quantitatively evaluating the improvement effect of the cascode structure on circuit performance. The generated simulation report provides a strong basis for design decisions, ensuring the effectiveness and reliability of the optimization design. While reducing parasitic effects, the circuit module significantly increases the operating frequency, meeting the requirements of high-performance chip design.

[0118] S6. According to the simulation report, when it is found that the reduction effect of parasitic RC does not meet the expected performance requirements, iterate and optimize the design and layout of the cascode structure until the performance requirements are met. This step ensures that our optimization process is continuous and effective until the best performance is achieved.

[0119] The above is only a preferred embodiment of the present invention, and it is not intended to limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content within the scope of the technical solution of the present invention to make equivalent embodiments with equivalent changes, but as long as the content of the technical solution of the present invention is not departed from, any brief modifications, equivalent changes, and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A layout processing method for reducing parasitic RC through a cascode structure, characterized in that: It includes the following steps: Parse the original layout file, extract the parameters of MOS transistors, and store them in the layout parameter list; Use the parasitic parameter extraction tool, input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS transistor and metal line segment, and then generate a parasitic parameter report; Among them, according to the parasitic parameter report, map the parasitic parameter values to the layout to generate a parasitic parameter distribution map. In the distribution map, mark the high parasitic regions with different colors or markings; According to the parasitic parameter distribution map, identify the MOS transistor combinations optimized through the cascode structure, determine the merging method of the source and drain terminals of the MOS transistors, and generate a design diagram of the cascode structure; In the layout design software, according to the cascode structure design diagram, re-layout and route the MOS transistors, and merge and optimize the connection paths between the source and drain terminals of the same group of devices; According to the optimized connection route, perform layout verification and circuit simulation, and compare the changes in parasitic parameters before and after the application of the cascode structure; Among them, according to the parasitic parameter distribution map, identify the MOS transistor combinations optimized through the cascode structure, determine the merging method of the source and drain terminals of the MOS transistors, and generate a design diagram of the cascode structure, specifically including: Obtain the parasitic parameter distribution map of the MOS transistors. According to the parasitic parameter characteristics of the MOS transistors in the distribution map, use the clustering algorithm to group the MOS transistors to obtain MOS transistor combinations with similar parasitic parameters; By analyzing the distribution characteristics of the parasitic parameters of each MOS transistor combination, judge whether it is suitable to be optimized by the cascode structure. If it is suitable, mark the MOS transistor combination as an optimizable combination; Then for each optimizable MOS transistor combination, according to the positional relationship and parasitic parameter distribution of the MOS transistors in it, determine whether to use a series or parallel method to merge the source and drain terminals of the MOS transistors; According to the determined MOS transistor merging method, generate the corresponding cascode structure design diagram, and clearly mark the connection relationship of the merged MOS transistors in the design diagram, including the connections between the gate, source, and drain; 2. The layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: Parse the original layout file, extract the parameters of MOS transistors, and store them in the layout parameter list, specifically including: Read the original layout file, obtain the graphic element information in the layout, including the parameters of MOS transistors, metal lines, and polysilicon graphic elements; According to the graphic element information of the MOS transistors, judge the type of the MOS transistors, determine the position coordinates of the source, drain, gate, and substrate of the MOS transistors, judge the layer of the metal lines, and determine the starting and ending coordinates of the metal lines, as well as the width and length parameters of the metal lines; Based on the graphic element information of polysilicon, determine the type of polysilicon, and determine the position coordinates, width, and length parameters of the polysilicon. Then, based on the position coordinates of the source, drain, gate, and substrate of the MOS transistor, as well as the position coordinates of the metal line and polysilicon, determine the connection relationship between the MOS transistor and the metal line and polysilicon, and store the connection relationship parameters in the layout parameter list; Based on the start and end coordinates of the metal line, as well as the width and length parameters of the metal line, extract the routing information in the layout, and store the routing information parameters in the layout parameter list. Store the extracted MOS transistor layout positions, connection relationships, and routing information in the layout parameter list according to the preset data format.

3. A layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: Use a parasitic parameter extraction tool, input the layout parameter list, calculate the parasitic resistance and parasitic capacitance of each MOS transistor and metal segment, and then generate a parasitic parameter report, specifically including: Based on the input layout parameter list, obtain the geometric parameter information of each MOS transistor and metal segment; Based on the geometric parameter information, use the pre-established parasitic resistance and parasitic capacitance calculation models to calculate the parasitic resistance value and parasitic capacitance value of each MOS transistor; then use the pre-established parasitic resistance and parasitic capacitance calculation models to calculate its parasitic resistance value and parasitic capacitance value; Associate the parasitic resistance value and parasitic capacitance value of each MOS transistor with its corresponding layout parameter information to obtain the parasitic parameter information of each MOS transistor. Then, associate the parasitic resistance value and parasitic capacitance value of each metal segment with its corresponding layout parameter information to obtain the parasitic parameter information of each metal segment; Based on the parasitic parameter information of each MOS transistor and the parasitic parameter information of each metal segment, generate a data table containing the parasitic parameters of all MOS transistors and metal segments, and generate the final parasitic parameter report file according to the preset report template and format requirements.

4. A layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: Based on the parasitic parameter report, map the parasitic parameter values onto the layout to generate a parasitic parameter distribution map. In the distribution map, mark the high parasitic regions with different colors or markings, specifically including: Obtain the parasitic parameter report, extract the parasitic parameter values and the corresponding layout position information in the report, and determine different color or marking methods according to the magnitude of the parasitic parameter values for representing different degrees of parasitic parameters in the layout; Use layout design software to load the layout file to be analyzed, overlay the parasitic parameter values at the corresponding positions according to the layout position information in the parasitic parameter report, and map the parasitic parameter values to different colors or markings through a data visualization tool to generate a parasitic parameter distribution map on the layout; Judge whether the parasitic parameter value exceeds the preset threshold. When it exceeds, mark the layout area where the parasitic parameter value exceeds the preset threshold as a high parasitic region and highlight it; Traverse all regions on the layout, generate a complete parasitic parameter distribution map according to the parasitic parameter values, and obtain a visualization result including the marking of high parasitic regions.

5. A layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: In the layout design software, according to the cascode structure design diagram, the MOS transistors are re - laid out and wired. The source and drain terminals between devices in the same group are merged and the connection paths are optimized. Specifically, it includes: According to the given cascode circuit structure diagram, obtain the layout information of the MOS transistor's position, direction, and connection relationship; judge whether the source and drain of the MOS transistors in the same group meet the merging conditions. If they meet, merge them into one node; Through the graphic recognition algorithm, determine the positions of the source and drain of the merged MOS transistors, and update the layout information. According to the updated layout information, use the minimum spanning tree algorithm to optimize the wiring scheme of the metal interconnect lines; Conduct design rule checking on the optimized wiring scheme to judge whether it meets the process requirements. If it does not meet, return for re - wiring; According to the wiring scheme that passes the DRC check, generate a new layout file, and update the device parameters and interconnection information; import the new layout file into the layout design software, and perform layout and wiring on the MOS transistors and metal interconnect lines to complete the optimized design of the cascode circuit.

6. A layout processing method for reducing parasitic RC through a cascode structure according to claim 5, characterized in that: After merging the source and drain terminals between devices in the same group, it also includes: according to the preset device grouping information, determine the devices in the same group that need to merge the source and drain, then obtain the layout positions and pin information of the devices in the same group, and judge the positional relationship between the source port and the drain port; when the source port and the drain port are adjacent, directly merge them in the layout to form a shared port structure; when the source port and the drain port are not adjacent, introduce additional interconnection structures in the layout; According to the signal integrity and parasitic parameter characteristics of the merged circuit, optimize the wiring topology of the interconnection structure; use the method of parasitic parameter extraction and post - simulation verification to evaluate the optimized wiring topology to ensure that it meets the design index requirements; after layout and wiring, perform layout extraction on the device unit after merging the source and drain.

7. A layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: Perform layout verification, specifically including: According to the optimized connection route, obtain the preset electrical rules and physical rules, and perform rule checking on the optimized layout. When electrical rule errors are found during the check, correct the circuit design according to the electrical rules to obtain a corrected circuit design scheme; When physical rule errors are found during the check, correct the physical design according to the physical rules to obtain a corrected physical design scheme, and fuse the corrected circuit design scheme and the physical design scheme to obtain a corrected layout design scheme; According to the corrected layout design scheme, use the simulated annealing algorithm to optimize the connection route again to obtain an optimized connection route again; According to the optimized connection route again, perform re - verification on the corrected layout design scheme to judge whether there are still electrical rule errors or physical rule errors. When the re - verification passes, determine the final layout design scheme; when the re - verification fails, continue with rule checking and correction until the verification passes.

8. A layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: Compare the changes in parasitic parameters before and after the application of the cascode structure, specifically including: Obtain the original circuit diagram of the circuit to be analyzed, determine the target module therein, and perform circuit simulation analysis on the target module; In the circuit simulation environment, build the simulation circuit diagram of the original circuit, set the circuit parameters, and perform simulation to obtain the performance index data of the parasitic parameters and operating frequency when the cascode structure is not applied; Adopt the cascode structure to conduct circuit optimization design on the target module of the original circuit to obtain the optimized circuit diagram; By building the optimized circuit simulation diagram, setting the same circuit parameters as the original circuit, and performing simulation, obtain the performance index data of the parasitic parameters and operating frequency after applying the cascode structure; Then compare and analyze the changes in parasitic parameters before and after applying the cascode structure, and visually display the impact of the cascode structure on parasitic parameters through data curves and values; compare and analyze the changes in operating frequency before and after applying the cascode structure, and visually display the impact of the cascode structure on operating frequency through data curves and values; Based on the comparative analysis results of parasitic parameters and operating frequency, judge the overall impact of the cascode structure on the performance of the circuit module, and generate a complete circuit simulation analysis report.

9. A layout processing method for reducing parasitic RC through a cascode structure according to claim 1, characterized in that: It also includes: According to the simulation report, when it is found that the reduction effect of parasitic RC cannot meet the expected performance requirements, iterate and optimize the design and layout of the cascode structure until the performance requirements are met.

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