Memory, memory system, and operating method of memory

Abstract

The embodiment of the invention discloses a memory, a memory system and an operation method of the memory, and belongs to the technical field of storage. In the method, before ISPP programming is carried out on storage units of a selected storage unit row, a first pre-programming pulse is provided for a selected word line so as to carry out pre-programming on a first type of storage units of the selected storage unit row. On one hand, due to the fact that the first type of storage units are programmed to be close to the first target programming state, the situation that the programming speed is too high during follow-up ISPP programming is avoided, and therefore the + 3 sigma tail of threshold voltage distribution is improved. On the other hand, when the first type of storage units are programmed to be close to the first target programming state and then ISPP programming is carried out, IVS is greatly reduced, and therefore the-3 sigma tail of threshold voltage distribution is improved. By improving the + 3 sigma tail and the-3 sigma tail of the threshold voltage distribution, the range of the threshold voltage distribution is narrowed, so that the effect of increasing the reading window is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of storage technology, and in particular, to a memory, a storage system, and a method for operating a memory. Background Art

[0002] When programming (i.e., writing data) storage cells in memories such as 3D NAND (NAND gates), in order to improve the accuracy of subsequent data reads, the threshold voltage distribution range of each storage cell that reaches the same target programming state is usually minimized as much as possible. This can increase the distance between the threshold voltage distribution ranges of two adjacent target programming states, that is, increase the read window. Summary of the invention

[0003] The embodiments of the present application provide a memory, a storage system, and a memory operation method, which can increase a read window. The technical solution is as follows:

[0004] In a first aspect, a memory is provided, the memory comprising:

[0005] A memory array, the memory array comprising a plurality of memory cell rows;

[0006] a plurality of word lines, the plurality of word lines being respectively coupled to the plurality of memory cell rows; and

[0007] a peripheral circuit coupled to the plurality of word lines and configured to:

[0008] Providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state;

[0009] A stepped programming pulse ISPP mode is adopted to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row.

[0010] Optionally, the peripheral circuit is further configured as:

[0011] providing a second pre-programming pulse to the selected word line to pre-program the second type of memory cells of the selected memory cell row;

[0012] Among them, the target programming state of the second type of storage cell is a second target programming state, and after providing the second pre-programming pulse, the threshold voltage of the second type of storage cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0013] Optionally, the distance between the state of the first type of memory cell and the first target programming state before providing the first pre-programming pulse is greater than the distance between the state of at least one other memory cell in the selected memory cell row and its respective target programming state.

[0014] Optionally, a difference between a voltage of the first pre-programming pulse and a first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on a programming voltage required for a programming state of the first type of memory cell to reach the first target programming state.

[0015] Optionally, the peripheral circuit is further configured as:

[0016] The first pre-program pulse is determined based on a difference between a current threshold voltage of at least one memory cell of the first type of memory cells and the first target threshold voltage.

[0017] Optionally, the peripheral circuit is configured as:

[0018] If the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage exceeds a second difference threshold, the first pre-programming pulse is configured for the first type of memory cells.

[0019] Optionally, the peripheral circuit is configured as:

[0020] In response to a program instruction from a controller, the first pre-program pulse is provided to the selected word line to pre-program the first type of memory cells of the selected memory cell row.

[0021] Optionally, the storage unit in the memory is a triple-level cell TLC.

[0022] Optionally, the peripheral circuit is configured as:

[0023] In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row;

[0024] providing the first pre-programming pulse to the selected word line to pre-program the first type of memory cells of the selected memory cell row;

[0025] Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row;

[0026] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0027] Optionally, the storage unit in the memory is a quad-level cell QLC.

[0028] In a second aspect, a storage system is provided, the storage system comprising a memory, and a controller coupled to the memory and configured to control the memory;

[0029] The memory is configured as:

[0030] Providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state;

[0031] A stepped programming pulse ISPP mode is adopted to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row.

[0032] Optionally, the controller is configured to: send a programming instruction to the memory;

[0033] The memory is configured to provide the first pre-program pulse to the selected word line in response to a program instruction from the controller to pre-program the first type of memory cells of the selected memory cell row.

[0034] Optionally, the controller is configured to: send a programming instruction to the memory;

[0035] The memory is further configured to:

[0036] In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row;

[0037] providing the first pre-programming pulse to the selected word line to pre-program the first type of memory cells of the selected memory cell row;

[0038] Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row;

[0039] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0040] Optionally, the memory is further configured to:

[0041] providing a second pre-programming pulse to the selected word line to pre-program the second type of memory cells of the selected memory cell row;

[0042] Among them, the target programming state of the second type of storage cell is a second target programming state, and after providing the second pre-programming pulse, the threshold voltage of the second type of storage cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0043] Optionally, the distance between the state of the first type of memory cell and the first target programming state before providing the first pre-programming pulse is greater than the distance between the state of at least one other memory cell in the selected memory cell row and its respective target programming state.

[0044] Optionally, a difference between a voltage of the first pre-programming pulse and a first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on a programming voltage required for a programming state of the first type of memory cell to reach the first target programming state.

[0045] Optionally, the memory is further configured to:

[0046] The first pre-program pulse is determined based on a difference between a current threshold voltage of at least one memory cell of the first type of memory cells and the first target threshold voltage.

[0047] Optionally, the memory is configured as:

[0048] If the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage exceeds a second difference threshold, the first pre-programming pulse is configured for the first type of memory cells.

[0049] Optionally, the memory is configured as:

[0050] In response to a program instruction from a controller, the first pre-program pulse is provided to the selected word line to pre-program the first type of memory cells of the selected memory cell row.

[0051] Optionally, the storage unit in the memory is a triple-level cell TLC.

[0052] Optionally, the memory is configured as:

[0053] In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row;

[0054] providing the first pre-programming pulse to the selected word line to pre-program the first type of memory cells of the selected memory cell row;

[0055] Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row;

[0056] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0057] Optionally, the storage unit in the memory is a quad-level cell QLC.

[0058] In a third aspect, a method for operating a memory is provided, the method comprising:

[0059] Providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state;

[0060] A stepped programming pulse ISPP mode is adopted to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row.

[0061] Optionally, before adopting the step programming ISPP mode to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row, the method further includes:

[0062] providing a second pre-programming pulse to the selected word line to pre-program the second type of memory cells of the selected memory cell row;

[0063] Among them, the target programming state of the second type of storage cell is a second target programming state, and after providing the second pre-programming pulse, the threshold voltage of the second type of storage cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0064] Optionally, the distance between the state of the first type of memory cell and the first target programming state before providing the first pre-programming pulse is greater than the distance between the state of at least one other memory cell in the selected memory cell row and its respective target programming state.

[0065] Optionally, a difference between a voltage of the first pre-programming pulse and a first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on a programming voltage required for a programming state of the first type of memory cell to reach the first target programming state.

[0066] Optionally, before providing the first pre-programming pulse to the selected word line, the method further comprises:

[0067] The first pre-program pulse is determined based on a difference between a current threshold voltage of at least one memory cell of the first type of memory cells and the first target threshold voltage.

[0068] Optionally, determining the first pre-programming pulse based on a difference between a current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage comprises:

[0069] If the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage exceeds a second difference threshold, the first pre-programming pulse is configured for the first type of memory cells.

[0070] Optionally, providing a first pre-programming pulse to a selected word line to pre-program the first type of memory cells in the selected memory cell row comprises:

[0071] In response to a program instruction from a controller, the first pre-program pulse is provided to the selected word line to pre-program the first type of memory cells of the selected memory cell row.

[0072] Optionally, the storage unit in the memory is a triple-level cell TLC.

[0073] Optionally, before providing a first pre-programming pulse to a selected word line to pre-program the first type of memory cells in the selected memory cell row, the method further comprises:

[0074] In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row;

[0075] The step-by-step programming (ISPP) method is used to provide a programming pulse to the selected word line to program the selected memory cell row, including:

[0076] Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row;

[0077] The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

[0078] Optionally, the storage unit in the memory is a quad-level cell QLC.

[0079] On the one hand, since the first type of memory cell is first programmed to the vicinity of the first target programming state, when the ISPP method is used for subsequent programming, the first type of memory cell can be slowly programmed to the first target programming state, thereby avoiding too fast a programming speed, and thus the +3σ tail of the threshold voltage distribution can be improved. On the other hand, since the first type of memory cell is first programmed to the vicinity of the first target programming state, when the ISPP method is used for subsequent programming, only a small amount of electrons need to be injected to program the first memory cell to the first target programming state, so that IVS will be much less, and thus the -3σ tail of the threshold voltage distribution can be improved. By improving the +3σ tail and -3σ tail of the threshold voltage distribution, the range of the threshold voltage distribution can be narrowed, thereby achieving the effect of increasing the read window. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0081] Figure 1 is a schematic diagram of a storage system 10 provided in an embodiment of the present application;

[0082] Figure 2 is a schematic diagram of a storage device provided in an embodiment of the present application;

[0083] Figure 3 is a schematic diagram of another storage device provided in an embodiment of the present application;

[0084] Figure 4 is a schematic diagram of a memory 100 provided in an embodiment of the present application;

[0085] Figure 5 is a cross-sectional schematic diagram of a memory array 110 including a memory string 111 provided in an embodiment of the present application;

[0086] Figure 6 is a schematic diagram of a peripheral circuit provided in an embodiment of the present application;

[0087] Figure 7 is a schematic diagram of threshold voltage distribution of a TLC provided in an embodiment of the present application;

[0088] Figure 8 is a flow chart of a method for operating a memory provided by an embodiment of the present application;

[0089] Fig. 9 This is a schematic diagram of a programming process using the ISPP method provided in an embodiment of the present application;

[0090] Fig.10 is a programming voltage (V PGM ) and the threshold voltage (Vt) of the memory cell;

[0091] Fig.11 is a schematic diagram of a -3σ tail for improving threshold voltage distribution provided by an embodiment of the present application;

[0092] Fig.12 This is a pulse comparison diagram provided in the programming process of scheme 1 and scheme 2 provided in an embodiment of the present application;

[0093] Fig.13 is a flow chart of another method for operating a memory provided by an embodiment of the present application;

[0094] Fig.14 is a schematic diagram of programming state distribution in a TLC programming process provided by an embodiment of the present application;

[0095] Fig.15 is a threshold voltage distribution comparison schematic diagram provided in an embodiment of the present application;

[0096] Fig.16 is a flow chart of another method for operating a memory provided by an embodiment of the present application;

[0097] Fig.17 This is a schematic diagram of programming state distribution in a QLC programming process provided by an embodiment of the present application;

[0098] Fig.18 is another threshold voltage distribution comparison schematic diagram provided in an embodiment of the present application;

[0099] Fig.19 It is a structural schematic diagram of a controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0100] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0101] Figure 1 is a schematic diagram of a storage system 10 provided in an embodiment of the present application. Figure 1 As shown, the memory system 10 includes: one or more memories 100 , and a controller 200 coupled to the memories 100 and configured to control the memories 100 .

[0102] The controller 200 may be configured to control operations performed by the memory 100. Such as read, erase and program operations. The controller 200 may also be configured to manage various functions regarding data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, conversion of logical addresses to physical addresses, wear leveling, etc. Optionally, the controller 200 may also be configured to process error correction codes (ECC) regarding data read from or written to the memory 100. The controller 200 may also perform any other suitable functions. For example, formatting the memory 100.

[0103] The controller 200 can also communicate with the external device according to a specific communication protocol. For example, the controller 200 can communicate with the external device through at least one of various interface protocols. The interface protocol can be a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Development Environment (IDE) protocol, a Firewire protocol, etc.

[0104] In some embodiments, the controller 200 and one or more memories 100 may be integrated into various types of electronic devices. The electronic device may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. In this scenario, Figure 1 As shown, the memory system 10 further includes a host 300. The controller 200 is coupled to the host 300. The controller 200 can manage data stored in the memory 100 and communicate with the host 300 to implement the functions of the aforementioned electronic device.

[0105] In other embodiments, the controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0106] As an example, Figure 2 As shown, the controller 200 and the single memory 100 may be integrated into a memory card 400. The memory card 400 may include a PCMCIA (PC) card, a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multi-Media Card (MMC), a RS-MMC, a micro-MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 400 may further include a connector 410 for coupling the memory card 400 with a host.

[0107] As another example, Figure 3 As shown, the controller 200 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 500. The solid state drive 500 may further include a connector 510 for coupling the solid state drive 500 with a host. The storage capacity and / or operating speed of the solid state drive 500 is greater than the storage capacity and / or operating speed of the memory card 400.

[0108] also, Figures 1 to 3 The memory 100 in the embodiment may be any memory involved in the embodiment of the present application. For example, it may be a 3D NAND (NAND gate) memory. The structure of the memory 100 is explained below.

[0109] Figure 4 is a schematic diagram of a memory 100 provided in an embodiment of the present application. Figure 4 As shown, the memory 100 includes:

[0110] A memory array 110, the memory array 110 includes a plurality of memory cell rows;

[0111] A plurality of word lines 120, wherein the plurality of word lines 120 are respectively coupled to a plurality of memory cell rows;

[0112] The peripheral circuit 130 is coupled to the plurality of word lines 120 and is configured to perform operations such as programming (i.e., writing data) or reading data on a selected memory cell row among the plurality of memory cell rows, wherein the selected memory cell row is a memory cell row coupled to the selected word line, wherein in order to perform operations such as programming or reading data, the peripheral circuit 130 is configured to execute the memory operation method provided in the embodiment of the present application.

[0113] The storage array 110 may be a NAND flash memory array. Figure 1 As shown, the NAND flash memory storage array includes a plurality of storage strings 111, which are arranged in an array on a substrate, and each storage string 111 extends vertically above the substrate (not shown). In some embodiments, each storage string 111 includes a plurality of storage cells 112 coupled in series and stacked vertically.

[0114] like Figure 4 As shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called a bottom select gate, a bottom select gate (BSG) or a source select gate, and the drain select gate is also called an upper select gate, a top select gate (TSG) or a drain select gate. The source select gate 113 and the drain select gate 114 may be configured to activate the selected memory string 111 during read and program operations.

[0115] In some embodiments, the drain select gate 114 of each memory string 111 is coupled to a corresponding bit line 115 , and data may be read from or written to the bit line 115 via an output bus (not shown).

[0116] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain selection gate 114) or a deselection voltage (e.g., 0V) to the corresponding drain selection gate 114 through one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source selection gate 113) or a deselection voltage (e.g., 0V) to the corresponding source selection gate 113 through one or more SSG lines 117.

[0117] like Figure 4 As shown, the storage strings 111 can be organized into multiple blocks 140. For any one of the multiple blocks 140, the block 140 can have a source line (source line, SL) 118. The sources of all the storage strings 111 in the block 140 are coupled through the source line 118. The source line is also called a common source line or an array common source (array common source, ACS).

[0118] The source line 118 can be used for grounding, so as to realize grounding the source of each memory cell of the memory string in the block 140 in some subsequent operations. Optionally, in some other operations, the source of each memory cell of the memory string in the block 140 can also be connected to a high voltage through the source line 118.

[0119] Each block 140 is a basic data unit for an erase operation, that is, all memory cells 112 on the same block 140 are erased simultaneously. To erase the memory cells 112 in a selected block, a source line coupled to the selected block may be biased with an erase voltage (Vers) such as a high positive voltage (20 V or higher).

[0120] It will be appreciated that in other embodiments, the erase operation may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level having any suitable number of blocks or blocks.

[0121] like Figure 4 As shown, the same layer of memory cells 112 of adjacent memory strings 111 in the same block 140 may be coupled via word lines 120, which are used to select which layer of memory cells 112 in the block 140 are affected by read and program operations.

[0122] In some embodiments, each word line 120 is coupled to a page 150 to which the memory cell 112 belongs, and the page 150 is a basic data unit for programming operations. The size of the page 150 may be related to the number of memory strings 111 coupled by the word line 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page 150. It is understood that a memory cell row is a plurality of memory cells 112 located in the same page 150.

[0123] It should be noted that the same layer of storage cells in a block 140 corresponds to the same word line, but the same layer of storage cells can be divided into one or more pages. That is, one word line can be coupled to one or more pages, for example, for SLC, one word line is coupled to one page, and for MLC, one word line is coupled to two pages.

[0124] Figure 5 1 is a cross-sectional schematic diagram of a memory array 110 including a memory string 111 provided in an embodiment of the present application. Figure 5 As shown, the memory string 111 may extend vertically above the substrate 101 and through the stacked layer 102. The substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0125] The stack 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stack 102 may determine the number of memory cells 112 in the memory array 110.

[0126] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. In addition, each gate conductive layer 103 may include a control gate surrounding the memory cell 112, and may extend laterally at the top of the stacked layer 102 as a DSG line 116, extend laterally at the bottom of the stacked layer 102 as an SSG line 117, or extend laterally between the DSG line 116 and the SSG line 117 as a word line 120.

[0127] like Figure 5As shown, the memory string 111 includes a channel structure 105 extending vertically and passing through the stacked layer 102. In some embodiments, the channel structure 105 includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a storage film). The semiconductor channel includes silicon, such as polysilicon. The storage film is a composite dielectric layer including a tunneling layer, a storage layer (also called a "charge trapping / storage layer") and a barrier layer.

[0128] In some embodiments, the channel structure 105 has a cylindrical shape (eg, a pillar shape). The layers in the semiconductor channel and the memory film are radially arranged in this order from the center of the pillar toward the outer surface of the pillar.

[0129] It should be understood that although Figure 5 Not shown in the figure, the memory array 110 may further include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0130] Return to reference Figure 4 , peripheral circuits 130 may be coupled to memory array 110 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116. Peripheral circuits 130 may include any suitable analog, digital, and mixed signal circuits for facilitating operation of memory array 110 by applying voltage signals and / or current signals to memory cells 112 and sensing voltage signals and / or current signals from memory cells 112 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116.

[0131] The peripheral circuit 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits 130 are shown, including page buffers / sense amplifiers 131, column decoders / bit line (BL) drivers 132, row decoders / word line (WL) drivers 133, voltage generators 134, control logic units 135, registers 136, interfaces 137, and data buses 138. It should be understood that in some examples, peripheral circuits 130 may also include Figure 6 Additional peripheral circuits not shown.

[0132] The page buffer / sense amplifier 131 may be configured to read data from the memory array 110 and program (write) data to the memory array 110 according to control signals from the control logic unit 135. For example, the page buffer / sense amplifier 131 may store a page of programming data (write data) to be programmed into one page 130 of the memory array 110. The page buffer / sense amplifier 131 may also perform verification operations to ensure that the data has been correctly programmed into the memory cell 112 coupled to the selected word line 120. The page buffer / sense amplifier 131 may also sense a low-power signal from the bit line 115, which represents a data bit stored in the memory cell 112, and amplify a small voltage swing to a recognizable logic level in a read operation.

[0133] The column decoder / bit line driver 132 may be configured to be controlled by the control logic unit 135 , and select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134 .

[0134] The row decoder / word line driver 133 may be configured to be controlled by the control logic unit 135, and select / deselect the block 140 of the memory array 110, and select / deselect the word line 120 of the block 140. The row decoder / word line driver 133 may also be configured to drive the word line 120 using the word line voltage (VWL) generated from the voltage generator 134. In some embodiments, the row decoder / word line driver 133 may also select / deselect and drive the SSG line 117 and the DSG line 116. As described in detail below, the row decoder / word line driver 133 is configured to perform an erase operation on the memory cell 112 coupled to the selected word line(s) 120.

[0135] The voltage generator 134 may be configured to be controlled by the control logic unit 135 and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, verification voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110 .

[0136] The control logic unit 135 may be coupled to each of the above-described peripheral circuits and configured to control operations of the respective circuits.

[0137] The register 136 may be coupled to the control logic unit 135 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each circuit in the peripheral circuit.

[0138] The interface (I / F) 137 may be coupled to the control logic unit 135 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 135, and to buffer status information received from the control logic unit 135 and relay them to the host. The interface 137 may also be coupled to the column decoder / bit line driver 132 via the data bus 138 and act as a data I / O interface and a data buffer to buffer data and relay them to or from the memory array 110.

[0139] The above description of the memory-related hardware embodiment has similar beneficial effects as the following method embodiment. For technical details not disclosed in the memory-related hardware embodiment, please refer to the description of the method embodiment of this application for understanding.

[0140] In the above Figures 1 to 6 In the embodiment, the memory cell 112 may be a floating gate memory cell including a floating gate transistor, or a charge capture memory cell including a charge capture transistor. When the data stored in these types of memory cells are different, the number of electrons captured in the memory cell will be different, so that the threshold voltage of the memory cell is different. Based on this, the amount of data stored in the memory cell is determined by determining the threshold voltage of the memory cell. When the data stored in the memory cell is different, the memory cell is in different states, that is, the memory cell corresponds to different states, and different states indicate that the data stored in the memory cell is different.

[0141] In some embodiments, the storage cell 112 may be a single-level cell (SLC). The SLC has two possible states for storing one bit of data, 0 and 1. The state corresponding to storing data 1 is called an erased state, and the state corresponding to storing data 0 is called a programmed state.

[0142] In some other embodiments, the storage cell 112 may be a multi-level cell (MLC). MLC has four possible states for storing two bits of data, namely 00, 01, 10, and 11. The state corresponding to the storage data 11 is called an erased state, and the states corresponding to the storage data 00, 01, and 10 are called programmed states. That is, for MLC, there is one erased state and three programmed states.

[0143] In some other embodiments, the storage unit 2 may be a triple-level cell (TLC). TLC has eight possible states for storing three bits of data, namely 000, 100, 010, 001, 110, 101, 011, and 111. The state corresponding to storing data 111 is called an erase state, and the states corresponding to storing the other seven data are called program states. That is, for TLC, there is one erase state and seven program states.

[0144] In some other embodiments, the storage cell 112 may be a quad-level cell (QLC). QLC has sixteen possible states for storing four-bit data, and the stored four-bit data is not illustrated one by one here. Among them, the state corresponding to the stored data 1111 is called the erased state, and the state corresponding to the storage of the other fifteen data is called the programmed state. That is, for QLC, there is one erased state and fifteen programmed states.

[0145] Figure 7 Schematic diagram of the threshold voltage distribution of a TLC provided in an embodiment of the present application. Figure 7 As shown, the TLC includes eight states from left to right, wherein the leftmost state is an erased state, followed by seven programmed states, labeled P1 to P7.

[0146] like Figure 7 As shown, each programming state corresponds to a threshold voltage (Vth) range. During programming, if the threshold voltage of a storage cell falls within the threshold voltage range corresponding to a certain programming state, it indicates that the storage cell currently reaches the programming state. Based on this, when reading data, the programming state corresponding to the storage cell is determined based on the threshold voltage of the storage cell, that is, the data stored in the storage cell is read.

[0147] In addition, if Figure 7 As shown, the distance between the right boundary of the left programming state and the left boundary of the right programming state in two adjacent programming states can be called a read window. After programming the memory, the larger the read window between two adjacent programming states, the more conducive it is to subsequent reading of data.

[0148] Based on this, an embodiment of the present application provides an operating method of a memory. Through the operating method provided by the embodiment of the present application, a read window between two adjacent programming states after programming can be increased.

[0149] The following is an explanation of the operation method of the memory provided in the embodiment of the present application.

[0150] Figure 8 is a flow chart of a memory operation method provided by an embodiment of the present application. The method is applied to Figure 1-6 The peripheral circuit of the memory shown in the figure is applied to the control logic unit in the peripheral circuit by way of example, and the subsequent embodiments are explained with the peripheral circuit as the execution subject. Figure 8 As shown, the method includes the following steps.

[0151] Step 801: Provide a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state.

[0152] The first type of memory cells may be understood as a set of a plurality of memory cells in a selected memory cell row whose target programming state is a first target programming state.

[0153] The first target threshold voltage can be understood as: the statistical result of each threshold voltage in the threshold voltage distribution corresponding to the first target programming state, and the statistical result can be the average value of each threshold voltage, or the maximum value of each threshold voltage, or the minimum value of each threshold voltage, etc. It should be noted that in the embodiment of the present application, for different target programming states, the target threshold voltage corresponding to the target programming state adopts the same determination method, for example, the average value of each threshold voltage in the threshold voltage distribution corresponding to the target programming state is used as the target threshold voltage.

[0154] After providing the first pre-programming pulse to the selected word line to pre-program the first type of memory cell, the threshold voltage of the first type of memory cell is less than the first target threshold voltage, that is, the current state of the first type of memory cell has not yet reached the first target programming state. Pre-programming the first type of memory cell will inevitably cause the threshold voltage of the first type of memory cell to shift toward the first target threshold voltage. In other words, the distance between the state of the first type of memory cell after providing the first pre-programming pulse and the first target programming state is less than the distance between the state of the first type of memory cell before providing the first pre-programming pulse and the first target programming state. Therefore, after providing the first pre-programming pulse to pre-program the first type of memory cell, the threshold voltage of the first type of memory cell is closer to the first target threshold voltage, in other words, the current state of the first type of memory cell is closer to the first target programming state.

[0155] Step 802: Provide a programming pulse to the selected word line using the ISPP method to program the memory cells in the selected memory cell row.

[0156] Fig. 9FIG. 1 is a schematic diagram of a programming process using an increment step programming pulse (ISPP) method provided in an embodiment of the present application. Fig. 9 As shown in FIG. 1 , the programming process includes: gradually providing a series of programming pulses (PP) with increasing amplitudes to the selected word line. The voltage amplitude of the first programming pulse provided is V PGM-START , the increment of each programming pulse step is ΔISPP. Among them, V PGM-START , ΔISPP and the duration of a single programming pulse can be preconfigured. After each programming pulse is provided, it is possible to verify whether the memory cell in the selected memory cell row has reached the target programming state, that is, to perform a program verify (PV) operation on the memory cell, wherein the PV operation is implemented by providing one or more PV pulses. Fig. 9 If the memory cell has not reached the corresponding target programming state, the memory cell is continuously verified after the next programming pulse is provided until the memory cell reaches the target programming state, and then the programming of the memory cell is terminated.

[0157] For the convenience of subsequent description, the process of programming the memory cells of the selected memory cell row by using the ISPP method is referred to as ISPP programming.

[0158] In the embodiment of the present application, before programming the memory cells of the selected memory cell row by the ISPP method, a first pre-programming pulse corresponding to the first target programming state is provided, so that the state of the first type of memory cells whose target programming state is the first target programming state in the selected memory cell row can reach the vicinity of the first target programming state. The following technical effects can be achieved by this programming method:

[0159] On the one hand, since the first type of memory cells are first programmed to the vicinity of the first target programming state, when the ISPP method is subsequently used for programming, the first type of memory cells can be slowly programmed to the first target programming state, thus avoiding too fast a programming speed, and thus improving the +3σ tail of the threshold voltage distribution.

[0160] On the other hand, since the first type of memory cell is first programmed to the vicinity of the first target programming state, when the ISPP method is subsequently used for programming, only a small amount of electrons need to be injected to program the first memory cell to the first target programming state, so that the initial threshold voltage drift (initial Vt shift, IVS) will be much less, thereby improving the -3σ tail of the threshold voltage distribution.

[0161] By improving the +3σ tail and the −3σ tail of the threshold voltage distribution, the range of the threshold voltage distribution can be narrowed, thereby achieving the effect of increasing the read window.

[0162] based on Figure 7 As shown, the threshold voltage distribution corresponding to any programming state usually presents a normal distribution, and the above σ can be understood as the standard deviation of the normal distribution. Accordingly, the +3σ tail of the threshold voltage distribution can be understood as: the data located to the right of μ+3σ in the normal distribution, where μ is the symmetry axis of the normal distribution. Improving the +3σ tail of the threshold voltage distribution can be understood as: the data falling to the right of μ+3σ in the normal distribution is as small as possible.

[0163] Accordingly, the -3σ tail of the threshold voltage distribution can be understood as the data on the left side of μ-3σ in the normal distribution. Improving the -3σ tail of the threshold voltage distribution can be understood as reducing the data on the left side of μ-3σ in the normal distribution as much as possible.

[0164] Fig.10 is a programming voltage (V PGM ) and the threshold voltage (Vt) of the storage cell. Fig.10 The slope in can represent the programming speed. Fig.10 As shown, the closer the initial threshold voltage of the storage cell is to the target threshold voltage, the slower the programming speed. Therefore, pre-programming the first type of storage cell to near the first target programming state and then performing ISPP programming can improve the +3σ tail of the threshold voltage distribution corresponding to the first target programming state.

[0165] Fig.11 Schematic diagram of a -3σ tail of an improved threshold voltage distribution provided by an embodiment of the present application. Fig.11 As shown in FIG. 1 , one programming method is to directly program the memory cell from the erased state to the target programming state through ISPP programming, and the other programming method is to first program the memory cell from the erased state to the vicinity of the target programming state through pre-programming, and then program the memory cell from the vicinity of the target programming state to the target programming state through ISPP programming. The threshold voltage distribution obtained by the ISPP direct programming method is shown in FIG. Fig.11 As shown by the solid line on the right, the threshold voltage distribution obtained by pre-programming and then ISPP programming is as follows Fig.11 As shown by the dotted line on the right. Fig.11 As shown, the -3σ tail of the threshold voltage distribution obtained by the method of pre-programming first and then ISPP programming is significantly shorter than the -3σ tail of the threshold voltage distribution obtained by the method of direct ISPP programming.

[0166] In some embodiments, the distance between the state of the first type memory cell before providing the first pre-programming pulse and the first target programming state is greater than the distance between the state of at least one other memory cell in the selected memory cell row and the respective target programming state.

[0167] In other words, before ISPP programming, the memory cells whose current state is far from the target programming state are pre-programmed. The farther the current state is from the target programming state, the more serious the IVS is during the ISPP programming process. Therefore, after pre-programming the memory cells whose current state is far from the target programming state, the IVS can be improved during the subsequent ISPP programming process.

[0168] The distance between the state of the memory cell and the corresponding target programming state can be understood as the distance between the threshold voltage of the memory cell and the threshold voltage distribution corresponding to the corresponding target programming state. Figure 7 In the embodiment, the distance between the state of the memory cell and the corresponding target programming state may be: the distance between the threshold voltage of the memory cell and the central axis or the left boundary of the threshold voltage distribution corresponding to the corresponding target programming state.

[0169] Optionally, in a scenario where the erase state and programming state are named with consecutive numbers, the distance between the state of the storage unit and the corresponding target programming state can be understood as: the difference between the number corresponding to the current state of the storage unit and the number corresponding to the corresponding target programming state.

[0170] For example, for Figure 7 As shown in the threshold voltage distribution, assuming that the erased state is marked as P0 and the seven programming states are marked as P1 to P7 in sequence, the distance between the state of the storage cell and the target programming state can be determined by the distance between the threshold voltage of the storage cell and the threshold voltage distribution corresponding to the corresponding target programming state, and can also be determined by the difference between the number corresponding to the current state of the storage cell and the number corresponding to the corresponding target programming state.

[0171] Based on this, for Figure 7 In the threshold voltage distribution of the TLC shown, before programming the TLC, all memory cells are in an erased state. In this scenario, the first type of memory cells may be a type of memory cells whose target programming state is P7.

[0172] Additionally, in some embodiments, a difference between a voltage of the first pre-programming pulse and a first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on a programming voltage required for the programming state of the first type of memory cells to reach the first target programming state.

[0173] The first difference threshold is a smaller value, so the voltage of the first pre-programming pulse is close to the first target programming voltage, so that the state of the first type of memory cell after pre-programming is close to the first target programming state.

[0174] The first target programming voltage may be set based on the programming voltage required for the programming state of the first type of storage cells to reach the first target programming state by a technician based on the voltage of the programming pulse provided by the first type of storage cells through ISPP programming in history. For example, the maximum value of the voltages of the programming pulses provided by the first type of storage cells through ISPP programming in history may be used as the first target programming voltage. Alternatively, several larger voltages among the voltages of the programming pulses provided by the first type of storage cells through ISPP programming in history may be screened out first, and then the average of these larger voltages may be used as the first target programming voltage. The embodiments of the present application do not limit the method for determining the first target programming voltage, and will not be illustrated one by one here.

[0175] Since the target programming states of the memory cells in the selected memory cell row are different, before providing the pre-programming pulse, the first type of memory cells that need to be pre-programmed can be screened out from the selected memory cell row.

[0176] In some embodiments, screening out first-type memory cells that need to be preprogrammed from a selected memory cell row may be implemented by determining a first preprogramming pulse based on a difference between a current threshold voltage of at least one memory cell in the first-type memory cell and a first target threshold voltage.

[0177] Based on the foregoing, it can be known that in an embodiment of the present application, storage cells whose current states are far from the target programming state can be pre-programmed before ISPP programming. Therefore, in some embodiments, it can be determined whether to configure the first pre-programming pulse for the first type of storage cells based on the difference between the current threshold voltage of at least one storage cell in the first type of storage cells and the first target threshold voltage.

[0178] For example, if the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage exceeds the second difference threshold, a first pre-program pulse is configured for the first type of memory cells.

[0179] The second difference threshold is a preset value, which can be set by a technician based on experience. If the difference between the current threshold voltage of at least one memory cell in the first type of memory cell and the first target threshold voltage exceeds the second difference threshold, it indicates that the current state of the first type of memory cell is far from the target programming state, so the first pre-programming pulse can be configured for the first type of memory cell.

[0180] Accordingly, if the difference between the current threshold voltage of at least one memory cell in the first type of memory cell and the first target threshold voltage does not exceed the second difference threshold, it indicates that the current state of the first type of memory cell is close to the target programming state, and therefore there is no need to configure a first pre-programming pulse for the first type of memory cell.

[0181] Optionally, for different types of memory cells corresponding to different target programming states in the selected memory cell row, the difference between the current threshold voltage of each type of memory cell and the target threshold voltage of the corresponding target programming state can be determined respectively, and then the multiple types of memory cells can be sorted in descending order according to the determined difference. From the sorting result, the first-ranked memory cell is selected as the first type of memory cell, and a first pre-programming pulse is configured for the first type of memory cell.

[0182] The current threshold voltage of each type of memory cell may be understood as an average value or other statistical result of the threshold voltages of each memory cell in the type of memory cell.

[0183] The above is to pre-program the first type of memory cells whose programming state is the first target programming state before ISPP programming to improve the ±3σ tail of the threshold voltage distribution corresponding to the first target programming state. In the embodiment of the present application, the second type of memory cells whose programming state is the second target programming state can also be pre-programmed before ISPP programming to improve the ±3σ tail of the threshold voltage distribution corresponding to the second target programming state.

[0184] Based on this, in some embodiments, a second pre-programming pulse is also provided to the selected word line before step 802 to pre-program the second type of memory cells in the selected memory cell row; wherein the target programming state of the second type of memory cells is a second target programming state, and after providing the second pre-programming pulse, the threshold voltage of the second type of memory cells is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

[0185] In other words, in the embodiment of the present application, multiple types of memory cells with different target programming states may be pre-programmed separately before ISPP programming to improve the ±3σ tails of the threshold voltage distribution corresponding to the corresponding target programming states.

[0186] The voltage of the second pre-programming pulse may refer to the related implementation method of the voltage of the first pre-programming pulse, which will not be described in detail here.

[0187] In addition, the second type of memory cells may also be memory cells of a type whose current state and target programming state are farther apart before ISPP programming. That is, the distance between the state of the second type of memory cells before providing the second pre-programming pulse and the second target programming state is greater than the distance between the state of at least one other memory cell in the selected memory cell row and the respective target programming state.

[0188] For example, for Figure 7In the threshold voltage distribution of the TLC shown, all memory cells are in the erased state before programming the TLC. In this scenario, the first type of memory cells may be a type of memory cells with a target programming state of P7, and the second type of memory cells may be a type of memory cells with a target programming state of P6.

[0189] The above description is made by taking the first type of storage cells and the second type of storage cells as examples. In the embodiment of the present application, more types of storage cells can be pre-programmed first and then ISPP programmed.

[0190] For example, before performing ISPP programming, multiple types of memory cells that need to be pre-programmed can be determined, each type of memory cell corresponds to a target programming state, and the distance between the current state of each type of memory cell in the multiple types of memory cells and the target programming state is greater than the distance between the current state of other types of memory cells in the selected memory cell row and the target programming state. Then, a pre-programming pulse is provided to each type of memory cell in the multiple types of memory cells for pre-programming. After pre-programming the multiple types of memory cells, ISPP programming is performed on the memory cells in the selected memory cell row.

[0191] For example, for Figure 7 As shown in the threshold voltage distribution of TLC, before programming the TLC, all memory cells are in the erased state. Figure 7 As shown, for the four types of memory cells whose target programming states are P4, P5, P6, and P7, the distances between the current states of the four types of memory cells and the target programming states are all greater than the distances between the current states of the other types of memory cells and the target programming states, so these four types of memory cells can be used as memory cells that need to be pre-programmed. Then, a pre-programming pulse is provided for each of the four types of memory cells for pre-programming. After the four types of memory cells are pre-programmed, the memory cells of the selected memory cell row are subjected to ISPP programming.

[0192] It should be noted that the above is described by taking the pre-programming of the memory cells whose current state is far from the target programming state as an example. Optionally, in the embodiment of the present application, it is also possible to pre-program each type of memory cell directly without screening, and then perform ISPP programming on the memory cells of the selected memory cell row after pre-programming, which will not be described in detail here.

[0193] Below Fig.12 For the convenience of subsequent description, the programming scheme provided in the embodiment of the present application is referred to as Scheme 1, and the scheme for directly performing ISPP programming on the selected memory cell row is referred to as Scheme 2. Fig.121 is a pulse comparison diagram provided by scheme 1 and scheme 2 in the programming process provided by the embodiment of the present application. Fig.12 As shown, Fig.12 The upper part is used to represent the programming pulse provided to the selected memory cell row in scheme 2. For the convenience of subsequent description, the programming pulse provided in ISPP programming is referred to as ISPP programming pulse. Fig.12 As shown in the upper part, in the second scheme, after each PP is provided, one or more PV pulses are provided to verify whether the memory cells in the selected memory cell row have reached the corresponding target programming state. Fig.12 The lower part is used to represent the programming pulses provided to the selected memory cell row in scheme 1. Fig.12 As shown in the lower part, before providing the ISPP programming pulse to the selected memory cell row, a pre-programming pulse is also provided to each type of memory cell in the multiple types of memory cells in the selected memory cell row to implement the programming scheme provided in the embodiment of the present application.

[0194] In summary, in the embodiment of the present application, before programming the selected memory cell row using the ISPP method, the first type of memory cells in the selected memory cell row are pre-programmed. On the one hand, since the first type of memory cells are first programmed to the vicinity of the first target programming state, when the ISPP method is subsequently used for programming, the first type of memory cells can be slowly programmed to the first target programming state, thereby avoiding the programming speed being too fast, and thus the +3σ tail of the threshold voltage distribution can be improved. On the other hand, since the first type of memory cells are first programmed to the vicinity of the first target programming state, when the ISPP method is subsequently used for programming, only a small amount of electrons need to be injected to program the first memory cell to the first target programming state, so that the IVS will be much less, and thus the -3σ tail of the threshold voltage distribution can be improved. By improving the +3σ tail and -3σ tail of the threshold voltage distribution, the range of the threshold voltage distribution can be narrowed, thereby achieving the effect of increasing the read window.

[0195] There are currently two ways to perform ISPP programming on a memory, one is called one-step ISPP programming, and the other is called two-step ISPP programming. Figure 8 The embodiment shown can be applied to one-step ISPP programming or two-step ISPP programming. One-step ISPP programming can be understood as one ISPP programming to make each memory cell in the selected memory cell row reach the corresponding target programming state. Two-step ISPP programming can be understood as two ISPP programming to make each memory cell in the selected memory cell row reach the corresponding target programming state.

[0196] This will be explained below through two embodiments.

[0197] Fig.131 is a flow chart of another memory operation method provided by an embodiment of the present application, which is applied to one-step ISPP programming. Fig.13 As shown, the method includes the following steps.

[0198] Step 1301: The controller sends a programming instruction to the memory.

[0199] Step 1302: In response to a program instruction from a controller, the memory provides a first pre-program pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row.

[0200] Step 1303: The memory uses the ISPP method to provide programming pulses to the selected word line to program the memory cells in the selected memory cell row.

[0201] exist Fig.13 In the method shown, when the memory receives a programming instruction from the controller, before performing one-step ISPP programming on the selected memory cell row, the first type of memory cells in the selected memory cell row are pre-programmed to improve the +3σ tail and -3σ tail of the threshold voltage distribution of the first target programming state.

[0202] Optionally, in Fig.13 In the method shown, before performing one-step ISPP programming on the selected memory cell row, each type of memory cell row in the multiple types of memory cells in the selected memory cell row can be pre-programmed to improve the +3σ tail and -3σ tail of the threshold voltage distribution of the corresponding target programming state. For specific implementation methods, please refer to Figure 8 The embodiments shown will not be described in detail here.

[0203] It should be noted that Fig.13 The order of execution of the steps in the operating method shown can be adjusted appropriately, and the sequence numbers of the steps do not constitute a limitation on the execution order of the steps. Any technician familiar with the technical field can easily think of changes within the technical scope disclosed in the embodiments of the present application, and they should all be covered within the protection scope of the embodiments of the present application, so they will not be repeated here.

[0204] in addition, Fig.13 The memory in the method shown can be exemplarily a TLC. In other words, when the TLC receives a programming instruction from the controller, it first pre-programs at least one type of memory cells in the memory cell row, and then programs the selected memory cell row through one-step ISPP programming.

[0205] For example, when TLC receives a programming instruction from the controller, it first pre-programs the four types of memory cells whose target programming states are P4, P5, P6, and P7 respectively through a pre-programming pulse, so that these four types of memory cells reach the vicinity of the corresponding target programming states, and then programs the selected memory cell row through ISPP programming, so that all memory cells in the selected memory cell row reach the corresponding target programming states.

[0206] Fig.14 Schematic diagram of programming state distribution in a TLC programming process provided by an embodiment of the present application. Fig.14 As shown, a pre-programming pulse is first provided to the four types of memory cells whose target programming states are P4, P5, P6, and P7 respectively for pre-programming. The threshold voltage distributions of the four types of memory cells after pre-programming are as follows: Fig.14 The dotted line in the upper part is shown. Then, an ISPP programming pulse is provided to the selected memory cell row. After the ISPP programming pulse is provided, the threshold voltage distribution of the memory cells in the selected memory cell row is as shown in FIG. Fig.14 As shown in the lower part. Fig.14 As shown in the upper and lower comparisons, the threshold voltage distributions of the four types of memory cells whose target programming states are P4, P5, P6, and P7 respectively, have not reached the corresponding target programming states after pre-programming, but are located near the corresponding target programming states, and only reach the corresponding target programming states after ISPP programming.

[0207] Fig.15 This is a threshold voltage distribution comparison diagram provided in an embodiment of the present application. Fig.15 The solid lines corresponding to the various programming states are schematic diagrams of the threshold voltage distribution of the TLC obtained by directly programming the selected memory cell row based on the one-step ISPP programming, that is, a schematic diagram of the threshold voltage distribution of the TLC obtained directly based on the one-step ISPP programming without pre-programming. Fig.15 The solid lines corresponding to the programming states P0-P3 and the dotted lines corresponding to the programming states P4-P7 are Fig.14 The threshold voltage distribution diagram of the TLC obtained by the programming method shown is a threshold voltage distribution diagram of the TLC obtained by first pre-programming and then programming based on the one-step ISPP method.

[0208] like Fig.15 As shown, before the one-step ISPP programming, a pre-programming pulse is provided to the four types of memory cells whose target programming states are P4, P5, P6, and P7 respectively for pre-programming. Therefore, the threshold voltage distribution of these four types of memory cells in the final threshold voltage distribution is much narrower, that is, the +3σ tail and -3σ tail of the threshold voltage distribution of these four types of memory cells are improved.

[0209] It should be noted that Fig.14 and Fig.15 TLC is used as an example for illustration. Optionally, Fig.13 The illustrated embodiment may also be applied to other types of memories, which will not be illustrated one by one here.

[0210] Fig.16 FIG. 1 is a flow chart of another memory operation method provided by an embodiment of the present application, and the method is applied to two-step ISPP programming. Fig.16 As shown, the method includes the following steps.

[0211] Step 1601: The controller sends a programming instruction to the memory.

[0212] Step 1602: In response to a programming instruction from a controller, the memory uses an ISPP method to provide a programming pulse to a selected word line to perform a first programming on the memory cells of the selected memory cell row.

[0213] Step 1603: The memory provides a first pre-programming pulse to the selected word line to pre-program the first type of memory cells in the selected memory cell row.

[0214] Step 1604: The memory uses ISPP to provide a programming pulse to the selected word line to perform a second programming on the memory cells in the selected memory cell row.

[0215] Among them, the number of programming states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programming states in the threshold voltage distribution of the selected memory cell row after the first programming. In other words, the selected memory cell row is first programmed to a smaller number of programming states through the first programming, and then the selected memory cell row is programmed to a larger number of programming states through the second programming. Therefore, the first programming is also called ISPP coarse programming, and the second programming is also called ISPP fine programming.

[0216] It should be noted that Fig.16 The order of execution of the steps in the operating method shown can be adjusted appropriately, and the sequence numbers of the steps do not constitute a limitation on the execution order of the steps. Any technician familiar with the technical field can easily think of changes within the technical scope disclosed in the embodiments of the present application, and they should all be covered within the protection scope of the embodiments of the present application, so they will not be repeated here.

[0217] In addition, two-step ISPP programming is usually suitable for memories with a large number of programming states. For example, if the memory is QLC, before programming the QLC, the programming state of all storage cells in the QLC is the erased state. Considering that the total number of target programming states of all storage cells is 16, in order to avoid serious IVS during the one-step ISPP programming process, the QLC can be programmed for the first time by ISPP, so that after the first programming, the threshold voltage distribution of the QLC includes 4 programming states in the MLC or 8 programming states in the TLC, and then the second programming is performed by ISPP, so that after the second programming, the threshold voltage distribution of the QLC includes 16 programming states of the QLC. This process is also called: first programming the memory to MLC or TLC, and then programming the MLC or TLC to QLC.

[0218] exist Fig.16 In the method shown, when the memory receives a programming instruction from a controller, it first performs the first programming in the two-step ISPP programming on the selected memory cell row, and after the first programming, pre-programs the first type of memory cells in the selected memory cell row, and then performs the second programming in the two-step ISPP programming on the selected memory cell row.

[0219] Optionally, when receiving a programming instruction from the controller, the memory first performs the first programming of the two-step ISPP programming on the selected memory cell row, and after the first programming, pre-programs the multiple types of memory cells in the selected memory cell row respectively, and then performs the second programming of the two-step ISPP programming on the selected memory cell row. For specific implementation methods, please refer to Figure 8 The embodiments shown will not be described in detail here.

[0220] Fig.17 Schematic diagram of programming state distribution in a QLC programming process provided by an embodiment of the present application. Fig.17 As shown, the memory cells in the selected memory cell row are first divided into four categories, one category is the memory cells whose target programming states include P0-P3, one category is the memory cells whose target programming states include P4, P5, P8 and P9, one category is the memory cells whose target programming states include P6, P7, P10 and P15, and one category is the memory cells whose target programming states include P11, P12, P13 and P14. After the first programming (i.e., after ISPP rough programming), the current state of the memory cells whose target programming states include P0-P3 is still Fig.17 The current state of the storage cells P0 in the first row of the target programming state includes P4, P5, P8 and P9 is Fig.17 The current state of the storage cells P1 in the first row of the target programming state includes P6, P7, P10 and P15 is Fig.17The current state of the storage cells P2 in the first row of the target programming state includes P11, P12, P13 and P14 is Fig.17 That is, after the first programming, the threshold voltage distribution of the selected memory cell row includes four programming states.

[0221] After the first programming, the target programming state is the current state of the memory cells of P8 and P9 ( Fig.17 The distance between the P1 in the first row of the target programming state and the corresponding target programming state is still relatively far. The current state of the storage cells whose target programming states are P10 and P15 ( Fig.17 The distance between the P2 in the first row of the target programming state and the corresponding target programming state is still relatively far. The current state of the storage cells whose target programming states are P13 and P14 ( Fig.17 The distance between the P3 in the first row of the 6 types of memory cells and the corresponding target programming state is still relatively far, so a pre-programming pulse is provided to each of the six types of memory cells to make the current state of each of the six types of memory cells (such as Fig.17 The second row shows that the corresponding target programming state is reached.

[0222] After pre-programming, each memory cell in the selected memory cell row is subjected to a second programming (ie, ISPP fine programming) so that the state of each memory cell in the selected memory cell row reaches the corresponding target programming state. Fig.17 As shown in the third row, after the second programming of the QLC, the threshold voltage distribution of the selected memory cell row includes 16 programming states.

[0223] Fig.18 This is another threshold voltage distribution comparison diagram provided in an embodiment of the present application. Fig.18 The solid lines corresponding to the various programming states are schematic diagrams of the threshold voltage distribution of the QLC obtained by directly programming the selected memory cell row based on the two-step ISPP method, that is, a schematic diagram of the threshold voltage distribution of the QLC obtained by directly programming based on the two-step ISPP method without pre-programming. Fig.18 The solid lines corresponding to the programming states P0-P7 and P11-P12, and the dotted lines corresponding to the programming states P8-P10 and P13-P15 are Fig.17 The threshold voltage distribution diagram of the QLC obtained by the programming method shown, that is, the first programming in the two-step ISPP programming is performed first, then the pre-programming is performed, and finally the second programming in the two-step ISPP programming is performed to obtain the threshold voltage distribution diagram of the QLC.

[0224] like Fig.18As shown, before the second programming of the two-step ISPP programming, the six types of memory cells whose target programming states are P8, P9, P10, P13, P14, and P15 are respectively provided with a pre-programming pulse for pre-programming. Therefore, the threshold voltage distribution of these six types of memory cells in the final threshold voltage distribution is much narrower, that is, the +3σ tail and -3σ tail of the threshold voltage distribution of these six types of memory cells are improved.

[0225] The programming state that each storage unit needs to reach after the first programming is related to the preset Gray code, and the embodiment of the present application does not limit the specific form of the Gray code.

[0226] It should be noted that Fig.17 and Fig.18 QLC is used as an example for illustration. Optionally, Fig.16 The illustrated embodiment may also be applied to other types of memories, which will not be illustrated one by one here.

[0227] in addition, Fig.13 and Fig.16 The application scenarios of the embodiments of the present application are described by taking one-step ISPP programming and two-step ISPP programming as examples. Figure 8 The illustrated embodiment can be applied to more types of ISPP programming, which will not be described one by one here.

[0228] based on Figure 8-Figure 18 The embodiment shown, the embodiment of the present application also provides a memory, which includes: a memory array, the memory array includes a plurality of memory cell rows; a plurality of word lines, the plurality of word lines are respectively coupled to the plurality of memory cell rows; and a peripheral circuit, the peripheral circuit is coupled to the plurality of word lines and is configured to implement the memory operation method provided by the embodiment of the present application.

[0229] Specifically, the peripheral circuit is configured as follows: providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state; and providing a programming pulse to the selected word line using a step programming ISPP method to program the selected memory cell row.

[0230] The specific implementation of the functions of the above peripheral circuits can refer to Figure 8-18 The embodiments shown will not be described in detail here.

[0231] In addition, an embodiment of the present application further provides a storage system, which includes a memory and a controller coupled to the memory and configured to control the memory.

[0232] The memory is configured to provide a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein the target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, the threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state; and a step programming ISPP method is used to provide a programming pulse to the selected word line to program the selected memory cell row.

[0233] The implementation of the functions of the above controller and memory can refer to Fig.13 and Fig.16 The embodiments shown will not be described in detail here.

[0234] Fig.19 Schematic diagram of a controller provided in an embodiment of the present application. Fig.19 As shown, the controller 1900 includes a processing unit 1901 and a memory 1902. The memory 1902 is used to store computer instructions, and the processing unit 1901 is used to execute computer instructions to implement the operation method provided in the embodiment of the present application. The processing unit 1901 can be MCU (microcontroller unit) or the like.

[0235] The controller 1900 is used to implement the functions of the controller in the aforementioned embodiment to implement the storage system provided by the embodiment of the present application. Fig.13 or Fig.16 The illustrated embodiment will not be described in detail here.

[0236] In addition, the embodiment of the present application further provides a peripheral circuit, wherein the control logic unit in the peripheral circuit includes at least one software module, and the at least one software module is used to implement Figure 8-18 Any step in the memory operation method in the illustrated embodiment.

[0237] In addition, the embodiment of the present application further provides a computer storage medium, wherein the computer readable storage medium stores instructions, and when the instructions are executed by the peripheral circuit in the memory, the Figure 8-18 Any step in the memory operation method in the illustrated embodiment.

[0238] In another aspect, a computer program product is provided which includes instructions which, when executed in a peripheral circuit, implement Figure 8-18Any step in the memory operation method in the illustrated embodiment.

[0239] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0240] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A memory, characterized in that: The memory comprises: A memory array, the memory array comprising a plurality of memory cell rows; a plurality of word lines, the plurality of word lines being respectively coupled to the plurality of memory cell rows; and a peripheral circuit coupled to the plurality of word lines and configured to: Providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state; A stepped programming pulse ISPP mode is adopted to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row.

2. The memory according to claim 1, wherein: The peripheral circuit is further configured as: providing a second pre-programming pulse to the selected word line to pre-program the second type of memory cells of the selected memory cell row; Among them, the target programming state of the second type of storage cell is a second target programming state, and after providing the second pre-programming pulse, the threshold voltage of the second type of storage cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

3. The memory according to claim 1, wherein: The distance between the state of the first type of memory cell before providing the first pre-programming pulse and the first target programming state is greater than the distance between the state of at least one other memory cell in the selected memory cell row and the respective target programming state.

4. The memory according to claim 1, wherein: A difference between a voltage of the first pre-programming pulse and a first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on a programming voltage required for a programming state of the first type of memory cells to reach the first target programming state.

5. The memory according to claim 1, wherein: The peripheral circuit is further configured as: The first pre-program pulse is determined based on a difference between a current threshold voltage of at least one memory cell of the first type of memory cells and the first target threshold voltage.

6. The memory according to claim 5, characterized in that The peripheral circuit is configured as: If the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage exceeds a second difference threshold, the first pre-programming pulse is configured for the first type of memory cells.

7. The memory according to any one of claims 1 to 6, characterized in that: The peripheral circuit is configured as: In response to a program instruction from a controller, the first pre-program pulse is provided to the selected word line to pre-program the first type of memory cells of the selected memory cell row.

8. The memory according to claim 7, wherein: The memory cells in the memory are triple-level cells (TLC).

9. The memory according to any one of claims 1 to 6, characterized in that: The peripheral circuit is configured as: In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row; providing the first pre-programming pulse to the selected word line to pre-program the first type of memory cells of the selected memory cell row; Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row; The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

10. The memory according to claim 9, wherein: The storage unit in the memory is a quad-level cell (QLC).

11. A storage system, characterized in that: The storage system includes a memory, and a controller coupled to the memory and configured to control the memory; The memory is configured as: Providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state; A stepped programming pulse ISPP mode is adopted to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row.

12. The storage system according to claim 11, characterized in that: The controller is configured to: send programming instructions to the memory; The memory is configured to provide the first pre-program pulse to the selected word line in response to a program instruction from the controller to pre-program the first type of memory cells of the selected memory cell row.

13. The storage system according to claim 11, characterized in that: The controller is configured to: send programming instructions to the memory; The memory is further configured to: In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row; providing the first pre-programming pulse to the selected word line to pre-program the first type of memory cells of the selected memory cell row; Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row; The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

14. A method for operating a memory, characterized in that: The method comprises: Providing a first pre-programming pulse to a selected word line to pre-program a first type of memory cell in a selected memory cell row, wherein a target programming state of the first type of memory cell is a first target programming state, and after providing the first pre-programming pulse, a threshold voltage of the first type of memory cell is less than a first target threshold voltage, and the first target threshold voltage is a threshold voltage corresponding to the first target programming state; A stepped programming pulse ISPP mode is adopted to provide a programming pulse to the selected word line to program the memory cells of the selected memory cell row.

15. The method according to claim 14, characterized in that Before providing a programming pulse to the selected word line in an ISPP manner to program the memory cells of the selected memory cell row, the method further includes: providing a second pre-programming pulse to the selected word line to pre-program the second type of memory cells of the selected memory cell row; Among them, the target programming state of the second type of storage cell is a second target programming state, and after providing the second pre-programming pulse, the threshold voltage of the second type of storage cell is less than the second target threshold voltage, and the second target threshold voltage is the threshold voltage corresponding to the second target programming state.

16. The method according to claim 14, characterized in that The distance between the state of the first type of memory cell before providing the first pre-programming pulse and the first target programming state is greater than the distance between the state of at least one other memory cell in the selected memory cell row and the respective target programming state.

17. The method according to claim 14, characterized in that A difference between a voltage of the first pre-programming pulse and a first target programming voltage is less than a first difference threshold, and the first target programming voltage is set based on a programming voltage required for a programming state of the first type of memory cells to reach the first target programming state.

18. The method of claim 14, wherein: Before providing the first pre-programming pulse to the selected word line, the method further comprises: The first pre-program pulse is determined based on a difference between a current threshold voltage of at least one memory cell of the first type of memory cells and the first target threshold voltage.

19. The method according to claim 18, characterized in that The step of determining the first pre-programming pulse based on a difference between a current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage comprises: If the difference between the current threshold voltage of at least one memory cell in the first type of memory cells and the first target threshold voltage exceeds a second difference threshold, the first pre-programming pulse is configured for the first type of memory cells.

20. The method according to any one of claims 14 to 19, characterized in that: The providing a first pre-programming pulse to a selected word line to pre-program the first type of memory cells of the selected memory cell row comprises: In response to a program instruction from a controller, the first pre-program pulse is provided to the selected word line to pre-program the first type of memory cells of the selected memory cell row.

21. The method of claim 20, wherein: The memory cells in the memory are triple-level cells (TLC).

22. The method according to any one of claims 14 to 19, characterized in that: Before providing a first pre-programming pulse to a selected word line to pre-program the first type of memory cells in the selected memory cell row, the method further comprises: In response to a programming instruction from a controller, providing a programming pulse to the selected word line using the ISPP method to perform a first programming on the memory cells of the selected memory cell row; The step programming ISPP method is used to provide a programming pulse to the selected word line to program the selected memory cell row, including: Providing a programming pulse to the selected word line by adopting the ISPP method to perform a second programming on the memory cells of the selected memory cell row; The number of programmed states in the threshold voltage distribution of the selected memory cell row after the second programming is greater than the number of programmed states in the threshold voltage distribution of the selected memory cell row after the first programming.

23. The method of claim 22, wherein: The storage unit in the memory is a quad-level cell (QLC).

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