Method, device and storage medium for optimizing flash threshold distribution offset

Abstract

The application discloses a flash memory threshold distribution offset optimization method, device and storage medium, and relates to the technical field of memories.The method comprises the following steps: obtaining working environment information of a storage unit of a flash memory device; inputting the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit; and adjusting an initial threshold voltage range of the storage unit according to the first threshold offset to obtain a target threshold voltage range.The application can improve the reliability and integrity of data and prolong the overall service life of the flash memory device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a flash memory threshold distribution offset optimization method, device and storage medium. BACKGROUND

[0002] In the long-term use of flash memory storage systems, due to the cumulative effect of programming and erasing, temperature, humidity, the number of erase-write times of flash physical blocks, flash operating voltage, flash type, external electronic and magnetic field interference and other factors, the threshold voltage distribution of reading correct data will gradually change, resulting in a decrease in data reliability and performance.

[0003] In order to solve the influence of threshold voltage change, at present, a specific and fixed threshold distribution offset is usually set in the flash firmware. When a data error is detected, all threshold distribution offsets are traversed in a loop. For each offset, the firmware will try to apply it to adjust or interpret the stored data. If the data can be successfully corrected and verified under a certain offset, that offset is considered valid, and the firmware will use it to update the stored data. This method relies on the accuracy and comprehensiveness of the preset offset. If the offset is not properly set, the data correction effect may be affected.

[0004] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide a flash memory threshold distribution offset optimization method, device and storage medium, aiming to solve the technical problem of how to detect and dynamically adjust the threshold voltage of flash memory in real time and improve data reliability.

[0006] To achieve the above purpose, the present application provides a flash memory threshold distribution offset optimization method, which comprises:

[0007] Obtain the working environment information of the storage unit of the flash memory device;

[0008] Input the working environment information into the preset target threshold offset prediction model to obtain the first threshold offset of the storage unit;

[0009] Adjust the initial threshold voltage range of the storage unit according to the first threshold offset to obtain the target threshold voltage range.

[0010] In an embodiment, before the step of obtaining the working environment information of the storage unit of the flash memory device, the method further comprises:

[0011] After the flash memory device enters the initialization operation, perform erase-write and read operations on the storage unit.

[0012] determining the initial threshold voltage range of the memory cell according to the results of the erase operation and the read operation.

[0013] In an embodiment, the step of determining the initial threshold voltage range of the memory cell according to the results of the erase operation and the read operation comprises:

[0014] performing an erase operation on the memory cell to reset the threshold voltage of the memory cell to the highest state;

[0015] performing a read operation on the erased memory cell to obtain an upper limit value of the threshold voltage;

[0016] performing at least one set of programming operation and read operation on the memory cell according to the test data sequence under a preset working environment to obtain a lower limit value of the threshold voltage;

[0017] determining the initial threshold voltage range according to the upper limit value of the threshold voltage and the lower limit value of the threshold voltage.

[0018] In an embodiment, the method further comprises:

[0019] performing an erase test and a read test on the memory cell according to the working environment information when it is detected that the initialization operation is completed;

[0020] obtaining a real-time threshold voltage corresponding to the read test under each working environment information;

[0021] determining an initial threshold offset prediction model, and training the initial threshold offset prediction model according to the real-time threshold voltage and the working environment information to obtain a target threshold offset prediction model.

[0022] In an embodiment, the target threshold offset prediction model is a time series analysis model, and the step of inputting the working environment information into the preset target threshold offset prediction model to obtain the first threshold offset of the memory cell comprises:

[0023] inputting the working environment information into the time series analysis model;

[0024] determining the first threshold voltage offset of the memory cell at a preset time according to the time series analysis model.

[0025] In an embodiment, the method further comprises, after the step of determining the first threshold voltage offset of the memory cell at the preset time:

[0026] determining whether to trigger an adjustment operation according to the first threshold voltage offset;

[0027] if the first threshold voltage offset is greater than or equal to a preset threshold value of the voltage offset, triggering the adjustment operation;

[0028] The initial threshold range is adjusted according to the first threshold voltage offset to obtain a target threshold voltage range.

[0029] In an embodiment, the method further comprises:

[0030] acquiring and identifying a storage region with abnormal threshold voltage offset according to the threshold voltage offset of each storage unit;

[0031] confirming the storage region with abnormal threshold voltage offset as a first storage region and other storage regions as second storage regions;

[0032] migrating data of the first storage region to the second storage region.

[0033] In an embodiment, confirming the storage region with abnormal threshold voltage offset as a first storage region and other storage regions as second storage regions comprises:

[0034] calculating an average value of the threshold voltage offset;

[0035] if the threshold voltage offset is greater than or less than the average value, determining the storage unit corresponding to the threshold voltage offset as a first storage region;

[0036] if the threshold voltage offset is equal to the average value, determining the storage unit corresponding to the threshold voltage offset as a second storage region.

[0037] In addition, to achieve the above object, the present application further provides a flash memory device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the optimization method of the flash memory threshold distribution offset as described above.

[0038] In addition, to achieve the above object, the present application further provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the optimization method of the flash memory threshold distribution offset as described above.

[0039] The application provides a method for optimizing a flash memory threshold distribution offset, obtaining and inputting working environment information of a storage unit of a flash memory device into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit; the target threshold offset prediction model is used to predict the threshold offset, which can comprehensively consider the influence of multiple factors such as the number of erasing and writing times, temperature, humidity, flash working voltage, flash type and external electronic magnetic field interference on the threshold offset, and improve the accuracy and reliability of the prediction. According to the first threshold offset, the initial threshold voltage range of the storage unit is adjusted to obtain a target threshold voltage range; by adjusting the threshold voltage range, it is helpful to reduce the read / write errors caused by voltage fluctuations, improve the reliability and integrity of data, and prolong the overall life of the flash memory device. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0042] Figure 1 A flowchart is provided for the first embodiment of the method for optimizing the flash memory threshold distribution offset of the application;

[0043] Figure 2 A detailed flowchart is provided for the first embodiment of the method for optimizing the flash memory threshold distribution offset of the application;

[0044] Figure 3 A flowchart is provided for the second embodiment of the method for optimizing the flash memory threshold distribution offset of the application;

[0045] Figure 4 A flowchart is provided for the fourth embodiment of the method for optimizing the flash memory threshold distribution offset of the application;

[0046] Figure 5 A device structure diagram of a hardware running environment involved in the method for optimizing the flash memory threshold distribution offset in the embodiments of the application.

[0047] The purpose of the application, functional features and advantages will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0048] It should be understood that the specific embodiments described herein are merely illustrative of the present application and do not limit the present application.

[0049] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and specific embodiments.

[0050] The main solution of the embodiment of the present application is: obtaining the working environment information of the storage unit of the flash memory device, the working environment information including the number of erasing and writing, temperature and humidity; inputting the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit; adjusting the initial threshold voltage range of the storage unit according to the first threshold offset to obtain a target threshold voltage range.

[0051] At present, the influence of threshold voltage change is usually solved by setting specific and fixed threshold distribution offset in the flash firmware. When detecting data errors, all threshold distribution offsets are traversed in a loop, and for each offset, the firmware tries to apply it to adjust or interpret the stored data. If the data can be successfully corrected and verified under a certain offset, the offset is considered valid, and the firmware will use it to update the stored data. This method depends on the accuracy and comprehensiveness of the preset offset. If the offset is not properly set or fails to cover all possible deviation cases, the effect of data correction may be affected.

[0052] The present application provides an optimization method for flash threshold distribution offset, obtains the working environment information of the storage unit of the flash memory device, and inputs the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit. Through the target threshold offset prediction model, the influence of multiple factors such as the number of erasing and writing, temperature, humidity, flash working voltage, flash type and external electronic magnetic field interference on threshold offset can be considered comprehensively to improve the accuracy and reliability of prediction. According to the first threshold offset, the initial threshold voltage range of the storage unit is adjusted to obtain a target threshold voltage range. By adjusting the threshold voltage range, it helps to reduce read / write errors caused by voltage fluctuations, improve the reliability and integrity of data, and prolong the overall life of the flash memory device.

[0053] It should be noted that the execution subject of the present embodiment can be a computing service device with network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, a Nandflash and its corresponding controller, an SSD and its corresponding controller, etc., or an electronic device, a program process exception monitoring device, etc. capable of realizing the above functions. The following takes a flash memory storage device as an example to describe the present embodiment and each of the following embodiments.

[0054] Based on this, the embodiment of the present application provides a flash memory threshold distribution offset optimization method, referring to Figure 1 , Figure 1 The flowchart of the first embodiment of the flash memory threshold distribution offset optimization method of the present application is shown.

[0055] In this embodiment, the flash memory threshold distribution offset optimization method includes steps S100-S300:

[0056] Step S100, obtain the working environment information of the storage unit of the flash memory device.

[0057] It should be noted that the flash memory (Flash Memory) is also called flash storage and read-only memory. It is a non-volatile electronic storage device. It can maintain the stored data when not powered by the outside world, and has the characteristics of high information density, large read-write capacity, short random access time, etc. Flash memory changes the charge state in the floating gate by controlling the gate voltage, thereby realizing data reading and writing. The number of erase and write times refers to the number of times a flash memory unit undergoes a programming and erasing operation, and the complete process of a flash memory unit undergoing a programming and erasing operation is called a P / E (Program / Erase) cycle.

[0058] In this embodiment, the working environment information includes temperature, humidity, the number of erase and write times of the flash physical block, the flash operating voltage, the flash type, and the external electronic and magnetic field interference. By obtaining the working environment information of the flash memory device and analyzing these information to adjust the threshold voltage range of the storage unit. After completing the information acquisition, the collected data is sorted into a format suitable for input into the prediction model, which usually includes fields such as timestamp, temperature, humidity, and erase and write times.

[0059] Step S200, input the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit.

[0060] In this embodiment, the current working environment information is input into the target threshold offset prediction model to obtain a first threshold offset of each storage unit.

[0061] In one possible implementation, referring to Figure 2 , the target threshold offset prediction model is a time series analysis model, and step S200 can include steps S210-S220:

[0062] Step S210, input the working environment information into the time series analysis model.

[0063] Step S220, according to the time series analysis model, determine the first threshold voltage offset of the storage unit at a preset time.

[0064] In this embodiment, a simple exponential smoothing is used to fit the drift trend of the threshold voltage. First, data collection is performed to obtain a series of threshold distribution shifts in chronological order, and the collected threshold distribution shifts should cover a sufficient time range to capture potential trends in the voltage. After collection, outliers in the data are checked and removed, which can be caused by measurement errors, hardware failures, or extreme operating conditions, etc. Second, a smoothing parameter a is selected, which is a parameter between 0 and 1 in simple exponential smoothing, used to control the degree of influence of historical observations on the current prediction. The closer the value of a to 1, the greater the influence of recent observations on the prediction; the closer the value of a to 0, the smaller the influence of recent observations on the prediction, and the greater the influence of historical data. The value of a can be selected by experiment or experience, or can be found by trial and error by trying different a values and comparing prediction errors. Then, an initial smoothing value S0 is selected, which represents the prediction or smoothing value at the first time point, which can be the first observation of the data sequence or the average of the data sequence. Using the selected a value and the initial smoothing value, the smoothing value (i.e. the prediction value) at each time point is calculated according to the recursive formula of simple exponential smoothing. The recursive formula is as follows: St = aYt + (1-a)St-1; where St is the smoothing value (also the prediction value) at time t, Yt is the actual observation at time t, and St-1 is the smoothing value at time t-1. After obtaining the smoothing values of the entire data sequence, the smoothing value at the last time point is used as the starting point for prediction at future time points.

[0065] In this embodiment, the performance of the prediction can also be evaluated using the leave-one-out method or cross-validation. The data set is divided into a training set and a test set, the training set is used to fit the model, and the test set is used to evaluate the accuracy of the prediction. The prediction error is calculated, and the smoothing parameter is adjusted as needed.

[0066] In another possible implementation, a machine learning model (such as random forest, gradient boosting tree GBDT, neural network, etc.) can be used to analyze the drift trend of the predicted threshold voltage offset. First, a large amount of data on the change of threshold voltage over time is needed. These data can come from actual running storage devices, including data under different temperature, usage frequency, write / erase cycle, etc. conditions. Second, feature extraction is performed: key features such as temperature, write / erase times, storage time, etc. that may have a direct relationship with the drift of threshold voltage are extracted from the collected data. According to the characteristics of the data and the prediction requirements, a suitable prediction model is selected, such as: random forest, gradient boosting tree GBDT, neural network, etc. Then, model training and verification are performed: the model is trained using historical data, and the accuracy and generalization ability of the model are evaluated by cross-validation, etc. Finally, using the trained model, the drift trend of the future threshold voltage is predicted according to the current and future conditions (such as the expected write / erase times, temperature, etc.).

[0067] Step S300, adjusting the initial threshold voltage range of the storage unit according to the first threshold voltage offset, to obtain a target threshold voltage range.

[0068] In this embodiment, the initial threshold voltage range of the storage unit is adjusted according to the predicted first threshold voltage offset. The upper and lower limits of the threshold voltage are shifted accordingly to compensate for the aging effect. The adjusted threshold voltage range is applied to the flash memory device, and it is ensured that all related firmware and drivers have been updated. After adjustment, the performance of the flash memory device is continuously monitored, including the write / erase times, temperature and threshold voltage offset, etc. to ensure that the adjusted settings are effective.

[0069] In this embodiment, the collected threshold voltage offset data measured under different conditions (such as different temperatures, different voltage biases, different stress conditions, etc.) is statistically analyzed to find the relationship between the threshold voltage offset and various influencing factors. Using regression analysis and other methods, a target threshold offset prediction model is established, and the expected working conditions (such as temperature range, write / erase times range, etc.) are input to predict the drift of the threshold voltage under these conditions. Evaluate the impact of the drift trend on device performance to determine whether the initial threshold voltage range needs to be adjusted. The initial threshold voltage range is adjusted according to the predicted threshold voltage drift. By predicting and adjusting the threshold voltage range, it can ensure that the flash memory maintains stable performance under different working conditions, reduces performance fluctuations caused by threshold voltage drift, and prolongs its service life.

[0070] In this embodiment, by monitoring and adjusting the threshold voltage range in real time, a stable voltage state of the storage cell can be ensured during read and write operations, thereby reducing the risk of data errors and loss and improving data reliability. A reasonable threshold voltage range can improve the read and write speed and efficiency of the flash memory device, reduce read and write latency and errors caused by voltage mismatch, and optimize read and write performance. By predicting and compensating for the drift trend of the threshold voltage, damage to the storage cell caused by excessively high or low voltage can be reduced, extending the lifespan of the flash memory device. In addition, different operating environments (such as temperature, humidity, external electromagnetic interference, etc.) may affect the threshold voltage of the flash memory device. By monitoring and adjusting the threshold voltage range in real time, the flash memory device can better adapt to different operating environments.

[0071] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 3 Steps S01 to S02 may be included before step S100:

[0072] Step S01: After the flash memory device enters the initialization operation, erase, write, and read operations are performed on the storage cells.

[0073] Step S02: Determine the initial threshold voltage range of the memory cell based on the results of the erase / write and read operations.

[0074] In this embodiment, performing erase, write, and read operations on the memory cells during the initialization phase of the flash memory device is an important step to determine their initial threshold voltage range. This helps to understand the basic performance characteristics of the memory cells and provides a basis for subsequent data writing, reading, and error correction operations.

[0075] In this embodiment, after the flash memory device enters the initialization phase, firstly, the set of memory cells to be initialized and whose initial threshold voltage range is determined is identified. This can be all blocks, pages, or individual cells of the entire flash memory chip. Secondly, erase / write operations are performed on the selected memory cells. In flash memory, erase / write operations typically reset the state of all memory cells to "1" (or the highest threshold voltage state). After the erase / write operations are completed, read operations are performed on the erased memory cells. Read operations can be accomplished by sending a read command to the flash memory controller and specifying the block, page, or memory cell to be read. During the read process, the flash memory controller determines the state of the memory cell (i.e., whether it stores "0" or "1") based on the configured read voltage threshold, gradually changes the read voltage threshold, and records the state transition points of the memory cells at different voltages, thereby inferring the distribution of the threshold voltage.

[0076] Exemplarily, a scrub operation is performed to reset the threshold voltage of all memory cells to below 1 V. An initial read reference voltage of 0.5 V is selected and a read operation is performed. Since the threshold voltage of all memory cells is below 1 V, they are all successfully read as logical "1"s. The read reference voltage is gradually increased: next, the read reference voltage is gradually increased, such as from 0.6 V to 0.7 V, 0.8 V, etc., and the read operation is repeated. At a certain read reference voltage (e.g., 0.9 V), some memory cells will no longer turn on, indicating that their threshold voltage is higher than the voltage.

[0077] In one possible implementation, step S02 can include the following steps:

[0078] A scrub operation is performed on the memory cells to reset the threshold voltage of the memory cells to the highest state.

[0079] A read operation is performed on the erased memory cells to obtain an upper limit of the threshold voltage.

[0080] At least one set of program and read operations are performed on the memory cells according to a test data sequence under a preset working environment to obtain a lower limit of the threshold voltage.

[0081] An initial threshold voltage range is determined according to the upper limit of the threshold voltage and the lower limit of the threshold voltage.

[0082] In this embodiment, an erase command is sent to the flash controller and the memory block or page to be erased is specified. It is confirmed that the scrub operation has been successfully completed and all selected memory cells have been reset to the erased state (i.e., the logical "1" state). Since the scrub operation resets the threshold voltage of the memory cells to the highest state, the threshold voltage of the erased state can be regarded as the upper limit of the initial threshold voltage range.

[0083] After the erase operation is completed, a read reference voltage range is selected. The read reference voltage range can be selected based on the flash memory specification and past experience. The range should cover the threshold voltage distribution of the memory cells after the erase operation. Within the selected range, a series of read reference voltages are set. The interval (step size) between the read reference voltages should be small enough to accurately depict the threshold voltage distribution. For each read reference voltage, a read operation is performed on the memory cells. For each read reference voltage, a read command is sent to the flash controller, and the memory block or page to be read and the read reference voltage value are specified. The flash controller performs the read operation on the memory cells according to the provided read reference voltage, and returns the state (usually logical "0" or "1") of each memory cell. For each read reference voltage, the voltage point at which the memory cell changes from logical "1" to logical "0" is recorded. This change point is an estimate of the threshold voltage of the memory cell. By collecting the change points of all memory cells at different read reference voltages, an estimated graph of the threshold voltage distribution can be generated. Finally, the initial threshold voltage range is determined based on the first threshold voltage and the plurality of second threshold voltages. The second threshold voltage obtained from the read operation is combined with the upper limit of the threshold voltage in the erase state to determine the initial threshold voltage range of the memory cells after erasing. The range can be a continuous interval starting from the upper limit of the threshold voltage in the erase state to the lowest second threshold voltage.

[0084] In a possible implementation, after step S02, the method for optimizing the flash threshold distribution offset can further include steps S03-S05:

[0085] Step S03, when detecting that the initialization operation is completed, performing an erase test and a read test on the memory cells according to the working environment information.

[0086] In this embodiment, the initialization process of the flash memory chip can be monitored by the flash controller. When the internal state register of the flash memory chip changes or an interrupt signal is received from the flash memory chip, the initialization operation is completed.

[0087] Alternatively, the initialization operation can be monitored by polling the state register. First, a state register address is defined, which is specified in the specification of the flash memory chip and is used to store the current state information of the chip. Second, a loop (polling) function is written in the flash controller, by which the value of the state register is read periodically. In the polling function, the read value of the state register is compared with a preset initialization completion flag (or a series of state codes). If the value of the state register indicates that the initialization is completed (i.e., the initialization completion flag is matched or the expected state code sequence is reached), the polling loop is exited, and an internal operation completion signal is generated or a corresponding interrupt service routine is triggered.

[0088] Optionally, the initialization operation is completed when receiving the interrupt signal from the flash chip. First, make sure that both the flash controller and the flash chip support the interrupt function, and their interrupt interfaces (such as GPIO pins) have been correctly connected. Second, configure the interrupt service routine in the flash controller, which is used to process the interrupt signal from the flash chip. During the initialization process of the flash chip, send a command to request an interrupt or set the corresponding register to generate an interrupt signal when the initialization is completed. When the flash chip completes the initialization and sends the interrupt signal, the interrupt controller of the flash controller will capture this signal and call the pre-configured interrupt service routine.

[0089] In this embodiment, when the initialization operation of the flash chip is completed, the real-time threshold voltage detection process is triggered to perform the erase-write test and the read test on the flash device. The flash controller sends a series of read-write commands to the flash chip, which are targeted at specific memory cells or blocks and set different voltage thresholds for trial.

[0090] In this embodiment, when the threshold voltage range of the memory cell is inferred through read-write operations, the real-time threshold voltage is obtained by using the "read retry" or "voltage threshold adjustment" method. First, determine the specific object to be tested and prepare the test data, which is used to verify the correctness of the read operation. The object to be tested can be the entire flash chip, a specific physical block, a page, or a single memory cell. Second, send a write command to the flash chip to write the prepared test data to the target memory cell or block. After the write operation is completed, check the status of the write operation to ensure that the data has been successfully written. Then, perform read retry. Set the initial read voltage threshold, which can be the default read voltage value of the flash chip or a preset starting value. Send a read command to the flash chip to try to read the data in the target memory cell or block at the currently set voltage threshold. Check the result of the read operation. If the read fails or the data is incorrect, adjust the read voltage threshold according to the specifications and algorithms of the flash chip, gradually increase or decrease the read voltage, until the voltage threshold range that can successfully and correctly read the data is found.

[0091] Step S04, obtaining the real-time threshold voltage corresponding to the read test under each working environment information.

[0092] In this embodiment, after the flash memory device is powered on, a special detection circuit or software tool is used to traverse each memory cell of the flash memory device, obtaining and recording its real-time threshold voltage. After ensuring that the flash memory device has been correctly connected to the test system or computer and the power supply is stable, according to the type and specifications of the flash memory device, select the appropriate detection tool and set appropriate detection parameters in the detection tool, such as voltage range, step size, detection speed, etc. These parameters can be set according to the specifications of the flash memory device and test requirements. Use the detection tool to traverse each memory cell of the flash memory device. This usually involves sending a series of read commands to the flash memory device and receiving the response data of the memory cell. During the traversal process, the detection tool measures and records the real-time threshold voltage of each memory cell. After the measurement is complete, record the measured real-time threshold voltage data and save it to an appropriate storage medium, such as a hard disk, database, or cloud storage, etc.

[0093] Optionally, during the process of traversing the flash memory device and measuring the real-time threshold voltage of each memory cell, first, connect the flash memory device to the detection tool through an appropriate interface (such as SPI or I 2 C interface). And configure the detection parameters required in the detection tool, including voltage range, step size, detection speed, scan mode (such as sequential scan or random access), etc. Secondly, the detection tool will generate an address sequence inside to access each memory cell in the flash memory device in turn. The address generation algorithm ensures that all memory cells can be traversed without omission or repetition. Then, according to the generated address, the detection tool sends a read command or a specific detection command to the flash memory device, which requests the flash memory device to provide the voltage information of the specified memory cell. The detection tool contains high-precision voltage detection circuits inside, which are used to measure the real-time threshold voltage of the memory cell in the flash memory device. These circuits usually have the characteristics of low noise, high stability and high resolution to ensure the accuracy of the measurement results. After sending the command, the detection tool will read the voltage data returned by the flash memory device, which reflects the voltage characteristics of the memory cell in a specific state. Finally, the detection tool will record the real-time threshold voltage data of each memory cell read and store it in the internal memory or external storage medium. The recorded data can include the address of the memory cell, the measured voltage value, the timestamp, etc.

[0094] Optionally, considering the capacity of the flash memory device and the limitation of detection speed, the entire traversal process may take a long time. Therefore, parallel processing or multi-threading techniques can be used to improve detection efficiency. First, a parallel processing strategy is designed, and the flash memory device is divided into multiple logical regions or partitions according to its capacity and the parallel capability of the system. Each partition can be independently subjected to voltage detection, thereby achieving parallel processing. Each partition is assigned an independent thread or processing unit responsible for the voltage detection task of that partition. Second, a thread pool containing multiple threads is created, and the threads in the thread pool can be reused as needed to reduce the overhead of thread creation and destruction. The voltage detection task of each partition is assigned to a thread in the thread pool. The thread obtains the task from the thread pool, performs voltage detection, and returns the result to the main thread or stores it in shared memory. To ensure data consistency and accuracy, a synchronization mechanism is set up. For example, mutex, semaphore, or condition variable can be used to synchronize operations between threads. Threads can communicate with each other using shared memory, message queues, or sockets. During the entire traversal process, performance indicators such as CPU usage, memory occupancy, and I / O bandwidth are monitored in real time, and the size of the thread pool, partition strategy, or synchronization mechanism is dynamically adjusted according to the usage of resources and performance monitoring results to optimize detection efficiency. Through the above steps and strategies, parallel processing or multi-threading techniques can be effectively used to improve the detection efficiency during the traversal process of the flash memory device. This not only shortens the detection time but also improves the overall performance and reliability of the system.

[0095] Optionally, the detection tool can be a dedicated test chip that integrates the necessary circuits and interfaces for connecting with the flash memory device and performing voltage detection. It can also be connected with the flash memory device through external circuits such as voltmeters, oscilloscopes, etc. to measure its voltage output under different states. AndroBench can also be used to trigger read and write operations of the flash memory device, thereby recording and observing voltage changes.

[0096] Exemplarily, for a 1GB NAND flash memory device, the following parameters are set during the real-time threshold voltage acquisition process: voltage range: 2.0V to 4.0V; step size: 0.01V; detection speed: 10,000 storage cells per second. During the traversal process, the detection tool will measure the voltage of each storage cell according to the set parameters. When the 100,000th storage cell is detected, its real-time threshold voltage is 3.25V.

[0097] In this embodiment, the threshold voltage offset can be calculated according to the average of the initial threshold voltage and the real-time threshold voltage. For example, the real-time threshold voltage Vt_real is 2.5V, the initial threshold voltage range Vinit_min is 2.0V, and Vinit_max is 2.4V, and then Vt_init_avg is (2.0V+2.4V) / 2=2.2V. Therefore, the threshold voltage offset AVt is 2.5V-2.2V=0.3V.

[0098] In step S05, the initial threshold offset prediction model is determined, and the initial threshold offset prediction model is trained according to the real-time threshold voltage and the working environment information to obtain the target threshold offset prediction model.

[0099] In this embodiment, after the data acquisition, the real-time threshold voltage, the number of erase-write tests, and the test temperature data are preprocessed to clean up abnormal values and missing values, and the data is standardized or normalized to generate a data set. The data set is divided into a training set, a validation set, and a test set, and the ratio is 70%, 15%, and 15%, respectively. A regression model is selected to predict the threshold offset, such as linear regression, polynomial regression, and neural network. The training set data is used to train the selected model, and the model hyperparameters are adjusted through cross-validation techniques. After training, the model performance is evaluated through the validation set, including accuracy and generalization ability. The model structure, parameters, or a new model are adjusted according to the validation results, and finally the target threshold offset prediction model is obtained.

[0100] In this embodiment, by establishing a target threshold offset prediction model based on the real-time threshold voltage, the number of erase-write tests, and the test temperature, the threshold offset of the storage device can be accurately predicted, which provides strong support for the maintenance and optimization of the device.

[0101] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as the above-mentioned first embodiment can be referred to the above introduction, and the subsequent will not be repeated. On this basis, after step S200, the following steps can be further included:

[0102] According to the first threshold voltage offset, it is determined whether to trigger the adjustment operation.

[0103] If the first threshold voltage offset is greater than or equal to the preset voltage offset threshold, the adjustment operation is triggered.

[0104] According to the first threshold voltage offset, the initial threshold range is adjusted to obtain the target threshold voltage range.

[0105] In the embodiment, a voltage offset threshold is set, and when the first threshold voltage offset exceeds a preset first threshold voltage, an adjustment operation is triggered. If it is predicted that the threshold voltage will drift in the low voltage direction, the lower limit of the threshold range of the read voltage is appropriately lowered to prevent misreading. If it is predicted that the threshold voltage will drift in the high voltage direction, the upper limit of the threshold range of the read voltage is raised.

[0106] In the embodiment, whether to trigger an adjustment operation is determined according to the first threshold voltage offset, and the initial threshold range is adjusted when necessary, so that unnecessary adjustments can be reduced by setting a threshold, resource allocation of the flash memory device can be optimized, resource utilization can be improved, and the service life of the flash memory can be prolonged.

[0107] Based on the first embodiment of the present application, in the fourth embodiment of the present application, the same or similar contents as the above-mentioned first embodiment can be referred to the above description, and will not be described hereinafter. On this basis, please refer to Figure 4 , after step S30, the optimization method of the flash memory threshold distribution offset further includes steps B10-B30:

[0108] In step B10, the threshold voltage offset of each storage unit is obtained and identified to identify a storage area with abnormal threshold voltage offset.

[0109] In step B20, the storage area with abnormal threshold voltage offset is confirmed as a first storage area, and other storage areas are confirmed as second storage areas.

[0110] In step B30, the data of the first storage area is migrated to the second storage area.

[0111] In this embodiment, first, the threshold voltage shift data of the storage blocks is collected and statistically analyzed. A hardware monitoring tool or software agent is used to periodically read the threshold voltage shift data of each storage block in the storage system. The threshold voltage shift data includes the unique identifier of each storage block, the current threshold voltage shift value, and possibly other performance indicators (such as read-write times, error rates, etc.). The collected data is classified and sorted, grouped by storage block or area. Second, the average, standard deviation, maximum and minimum of the threshold voltage shift of each storage block or area are calculated. Identify the storage blocks or areas with abnormal threshold voltage shift (such as much higher or lower than the average). According to the characteristics and requirements of the storage system, set a reasonable threshold voltage shift range as the judgment standard. This range can be determined based on the historical performance of the storage blocks, manufacturer's recommendations or actual operation of the system. Compare the statistical analysis results with the set threshold range. Identify the area where the storage unit with threshold voltage shift exceeding the abnormal threshold as the first storage area, and confirm the area where all storage units not identified as the first storage area as the second storage area. Backup the data in the first storage area to prevent data loss during migration. Migrate all data in the first storage area to the second storage area.

[0112] After migration is complete, evaluate the performance of the migrated storage system, including read-write speed, delay and error rate, etc. Compare the performance data before and after migration to confirm whether the migration has brought performance improvement. After data migration, use data consistency checking tools or scripts to check whether the migrated data is consistent with the original data to verify the integrity and accuracy of the data, ensuring that there is no data loss or damage. Finally, based on the migration results and performance evaluation feedback, further adjust and optimize the layout and configuration of the storage system. Minimize the risks and problems during migration.

[0113] In this embodiment, a load balancing strategy is adopted to dynamically adjust the data layout according to the threshold voltage shift and current load of the storage blocks. Avoid concentrating too much data on a few storage blocks with declining performance to reduce read-write conflicts and wear of these blocks. When adjusting the data layout, the remaining life and write limit of the storage blocks can also be considered. Through data migration and relocation, ensure that the wear level of all storage blocks is as consistent as possible to extend the overall life.

[0114] In a possible implementation, step B20 can further include the following steps:

[0115] Calculate the average of the threshold voltage shift.

[0116] If the threshold voltage shift is greater than or less than the average, determine the storage unit corresponding to the threshold voltage shift as the first storage area.

[0117] If the threshold voltage offset is equal to the average value, the storage unit corresponding to the threshold voltage offset is determined as the second storage area.

[0118] In this embodiment, the average value of the threshold voltage offset is calculated, and the threshold voltage offset of each storage unit is conditionally judged. If the threshold voltage offset of a certain storage unit is greater than or less than the average value of the threshold voltage offset, the storage unit is determined as the first storage area. If the threshold voltage offset of a certain storage unit is equal to the average value of the threshold voltage offset, the storage unit is determined as the second storage area. Finally, the classification results of each storage unit are recorded and applied to actual storage management, data access optimization or error correction strategy as needed.

[0119] In this embodiment, after dynamically adjusting the threshold range of the storage unit according to the real-time monitored threshold distribution offset data and analysis results, the data write strategy can also be optimized, such as adjusting the programming parameters, the erase strategy and the FTL (Flash Translation Layer) application layer algorithm.

[0120] When adjusting the programming parameters, the programming voltage level is adjusted according to the new threshold range to ensure that the data can be accurately written to the correct storage state. The width and number of programming pulses are optimized to reduce programming errors and improve programming speed. Verification reading steps are added to ensure that the written data is accurate and correct.

[0121] When optimizing the erase strategy, the voltage threshold of the erase-write operation is dynamically adjusted according to the change of the threshold offset to ensure that the old data is completely erased. Those storage blocks with large threshold offset or close to the life limit are preferentially erased to balance the wear of the storage blocks. Verification steps are performed after the erase-write operation to ensure that the storage blocks are completely emptied and avoid data residue.

[0122] When adjusting the FTL application layer algorithm, the garbage collection strategy is optimized according to the new threshold range and the state of the storage block to reduce the impact of invalid data on performance. The wear leveling algorithm is strengthened to ensure that the wear degree of all storage blocks is as consistent as possible, prolonging the overall life. According to the change of the threshold offset, the layout of the data in the storage block is adjusted to reduce read-write conflicts and improve performance.

[0123] In this embodiment, by dynamically adjusting the threshold range of the storage unit and optimizing the data write strategy through real-time monitoring of the threshold distribution offset data and analysis results, the reliability of the data and the performance of the storage system can be ensured.

[0124] It should be noted that the above examples are only used for understanding the present application and do not constitute a limitation on the optimization method of the flash memory threshold distribution offset of the present application, and more forms of simple transformation based on this technical concept are within the protection scope of the present application.

[0125] The present application provides an optimization device for flash memory threshold distribution offset, which comprises at least one processor and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the optimization method for flash memory threshold distribution offset in the above-mentioned embodiment one.

[0126] Reference will be made to the following description of the embodiments of the present application, taken in conjunction with the accompanying drawings, in which Figure 5 which shows a structural schematic diagram of the optimization device for flash memory threshold distribution offset suitable for being used to implement the embodiments of the present application. The optimization device for flash memory threshold distribution offset in the embodiments of the present application can include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistant), PADs (Portable Application Description), PMPs (Portable Media Player), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, products with embedded electronic storage functions, and the like. Figure 5 The shown optimization device for flash memory threshold distribution offset is only an example and should not bring any limitation on the functions and use range of the embodiments of the present application.

[0127] As Figure 5As shown, the flash threshold distribution offset optimization device can include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to programs stored in a read only memory (ROM) 1002 or programs loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for the operation of the flash threshold distribution offset optimization device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the flash threshold distribution offset optimization device to communicate with other devices wirelessly or by wire to exchange data. Although the flash threshold distribution offset optimization device with various systems is shown in the figure, it should be understood that all the shown systems are not required to be implemented or possessed. More or fewer systems can be alternatively implemented or possessed.

[0128] In particular, according to embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the methods of the embodiments disclosed in the present application are performed.

[0129] The flash threshold distribution offset optimization device provided by the present application adopts the flash threshold distribution offset optimization method in the above-mentioned embodiments, and can solve the technical problem of how to detect and dynamically adjust the threshold voltage of the flash memory in real time and improve data reliability. Compared with the prior art, the flash threshold distribution offset optimization device provided by the present application has the same beneficial effects as the flash threshold distribution offset optimization method provided by the above-mentioned embodiments, and other technical features in the flash threshold distribution offset optimization device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0130] It is to be understood that the various parts of the disclosure can be implemented in hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0131] The above description is merely illustrative of the application and not restrictive.

[0132] The application provides a computer readable storage medium having stored thereon computer readable program instructions (i.e., a computer program) for performing the optimization method of the flash threshold distribution offset in the above embodiments.

[0133] The computer readable storage medium provided by the application may, for example, be a U disk, but is not limited to an electric, magnetic, optical, electromagnetic, infrared, or semiconductor system, system or device, or any combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electric connection with one or more conductive wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present embodiment, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer readable storage medium can be transmitted by any suitable medium, including but not limited to an electric wire, an optical cable, an RF (Radio Frequency), etc., or any suitable combination thereof.

[0134] The above computer readable storage medium can be included in the optimization device of the flash threshold distribution offset; or can exist separately and not be assembled into the optimization device of the flash threshold distribution offset.

[0135] The computer readable storage medium described above carries one or more programs, when the one or more programs are executed by the flash threshold distribution offset optimization device, the flash threshold distribution offset optimization device: obtains working environment information of a storage unit of a flash device, the working environment information includes erasing times, temperature and humidity; inputs the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit; and adjusts an initial threshold voltage range of the storage unit according to the first threshold offset to obtain a target threshold voltage range.

[0136] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0137] The flow diagrams and the block diagrams in the drawings are illustrations of architectures, functionalities, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a procedure, or a part of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in a different order than that noted in the figures. For example, two blocks noted in succession can in fact be executed substantially concurrently or in the opposite order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, can be implemented by dedicated hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0138] The modules involved in the embodiments of the present application can be implemented in a software manner or in a hardware manner. In some cases, the name of the module does not constitute a limitation on the module itself.

[0139] The readable storage medium provided by the application is a computer readable storage medium, which stores computer readable program instructions (i.e. computer programs) for executing the above-mentioned optimization method of flash threshold distribution offset, and can solve the technical problem of how to detect and dynamically adjust the threshold voltage of the flash memory in real time and improve data reliability. Compared with the prior art, the computer readable storage medium provided by the application has the same beneficial effects as the optimization method of flash threshold distribution offset provided by the above-mentioned embodiments, and will not be described here.

[0140] The above-mentioned is only part of the embodiments of the application, and does not limit the patent scope of the application. Any equivalent structural transformation, direct / indirect application in other related technical fields based on the technical concept of the application and the content of the specification and drawings are included in the patent protection scope of the application.

Claims

1. A method for optimizing flash memory threshold distribution offset, characterized in that, The method comprises: acquiring working environment information of a storage unit of a flash memory device; inputting the working environment information into a preset target threshold offset prediction model to obtain a first threshold offset of the storage unit; adjusting an initial threshold voltage range of the storage unit according to the first threshold offset to obtain a target threshold voltage range; acquiring and identifying a storage area with an abnormal threshold voltage offset according to threshold voltage offsets of each storage unit; confirming the storage area with the abnormal threshold voltage offset as a first storage area and other storage areas as second storage areas, comprising: calculating an average value of the threshold voltage offsets; if the threshold voltage offset is greater than or less than the average value, determining that the storage unit corresponding to the threshold voltage offset is the first storage area; if the threshold voltage offset is equal to the average value, determining that the storage unit corresponding to the threshold voltage offset is the second storage area; migrating data of the first storage area to the second storage area.

2. The method of claim 1, wherein, The method further comprises, before the step of acquiring the working environment information of the storage unit of the flash memory device: performing an erase operation and a read operation on the storage unit after the flash memory device enters an initialization operation; determining the initial threshold voltage range of the storage unit according to results of the erase operation and the read operation.

3. The method of claim 2, wherein, The step of determining the initial threshold voltage range of the storage unit according to the results of the erase operation and the read operation comprises: performing an erase operation on the storage unit to reset the threshold voltage of the storage unit to a highest state; performing a read operation on the erased storage unit to obtain an upper limit value of the threshold voltage; performing at least one set of programming operation and read operation on the storage unit according to a test data sequence under a preset working environment to obtain a lower limit value of the threshold voltage; determining the initial threshold voltage range according to the upper limit value and the lower limit value of the threshold voltage.

4. The method of claim 2, wherein, The method further comprises: after detecting completion of the initialization operation, performing an erase test and a read test on the storage unit according to the working environment information; acquiring real-time threshold voltages corresponding to the read test under each working environment information; determining an initial threshold offset prediction model and training the initial threshold offset prediction model according to the real-time threshold voltages and the working environment information to obtain the target threshold offset prediction model.

5. The method of claim 1, wherein, The target threshold offset prediction model is a time series analysis model, and the step of inputting the working environment information into the preset target threshold offset prediction model to obtain the first threshold offset of the storage unit comprises: inputting the working environment information into the time series analysis model; determining the first threshold voltage offset of the storage unit at a preset time according to the time series analysis model.

6. The method of claim 5, wherein, The method further comprises, after the step of determining the first threshold voltage offset of the storage unit at the preset time: judging whether to trigger an adjustment operation according to the first threshold voltage offset. If the first threshold voltage offset is greater than or equal to a preset threshold voltage offset, an adjustment operation is triggered. The initial threshold voltage range is adjusted according to the first threshold voltage offset to obtain the target threshold voltage range.

7. A flash memory device, comprising: The device comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the optimization method of the flash memory threshold distribution offset according to any one of claims 1 to 6.

8. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the optimization method of the flash memory threshold distribution offset according to any one of claims 1 to 6. The storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the optimization method of the flash memory threshold distribution offset according to any one of claims 1 to 6.

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