Packaging method of IGCT device and packaging structure of IGCT device

Abstract

The invention relates to a packaging method of an IGCT device and a packaging structure of the IGCT device, and the packaging method of the IGCT device comprises the steps: providing an electrode and a wafer; forming a patterned interconnection material layer on the surface of the electrode, wherein the interconnection material layer comprises a plurality of interconnection material units arranged at intervals; arranging the wafer on one side, far away from the electrode, of the interconnection material layer; enabling the interconnection material unit to deform by adopting a bonding process or a welding process so as to connect the wafer and the electrode; wherein at least two adjacent and deformed interconnection material units are partially connected. According to the packaging structure, a space for releasing thermal stress is provided in the interconnection process of the wafer and the electrode, the risk of buckling deformation caused by thermal stress in the interconnection process is reduced or avoided, and therefore the reliability of the packaging structure of the IGCT device is improved while the thermal resistance optimization effect is not affected.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a packaging method of an IGCT device and a packaging structure of an IGCT device. Background Art

[0002] Integrated Gate-Commutated Thyristor (IGCT) is a fully controlled power device with the largest single-tube capacity. It is widely used in fields such as DC transmission, smart grid, power converter, and power inverter due to its superior performance such as large capacity, fast switching speed, low switching loss, and high current rise rate (di / dt) tolerance. It has broad prospects and huge future development space.

[0003] IGCT devices are mainly composed of gate-commutated thyristor (GCT) components and driver circuit boards connected to the lead electrodes. Among them, the GCT component is the core component of the IGCT device, which is mainly composed of semiconductor chips and package shells. The package shell includes a shell base, a gate assembly, a cathode sheet, an anode sheet, a shell cover, etc. Among them, the gate assembly is mainly composed of a gasket, an elastic support, an insulating seat and a gate lead ring.

[0004] The general packaging structure is a five-layer structure composed of an anode copper electrode, an anode molybdenum sheet, a silicon chip, a cathode molybdenum sheet, and a cathode copper electrode, and the electrical connection is achieved through mechanical pressure rigid contact. However, with the continuous improvement of the power level of IGCT devices, higher requirements are placed on the thermal resistance of semiconductor device packaging. Therefore, how to reduce the thermal resistance of semiconductor devices during the whole wafer packaging of GCT components or other power semiconductor devices, while avoiding the problem of sample warping and deformation under thermal stress, has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] Based on this, it is necessary to provide a packaging method and a packaging structure of an IGCT device to reduce or avoid the warping deformation problem during the interconnection process, and to improve the reliability of the packaging structure of the IGCT device while reducing the thermal resistance of the IGCT device.

[0006] In a first aspect, the present application provides a packaging method for an IGCT device, comprising:

[0007] providing an electrode and a wafer;

[0008] forming a patterned interconnect material layer on the surface of the electrode, wherein the interconnect material layer comprises a plurality of interconnect material units arranged at intervals;

[0009] placing the wafer on a side of the interconnect material layer away from the electrode;

[0010] Using a bonding process or a welding process to deform the interconnect material unit so as to connect the wafer and the electrode;

[0011] Wherein, at least two adjacently arranged and deformed interconnected material unit portions are connected.

[0012] In one embodiment, forming a patterned interconnect material layer on the surface of the electrode includes:

[0013] Each of the interconnection material units is arranged on the surface of the electrode according to a set track to form the interconnection material layer.

[0014] In one of the embodiments, the set trajectory is symmetrically arranged on the surface of the electrode based on a central axis, and the central axis is parallel to the surface of the electrode and passes through the geometric center of the electrode.

[0015] In one embodiment, the shape of the set trajectory includes at least one of a concentric ring shape, a spiral shape, a radial shape, and a grid shape.

[0016] In one embodiment, the distance between two adjacent interconnect material units ranges from 50 μm to 100 μm.

[0017] In one of the embodiments, the orthographic projection area of ​​the interconnect material layer toward the electrode is 80% to 90% of the total area of ​​the electrode.

[0018] In one embodiment, after providing an electrode and a wafer and before forming a patterned interconnect material layer on the surface of the electrode, the packaging method of the IGCT device includes:

[0019] The wafer and the electrode are pre-metallized to form a first pre-metal layer covering the wafer and a second pre-metal layer covering the electrode, wherein the first pre-metal layer covers the surface of the wafer close to the electrode, and the second pre-metal layer covers the surface of the electrode close to the wafer.

[0020] In one embodiment, the materials of the first pre-metal layer and the second pre-metal layer are bondable with the material of the interconnection material unit.

[0021] In one embodiment, the material of the first pre-metal layer and the second pre-metal layer includes at least one of metal gold and metal silver.

[0022] In one embodiment, the first pre-metal layer, the second pre-metal layer and the interconnect material unit are made of at least one material.

[0023] In one of the embodiments, the material of the interconnection material unit is conductive.

[0024] In one embodiment, the material of the interconnection material unit includes one of a tin-based material, a solder-based material and a nano-silver material.

[0025] In a second aspect, the present application further provides a semiconductor interconnect structure, which is manufactured using the packaging method of the IGCT device provided in the first aspect of the present application.

[0026] In a third aspect, the present application further provides a packaging structure of an IGCT device, including:

[0027] electrode;

[0028] An interconnect material layer, located on one side surface of the electrode; wherein the interconnect material layer comprises a plurality of interconnect material units; the interconnect material units have a variable shape;

[0029] The wafer is located on a side of the interconnect material layer away from the electrode.

[0030] In one embodiment, the interconnect material unit has a first form and a second form; wherein,

[0031] When the interconnect material unit is in the first form, the interconnect material unit has a first height, and an area of ​​a cross section of the interconnect material unit parallel to the electrode gradually decreases in a direction away from the surface of the electrode;

[0032] When the interconnect material unit is in the second form, the electrode is connected to the wafer, and the interconnect material unit has a second height, and the second height is smaller than the first height.

[0033] In one of the embodiments, the shapes of the interconnected material units include cylindrical and truncated cone;

[0034] When the interconnect material unit is cylindrical, a ratio of an area of ​​a cross section of the interconnect material unit parallel to the electrode to a height of the interconnect material unit is in a range of 0.5 to 1;

[0035] When the interconnect material unit is in a truncated cone shape, the interconnect material unit includes a first top surface and a second top surface parallel to the electrode, and a ratio of an average area of ​​the first top surface and the second top surface to a height of the interconnect material unit is in a range of 0.5 to 1.

[0036] The packaging method of the IGCT device and the packaging structure of the IGCT device provided in the embodiments of the present application realize effective connection between the wafer and the electrode by forming a patterned interconnect material layer on the electrode and then connecting the interconnect material layer to the wafer; a patterned interconnect material layer is formed by a plurality of spaced-apart interconnect material units, which provides space for releasing thermal stress during the interconnection process, and utilizes the deformation process of the interconnect material unit during the connection process to absorb thermal stress, thereby reducing or avoiding the problem of warping and deformation of the wafer due to thermal stress during the interconnection process, thereby reducing the thermal resistance of the IGCT device and improving the reliability of the packaging structure of the IGCT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A flow chart of a packaging method for an IGCT device provided in one embodiment of the present application.

[0039] Figure 2 A structural schematic diagram corresponding to the step of forming a patterned interconnect material layer on the electrode surface in the packaging method of the IGCT device provided in one embodiment of the present application.

[0040] Figure 3 This is a schematic structural diagram corresponding to setting the shape of the track to a concentric ring shape in the packaging method of the IGCT device provided in one embodiment of the present application.

[0041] Figure 4 A schematic structural diagram corresponding to setting the shape of the track to a grid-like pattern in the packaging method of the IGCT device provided in one embodiment of the present application.

[0042] Figure 5 A schematic diagram of the structure corresponding to setting the shape of the track as a radial pattern in the packaging method of the IGCT device provided in one embodiment of the present application.

[0043] Figure 6 A structural schematic diagram of the step of deforming an interconnect material unit to connect a wafer and an electrode in a packaging method of an IGCT device provided in an embodiment of the present application.

[0044] Description of reference numerals: 200 - electrode; 210 - interconnection material layer; 220 - wafer; X1, X2 - interconnection material units; a - first top surface; b - second top surface. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In general semiconductor manufacturing processes, nanosilver low-temperature bonding technology with excellent heat transfer performance is usually used to package GCT devices or other power devices in the whole wafer to significantly reduce the thermal resistance of semiconductor devices. However, when using low-temperature bonding technology to package semiconductor devices in the whole wafer, serious sample warping and deformation may occur, which may even affect the thermal resistance optimization effect and the long-term reliability of semiconductor devices.

[0051] In view of this, the present application provides a packaging method and a packaging structure of an IGCT device to reduce or avoid the warping deformation or thermal stress deformation problem of the wafer during the interconnection process, thereby reducing the thermal resistance of the IGCT device while improving the reliability of the packaging structure of the IGCT device.

[0052] Figure 1 A flowchart of a packaging method for an IGCT device provided in one embodiment of the present application. Figure 1 The packaging method of the IGCT device provided in the embodiment of the present application includes the following steps S1 to S4.

[0053] Step S1: providing an electrode and a wafer.

[0054] Exemplarily, the material of the electrode is a metal material or an alloy material, for example, the material of the electrode includes one of metal copper, metal molybdenum, molybdenum-copper alloy, tungsten-copper alloy and copper diamond. Exemplarily, the material of the wafer includes single crystal silicon or silicon carbide.

[0055] Step S2: forming a patterned interconnect material layer on the surface of the electrode, wherein the interconnect material layer comprises a plurality of interconnect material units arranged at intervals.

[0056] Step S3: placing the wafer on a side of the interconnect material layer away from the electrode.

[0057] Step S4: using a bonding process or a welding process to deform the interconnection material unit so as to connect the wafer and the electrode; wherein at least two adjacently disposed and deformed interconnection material units are partially connected.

[0058] It should be noted that, during step S4, the thermal stress of the interconnect material layer is released as the interconnect material unit deforms and spreads; at the same time, since adjacent interconnect material units are spaced apart, the interconnect material units have enough space to release thermal stress, thereby reducing or avoiding the warping deformation problem of the IGCT device due to excessive thermal stress.

[0059] At the same time, it should be emphasized that the specific process method for deforming the interconnect material unit to connect the wafer and the electrode can be adjusted according to the actual process requirements. Technical personnel in this field can select a suitable interconnect process based on the difficulty of operation and other practical factors. It is only necessary to ensure that the selected process can meet the technical effects of "connecting the wafer and the electrode through the interconnect material layer" and "the interconnect material unit can reduce or eliminate thermal stress by deformation during the connection process". This application does not impose any restrictions on this.

[0060] It can be seen that the packaging method of the IGCT device as described above realizes the effective connection between the wafer and the electrode by forming a patterned interconnect material layer on the electrode and then connecting the interconnect material layer to the wafer; the patterned interconnect material layer is formed by a plurality of spaced interconnect material units, which provides a space for releasing thermal stress during the interconnection process, and utilizes the deformation process of the interconnect material unit during the connection process to absorb thermal stress, thereby reducing or avoiding the problem of warping and deformation of the wafer due to thermal stress during the interconnection process, thereby reducing the thermal resistance of the IGCT device and improving the reliability of the packaging structure of the IGCT device.

[0061] See also Figure 2In one embodiment, the process of forming a patterned interconnect material layer 210 on the surface of the electrode 200 includes: arranging each interconnect material unit X1 on the surface of the electrode 200 according to a set trajectory to form the interconnect material layer 210, thereby improving the accuracy and uniformity of the arrangement position of the interconnect material unit X1 on the electrode 200, thereby reducing or even avoiding the probability that the position deviation of the interconnect material unit X1 will have a negative impact on the stress release ability of the interconnect material layer 210.

[0062] In one embodiment, the interconnect material unit is cylindrical or truncated cone-shaped; wherein, when the interconnect material unit is cylindrical, the ratio of the area of ​​the cross section of the interconnect material unit parallel to the electrode to the height of the interconnect material unit is in the range of 0.5 to 1; when the interconnect material unit is truncated cone-shaped (see Figure 2 ), the interconnection material unit X1 includes a first top surface a and a second top surface b parallel to the electrode 200, and the average area of ​​the first top surface a and the second top surface b is equal to the height of the interconnection material unit X1 (i.e. Figure 2 The ratio of the first height H1 in the equation ranges from 0.5 to 1, that is, (in is the area of ​​the first top surface a, It should be noted that, in other embodiments of the present application, the specific shape and size parameters of the interconnection material unit can be adjusted according to actual needs, and the present application does not limit this.

[0063] In one embodiment, the material of the interconnection material unit is conductive. Preferably, the material of the interconnection material unit includes one of tin-based materials, brazing-based materials and nanosilver, so as to ensure that the interconnection material layer has good conductivity, thereby ensuring stable performance of the packaging structure of the IGCT device.

[0064] Continue reading Figure 2 In one embodiment, the positive projection area of ​​the interconnect material layer 210 toward the electrode 200 is 80% to 90% of the total area of ​​the electrode 200, so as to ensure that the interconnect material layer 210 has sufficient stress release space and at the same time ensure that the electrical conductivity and thermal conductivity of the semiconductor device after the interconnection process meet the process requirements.

[0065] In one embodiment, the distance between two adjacent interconnect material units ranges from 50 μm to 100 μm, so as to provide sufficient deformation space and stress release space for the interconnect material units in the subsequent interconnect process, thereby reducing or even avoiding the warping deformation problem caused by thermal stress in the subsequent interconnect process.

[0066] In one of the embodiments, in the process of setting all interconnection material units on the surface of the electrode according to a set trajectory, the shape of the set trajectory can be set to at least one of a concentric ring shape, a spiral shape, a radial shape and a grid shape, or the shape of the set trajectory can also be set to a trajectory shape composed of several common geometric shapes, so as to disperse the thermal stress exerted on the wafer during the interconnection process by adjusting the distribution of different interconnection material units, thereby reducing or even eliminating the warping deformation problem caused by thermal stress.

[0067] It should be emphasized that the specific shape of the set track can be comprehensively considered in combination with the size parameters of the wafer and the electrode, the relevant process requirements, the difficulty of setting the interconnection material layer according to the set track, and the absorption effect of different track patterns on thermal stress, so as to select a suitable set track pattern to prepare the interconnection material layer. The present application does not impose any restrictions on this. When selecting the set track, technical personnel in this field only need to ensure that the interconnection material layer formed according to the set track satisfies the two conditions of "the positive projection area of ​​the interconnection material layer toward the electrode is 80% to 90% of the total area of ​​the electrode" and "the interconnection material layer after interconnection does not overflow from the area between the wafer and the electrode".

[0068] In one embodiment, the set track can be symmetrically arranged on the surface of the electrode based on a central axis, wherein the central axis is parallel to the surface of the electrode and passes through the geometric center of the electrode. Figure 3 ), grid-like graphics (see Figure 4 ) or radial patterns (see Figure 5 ), the set trajectories are symmetrically arranged on the surface of the electrode 200 along the central axis MN to improve the distribution uniformity of the interconnection material unit X1 on the electrode 200, so as to utilize the interconnection material unit X1 to uniformly absorb the thermal stress of various parts of the wafer (not shown in the figure) and improve the thermal stress absorption effect of the interconnection material layer.

[0069] See also Figure 3 When the shape of the track is set to be a concentric ring, the diameter of each ring track can be set according to the thermal stress distribution of the wafer to specifically alleviate the thermal stress of different parts of the wafer, thereby reducing or avoiding the risk of deformation of the wafer due to thermal stress.

[0070] See also Figure 4 When the shape of the track is set to a grid pattern, the length and width of each grid pattern can be set according to the thermal stress distribution of the wafer to improve the thermal stress dispersion effect and dispersion uniformity of the interconnect material layer, thereby reducing or avoiding the risk of deformation of the wafer due to thermal stress.

[0071] See also Figure 5When the shape of the trajectory is set to a radial pattern, the pattern density of the radial pattern can be set according to the thermal stress distribution of the wafer to improve the thermal stress dispersion effect and dispersion uniformity of the interconnect material layer, thereby reducing or avoiding the risk of deformation of the wafer due to thermal stress.

[0072] It should be noted that in the set trajectory described above and other set trajectories that meet process requirements, the distance between any two adjacent interconnected material units along the direction parallel to the electrode surface is between 50μm and 100μm to ensure that each interconnected material unit has sufficient deformation space.

[0073] In one embodiment, the interconnection material unit can be arranged on the electrode surface according to a set trajectory with the help of a special tool to improve the setting efficiency and accuracy of the interconnection material unit, wherein the special tool includes one of a screen, a glue dispenser or a glue coater.

[0074] Continue reading Figure 2 In one embodiment, after providing an electrode 200 and a wafer 220 (i.e., after step S1), before forming a patterned interconnect material layer 210 on the surface of the electrode 200 (i.e., before step S2), the packaging method of the IGCT device further includes: performing pre-metallization treatment on the wafer 220 and the electrode 200 to form a first pre-metal layer (not shown in the figure) covering the wafer 220 and a second pre-metal layer (not shown in the figure) covering the electrode 200, wherein the first pre-metal layer covers the surface of the wafer 220 close to the electrode 200, and the second pre-metal layer covers the surface of the electrode 200 close to the wafer 220, thereby improving the connection effect between the wafer 220 and the electrode 200 in the interconnection process.

[0075] It should be noted that the materials of the first pre-metal layer and the second pre-metal layer are bondable with the materials of the interconnection material unit. Optionally, the materials of the first pre-metal layer and the second pre-metal layer include at least one of metal silver and metal gold.

[0076] In one embodiment, the first premetal layer, the second premetal layer and the interconnection material unit are made of at least one material. Exemplarily, when the materials selected for the first premetal layer, the second premetal layer and the interconnection material unit are not completely the same, for example, the materials of the first premetal layer and the second premetal layer are the same, and the materials of the two are different from the materials of the interconnection material unit, or, for example, when the materials of the first premetal layer, the second premetal layer and the interconnection material unit are all different, since the materials of the first premetal layer, the second premetal layer and the interconnection material unit are bondable, the three can still be connected to each other through a bonding process, thereby ensuring the yield and stability of the packaging structure of the IGCT device structure.

[0077] Exemplarily, when the first pre-metal layer, the second pre-metal layer and the interconnect material unit are made of the same material (for example, all are nanosilver materials), since the same metal materials have the best effect when bonded to each other, the bonding effect between the various film layers in the packaging structure of the IGCT device manufactured at this time is the best.

[0078] See also Figure 6 In one embodiment, the wafer 220 is placed on the interconnect material layer 210; a bonding process or a welding process is used to deform the interconnect material unit X2 (the interconnect material unit is deformed from Figure 2 X1 in the image is transformed into Figure 6 X2 in the figure) to connect the wafer 220 and the electrode 200, thereby effectively reducing the thermal resistance of the semiconductor device; wherein at least two adjacently arranged and deformed interconnect material units X2 are at least partially connected (not shown in the figure).

[0079] It should be noted that, since the thermal resistance of the IGCT device is inversely proportional to the cross-sectional area of ​​the interconnect material layer in the direction parallel to the wafer surface, the at least two interconnect material units arranged at intervals can be connected together during the deformation process by adjusting the set trajectory, the distance between two adjacent interconnect material units, and the size parameters of each interconnect material unit, so that the cross-sectional area of ​​the interconnect material layer after the interconnection process is greater than the cross-sectional area before the interconnection process, thereby reducing the thermal resistance of the IGCT device. Optionally, after the wafer and the electrode are connected (that is, after the interconnect material unit is deformed and the wafer and the electrode are connected), the positive projection area of ​​the interconnect material layer toward the electrode accounts for 90% to 100% of the total area of ​​the electrode.

[0080] Accordingly, continue to refer to Figure 2 and Figure 6 One embodiment of the present application further provides a packaging structure of an IGCT device, including an electrode 200, an interconnection material layer 210 and a wafer 220; wherein the interconnection material layer 210 is located on one side surface of the electrode 200, and the interconnection material layer 210 includes a plurality of interconnection material units, and the interconnection material units have a variable shape (for example Figure 2 X1 and Figure 6 X2 in the figure); the wafer 220 is located on a side of the interconnect material layer 210 away from the electrode 200.

[0081] The packaging structure of the IGCT device as described above, by setting a plurality of interconnect material units with variable shapes, reduces or eliminates the thermal stress generated during the packaging process of the IGCT device by utilizing the shape changes of the interconnect material units, thereby reducing or even avoiding the problem of thermal stress deformation or wafer warping deformation, thereby reducing thermal resistance and improving the reliability of the packaging structure of the IGCT device.

[0082] In one embodiment, the material of the electrode is a metal material or an alloy material, for example, the material of the electrode includes one of metal copper, metal molybdenum, molybdenum-copper alloy, tungsten-copper alloy, and copper-diamond. Optionally, the material of the wafer includes silicon or silicon carbide.

[0083] See also Figure 2 and Figure 6 In one embodiment, the interconnect material unit has a first form and a second form; wherein, when the interconnect material unit is in the first form (see Figure 2 ) The interconnection material unit X1 has a first height H1, and the area of ​​the cross section of the interconnection material unit X1 parallel to the electrode 200 gradually decreases in the direction away from the surface of the electrode 200 (ie, the X direction); when the interconnection material unit is in the second form (see Figure 6 ), the electrode 200 is connected to the wafer 220, the interconnect material unit X2 has a second height H2, and the second height H2 is less than the first height H1, that is, H2

[0084] It should be noted that, in the process of the interconnect material unit transforming from the first form to the second form, the thermal stress of the interconnect material layer is released as the interconnect material unit deforms and spreads; at the same time, the multiple interconnect material units are arranged at intervals, so that the interconnect material units have enough space to release thermal stress, thereby avoiding the problem of warping and deformation of the packaging structure of the IGCT device due to excessive thermal stress.

[0085] In one embodiment, the first form of the interconnect material unit is cylindrical or truncated cone; wherein, when the interconnect material unit is cylindrical, the ratio of the area of ​​the cross section of the interconnect material unit parallel to the electrode to the height of the interconnect material unit is in the range of 0.5 to 1; when the interconnect material unit is truncated cone (see Figure 2 ), the interconnection material unit X1 includes a first top surface a and a second top surface b parallel to the electrode 200, and the ratio of the average area of ​​the first top surface a and the second top surface b to the first height H1 of the interconnection material unit X1 is in the range of 0.5 to 1, that is, (in is the area of ​​the first top surface a, It should be noted that, in other embodiments of the present application, the specific shape and size parameters of the interconnection material unit can be adjusted according to actual needs, and the present application does not limit this.

[0086] In one embodiment, the projected area of ​​the interconnect material layer toward the electrode is 80% to 90% of the total area of ​​the electrode, so as to ensure that the interconnect material layer has sufficient stress release space while ensuring that the packaging structure of the IGCT device meets the process requirements in terms of electrical conductivity and thermal conductivity.

[0087] ​In one embodiment, the distance between two adjacent interconnect material units (first form) ranges from 50 μm to 100 μm to ensure that there is sufficient stress release space in the interconnect material layer. Optionally, the material of the interconnect material unit is conductive. Preferably, the material of the interconnect material unit includes one of a tin-based material, a solder-based material and nanosilver.

[0088] In one embodiment, the interconnect material unit of the first form is arranged in the interconnect material layer according to a set track, and the shape of the set track can be set to at least one of a concentric ring, a spiral, a radial pattern, and a grid pattern, or the shape of the set track can also be set to a track pattern composed of several common geometric patterns, so as to disperse the thermal stress of the wafer during the interconnection process by adjusting the distribution of different interconnect material units, thereby reducing or even eliminating the warping deformation problem caused by thermal stress. The specific shape and setting rules of the set track have been discussed in detail in the above content, and this application will not repeat them here.

[0089] In one embodiment, a first pre-metal layer (not shown in the figure) is further provided on the surface of the wafer close to the electrode, and a second pre-metal layer (not shown in the figure) is provided on the surface of the electrode close to the wafer, and the second pre-metal layer covers the interconnect material layer on the electrode to improve the connection effect between the wafer and the electrode. It should be noted that the materials of the first pre-metal layer and the second pre-metal layer are bondable with the materials of the interconnect material unit. Optionally, the materials of the first pre-metal layer and the second pre-metal layer include at least one of metal silver and metal gold.

[0090] In one embodiment, the first premetal layer, the second premetal layer and the interconnection material unit are made of at least one material. Exemplarily, when the materials selected for the first premetal layer, the second premetal layer and the interconnection material unit are not completely the same, for example, the materials of the first premetal layer and the second premetal layer are the same, and the materials of the two are different from the materials of the interconnection material unit, or, for example, when the materials of the first premetal layer, the second premetal layer and the interconnection material unit are all different, since the materials of the first premetal layer, the second premetal layer and the interconnection material unit are bondable, the three can still be connected to each other through a bonding process, thereby ensuring the yield and stability of the packaging structure of the IGCT device.

[0091] Exemplarily, when the first pre-metal layer, the second pre-metal layer and the interconnect material unit are made of the same material (for example, all are nanosilver materials), since the same metal materials have the best effect when bonded to each other, the bonding effect between the various film layers in the packaging structure of the IGCT device manufactured at this time is the best.

[0092] The present application also provides a packaging structure of an IGCT device, which is made by the packaging method of the IGCT device as described above. Since the packaging structure of the IGCT device made by the packaging method of the IGCT device has been described in detail in the previous text, the present application will not repeat it here. At the same time, it should be emphasized that the packaging structure of the IGCT device made by the packaging method of the IGCT device provided by the present application reduces or eliminates the thermal stress generated in the interconnection process of the wafer and the electrode by using the morphological change of the interconnection material unit, thereby avoiding the problem of thermal stress deformation or wafer warping deformation, and improving the reliability of the packaging structure of the IGCT device.

[0093] The packaging method of the IGCT device and the packaging structure of the IGCT device provided in the embodiments of the present application realize effective connection between the wafer and the electrode by forming a patterned interconnect material layer on the electrode and then connecting the interconnect material layer to the wafer; a patterned interconnect material layer is formed by a plurality of spaced interconnect material units, which provides space for releasing thermal stress during the interconnection process, and utilizes the deformation process of the interconnect material unit during the connection process to absorb thermal stress, thereby reducing or avoiding the problem of warping and deformation of the wafer due to thermal stress during the interconnection process, and improving the reliability of the packaging structure of the IGCT device without affecting the thermal resistance optimization effect.

[0094] It should be understood that, although the steps in the above-mentioned flowcharts are shown in sequence according to the diagrams, these steps are not necessarily executed in sequence according to the order shown in the diagrams. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in each figure may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0095] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0096] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A packaging method for an IGCT device, characterized in that: include: providing an electrode and a wafer; forming a patterned interconnect material layer on the surface of the electrode, wherein the interconnect material layer comprises a plurality of interconnect material units arranged at intervals; placing the wafer on a side of the interconnect material layer away from the electrode; Using a bonding process or a welding process to deform the interconnect material unit so as to connect the wafer and the electrode; Wherein, at least two adjacently arranged and deformed interconnected material unit portions are connected.

2. The packaging method of the IGCT device according to claim 1, characterized in that: The step of forming a patterned interconnect material layer on the surface of the electrode comprises: Each of the interconnection material units is arranged on the surface of the electrode according to a set track to form the interconnection material layer.

3. The packaging method of the IGCT device according to claim 2, characterized in that: The set trajectory is symmetrically arranged on the surface of the electrode based on a central axis, and the central axis is parallel to the surface of the electrode and passes through the geometric center of the electrode.

4. The packaging method of the IGCT device according to claim 2, characterized in that: The shape of the set trajectory includes at least one of a concentric ring shape, a spiral shape, a radial shape, and a grid shape.

5. The packaging method of the IGCT device according to claim 1, characterized in that: The distance between two adjacent interconnection material units ranges from 50 μm to 100 μm.

6. The packaging method of the IGCT device according to claim 1, characterized in that: The orthographic projection area of ​​the interconnect material layer toward the electrode is 80% to 90% of the total area of ​​the electrode.

7. The packaging method of the IGCT device according to claim 1, characterized in that: After providing an electrode and a wafer, and before forming a patterned interconnect material layer on the surface of the electrode, the packaging method of the IGCT device includes: The wafer and the electrode are pre-metallized to form a first pre-metal layer covering the wafer and a second pre-metal layer covering the electrode, wherein the first pre-metal layer covers the surface of the wafer close to the electrode, and the second pre-metal layer covers the surface of the electrode close to the wafer.

8. The packaging method of the IGCT device according to claim 7, characterized in that: The materials of the first pre-metal layer and the second pre-metal layer are bondable with the material of the interconnection material unit.

9. The packaging method of the IGCT device according to claim 8, characterized in that: The materials of the first pre-metal layer and the second pre-metal layer include at least one of metal gold and metal silver.

10. The packaging method of the IGCT device according to claim 8 or 9, characterized in that: The first pre-metal layer, the second pre-metal layer and the interconnect material unit are made of at least one material.

11. The packaging method of the IGCT device according to claim 1 or 8, characterized in that: The material of the interconnection material unit has conductivity.

12. The packaging method of the IGCT device according to claim 11, characterized in that: The material of the interconnection material unit includes one of a tin-based material, a solder-based material and a nano-silver material.

13. A packaging structure of an IGCT device, characterized in that: The IGCT device is manufactured by the packaging method of any one of claims 1 to 12.

14. A packaging structure of an IGCT device, characterized in that: include: electrode; An interconnect material layer, located on one side surface of the electrode; wherein the interconnect material layer comprises a plurality of interconnect material units; the interconnect material units have a variable shape; The wafer is located on a side of the interconnect material layer away from the electrode.

15. The packaging structure of the IGCT device according to claim 14, characterized in that: The interconnect material unit has a first form and a second form; wherein, When the interconnect material unit is in the first form, the interconnect material unit has a first height, and an area of ​​a cross section of the interconnect material unit parallel to the electrode gradually decreases in a direction away from the surface of the electrode; When the interconnect material unit is in the second form, the electrode is connected to the wafer, and the interconnect material unit has a second height, and the second height is smaller than the first height.

16. The packaging structure of the IGCT device according to claim 14, characterized in that: The shapes of the interconnected material units include cylindrical and truncated cone; When the interconnect material unit is cylindrical, a ratio of an area of ​​a cross section of the interconnect material unit parallel to the electrode to a height of the interconnect material unit is in a range of 0.5 to 1; When the interconnect material unit is in a truncated cone shape, the interconnect material unit includes a first top surface and a second top surface parallel to the electrode, and a ratio of an average area of ​​the first top surface and the second top surface to a height of the interconnect material unit is in a range of 0.5 to 1.

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