Wafer bonding method

Abstract

A wafer bonding method is provided. The wafer bonding method includes overlapping a first wafer and a second wafer with each other. The first wafer includes a transparent or translucent material having a first alignment mark thereon. The second wafer has a second alignment mark. The method includes providing light through the first wafer to inspect alignment of the first alignment mark and the second alignment mark. The method includes bonding a first wafer to a second wafer. Further, the method includes removing the transparent or translucent material while the first alignment mark remains bonded to the second wafer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor device manufacturing and, more particularly, to wafer bonding processes. Background Art

[0002] The size of transistors continues to decrease to facilitate the scaling down of logic elements. To facilitate this scaling down, three-dimensional (3D) device structures and 3D stacking processes have been proposed.

[0003] One type of 3D device structure under consideration is a stacked transistor. The stacked transistor may include a first transistor and a second transistor. The first transistor may be a transistor of a first type (e.g., an n-type field effect transistor (nFET)), and the second transistor may be a transistor of a second type (e.g., a p-type field effect transistor (pFET)). The first transistor and the second transistor may be stacked in any order (e.g., the first transistor on top of the second transistor, or the second transistor on top of the first transistor), thereby producing a stacked structure including a top device and a bottom device.

[0004] Wafer bonding techniques can be used to implement 3D (e.g., stacked) structures, such as backside power rails. During the wafer bonding process, it may be necessary to correct for misalignment between two wafers. However, wafer thickness and / or other limitations of conventional alignment processes may make it difficult to correct for such misalignment. Summary of the invention

[0005] According to some embodiments of the present invention, a wafer bonding method may include overlapping a first wafer and a second wafer with each other. The first wafer may include a transparent or translucent material having a first alignment mark thereon. The second wafer may have a second alignment mark. The method may include providing light through the first wafer to check the alignment of the first alignment mark with the second alignment mark. The method may include bonding the first wafer to the second wafer. In addition, the method may include removing the transparent or translucent material while the first alignment mark remains bonded to the second wafer.

[0006] According to some embodiments of the present invention, a wafer bonding method may include providing a first wafer above a second wafer. The first wafer may include a transparent or translucent material having a release material thereon and a first alignment mark thereon. The second wafer may include a second alignment mark. The method may include providing light through the transparent or translucent material and the release material to check the alignment of the first alignment mark with the second alignment mark. The method may include bonding the first wafer to the second wafer after providing light through the transparent or translucent material and the release material. In addition, the method may include removing the transparent or translucent material and the release material while the first alignment mark remains bonded to the second wafer.

[0007] According to some embodiments herein, a wafer bonding method may include forming a release material on a first wafer including a transparent or translucent material. The method may include forming a bonding material on the release material. The method may include etching the bonding material to form a first alignment mark. The method may include providing a first wafer above a second wafer. The second wafer may include a second alignment mark. The method may include providing light through the transparent or translucent material and the release material to check the alignment of the first alignment mark with the second alignment mark. The method may include bonding the first alignment mark to an adhesive layer on the second wafer after providing light through the transparent or translucent material and the release material. In addition, the method may include removing the transparent or translucent material and the release material while the first alignment mark remains bonded to the adhesive layer on the second wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic block diagram of a wafer alignment system according to some embodiments herein.

[0009] Figure 1B yes Figure 1A Example top view of an upper wafer.

[0010] Figure 1C yes Figure 1B An example top view of a die in an upper wafer.

[0011] FIG. 2A to FIG. 2D is a cross-sectional view illustrating a wafer bonding operation according to some embodiments herein.

[0012] FIG. 3A to FIG. 3D is a diagram showing the embodiment of the present invention according to some embodiments of the present invention. Figure 1A A cross-sectional view of an operation of forming an alignment mark on an upper wafer.

[0013] Figure 4 is corresponding to FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D Flowchart of the operations shown in . DETAILED DESCRIPTION

[0014] According to an embodiment of the present invention, a wafer bonding method is provided, which includes directly aligning an upper alignment mark on an upper wafer with a lower alignment mark on a lower wafer. This direct alignment can be facilitated by using an upper wafer including a transparent (or translucent) material (such as quartz or glass). As used herein, the term "direct alignment" refers to the use of an alignment measurement light (e.g., visible light, infrared (IR) light, or other light) that passes through a transparent (or translucent) upper wafer to reach a lower wafer, so that a bonding device or a human user can determine whether the upper wafer and the lower wafer are aligned based on an overlapping image (i.e., an image showing the overlap of the wafer) generated when using upper alignment marks and lower alignment marks on the upper wafer and the lower wafer, respectively. For example, a bonding device or a user can use an overlapping image to verify that the upper wafer overlaps the lower wafer correctly, which can only be achieved when the upper alignment mark and the lower alignment mark are correctly aligned. In addition, a bonding device or a user can adjust (i.e., move) the upper wafer and / or the lower wafer until a single image showing proper overlap is generated.

[0015] On the other hand, as used herein, the term "indirect alignment" refers to estimating only the relative position of the upper alignment mark and the lower alignment mark. For example, a bonding device or user can capture a first image of an upper alignment mark and a second image of a lower alignment mark separately. Then, the bonding device or user can calculate the relative position of the two images and move the upper wafer and the lower wafer to a position where these images can be aligned. The device or user cannot directly see whether the upper alignment mark and the lower alignment mark are actually aligned. Instead, separate images are used to estimate (e.g., calculate) such alignment.

[0016] The upper wafer can be a donor (e.g., carrier) wafer to be bonded to the lower wafer, and the transparent (or translucent) material of the upper wafer can be removed (e.g., together with the stripping material) after the wafers are bonded together. In addition, the wafers can facilitate high-order correction of wafer misalignment because the wafers can each include a large number of alignment marks. Because the upper wafer is transparent (or translucent), the alignment marks can be located not only outside the tube core, but also inside the tube core. These internal alignment marks of the tube core allow high-order correction to be performed to achieve better alignment. Therefore, the high-order correction compares more alignment marks, thereby improving the alignment accuracy. The high-order correction can use, for example, at least a second-order equation (e.g., a second-order to a fifth-order equation) to determine whether the alignment is acceptable.

[0017] Compared with direct alignment, conventional indirect alignment techniques may make it difficult to correct misalignment between wafers. When using conventional wafer bonding processes and equipment, thick wafers and / or relatively small amounts of alignment marks also increase the difficulty of correcting misalignment. Non-high-order corrections that compare relatively small amounts of alignment marks can use only, for example, first-order equations when determining whether alignment is acceptable, and may therefore result in lower alignment accuracy. When using indirect alignment techniques, alignment marks only on the die boundary or outside the die are often useful. Since many other alignment marks (e.g., those alignment marks inside the die) may be undetectable when using indirect alignment techniques, it may not be helpful to try to use a large number of alignment marks using indirect alignment techniques. Even if those alignment marks may be detectable (e.g., visible) when using indirect alignment techniques, this detectability may not significantly improve alignment accuracy because indirect alignment techniques still rely on estimates, which are not as accurate as direct alignment.

[0018] In addition, although some embodiments herein can facilitate (after bonding) easy removal of the transparent (or translucent) material of the upper wafer by removing the transparent (or translucent) material together with the stripping material, conventional bonding processes may not remove the transparent (or translucent) material of the wafer and / or may not use the stripping material. According to some embodiments, the bonding material of the upper wafer can be well adhered by using a stripping material on one side of the bonding material and an adhesive layer on the opposite side of the bonding material (on the lower wafer). Conventional wafer bonding processes may lack this combination of stripping material and adhesive layer.

[0019] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0020] Figure 1A 1 is a schematic block diagram of a wafer alignment system 100 according to some embodiments herein. The system 100 includes an alignment light source 130 configured to provide light 132 onto (and through) an upper wafer 120 and then onto a lower wafer 110 to help align the wafers 110, 120. For example, the light source 130 may include a laser light source and the light 132 may include a laser beam. In some embodiments, the light 132 may include visible light. In other embodiments, the light 132 may include invisible light, such as IR light.

[0021] Light source 130 is used to provide light 132 onto wafers 110, 120 when wafer 120 overlaps wafer 110 in a vertical direction Z. For example, light source 130 may be configured to provide light 132 downward onto wafers 110, 120 in direction Z. Direction Z is perpendicular to horizontal directions X,Y.

[0022] In some embodiments, the light source 130 may be part of a bonding device used to bond the wafers 110, 120 to each other. In other embodiments, the light source 130 may be separate from the bonding device. Figure 1A The engaging device is omitted from the view.

[0023] The system 100 may also include a wafer handling device (e.g., a wafer handling robot) configured to move the wafers 110, 120 and / or provide mechanical support for the wafers 110, 120 when bonding / aligning the wafers 110, 120. However, for simplicity of description, Figure 1A The wafer handling equipment is omitted from the view of FIG. In some embodiments, the wafer handling equipment may be part of the bonding equipment. In addition, the system 100 may include one or more additional light sources, and / or may include equipment (e.g., bonding equipment) that applies heat to the wafers 110, 120. However, to simplify the description, the wafer handling equipment is omitted from the view of FIG. Figure 1A Additional light source(s) and equipment for applying heat are omitted from the view.

[0024] Figure 1B FIG. 1 is an exemplary top view of the upper wafer 120. Figure 1B As shown in , the wafer 120 includes a number of dies 128, each of which includes a number of alignment marks 126. For example, the wafer 120 may include at least five rows (in direction X) and at least four columns (in direction Y) of dies 128, and the inner / main region of each die 128 may include at least three rows and at least three columns of alignment marks 126. Therefore, the alignment marks 126 may be an array including at least fifteen rows and at least twelve columns on the wafer 120. Therefore, the wafer 120 may include at least 180 alignment marks 126. As an example, the wafer 120 (e.g., all inner / main regions of the dies 128) may include at least 234 alignment marks 126.

[0025] In addition, the perimeter region of each die 128 may include, for example, twenty alignment marks 126, some of which may be shared with adjacent dies 128. Thus, when the wafer 120 is transparent or translucent (i.e., for direct alignment), each die 128 may include a total of about 25-30 (e.g., at least 25) alignment marks 126. Including both perimeter alignment marks 126 and interior alignment marks 126, the wafer 120 may include at least 500 alignment marks 126. In some embodiments, the wafer 120 may include more than 540 alignment marks 126, or even more than 1,000 alignment marks 126. For example, when the wafer 120 includes many (e.g., 60 or more) dies 128, the wafer 120 may include about 1,800-2,000 alignment marks 126. The large number of alignment marks 126 that facilitate direct alignment by using the transparent or translucent material of the wafer 120 may help improve alignment accuracy.

[0026] Figure 1C The upper wafer 120 ( Figure 1B ) is an example top view of the tube core 128. Figure 1C As shown in , the interior / main area of ​​the die 128 includes a first column of alignment marks 126a, a second column of alignment marks 126b, and a third column of alignment marks 126c. In some embodiments, each column can include three alignment marks 126. Therefore, the interior / main area of ​​the die 128 can include nine alignment marks 126. In addition, each perimeter edge of the die 128 can include five alignment marks 126d. Therefore, the perimeter of the die 128 can include twenty alignment marks 126d, and the die 128 can include a total of 29 alignment marks 126.

[0027] FIG. 2A to FIG. 2D is a cross-sectional view illustrating a wafer bonding operation according to some embodiments herein. FIG. 3A to FIG. 3D FIG. 1 is a diagram showing an upper wafer 120 ( Figure 1A ) is a cross-sectional view of an operation of forming an alignment mark 126 on the surface. Figure 4 is corresponding to FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D Flowchart of the operations shown in .

[0028] like Figure 2A and Figure 4As shown in , the wafer bonding operation may include overlapping the upper wafer 120 and the lower wafer 110 with each other (block 418). As used herein, the phrase "causing the [first / upper] wafer and the [second / lower] wafer to overlap each other" may refer to (a) providing the upper wafer 120 above the lower wafer 110 or (b) providing the lower wafer 110 above the upper wafer 120. The wafer 120 may include a transparent (or translucent) material 222 having a plurality of alignment marks 126 thereon. For example, the transparent (or translucent) material 222 may include glass or quartz and may have a pair of alignment marks 126a, 126b thereon, the pair of alignment marks 126a, 126b being spaced apart from each other in the direction X by a gap 228 having a width w3.

[0029] The wafer 110 has a plurality of alignment marks 214. In some embodiments, the alignment marks 214 may be in the main material / layer 212 of the wafer 110. For example, the main material / layer 212 may include a semiconductor layer, and the uppermost surface of a pair of alignment marks 214a, 214b may be coplanar with the uppermost surface of the semiconductor layer.

[0030] To simplify the explanation, Figure 2A Only two alignment marks 126 and two alignment marks 214 are shown. Figure 1B As described, wafer 120 may have a large number (e.g., hundreds) of alignment marks 126 thereon. Similarly, wafer 110 may have hundreds of alignment marks 214. According to some embodiments, wafer 110 may have the same number of alignment marks as wafer 120. Thus, wafer 120 may be aligned with wafer 110 by comparing (and matching) the alignment marks 126 of wafer 120 with the alignment marks 214 of wafer 110.

[0031] In some embodiments, the size of the alignment marks 126 of the wafer 120 may be different from the size of the alignment marks 214 of the wafer 110. For example, the alignment marks 126 may each have a width w1 that is wider than the width w2 of each alignment mark 214 in the direction X. Therefore, the alignment marks 126 of the wafer 120 may be referred to herein as "wide" alignment marks, and the alignment marks 214 of the wafer 110 may be referred to herein as "narrow" alignment marks. However, in other embodiments, the alignment marks 126 of the wafer 120 may have the same width as the alignment marks 214 of the wafer 110. In addition, according to some embodiments, the width w3 of the gap 228 may be narrower than the width w2 of the alignment marks 214.

[0032] The wafers 110, 120 may have different thicknesses. As an example, the main material / layer 212 of the wafer 110 may have a thickness t6 that is thicker than the thickness t1 of the transparent (or translucent) material 222 of the wafer 120 in the direction Z. Because the transparent (or translucent) material 222 is both transparent (or translucent) and relatively thin, it may help provide light 132 ( Figure 2B ) to check the alignment of the wafers 110 , 120 .

[0033] The alignment mark 126 may have a thickness t3, and the alignment mark 214 may have a thickness t7. In some embodiments, the thickness t3 of the alignment mark 126 may be the same as the thickness t7 of the alignment mark 214, which is thinner than the thickness t6 of the main material / layer 212 of the wafer 110. According to some embodiments, the thickness t3 of the alignment mark 126 may be thinner than the thickness t1 of the transparent (or translucent) material 222 of the wafer 120. In other embodiments, the thickness t3 of the alignment mark 216 may be equal to the thickness t1 of the transparent (or translucent) material 222 of the wafer 120.

[0034] The peeling material 224 may be located between the transparent (or translucent) material 222 and the alignment mark 126 in the direction Z. For example, a first surface of the peeling material 224 may contact the transparent (or translucent) material 222, and an opposite second surface of the peeling material 224 may contact the alignment mark 126. The peeling material 224 is used in a subsequent operation to separate the wafer 120 from the wafer 110. The peeling material 224 may have a thickness t2 that is thinner than each of the thicknesses t1, t3 in the direction Z. Therefore, the peeling material 224 may be thinner than the transparent (or translucent) material 222 and thinner than the alignment mark 126. The thinner the peeling material 224 is, the easier it is to separate the wafer 120 from the wafer 110. FIG. 2A to FIG. 2D The more the operation shown in , the more the cost and size can be reduced. In addition, the stripping material 224 can include, for example, a temperature-sensitive and / or ultraviolet (UV) light-sensitive material, because a subsequent heat and / or UV process can be used to separate the stripping material 224 from the wafer 110 after bonding the wafers 110, 120 together. According to some embodiments, the stripping material 224 can include an amorphous fluoropolymer material, a fluorinated alkylchlorosilane, or a silane coupling agent.

[0035] The bonding oxide 216 may be on the alignment mark 214 and the main material / layer 212 of the wafer 110. The thickness t5 of the bonding oxide 216 in the direction Z may be thinner than the thickness t6 of the main material / layer 212 of the wafer 110. The bonding oxide 216 may include, for example, an oxide (e.g., silicon oxide or silicon oxynitride) or a silicon nitride.

[0036] Adhesive layer 218 may be on bonding oxide 216, with bonding oxide 216 between adhesive layer 218 and alignment mark 214. As an example, an upper surface of bonding oxide 216 may contact a lower surface of adhesive layer 218. A lower surface of bonding oxide 216 may contact an upper surface of alignment mark 214 and / or an upper surface of primary material / layer 212 of wafer 110. Adhesive layer 218 is used in subsequent operations to bond wafers 110, 120 to each other. A thickness t4 of adhesive layer 218 in direction Z may be thinner than thicknesses t5, t7 of bonding oxide 216 and alignment mark 214. Thus, adhesive layer 218 may be thinner than bonding oxide 216 and thinner than alignment mark 214. The thinner adhesive layer 218 is, the better the bonding performance. FIG. 2A to FIG. 2D The more the operation shown in , the more the cost and size can be reduced. In some embodiments, the thickness t4 of the adhesive layer 218 can be thinner than the thickness t2 of the stripping material 224. In other embodiments, the thickness t4 of the adhesive layer 218 can be equal to the thickness t2 of the stripping material 224. In addition, the adhesive layer 218 can include, for example, a temperature-sensitive and / or UV-sensitive material, such as benzocyclobutene (BCB) or a UV-sensitive epoxy resin. In some embodiments, the adhesive layer 218 can include methacryloxypropyltrichlorosilane.

[0037] like Figure 2B and Figure 4 As shown in FIG. 4 , light 132 from a light source 130 may be provided through a transparent (or translucent) material 222 (block 420) to check (e.g., compare / verify) the alignment of the alignment mark 126 with the alignment mark 214. For example, the light 132 may be used to check the alignment of the alignment mark 126a with the alignment mark 214a. As an example, the light 132 may be used to check the alignment of the sidewall s1 of the alignment mark 126a with the sidewall s2 of the alignment mark 214a. Since the alignment mark 126a may be wider than the alignment mark 214a, the second sidewall of the alignment mark 126a opposite to the sidewall s1 of the alignment mark 126a may not be aligned with the second sidewall of the alignment mark 214a opposite to the sidewall s2 of the alignment mark 214a. More specifically, the inner / middle portion of the alignment mark 126a may vertically overlap with the second sidewall of the alignment mark 214a.

[0038] In some embodiments, light 132 can also be used to check the alignment of alignment mark 126b (e.g., its sidewalls) with alignment mark 214b (e.g., its sidewalls). Light 132 can pass through transparent (or translucent) material 222, then through release material 224, and then through gap 228 between alignment marks 126a, 126b. Subsequently, light 132 can pass between alignment marks 214a, 214b of wafer 110.

[0039] like Figure 2C and Figure 4 As shown in FIG. 1 , light 132 ( Figure 2B ), wafer 120 may be bonded (block 422) to wafer 110. As an example, wafers 110, 120 may be bonded by applying heat (i.e., heating) and / or light treatment 240 to wafers 110, 120. According to some embodiments, heat / light treatment 240 may apply a temperature of 25°C to 150°C to bond wafers 110, 120. Heat / light treatment 240 may help adhesive layer 218 on wafer 110 to bond with alignment mark 126 on wafer 120. For example, alignment mark 126 may contact (and bond with) an upper surface of adhesive layer 218. In addition, alignment mark 126 may include a bonding material such as oxide, silicon nitride, silicon oxynitride, silicon, germanium, or silicon germanium. In some embodiments, heat / light treatment 240 may include UV light. The UV light may be provided, for example, by light source 130 or another light source.

[0040] In some embodiments, alignment mark 126 can be at the same vertical level in direction Z as at least a portion of a back side power delivery network (BSPDN), which can include components such as back side power rails. Thus, the operation(s) of bonding wafers 110, 120 together can include bonding the BSPDN (or a portion thereof) to wafer 110. However, to simplify the description, the alignment mark 126 is not shown in FIG. 1 . Figure 2C BSPDN is omitted from the view.

[0041] like Figure 2D and Figure 4 As shown in FIG. 4 , the transparent (or translucent) material 222 may be removed (block 424) from the alignment mark 126 while the alignment mark 126 remains bonded to the wafer 110 (e.g., bonded to the adhesive layer 218 on the wafer 110). According to some embodiments, the release material 224 may be removed along with (i.e., together with) the transparent (or translucent) material 222. For example, Figure 2D An operation 250 of loosening (eg, lifting) the transparent (or translucent) material 222 and the peeling material 224 upward in the direction Z is shown.

[0042] The stripping material 224 may be removed by providing UV light to the stripping material 224. As an example, the UV light may be provided to the stripping material 224 by the light source 130 or another light source through the transparent (or translucent) material 222. UV light is less likely to deform the wafer 110 than heat. Therefore, using UV light to remove the stripping material 224 may help reduce / prevent wafer deformation. In order to combine the UV light with the light 132 ( Figure 2B ), light 132 and UV light may be referred to herein as “first” light and “second” light, respectively.

[0043] After removing the stripping material 224, wafer patterning can be performed (block 426). For example, patterning can be performed on the wafer 110. As an example, the wafer 110 can be rotated 180 degrees, and patterning can be performed to form circuit elements on a first side of the wafer 110, which is opposite to a second side of the wafer 110 having the alignment mark 214 therein / on it. Thus, the stripping material 224 facilitates easy removal of the transparent (or translucent) material 222, so that structures previously located under the transparent (or translucent) material 222 can be patterned. In addition, before removing the stripping material 224 (and after bonding the wafers 110, 120), the portion of the stripping material 224 exposed by the gap 228 (block 426) is removed. Figure 2C ) may face the portion of adhesive layer 218 exposed by gap 228.

[0044] Although the adhesive layer 218 and the release material 224 are Figure 2C and Figure 2D 218, but in some embodiments, they may be omitted. For example, using certain gases, catalysts, and / or atmospheres, the wafers 110, 120 may be bonded without the use of adhesive layer 218, and / or the wafers 110, 120 may be separated without the use of release material 224. Thus, under certain gas, catalyst, and / or atmosphere conditions, (i) adhesive layer 218, (ii) release material 224, or (iii) both adhesive layer 218 and release material 224 may be omitted.

[0045] like FIG. 3A to FIG. 3D and Figure 4 As shown in FIG. 1 , before providing the wafer 120 on the wafer 110 (and thus before checking the alignment of the wafers 110 , 120 ), the alignment marks 126 are formed on the wafer 120 . Figure 3A , providing a transparent (or translucent) material 222. Figure 3B and Figure 4 , a release material 224 is formed on the transparent (or translucent) material 222 (block 410 ). As an example, the release material 224 may be deposited on the transparent (or translucent) material 222 .

[0046] refer to Figure 3C and Figure 4, a bonding material 360 is formed on the lift-off material 224 (block 412). In addition, a mask layer 370 may be formed on the bonding material 360 and may be patterned to have an opening 380 exposing a portion of the bonding material 360. The mask layer 370 may have an etch selectivity relative to the bonding material 360 and may be patterned by, for example, photo patterning (e.g., photolithography).

[0047] The bonding material 360 may be deposited on the stripping material 224 and may include a material configured to limit / reduce stress on the wafer 110. For example, in some embodiments, the bonding material 360 may be a tensile stress material. In other embodiments, the bonding material 360 may be a compressive stress material. Examples of the bonding material 360 include oxides or silicon nitrides (or silicon oxynitrides). Other examples include silicon, germanium, or silicon germanium.

[0048] refer to Figure 3D and Figure 4 , the exposed portion of the bonding material 360 is etched (block 414) to form the alignment marks 126a, 126b with the gap 228 therebetween. Etching the bonding material 360 may include exposing a portion of the lift-off material 224 through the gap 228, according to some embodiments.

[0049] To simplify the explanation, Figure 3C and Figure 3D The formation of only two alignment marks 126 is shown. However, it will be understood that the mask layer 370 can be patterned to have a large number (e.g., hundreds) of openings 380 therein, and etching of the bonding material 360 can be performed through each opening 380 to form a corresponding gap 228 in the bonding material 360. As a result, a large number (e.g., hundreds or even more than 1,000) of alignment marks 126 can be formed from the bonding material 360. In addition, referring to Figure 2A and Figure 3D , the wafer 120 may be rotated 180 degrees so that the alignment mark 126 faces the wafer 110 before checking the alignment of the wafers 110 , 120 .

[0050] The BSPDN (or a portion thereof) may be formed on the wafer 120 at the same vertical level as the alignment mark 126. In some embodiments, the BSPDN may be formed on the lift-off material 224 after forming the alignment mark 126 (block 416). In other embodiments, the BSPDN may be formed on the lift-off material 224 before forming the alignment mark 126. However, for simplicity of illustration, the BSPDN is not shown in FIG. FIG. 3B to FIG. 3D BSPDN is omitted from the view.

[0051] The wafer bonding method according to the embodiments of the present invention can provide many advantages. These advantages include: Figure 2B ) to provide enhanced direct alignment of the upper wafer 120 with the lower wafer 110. The transparent (or translucent) material 222 can facilitate checking the alignment of the wafers 110, 120 before the wafers 110, 120 are bonded together, and thus can make it easier to detect and correct misalignment. In addition, the wafer 120 can have a large number (e.g., hundreds) of alignment marks 126 ( Figure 1B ), which can facilitate high-order correction of misalignment between the wafers 110, 120 before the wafers 110, 120 are bonded together. The alignment mark 126 can be aligned with the alignment mark 214 ( Figure 2B ) is directly aligned. In addition, the alignment mark 126 includes a bonding material 360 ( Figure 3C ), which can adhere well to the adhesive layer 218 on the wafer 110.

[0052] When the wafers 110, 120 are bonded together, the release material 224 may be between the transparent (or translucent) material 222 of the wafer 120 and the alignment mark 126. Therefore, the transparent (or translucent) material 222 may be easily removed by removing the release material 224.

[0053] Example embodiments are described herein with reference to the accompanying drawings. Without departing from the teachings of the present disclosure, many different forms and embodiments are possible, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0054] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the embodiments herein should not be construed as limited to the particular shapes shown herein but may include deviations in shape that result, for example, from manufacturing.

[0055] It should also be noted that in some alternative embodiments, the function / action pointed out in the flow chart frame of this paper may not occur in the order pointed out in the flow chart.For example, two frames shown continuously can actually be performed substantially simultaneously, or frame can sometimes be performed in reverse order, depending on the function / action involved.In addition, the function of the given frame of flow chart and / or block diagram can be divided into a plurality of frames, and / or the function of two or more frames of flow chart and / or block diagram can be integrated at least in part.Finally, without departing from the scope of the present invention, other frames can be added / inserted between the frames shown, and / or frame / operation can be omitted.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0057] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprising", "comprising ... ", "including" and / or "comprising ... " indicate the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups.

[0058] It will be understood that when an element is referred to as being "coupled," "connected" to another element, or "responsive to" another element, or "on" another element, it may be directly coupled, connected to, or responsive to, or on another element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly coupled," "directly connected" to another element, or "directly responsive to," or "directly on" another element, there are no intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0059] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of this embodiment, the first element may be referred to as the second element.

[0060] For ease of description, spatial relative terms may be used herein, such as "below ... ", "below ... ", "below", "above ... ", "on", etc. to describe the relationship of an element or feature to another (multiple) element or (multiple) feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "below ... " can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0061] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein and the ways and processes of making and using them, and should support claims to any such combination or subcombination.

[0062] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0063] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 594,435, filed on October 31, 2023, and U.S. Non-Provisional Application No. 18 / 644,210, filed on April 24, 2024, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A wafer bonding method, comprising: overlapping a first wafer and a second wafer with each other, wherein the first wafer includes a transparent or translucent material having a first alignment mark thereon, and wherein the second wafer includes a second alignment mark; providing light through the first wafer to check alignment of the first alignment mark with the second alignment mark; bonding the first wafer to the second wafer; as well as The transparent or translucent material is removed while the first alignment mark remains bonded to the second wafer. 2 . The wafer bonding method according to claim 1 , wherein providing the light comprises providing the light through a release material between the transparent or translucent material and the first alignment mark. 3 . The wafer bonding method according to claim 2 , wherein the release material is removed together with the transparent or translucent material.

4. The wafer bonding method according to claim 3, wherein the light comprises a first light, and The second light including ultraviolet light is used to remove the release material. 5 . The wafer bonding method according to claim 2 , wherein the release material is thinner than the transparent or translucent material and thinner than the first alignment mark. The wafer bonding method according to claim 1 , wherein the transparent or translucent material comprises glass or quartz.

7. The wafer bonding method according to claim 1, wherein the first alignment mark comprises a wide alignment mark, wherein the second alignment mark comprises a narrow alignment mark, the narrow alignment mark being narrower than the wide alignment mark, and Wherein providing the light includes checking whether a sidewall of the wide alignment mark is aligned with a sidewall of the narrow alignment mark.

8. The wafer bonding method according to claim 1, further comprising forming the first alignment mark before providing the first wafer on the second wafer, wherein forming the first alignment mark comprises: forming a release material on the transparent or translucent material; forming a bonding material on the release material; as well as The bonding material is etched to form the first alignment mark and expose a portion of the lift-off material. 9 . The wafer bonding method of claim 8 , wherein bonding the first wafer to the second wafer comprises bonding the first alignment mark to an adhesive layer on the second wafer.

10. The wafer bonding method according to claim 9, wherein: After bonding the first wafer to the second wafer and before removing the transparent or translucent material, the exposed portion of the release material faces a portion of the adhesive layer exposed through a gap between the first alignment marks.

11. The wafer bonding method according to claim 9, wherein a bonding oxide is between the adhesive layer and the second alignment mark, and The adhesive layer is thinner than the bonding oxide and thinner than the second alignment mark. 12 . The wafer bonding method according to claim 1 , wherein the first alignment marks are in an array, the array comprising at least fifteen rows and at least twelve columns of the first alignment marks.

13. The wafer bonding method according to claim 1, wherein the first wafer comprises a die, and Each of the tube dies includes at least 25 of the first alignment marks.

14. The wafer bonding method of claim 13, wherein at least some of the first alignment marks are in an inner region of the die. 15 . The wafer bonding method of claim 1 , further comprising forming a backside power delivery network, at least a portion of the backside power delivery network being at the same vertical level as the first alignment mark.

16. A wafer bonding method, comprising: providing a first wafer on a second wafer, wherein the first wafer comprises a transparent or translucent material having a release material thereon and having a first alignment mark thereon, and wherein the second wafer comprises a second alignment mark; providing light through the transparent or translucent material and the release material to check alignment of the first alignment mark with the second alignment mark; bonding the first wafer to the second wafer after providing the light through the transparent or translucent material and the release material; as well as The transparent or translucent material and the release material are removed while the first alignment mark remains bonded to the second wafer.

17. The wafer bonding method according to claim 16, further comprising forming the first alignment mark on the first wafer before providing the first wafer on the second wafer, wherein forming the first alignment mark comprises: forming the release material on the transparent or translucent material; forming a bonding material on the release material; as well as The bonding material is etched to form the first alignment mark and expose a portion of the lift-off material.

18. The wafer bonding method according to claim 17, wherein the method further comprises forming at least a portion of a backside power delivery network on the release material; wherein bonding the first wafer to the second wafer comprises bonding the first alignment mark to an adhesive layer on the second wafer, and Wherein after bonding the first wafer to the second wafer and before removing the transparent or translucent material, the exposed portion of the release material faces a portion of the adhesive layer exposed by a gap between the first alignment marks.

19. A wafer bonding method, comprising: forming a release material on a first wafer, the first wafer comprising a transparent or translucent material; forming a bonding material on the release material; etching the bonding material to form a first alignment mark; as well as providing the first wafer on a second wafer, wherein the second wafer includes a second alignment mark; providing light through the transparent or translucent material and the release material to check alignment of the first alignment mark with the second alignment mark; bonding the first alignment mark to the adhesive layer on the second wafer after providing the light through the transparent or translucent material and the release material; as well as The transparent or translucent material and the release material are removed while the first alignment mark remains bonded to the adhesive layer on the second wafer.

20. The wafer bonding method according to claim 19, wherein etching the bonding material comprises exposing a portion of the lift-off material, wherein after bonding the first alignment mark to the adhesive layer and before removing the transparent or translucent material and the release material, the exposed portion of the release material faces the portion of the adhesive layer exposed by the gap between the first alignment marks, wherein the release material is thinner than the transparent or translucent material and thinner than the first alignment mark, and The adhesive layer is thinner than the second alignment mark.

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