Power semiconductor packaging structure and power semiconductor device with same

Abstract

The invention provides a power semiconductor packaging structure and a power semiconductor device with the power semiconductor packaging structure, and the power semiconductor packaging structure comprises a semiconductor chip; a first pole electrical connection structure disposed on a first side of the semiconductor chip; the second electrode electric connection structure is arranged on the second side of the semiconductor chip, the second electrode electric connection structure comprises a buffer structure, an electrode base and a liquid metal medium, the buffer structure is arranged between the semiconductor chip and the electrode base, a containing space is formed between the buffer structure and the electrode base, and the liquid metal medium is arranged in the containing space; the buffer structure and the pole base are in sealed connection to prevent the liquid metal medium from being separated from the containing space. According to the technical scheme of the invention, the problems of high crimping packaging difficulty and high cost of the power semiconductor device in the prior art can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor packaging structure and a power semiconductor device having the same. Background Art

[0002] In the field of power semiconductors, hard compression packaging technology is a packaging technology for power semiconductor devices. This technology requires that the surface flatness and roughness of each packaged component reach the micron level. In order to achieve this technical requirement, it is necessary to reduce the flatness and roughness of each contact surface through high-precision machining or surface fine grinding, reduce the contact resistance and contact thermal resistance, and make each contact surface meet the requirements of uniform pressure distribution. However, in actual application, for a single power semiconductor device, the required pressure uniformity is guaranteed by high-precision machining, which leads to the problem of large economic and time costs, which is not conducive to large-scale industrial production; for multiple power semiconductor devices packaged in parallel, due to the height difference between each power semiconductor device, the hard compression technology in the related technology cannot guarantee the pressure uniformity between the power semiconductor devices, resulting in a large difference in the contact state between the chip and the packaging structure, making the current distribution between the chips of each power semiconductor device uneven, and the junction temperature difference is large, which ultimately affects the working performance and reliability of the power semiconductor device. Summary of the invention

[0003] The main purpose of the present invention is to provide a power semiconductor packaging structure and a power semiconductor device having the same, so as to solve the problem of great difficulty and high cost in the compression packaging of power semiconductor devices in the related art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a power semiconductor packaging structure is provided, comprising: a semiconductor chip; a first pole electrical connection structure, arranged on a first side of the semiconductor chip; a second pole electrical connection structure, arranged on a second side of the semiconductor chip, the second pole electrical connection structure comprising a buffer structure, a pole seat and a liquid metal medium, the buffer structure is arranged between the semiconductor chip and the pole seat, a receiving space is formed between the buffer structure and the pole seat, the liquid metal medium is arranged in the receiving space, and the buffer structure and the pole seat are sealed and connected to prevent the liquid metal medium from escaping from the receiving space.

[0005] Furthermore, one of the buffer structure and the pole seat is provided with a groove structure, and the other of the buffer structure and the pole seat is provided with a convex structure, the convex structure is inserted into the groove structure, and a receiving space is formed between the surface of the convex structure facing the groove bottom wall of the groove structure and the groove bottom wall of the groove structure. The convex structure and the groove structure have the advantages of simple processing and easy molding, and a receiving space is formed between the surface of the convex structure facing the groove bottom wall of the groove structure and the groove bottom wall of the groove structure, so that the liquid metal medium can first exist in the groove structure and then the convex structure and the groove structure are docked and arranged, so that the assembly of the convex structure, the liquid metal medium and the groove structure is relatively easy.

[0006] Furthermore, the buffer structure includes a first substrate and a convex structure disposed on the first substrate, the pole seat includes a second substrate, the groove structure is disposed on the second substrate, and the first substrate and the second substrate are spaced apart to form an adjustment gap, so that the distance between the first substrate and the second substrate can be adjusted. Since the pressure on the pole seat or the buffer structure may not be balanced during the actual crimping process, when part of the structure is subjected to greater pressure, the adjustment gap will be reduced, the first substrate and the second substrate will be closer to each other, and the corresponding liquid metal medium will be relatively squeezed away; vice versa, thereby forming a flexible crimping effect.

[0007] Furthermore, the width of the adjustment gap in the direction from the first side to the second side of the semiconductor chip is greater than 0 and less than or equal to 0.2 mm. In this way, it is ensured that the adjustment gap is not too large and that there is enough space for the buffer structure and the pole seat to be adjusted.

[0008] Furthermore, the ratio of the cross-sectional area of ​​the groove structure to the cross-sectional area of ​​the second substrate is greater than or equal to 0.7 and less than or equal to 0.8. The ratio of the cross-sectional area of ​​the groove structure to the cross-sectional area of ​​the second substrate that meets the above requirements makes the cross-sectional area of ​​the groove structure large enough, and the area that can contact the liquid metal medium is large enough, and then the contact area for balancing the pressure is large enough, thereby ensuring that the liquid metal medium can play a good effect of balancing the pressure at various locations.

[0009] Furthermore, the center line of the groove structure is arranged to coincide with the center line of the second substrate, so that the groove structure and the second substrate are arranged symmetrically, and the buffer structure and the pole seat can be affected by the liquid metal medium at all locations in the circumferential direction, so that the buffer structure and the pole seat can have a balanced pressure effect at all locations in the circumferential direction, and the uniformity of pressure application is further ensured.

[0010] Furthermore, the minimum distance between the surface of the protrusion structure facing the groove bottom wall of the groove structure and the groove bottom wall of the groove structure is greater than or equal to 0.2 mm and less than or equal to 0.4 mm. When a large pressure limit is encountered and the buffer structure and the pole seat are squeezed to the limit position, there is still a certain gap between the surface of the protrusion structure facing the groove bottom wall of the groove structure and the groove bottom wall of the groove structure to accommodate the liquid metal medium, so that there will be no hard contact between the protrusion structure and the groove structure.

[0011] Furthermore, the sidewall of the bump structure is in abutment with the sidewall of the groove structure. This arrangement can ensure that the liquid metal medium will not leak out of the accommodating space, thereby ensuring the stability and reliability of the power semiconductor packaging structure.

[0012] Furthermore, the material of the liquid metal medium is mercury, cesium, pure gallium or gallium alloy. The liquid metal medium using the above materials not only ensures the characteristics of liquid flow, but also ensures the overall conductivity of the power semiconductor packaging structure.

[0013] Furthermore, the second pole electrical connection structure also includes a sealing structure disposed between the buffer structure and the pole seat to seal the accommodation space. This arrangement further ensures that the liquid metal medium will not leak out of the accommodation space, thereby further ensuring the stability and reliability of the power semiconductor packaging structure.

[0014] Furthermore, the groove structure includes a first groove section and a second groove section, the diameter of the first groove section is smaller than the diameter of the second groove section, a receiving space is formed between the groove bottom wall of the first groove section and the protrusion structure, the sealing structure is located in the second groove section and at the periphery of the protrusion structure, the inner side wall of the sealing structure is abutted with the protrusion structure, and the outer side wall of the sealing structure is abutted with the side wall of the second groove section. The sealing structure can be located at a suitable position to seal the receiving space, thereby preventing leakage of the liquid metal medium.

[0015] Further, the sealing structure includes a first pole shoe, a second pole shoe, a magnet part and a magnetic fluid part, the magnet part is arranged between the first pole shoe and the second pole shoe, the magnetic fluid part is arranged between the first pole shoe and the bump structure and between the second pole shoe and the bump structure, and the magnet part can apply a force to the magnetic fluid part so that the magnetic fluid part and the bump structure are abutted and matched. The sealing structure is a magnetic fluid sealing structure, and the magnetic fluid part is sealed between the buffer structure and the pole seat under the action of the magnetic field of the magnet part, thereby achieving the effect of preventing the leakage of the liquid metal medium.

[0016] According to another aspect of the present invention, a power semiconductor device is provided, including a power semiconductor packaging structure, wherein the power semiconductor packaging structure is the above-mentioned power semiconductor packaging structure. The power semiconductor device having the above-mentioned power semiconductor packaging structure can also solve the problem of difficulty and high cost of press-fit packaging of power semiconductor devices in related technologies.

[0017] Furthermore, there are multiple power semiconductor packaging structures, and the multiple power semiconductor packaging structures are arranged along a preset direction, and the accommodating spaces of adjacent power semiconductor packaging structures are arranged in a connected manner, wherein the preset direction is arranged perpendicular to the direction from the first side to the second side of the semiconductor chip of the power semiconductor packaging structure. By using the communicating vessel principle, the heights of two power semiconductor packaging structures with a relative height difference are kept consistent during the flexible pressing process, thereby ensuring the pressure uniformity between the multiple power semiconductor packaging structures.

[0018] Furthermore, the semiconductor device further comprises a connecting tube, a connecting channel connecting the outer wall of the connecting tube and the accommodation space is arranged on the pole seat of the power semiconductor packaging structure, and the connecting tube is connected between the connecting channels of adjacent power semiconductor packaging structures. In this way, the accommodation spaces of adjacent power semiconductor packaging structures can be connected through the connecting tube with a simple structure.

[0019] By applying the technical solution of the present invention, the semiconductor chip is used to provide basic functions for the power semiconductor packaging structure, the first pole electrical connection structure is arranged on the first side of the semiconductor chip; the second pole electrical connection structure is arranged on the second side of the semiconductor chip, and the electrical connection function of the semiconductor chip and other structures is realized through the first pole electrical connection structure and the second pole electrical connection structure, the second pole electrical connection structure includes a buffer structure, a pole seat and a liquid metal medium, the buffer structure is arranged between the semiconductor chip and the pole seat to buffer the semiconductor chip, a receiving space is formed between the buffer structure and the pole seat, the liquid metal medium is arranged in the receiving space, and the liquid characteristics of the liquid metal medium, that is, the principle that the pressure of the liquid is equal everywhere in a closed environment, is used to balance the pressure distribution of each contact surface, so as to achieve the effect of flexible crimping and uniform pressure, and at the same time, the conductivity of the liquid metal medium can also meet the flow capacity of the power semiconductor packaging structure, thereby improving the overall performance of the power semiconductor packaging structure; the buffer structure and the pole seat are sealed and connected to prevent the liquid metal medium from escaping from the receiving space, thereby ensuring the structural reliability of the overall power semiconductor packaging structure. In this way, compared with the hard compression packaging technology that requires high precision in the related art, the power semiconductor packaging device using this embodiment does not require the contact surfaces of each structure to have high flatness and roughness. The liquid properties of the liquid metal medium can be used to achieve the effect of uniform pressure distribution on each contact surface, reducing the processing cost and difficulty. Therefore, the technical solution of this application can effectively solve the problem of high difficulty and high cost of compression packaging of power semiconductor devices in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 A schematic cross-sectional view of an embodiment of a power semiconductor packaging structure according to the present invention is shown;

[0022] Figure 2 Shows Figure 1 An enlarged schematic diagram of a power semiconductor package structure at A;

[0023] Figure 3 Shows Figure 1 An enlarged schematic diagram of a partial structure of a power semiconductor packaging structure;

[0024] Figure 4 Shows Figure 1 A schematic diagram of a partial structure of a power semiconductor packaging structure;

[0025] Figure 5 Shows Figure 4 A schematic side view of a semiconductor chip of a power semiconductor packaging structure;

[0026] Figure 6 Shows Figure 4 A schematic side view of a buffer structure of a power semiconductor package structure;

[0027] Figure 7 Shows Figure 4 A schematic side view of a pole seat of a power semiconductor packaging structure;

[0028] Figure 8 Shows Figure 7 An enlarged schematic diagram of the pole seat at B;

[0029] Fig. 9 A schematic cross-sectional view of an embodiment of a power semiconductor device according to the present invention is shown;

[0030] Fig.10 Shows Fig. 9 An enlarged schematic diagram of a power semiconductor device at C.

[0031] The above drawings include the following reference numerals:

[0032] a. Preset direction;

[0033] 10. Semiconductor chips;

[0034] 20. A first pole electrical connection structure;

[0035] 30. Second pole electrical connection structure; 31. Buffer structure; 311. Bump structure; 312. First substrate; 32. Pole seat; 321. Groove structure; 322. Second substrate; 323. First slot section; 324. Second slot section; 33. Liquid metal medium; 34. Adjust gap; 35. Sealing structure; 351. First pole shoe; 352. Second pole shoe; 353. Magnet part; 354. Magnetic fluid part;

[0036] 40. Connecting pipe; 41. Connecting channel. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0039] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0040] like Figures 1 to 3As shown, the present application provides a power semiconductor packaging structure. An embodiment of the power semiconductor packaging structure of the present application includes: a semiconductor chip 10, a first pole electrical connection structure 20, and a second pole electrical connection structure 30; the first pole electrical connection structure 20 is arranged on the first side of the semiconductor chip 10; the second pole electrical connection structure 30 is arranged on the second side of the semiconductor chip 10, and the second pole electrical connection structure 30 includes a buffer structure 31, a pole seat 32 and a liquid metal medium 33, the buffer structure 31 is arranged between the semiconductor chip 10 and the pole seat 32, and a receiving space is formed between the buffer structure 31 and the pole seat 32, and the liquid metal medium 33 is arranged in the receiving space, and the buffer structure 31 and the pole seat 32 are sealed and connected to prevent the liquid metal medium 33 from escaping from the receiving space.

[0041] By applying the technical solution of this embodiment, the semiconductor chip 10 is used to provide a basic function for the power semiconductor packaging structure. The first-pole electrical connection structure 20 is arranged on the first side of the semiconductor chip 10; the second-pole electrical connection structure 30 is arranged on the second side of the semiconductor chip 10. The electrical connection function of the semiconductor chip 10 and other structures is realized through the first-pole electrical connection structure 20 and the second-pole electrical connection structure 30. The second-pole electrical connection structure 30 includes a buffer structure 31, a pole seat 32 and a liquid metal medium 33. The buffer structure 31 is arranged between the semiconductor chip 10 and the pole seat 32 to buffer the semiconductor chip 10. A holding space is formed between the punch structure 31 and the pole seat 32, and the liquid metal medium 33 is arranged in the holding space. The liquid characteristics of the liquid metal medium 33, that is, the principle that the pressure of the liquid is equal everywhere in a closed environment, are used to balance the pressure distribution of each contact surface, so as to achieve the effect of flexible crimping and uniform pressure. At the same time, the conductivity of the liquid metal medium 33 can also meet the flow capacity of the power semiconductor packaging structure, and improve the overall performance of the power semiconductor packaging structure; the buffer structure 31 and the pole seat 32 are sealed to prevent the liquid metal medium 33 from escaping from the holding space, thereby ensuring the structural reliability of the overall power semiconductor packaging structure. In this way, compared with the hard crimping packaging technology that requires high precision in the related art, the power semiconductor packaging device of this embodiment does not require the contact surfaces of each structure to have high flatness and roughness, and the liquid characteristics of the liquid metal medium 33 can be used to achieve the effect of uniform pressure distribution on each contact surface, thereby reducing the processing cost and difficulty. Therefore, the technical solution of this embodiment can effectively solve the problem of high difficulty and high cost of crimping packaging of power semiconductor devices in the related art.

[0042] It should be noted that “the buffer structure 31 and the pole seat 32 are sealed to prevent the liquid metal medium 33 from escaping from the containing space” refers to the situation that the buffer structure 31 and the pole seat 32 can be self-sealed, or the situation that a sealing structure is set between the buffer structure 31 and the pole seat 32 for sealing. The “first pole electrical connection structure 20” and the “second pole electrical connection structure 30” are respectively connected to the anode side and the cathode side of the semiconductor chip 10. In the present embodiment, the first pole electrical connection structure 20 is connected to the anode side of the semiconductor chip 10, and the second pole electrical connection structure 30 is connected to the cathode side of the semiconductor chip 10. In other embodiments, the first pole electrical connection structure is connected to the cathode side of the semiconductor chip, and the second pole electrical connection structure is connected to the anode side of the semiconductor chip.

[0043] It should be noted that "the liquid metal medium 33 is arranged in the accommodation space, and the liquid characteristics of the liquid metal medium 33, that is, the principle that the pressure of the liquid is equal everywhere in a closed environment, are used to balance the pressure distribution of each contact surface, so as to achieve the effect of flexible crimping and uniform pressure" means: using Pascal's law, the pressure of the liquid metal medium in a closed environment is equal everywhere. This means that when the liquid metal medium is placed in the accommodation space between the buffer structure and the pole seat of the semiconductor chip, it can evenly transfer the externally applied pressure to each contact surface. This uniform pressure distribution helps to avoid chip damage or poor contact caused by excessive local pressure, thereby achieving the effect of flexible crimping and uniform pressure. The liquid metal medium has good fluidity and can fill the tiny gap between the buffer structure and the pole seat of the semiconductor chip to form a uniform contact surface. This fluidity enables the liquid metal medium to form a uniform pressure distribution on each contact surface, thereby improving the stability and reliability of the electrical connection. The fluidity of the liquid metal medium can also adapt to contact surfaces of different shapes and sizes, ensuring that good pressure balance can be achieved in various packaging structures. In a closed accommodation space, the pressure of the liquid metal medium can be kept balanced. This means that no matter how the shape of the contact surface between the buffer structure and the pole seat of the semiconductor chip changes, the liquid metal medium can adapt to these changes through its own fluidity and maintain a uniform distribution of pressure. This pressure balance helps to improve the overall performance and reliability of the packaging structure, ensuring that the pressure between the contact surfaces will not change significantly due to environmental changes during long-term operation. The liquid metal medium not only has good conductivity, but also can meet the flow capacity requirements of the power semiconductor packaging structure while maintaining pressure balance. This conductivity enables the liquid metal medium to effectively conduct current while achieving pressure balance, thereby improving the electrical performance of the packaging structure. The conductivity of the liquid metal medium can also reduce resistance, reduce energy loss, and improve the efficiency of power transmission. In actual power semiconductor packaging, by placing the liquid metal medium in the accommodation space between the buffer structure and the pole seat of the semiconductor chip, and preventing the liquid metal medium from leaking through sealing, the effect of flexible crimping and uniform pressure can be effectively achieved. This design not only improves the electrical connection performance of the packaging structure, but also enhances its heat dissipation performance and overall reliability. The application of liquid metal medium can also simplify the packaging process, reduce production costs and improve production efficiency.

[0044] like Figures 1 to 8As shown, one of the buffer structure 31 and the pole seat 32 is provided with a groove structure 321, and the other of the buffer structure 31 and the pole seat 32 is provided with a convex structure 311, the convex structure 311 is inserted into the groove structure 321, and a receiving space is formed between the surface of the convex structure 311 facing the groove bottom wall of the groove structure 321 and the groove bottom wall of the groove structure 321. Specifically, the convex structure 311 and the groove structure 321 have the advantages of simple processing and easy molding, and a receiving space is formed between the surface of the convex structure 311 facing the groove bottom wall of the groove structure 321 and the groove bottom wall of the groove structure 321, so that the liquid metal medium 33 can first exist in the groove structure 321 and then the convex structure 311 and the groove structure 321 are docked and arranged, so that the assembly of the convex structure 311, the liquid metal medium 33 and the groove structure 321 is relatively easy.

[0045] like Figures 1 to 3 As shown, the buffer structure 31 includes a first substrate 312 and a protrusion structure 311 arranged on the first substrate 312, the pole seat 32 includes a second substrate 322, the groove structure 321 is arranged on the second substrate 322, the first substrate 312 and the second substrate 322 are spaced apart and form an adjustment gap 34 so that the distance between the first substrate 312 and the second substrate 322 can be adjusted. Specifically, the pole seat 32 is provided with a groove structure 321, which is arranged on the second substrate 322, and the buffer structure 31 is provided with a bump structure 311, which is arranged on the second substrate 322. The surface of the first substrate 312 facing the pole seat 32 and the surface of the second substrate 322 facing the buffer structure 31 are arranged at intervals to form an adjustment gap 34; because in the actual crimping process, the pressure on the pole seat 32 or the buffer structure 31 may not be balanced, when part of the structure is subjected to a large pressure, the adjustment gap 34 will be reduced, the first substrate 312 and the second substrate 322 will be closer to each other, and the corresponding liquid metal medium 33 will also be relatively squeezed away; vice versa, thereby forming a flexible crimping effect. More specifically, the width of the adjustment gap 34 in the direction from the first side to the second side of the semiconductor chip 10 is greater than 0 and less than or equal to 0.2mm. In this way, it is ensured that the adjustment gap will not be too large, and that there is enough space for the buffer structure 31 and the pole seat 32 to adjust. The width of the adjustment gap 34 in the direction from the first side to the second side of the semiconductor chip 10 may be 0.05 mm, 0.1 mm, 0.13 mm, 0.15 mm, 0.18 mm or 0.2 mm. It should be noted that the width of the adjustment gap 34 in the direction from the first side to the second side of the semiconductor chip 10 refers to Figure 2 As shown, the width of the gap 34 in the vertical direction is adjusted.

[0046] In addition, in this embodiment, a movable partition is provided on the bottom wall of the groove structure 321 in the direction from the first side to the second side of the semiconductor chip 10 to adjust the size of the accommodation space. Since the accommodation space is filled with liquid metal medium 33, as the power semiconductor packaging structure generates heat during operation, the change in temperature will cause the volume of the liquid metal medium 33 to change, and the partition can move with the change in the volume of the liquid metal medium 33 to ensure that the liquid metal medium 33 can always fill the accommodation space. The partition includes a plate body and a compression spring connected between the plate body and the bottom wall of the groove structure 321.

[0047] In addition, in this embodiment, the ratio of the cross-sectional area of ​​the groove structure 321 to the cross-sectional area of ​​the second substrate 322 is greater than or equal to 0.7 and less than or equal to 0.8. Specifically, the ratio of the cross-sectional area of ​​the groove structure 321 to the cross-sectional area of ​​the second substrate 322 that meets the above requirements makes the cross-sectional area of ​​the groove structure 321 large enough, and the area that can contact with the liquid metal medium 33 is large enough, so that the contact area for balancing the pressure is large enough, thereby ensuring that the liquid metal medium 33 can play a good effect of balancing the pressure at various locations. The ratio of the cross-sectional area of ​​the groove structure 321 to the cross-sectional area of ​​the second substrate 322 can be 0.7, 0.71, 0.73, 0.75, 0.78, 0.79 or 0.8.

[0048] In addition, in this embodiment, the center line of the groove structure 321 is arranged to coincide with the center line of the second substrate 322. Specifically, the groove structure 321 and the second substrate 322 are arranged symmetrically, so that the buffer structure 31 and the pole seat 32 can be affected by the liquid metal medium 33 at all locations in the circumferential direction, so that the buffer structure 31 and the pole seat 32 can have a balanced pressure effect at all locations in the circumferential direction, and the uniformity of pressure application is further guaranteed.

[0049] In addition, in the present embodiment, the minimum distance between the surface of the protrusion structure 311 facing the groove bottom wall of the groove structure 321 and the groove bottom wall of the groove structure 321 is greater than or equal to 0.2 mm and less than or equal to 0.4 mm. Specifically, the minimum distance between the surface of the protrusion structure 311 facing the groove bottom wall of the groove structure 321 and the groove bottom wall of the groove structure 321 that meets the above requirements makes the size of the accommodation space in the direction from the first side to the second side of the semiconductor chip 10 large enough, even if a large pressure limit value is encountered, and the buffer structure 31 and the pole seat 32 are squeezed to the limit position, there is still a certain gap between the surface of the protrusion structure 311 facing the groove bottom wall of the groove structure 321 and the groove bottom wall of the groove structure 321 to accommodate the liquid metal medium 33, so that there will be no hard contact between the protrusion structure 311 and the groove structure 321.

[0050] In addition, in this embodiment, the sidewall of the bump structure 311 is in abutment with the sidewall of the groove structure 321. This arrangement can ensure that the liquid metal medium 33 will not leak out of the accommodation space, thereby ensuring the stability and reliability of the power semiconductor packaging structure.

[0051] like Figures 1 to 3 As shown, the second pole electrical connection structure 30 further includes a sealing structure 35 disposed between the buffer structure 31 and the pole seat 32 to seal the accommodation space. In this way, the sealing structure 35 is further provided to further improve the sealing of the accommodation space, further prevent the liquid metal medium 33 from leaking out of the accommodation space, and further ensure the stability and reliability of the power semiconductor packaging structure.

[0052] like Figures 1 to 8 As shown, the groove structure 321 includes a first groove section 323 and a second groove section 324, the diameter of the first groove section 323 is smaller than the diameter of the second groove section 324, and an accommodating space is formed between the groove bottom wall of the first groove section 323 and the protrusion structure 311, the sealing structure 35 is located in the second groove section 324 and on the outer periphery of the protrusion structure 311, the inner side wall of the sealing structure 35 abuts and cooperates with the protrusion structure 311, and the outer side wall of the sealing structure 35 abuts and cooperates with the side wall of the second groove section 324. Specifically, the groove structure 321 is a stepped groove, including a first groove section 323 and a second groove section 324. The diameter of the first groove section 323 is smaller than the diameter of the second groove section 324. That is to say, the first groove section 323 is located on the side of the second groove section 324 away from the semiconductor chip 10. A receiving space is formed between the groove bottom wall of the first groove section 323 and the bump structure 311. "The side wall of the bump structure 311 abuts against the side wall of the groove structure 321" refers to the abutment between the side wall of the bump structure 311 and the side wall of the first groove section 323 to seal the receiving space and prevent the liquid metal medium 33 from leaking out of the receiving space. The second groove section 324 is used to install the sealing structure 35. The inner side wall of the sealing structure 35 abuts against the bump structure 311, and the outer side wall of the sealing structure 35 abuts against the side wall of the second groove section 324, thereby further sealing the receiving space and preventing the liquid metal medium 33 from leaking out of the receiving space.

[0053] like Figures 1 to 3As shown, the sealing structure 35 includes a first pole shoe 351, a second pole shoe 352, a magnet portion 353 and a magnetic fluid portion 354. The magnet portion 353 is arranged between the first pole shoe 351 and the second pole shoe 352, and the magnetic fluid portion 354 is arranged between the first pole shoe 351 and the bump structure 311 and between the second pole shoe 352 and the bump structure 311. The magnet portion 353 can apply a force to the magnetic fluid portion 354 so that the magnetic fluid portion 354 abuts against the bump structure 311. Specifically, the magnetic fluid portion 354 forms an "O-ring" shape under the action of the magnet portion 353 to seal the accommodation space.

[0054] The sealing structure 35 of this embodiment is a magnetic fluid sealing ring, which is a structure that uses the characteristics of magnetic liquid to achieve sealing. It is mainly composed of magnetic liquid (that is, the magnetic fluid part 354 in this embodiment), permanent magnet (that is, the magnet part 353 in this embodiment), pole shoes and other parts. Magnetic liquid is a colloidal solution composed of nano-scale magnetic particles, carrier liquid and surfactant, which has the characteristic of showing magnetism under the action of a magnetic field. In the absence of an external magnetic field, the behavior of magnetic fluid is the same as that of ordinary liquid, but when it is subjected to a magnetic field, it will respond quickly and show magnetism. The working principle of the magnetic fluid sealing ring is to use the "O"-shaped sealing ring formed by the magnetic fluid under the action of a magnetic field to achieve sealing. Permanent magnets are arranged around the sealed area to fix the magnetic fluid and form a sealing ring to prevent gas or liquid leakage. The magnetic fluid sealing ring has many advantages. First, it can achieve zero leakage. Under normal temperature and pressure conditions, helium mass spectrometry shows that the leakage rate is less than 10⁻¹² (Pa·m³) / s, effectively maintaining constant pressure. Secondly, the wear of the magnetic fluid seal ring is very small. Since the sealing gap is filled with magnetic fluid, there is almost no friction and little heat is generated. In addition, the magnetic fluid seal ring has excellent reliability. By utilizing the sputtering characteristics of the magnetic fluid, the seal is easy to restore to its original state and is not easy to damage. The magnetic fluid seal ring also has non-directional pressure resistance. Finally, the magnetic fluid seal ring is pollution-free. The O-ring formed by the magnetic fluid during the sealing process will not produce contamination particles. In addition, the carrier fluid and magnetic particles in the magnetic fluid have stable characteristics and extremely low volatilization consumption.

[0055] In this embodiment, the material of the liquid metal medium 33 is mercury, cesium, pure gallium or gallium alloy. Selecting mercury as the material of the liquid metal medium 33 has the following advantages: First, mercury has good electrical conductivity. Although its electrical conductivity is lower than that of most other metals, it performs well in liquid metal. This enables mercury to effectively conduct current, reduce resistance and reduce energy loss in power semiconductor packaging. The electrical conductivity of mercury enables it to perform well in high-frequency and high-power applications, and can meet the needs of power semiconductors for efficient current conduction. Second, mercury has a high thermal conductivity and can effectively conduct heat. In power semiconductor packaging, mercury can be used as a thermal interface material to help dissipate heat. The high thermal conductivity of mercury helps to reduce the thermal resistance of power devices and improve the heat dissipation efficiency, thereby ensuring the stable operation of the device in a high-temperature environment. The thermal conductivity of mercury gives it a significant advantage in high-power density packaging, and can effectively prevent the degradation of device performance caused by heat accumulation. Third, mercury can maintain its physical and chemical properties for a long time in power semiconductor packaging, and is not prone to chemical corrosion or deterioration. The chemical stability of mercury enables it to work reliably in the package and extend the service life of the device. In addition, the stability of mercury also means that no additional chemical protection measures are required during the packaging process, simplifying the process flow. Fourth, mercury has a high density, which enables mercury to provide good structural stability and vibration resistance in the package. High-density mercury can effectively fill the tiny gaps in the package and improve the overall reliability of the package. The high density of mercury also enables it to withstand greater structural stress in the package, reducing connection failures caused by structural vibration or impact. Fifth, mercury has good wettability on most solid surfaces and can evenly cover the electrode surface to form a good electrical contact. In power semiconductor packaging, the wettability of mercury helps to increase the contact area between electrodes, reduce contact resistance, and improve current conduction efficiency. The wettability of mercury also makes it easier to achieve a uniform liquid metal layer during the packaging process, improving the consistency and reliability of the package. Choosing cesium as the material of the liquid metal medium 33 has the following advantages: cesium also has excellent electrical conductivity and high thermal conductivity. In addition, cesium has a low melting point, which allows it to remain liquid at room temperature. This property makes cesium easy to handle and process during the packaging process, and it can better fill the tiny gaps in the package and ensure close contact between the electrodes. The low melting point also means that high temperature treatment is not required during the packaging process, thereby reducing process complexity and cost. Cesium also has chemical stability and good wettability.

[0056] In addition, in other embodiments, the material of the liquid metal medium can also be an alloy formed by indium (In), tin (Sn), etc., for example, gallium-tin-indium (Ga-In-Sn) alloy; sodium-potassium alloy, etc. In power semiconductor packaging, the material selection of the liquid metal medium is of great significance. Different liquid metal alloys show their own unique advantages in packaging: For gallium-tin-indium alloy, gallium-tin-indium alloy has a very low melting point and can usually remain liquid at room temperature or slightly above room temperature, which makes it easy to handle and process during the packaging process, and can better fill the tiny gaps in the package to ensure close contact between the electrodes. The alloy has excellent thermal conductivity, can effectively conduct heat, reduce the thermal resistance of power devices, and improve heat dissipation efficiency, thereby ensuring stable operation of the device in a high temperature environment. Gallium-tin-indium alloy has good wettability on most solid surfaces, can evenly cover the electrode surface, form good electrical contact, and improve current conduction efficiency. At room temperature, the chemical properties of gallium-tin-indium alloy are stable and not easy to react with other substances, which enables it to maintain its physical and chemical properties for a long time in the package and is not prone to chemical corrosion or deterioration. Gallium-tin-indium alloy is recyclable and can be processed through professional recycling processes after being discarded, reducing resource waste and environmental pollution. For sodium-potassium alloy, sodium-potassium alloy has extremely high thermal conductivity. For example, the thermal conductivity of liquid sodium at 100°C is 86.9W / m·K, which enables it to provide excellent heat dissipation performance in the package and effectively reduce the thermal resistance of the device. The eutectic melting point of sodium-potassium alloy is -12.65°C, and it can remain liquid at room temperature, which is convenient for handling and processing during the packaging process. Although the chemical properties of sodium-potassium alloy are active, it can provide good heat exchange performance when used in a closed system. At the same time, the price is relatively low and it has certain economy.

[0057] like Fig. 9 as well as Fig.10 As shown, the present application also provides a power semiconductor device, and the power semiconductor device of the present application includes a power semiconductor packaging structure, wherein the power semiconductor packaging structure is the above-mentioned power semiconductor packaging structure. The above-mentioned power semiconductor packaging structure can effectively solve the problem of high difficulty and high cost of press-fit packaging of power semiconductor devices in related technologies, and the power semiconductor device having the above-mentioned power semiconductor packaging structure also has the above-mentioned advantages.

[0058] like Fig. 9 as well as Fig.10As shown, there are multiple power semiconductor packaging structures, and the multiple power semiconductor packaging structures are arranged along a preset direction a, and the accommodation spaces of adjacent power semiconductor packaging structures are connected, wherein the preset direction a is arranged perpendicular to the direction from the first side to the second side of the semiconductor chip 10 of the power semiconductor packaging structure. More specifically, the semiconductor device also includes a connecting tube 40, and a connecting channel 41 connecting the outer wall of the pole seat 32 and the accommodation space is arranged on the pole seat 32 of the power semiconductor packaging structure, and the connecting tube 40 is connected between the connecting channels 41 of adjacent power semiconductor packaging structures. It should be particularly noted that: when a power semiconductor device is arranged in this way, when multiple power semiconductor packaging structures are connected in parallel, the height difference of the multiple power semiconductor packaging structures can be compensated by using flexible pressing technology.

[0059] The communicating vessel principle refers to the physical law that the liquid levels of the same static liquid in a container with an open top and a connected bottom always remain level. This principle is based on the concept of pressure balance in liquid statics. When the liquid in the communicating vessel is at rest, due to the incompressibility of the liquid and the effect of gravity, the liquid level in each container will automatically adjust to ensure that the liquid level is on the same horizontal line. The working principle of the communicating vessel is based on the static pressure balance of the liquid. When two or more containers with connected bottoms are filled with the same liquid and the liquid is at rest, the pressure distribution inside is the key.

[0060] This embodiment is mainly based on the expansion of the flexible uniform pressing technology of a single power semiconductor packaging structure. Using the principle of the communicating vessel, when the liquid metal medium 33 in the closed accommodation space is subjected to pressure, the pressure is transmitted to all directions without changing in magnitude. In this embodiment, two power semiconductor packaging structures are packaged in parallel as an example for explanation. The power semiconductor packaging structure includes a first power semiconductor packaging structure and a second power semiconductor packaging structure. The second pole electrical connection structure 30 of the first power semiconductor packaging structure and the second power semiconductor packaging structure is provided with a liquid metal medium 33 inside, and the outer wall surface of the pole seat 32 of the second pole electrical connection structure 30 is processed with a connection interface, which is connected to the accommodation space through a connecting channel 41, and the connection interface between the first power semiconductor packaging structure and the second power semiconductor packaging structure is connected through a connecting pipe 40, ensuring that all connected accommodation spaces, connecting channels 41 and the inside of the connecting pipe 40 are filled with liquid metal medium 33. Since the structure of the power semiconductor packaging structure itself is an assembly of multi-layer materials that cooperate with each other, there will be a certain height difference between different power semiconductor packaging structures during the press-fitting process (that is, there is a certain height difference between the first power semiconductor packaging structure and the second power semiconductor packaging structure). When the power semiconductor package device is press-assembled, the accommodating cavities of the first power semiconductor package structure and the second power semiconductor package structure are connected to each other through the connecting tube 40. If the relative height of the first power semiconductor package structure is higher than that of the second power semiconductor package structure, the first pole electrical connection structure of the first power semiconductor package structure is pressed downward first (that is, Fig. 9 The first power semiconductor package structure is formed by a plurality of power semiconductor packaging structures, and the first power semiconductor package structure is formed by a plurality of power semiconductor packaging structures. ...

[0061] In addition, in this embodiment, the connecting tube 40 is connected to the pole seat 32 of the power semiconductor packaging structure by a tight welding technology. In other embodiments, the connecting tube and the pole seat are detachably connected, and the power semiconductor device further includes a plugging member. When the connecting tube is separated from the pole seat, the plugging member blocks the connecting channel so that the power semiconductor packaging structure can be used alone; the connecting tube includes a tube body, a connecting plate, an elastic gasket and a fastening bolt. The connecting plate is arranged on the tube body. The tube body can extend into the connecting channel and make the connecting plate abut against the pole seat. The elastic gasket is located between the connecting plate and the pole seat. The fastening bolt is passed through the connecting plate and the pole seat to firmly connect the connecting tube and the pole seat.

[0062] The power semiconductor packaging structure and power semiconductor device of the present application can have the following advantages:

[0063] 1) The pressure uniformity of power semiconductor devices is greatly improved. The direct contact between the liquid metal medium and the buffer structure (such as buffer materials such as molybdenum sheets) ensures that the pressure at the contact point is equal. In this way, whether it is a single packaged semiconductor packaging structure or multiple semiconductor packaging structures are packaged in parallel, as long as the liquid metal medium in the closed accommodation space is the same liquid metal medium and is interconnected, the pressure at the contact point of the liquid metal medium is equal everywhere, which improves the overall packaging performance of the power semiconductor device.

[0064] 2) The magnetic fluid sealing technology is used to seal the liquid metal medium in the containment space. The magnetic fluid part can form a "liquid O-ring" under the action of the magnetic field, achieving zero leakage during the disassembly and assembly of power semiconductor devices.

[0065] 3) Reduce processing cost and time cost. The present invention uses liquid pressure equalization technology, which can well adjust the pressure of the contact surface, thereby reducing the processing difficulty and processing time of the packaging structure and improving industrial application.

[0066] 4) High compatibility. The packaging structure is compatible with a variety of press-fit packaging forms and semiconductor chip structures.

[0067] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0068] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0069] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power semiconductor packaging structure, characterized in that: include: Semiconductor chip (10); A first-pole electrical connection structure (20) arranged on a first side of the semiconductor chip (10); A second-pole electrical connection structure (30) is arranged on the second side of the semiconductor chip (10), the second-pole electrical connection structure (30) comprising a buffer structure (31), a pole seat (32) and a liquid metal medium (33), the buffer structure (31) being arranged between the semiconductor chip (10) and the pole seat (32), a receiving space being formed between the buffer structure (31) and the pole seat (32), the liquid metal medium (33) being arranged in the receiving space, and the buffer structure (31) and the pole seat (32) being sealed and connected to prevent the liquid metal medium (33) from escaping from the receiving space.

2. The power semiconductor packaging structure according to claim 1, characterized in that: One of the buffer structure (31) and the pole seat (32) is provided with a groove structure (321), and the other of the buffer structure (31) and the pole seat (32) is provided with a protrusion structure (311), the protrusion structure (311) is inserted into the groove structure (321), and the accommodating space is formed between a surface of the protrusion structure (311) facing the groove bottom wall of the groove structure (321) and the groove bottom wall of the groove structure (321).

3. The power semiconductor packaging structure according to claim 2, characterized in that: The buffer structure (31) comprises a first substrate (312) and the convex block structure (311) arranged on the first substrate (312); the pole seat (32) comprises a second substrate (322); the groove structure (321) is arranged on the second substrate (322); the first substrate (312) and the second substrate (322) are spaced apart and form an adjustment gap (34) so ​​that the distance between the first substrate (312) and the second substrate (322) can be adjusted.

4. The power semiconductor packaging structure according to claim 3, characterized in that: The width of the adjustment gap (34) in the direction from the first side to the second side of the semiconductor chip (10) is greater than 0 and less than or equal to 0.2 mm.

5. The power semiconductor packaging structure according to claim 3, characterized in that: The ratio of the cross-sectional area of ​​the groove structure (321) to the cross-sectional area of ​​the second base body (322) is greater than or equal to 0.7 and less than or equal to 0.

8.

6. The power semiconductor packaging structure according to claim 3, characterized in that: The center line of the groove structure (321) is arranged to coincide with the center line of the second base body (322).

7. The power semiconductor packaging structure according to claim 2, characterized in that: The minimum distance between the surface of the convex block structure (311) facing the groove bottom wall of the groove structure (321) and the groove bottom wall of the groove structure (321) is greater than or equal to 0.2 mm and less than or equal to 0.4 mm.

8. The power semiconductor packaging structure according to claim 2, characterized in that: The side wall of the protrusion structure (311) is in abutment with the side wall of the groove structure (321).

9. The power semiconductor packaging structure according to claim 1, characterized in that: The material of the liquid metal medium (33) is mercury, cesium, pure gallium or a gallium alloy.

10. The power semiconductor packaging structure according to any one of claims 3 to 7, characterized in that: The second pole electrical connection structure (30) further comprises a sealing structure (35) arranged between the buffer structure (31) and the pole seat (32) to seal the accommodation space.

11. The power semiconductor packaging structure according to claim 10, characterized in that: The groove structure (321) comprises a first groove section (323) and a second groove section (324); the diameter of the first groove section (323) is smaller than the diameter of the second groove section (324); the accommodating space is formed between the groove bottom wall of the first groove section (323) and the protrusion structure (311); the sealing structure (35) is located in the second groove section (324) and on the periphery of the protrusion structure (311); the inner side wall of the sealing structure (35) is in abutment with the protrusion structure (311); and the outer side wall of the sealing structure (35) is in abutment with the side wall of the second groove section (324).

12. The power semiconductor packaging structure according to claim 11, characterized in that: The sealing structure (35) comprises a first pole shoe (351), a second pole shoe (352), a magnet portion (353) and a magnetic fluid portion (354); the magnet portion (353) is arranged between the first pole shoe (351) and the second pole shoe (352); the magnetic fluid portion (354) is arranged between the first pole shoe (351) and the bump structure (311) and between the second pole shoe (352) and the bump structure (311); the magnet portion (353) is capable of applying a force to the magnetic fluid portion (354) so ​​that the magnetic fluid portion (354) and the bump structure (311) are in abutment with each other.

13. A power semiconductor device, comprising a power semiconductor packaging structure, characterized in that: The power semiconductor package structure is the power semiconductor package structure according to any one of claims 1 to 12.

14. The power semiconductor device according to claim 13, characterized in that: There are a plurality of power semiconductor packaging structures, and the plurality of power semiconductor packaging structures are arranged along a preset direction (a), and the accommodating spaces of adjacent power semiconductor packaging structures are arranged in a connected manner, wherein the preset direction (a) is arranged perpendicular to the direction from the first side to the second side of the semiconductor chip (10) of the power semiconductor packaging structure.

15. The power semiconductor device according to claim 14, characterized in that: The semiconductor device further comprises a connecting tube (40); a connecting channel (41) connecting an outer wall of the connecting tube (32) and the accommodating space is provided on the pole seat (32) of the power semiconductor packaging structure; the connecting tube (40) is connected between the connecting channels (41) of adjacent power semiconductor packaging structures.

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