Semiconductor packaging structure
By configuring the cutting channel through-holes and contact pads in the cutting channel area of the wafer and achieving electrical connections through the redistribution layer, the problem of waste in the cutting channel area in traditional packaging is solved, and a more efficient utilization area is achieved and a package that supports three-dimensional stacking and CIS image sensors is supported.
CN119920792APending Publication Date: 2025-05-02FLY SKY INNOTECH INC
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Patent Information
- Application Number
- CN202311415672.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-30
- Publication Date
- 2025-05-02
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Figure CN119920792A_ABST
Abstract
A semiconductor package structure includes: a wafer chip; the plurality of cutting channel through hole pieces are arranged in areas, which are originally designed to be cutting channels, in the wafer and penetrate between the upper surface and the lower surface of the wafer; the plurality of contact pads are positioned on the upper surface of the wafer and are respectively configured corresponding to the cutting channel through hole pieces; and a redistribution layer over the wafer wafer and the contact pads, respectively connecting the contact pads to the scribe line vias.
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