Interconnection process defect test structure and critical defect value acquisition method, interconnection process defect control method

Abstract

The present invention discloses an interconnection process defect test structure and a critical defect value acquisition method, as well as an interconnection process defect control method. The present invention designs a test structure and method that can obtain dish-shaped defects caused by the interconnection process, and obtains the corresponding critical defect value. According to the critical defect value, the layer-by-layer cumulative effect of dish-shaped defects can be monitored online; when the dish-shaped defects accumulate to the corresponding critical defect value, they can be discovered online in a timely manner, controlled, and remedied to avoid the occurrence of low-quality products. It is also possible to achieve online control of wafers with different metal line widths by establishing a comparison table of critical defect values ​​and metal line widths. Since the short circuit between wires caused by dish-shaped defects is a layer-by-layer cumulative effect, the present invention can be controlled online in a timely manner according to the critical defect value and can take remedial measures to avoid the occurrence of low-quality products and ensure stable product quality.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an interconnection process defect test structure, a critical defect value acquisition method, and an interconnection process defect control method. Background Art

[0002] In the dual damascene process, excess copper (Cu) is removed through chemical mechanical polishing (CMP) to form embedded copper interconnect structures. Since materials with different polishing rates are polished simultaneously, it is easy for the copper wire to be locally over-polished, resulting in dishing defects. The extent of the dishing defect is related to the width of the copper wire being polished. The wider the copper wire, the greater the copper wire density, and the more severe the dishing defect. The dishing defect reduces the effective thickness of the copper wire, resulting in increased resistance. More seriously, due to the cumulative effect of dishing defects, copper residue defects (Cu Residue) are generated in areas at the polishing limit of the copper CMP process, causing short circuits between wires, resulting in reduced chip yield and even scrapping.

[0003] Existing test keys that detect shorts between conductors cannot fully represent the distribution of copper wires within a chip. Wafer acceptance testing (WAT), performed after the process is complete, is time-consuming and often goes undetected due to process fluctuations and severe dishing defects.

[0004] Therefore, how to perform inline monitoring of dishing defects in the interconnection process and timely discover dishing defects is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an interconnection process defect test structure and a critical defect value acquisition method, as well as an interconnection process defect control method, which can monitor the layer-by-layer accumulation effect of dish-shaped defects in the interconnection process, and then realize online control of interconnection process defects to avoid the occurrence of low-quality products.

[0006] To solve the above problems, an embodiment of the present invention provides an interconnection process defect test structure, comprising: multiple test units; each of the test units comprises an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer undergo the same dielectric layer process, and only the experimental test wafer undergoes an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process comprises a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process comprises a metal filling sub-process and a metal grinding sub-process; the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes, so that the dish-shaped defect values ​​corresponding to the multiple test units gradually change, the dish-shaped defect value being the difference in film thickness between the film thickness of the top dielectric layer of the experimental test wafer in the test unit and the film thickness of the top dielectric layer of the control test wafer; through the interconnection process defect test structure, the minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all the experimental test wafers can be obtained as the critical defect value.

[0007] In some embodiments, the interconnection process defect test structure includes multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, and the critical defect value corresponding to each metal line width can be obtained through the interconnection process defect test structure.

[0008] In some embodiments, the experimental test wafer has an ID, the dielectric layer materials deposited in two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same and each dielectric layer process forms at least two dielectric layers of different materials.

[0009] To solve the above problems, an embodiment of the present invention further provides a critical defect value acquisition method for an interconnection process defect test structure, comprising the following steps: preparing multiple test units, each of the test units comprising an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer performing the same dielectric layer process, only the experimental test wafer performing one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes, wherein the dielectric layer process comprises a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process comprises a dielectric layer etching sub-process, a metal filling sub-process, and a metal grinding sub-process; obtaining the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer in each of the test units and the film thickness of the top dielectric layer of the control test wafer as the dish defect value of the test unit; obtaining the minimum value among the dish defect values ​​of the test units with abnormal experimental test wafers as the critical defect value.

[0010] In some embodiments, the method further includes: preparing multiple test unit groups with different metal line widths, each of the test unit groups including multiple test units with the same metal line width; obtaining the critical defect value of each of the test unit groups, and establishing a comparison table between critical defect value and metal line width.

[0011] To solve the above problem, an embodiment of the present invention further provides an interconnection process defect control method, comprising the following steps: obtaining a target critical defect value for wafers corresponding to a current batch of wafers that have an abnormality; performing the same dielectric layer process on the current batch of wafers and the current control wafers, with only the current batch of wafers performing an interconnection process once between two adjacent dielectric layer processes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process, and a metal grinding sub-process; obtaining a film thickness difference between the film thickness of the top dielectric layer of the current batch of wafers and the film thickness of the top dielectric layer of the current control wafer as a current dish-shaped defect value; determining whether the current dish-shaped defect value is greater than or equal to the target critical defect value, and if the current dish-shaped defect value is greater than or equal to the target critical defect value, determining that the current batch of wafers has an abnormality.

[0012] In some embodiments, after determining that the current batch of wafers has an abnormality, the method further includes: re-performing a dielectric layer grinding process on the wafers having the abnormality, and re-obtaining a current dishing defect value for determination.

[0013] The above technical solution designs a test structure and method that can obtain the dish-shaped defects caused by the interconnection process and obtain the corresponding critical defect value. According to the critical defect value, the layer-by-layer accumulation effect of the dish-shaped defects can be monitored online; when the dish-shaped defects accumulate to the corresponding critical defect value, they can be discovered online in time for control and remediation to avoid the occurrence of low-quality products. It is also possible to achieve online control of wafers with different metal line widths by establishing a comparison table of critical defect values ​​and metal line widths. Since the short circuit between wires caused by dish-shaped defects is a layer-by-layer accumulation effect, compared with the existing technology, it cannot detect the abnormality in time and cannot be remedied by the WAT test / CP test, and the wafers in the batches (Lot) during the period may face the same problem. The present invention can timely control online according to the critical defect value and take remedial measures to avoid the occurrence of low-quality products and ensure stable product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0015] Figure 1 A schematic diagram of an interconnection process defect test structure provided by an embodiment of the present invention;

[0016] Figure 2 A schematic diagram of the steps of a method for obtaining a critical defect value of an interconnect process defect test structure provided by an embodiment of the present invention.

[0017] Figure 3 A schematic diagram of the steps of a method for controlling interconnection process defects provided by one embodiment of the present invention.

[0018] Description of reference numerals:

[0019] 11 First test unit 12 Second test unit 13 Third test unit

[0020] 111 first experimental test wafer 112 first control test wafer

[0021] 121 Second experimental test wafer 122 Second control test wafer

[0022] 131 third experimental test wafer 132 third control test wafer

[0023] 100 substrate 101 first dielectric layer 102 second dielectric layer

[0024] 103 third dielectric layer 104 fourth dielectric layer

[0025] 191 first metal layer 192 second metal layer 193 third metal layer DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0027] One embodiment of the present invention provides an interconnect process defect test structure comprising multiple test units, each of which includes an experimental test wafer and a control test wafer. The experimental test wafer and the control test wafer undergo the same dielectric layer process (the same number of dielectric layer processes and the same process parameters for each dielectric layer process), with only the experimental test wafer undergoing an interconnect process between two adjacent dielectric layer processes. The dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer polishing sub-process, and the interconnect process includes a metal filling sub-process and a metal polishing sub-process. The number of interconnect processes performed on the experimental test wafers of the multiple test units gradually changes, thereby gradually changing the dish-shaped defect values ​​corresponding to the multiple test units. The dish-shaped defect value is the difference between the film thickness of the top dielectric layer of the experimental test wafer and the film thickness of the top dielectric layer of the control test wafer in the test unit. The interconnect process defect test structure can obtain the minimum value among the dish-shaped defect values ​​of all test units experiencing abnormalities on the experimental test wafers as a critical defect value.

[0028] See also Figure 1 , which is a schematic diagram of an interconnection process defect test structure provided by an embodiment of the present invention. Figure 1 As shown, the interconnection process defect test structure described in this embodiment includes: a first test unit 11 , a second test unit 12 , and a third test unit 13 .

[0029] The first test unit 11 includes a first experimental test wafer 111 and a first control test wafer 112. Both the first experimental test wafer 111 and the first control test wafer 112 undergo the same dielectric layer process twice, forming a first dielectric layer 101 and a second dielectric layer 102 on a substrate 100. Only the first experimental test wafer 111 undergoes an interconnect process between two adjacent dielectric layer processes, forming a first metal layer 191 on the first dielectric layer 101. The difference in film thickness D11 between the film thickness T11 of the top dielectric layer (second dielectric layer 102) of the first experimental test wafer 111 and the film thickness T12 of the top dielectric layer (second dielectric layer 102) of the first control test wafer 112 serves as the dishing defect value for the test unit; that is, the dishing defect value corresponding to the first test unit 11 is D11 = T12 - T11.

[0030] The second test unit 12 includes a second experimental test wafer 121 and a second control test wafer 122. Both the second experimental test wafer 121 and the second control test wafer 122 undergo the same dielectric layer process three times, forming a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 103 on the substrate 100. Only the second experimental test wafer 121 undergoes an interconnection process between two adjacent dielectric layer processes. That is, only the second experimental test wafer 121 undergoes two interconnection processes, forming a first metal layer 191 on the first dielectric layer 101 and a second metal layer 192 on the second dielectric layer 102. The difference D21 in film thickness between the film thickness T21 of the top dielectric layer (third dielectric layer 103) of the second experimental test wafer 121 and the film thickness T22 of the top dielectric layer (third dielectric layer 103) of the second control test wafer 122 is used as the dishing defect value for that test unit. That is, the dishing defect value corresponding to the second test unit 12 is D21 = T22 - T21, and D21 > D11.

[0031] The third test unit 13 includes a third experimental test wafer 131 and a third control test wafer 132. The third experimental test wafer 131 and the third control test wafer 132 both underwent four identical dielectric layer processes, forming a first dielectric layer 101, a second dielectric layer 102, a third dielectric layer 103, and a fourth dielectric layer 104 on the substrate 100. Only the third experimental test wafer 131 underwent one interconnection process between two adjacent dielectric layer processes, i.e., only the third experimental test wafer 131 underwent three interconnection processes, forming a first metal layer 191 on the first dielectric layer 101, a second metal layer 192 on the second dielectric layer 102, and a third metal layer 193 on the third dielectric layer 103. The difference D31 in film thickness between the film thickness T31 of the top dielectric layer (fourth dielectric layer 104) of the third experimental test wafer 131 and the film thickness T32 of the top dielectric layer (fourth dielectric layer 104) of the third control test wafer 132 is used as the dishing defect value for that test unit. That is, the dishing defect value corresponding to the third test unit 13 is D31 = T32 - T31, and D31 > D21.

[0032] By analogy, the number of interconnection processes performed on the experimental test wafers of multiple test units gradually changes, so that the dishing defect values ​​corresponding to the multiple test units gradually change, that is, the multiple test units reflect the layer-by-layer accumulation effect of the dishing defect values.

[0033] In some embodiments, electron beam measurement can be used to measure the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer online, and the difference in film thickness between the two can be obtained as the dishing defect value of the test unit. For the control test wafer, electron beam measurement can be used with the dielectric layer material deposited in the previous dielectric layer process as the target point. For the experimental test wafer, electron beam measurement can be used with the metal layer formed in the interconnection process before the current dielectric layer process as the target point.

[0034] In some embodiments, the dielectric layer materials deposited in two consecutive dielectric layer processes are different, and the metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness (Thickness) of the top dielectric layer; the top dielectric layer is a single dielectric layer made of the corresponding material formed after the current dielectric layer process. The dielectric layer (IMD) material deposited in two consecutive dielectric layer processes can be selected from one of silicon oxide, silicon oxynitride, and silicon nitride; for example, the dielectric layer material deposited in the previous dielectric layer process can be silicon oxide, and the dielectric layer material deposited in the next dielectric layer process can be silicon oxynitride. For the control test wafer, since the dielectric layers formed by each dielectric layer process can be distinguished by material, the dielectric layer material deposited by the previous dielectric layer process can be used as the target point for electron beam measurement. For the experimental test wafer, the metal layer formed by the interconnection process before the current dielectric layer process can be used as the target point for electron beam measurement.

[0035] In some embodiments, all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers of different materials. The metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness of the top dielectric layer; the top dielectric layer is a multi-layer composite dielectric layer using different materials formed after the current dielectric layer process. For example, the dielectric layer (IMD) material deposited in each dielectric layer process can be a three-layer composite dielectric layer of silicon oxide, silicon oxynitride, and silicon nitride. For control test wafers, electron beam measurement can be used with the dielectric layer material corresponding to the topmost dielectric layer deposited by the previous dielectric layer process as the target point. For experimental test wafers, electron beam measurement can be used with the metal layer formed by the interconnection process before the current dielectric layer process as the target point.

[0036] By gradually varying the number of interconnection processes performed on the experimental test wafers of multiple test units, the dish-shaped defect values ​​corresponding to the multiple test units gradually vary; that is, the multiple test units reflect the layer-by-layer accumulation of dish-shaped defect values. When the dish-shaped defect values ​​accumulate to the point where an abnormality occurs on the experimental test wafer, the minimum dish-shaped defect value among all the test units with abnormalities on the experimental test wafers can be obtained as the critical defect value. Specifically, by performing a WAT ​​test or a CP test on the experimental test wafers of all the test units, the test units with abnormalities on the experimental test wafers can be screened out, thereby obtaining the critical defect value.

[0037] In some embodiments, the interconnection process may be a metal copper interconnection process for forming an embedded copper interconnection structure. The anomaly is a short circuit between conductors caused by a copper residual defect.

[0038] In some embodiments, multiple test unit groups with different metal line widths can be provided, each of which includes multiple test units with the same metal line width, thereby obtaining a critical defect value corresponding to each metal line width. The critical defect value can be used to perform online detection of interconnection process defects.

[0039] Based on the same inventive concept, the present invention also provides a method for obtaining critical defect values ​​of an interconnection process defect test structure. The method prepares the interconnection process defect test structure described in the above embodiment of the present invention and performs measurements to obtain corresponding critical defect values, and further establishes a corresponding relationship between the dish-shaped defect value and the number of interconnection processes, which is then used to perform online card control of interconnection process defects to avoid the occurrence of low-quality products.

[0040] See also Figure 2 , which is a schematic diagram of the steps of a method for obtaining a critical defect value of an interconnection process defect test structure provided by an embodiment of the present invention. Figure 2 As shown, in this embodiment, the method includes the following steps: S21, preparing multiple test units, each of the test units including an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer performing the same dielectric layer process, only the experimental test wafer performing one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes; S22, obtaining the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer and the film thickness of the top dielectric layer of the control test wafer in each of the test units as the dish defect value of the test unit; S23, obtaining the minimum value among the dish defect values ​​of the test units with abnormal experimental test wafers as the critical defect value.

[0041] Regarding step S21, multiple test units are prepared, each of which includes an experimental test wafer and a control test wafer. The experimental test wafer and the control test wafer perform the same dielectric layer process, and only the experimental test wafer performs an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of multiple test units gradually changes. Among them, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process, and a metal grinding sub-process. The specific process flow can refer to the existing process and will not be repeated here. The multiple test units prepared can refer to Figure 1 shown.

[0042] The test unit preparation steps are as follows: (1) The same dielectric layer process is performed on the experimental test wafer and the control test wafer in the same test unit to form a dielectric layer with the same film thickness. (2) A bright field mask (Clear Mask) and a dark field mask (Dark Mask) can be used in conjunction with positive photoresist and negative photoresist to form grooves for filling metal only on the experimental test wafer, and the experimental test wafer is subjected to an interconnection process. Since materials with different polishing rates are polished simultaneously, the experimental test wafer is prone to local over-polishing of metal lines. (3) The same dielectric layer process is performed on the experimental test wafer and the control test wafer again to generate a dishing defect (Dishing). Since the experimental test wafer has local over-polishing of metal lines, the dielectric layer grinding sub-process in the current dielectric layer process will accumulate this dishing defect. Therefore, the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer are measured separately. The dishing defect value of the test unit after the current dielectric layer process can be obtained based on the difference in film thickness between the two. As needed, repeat the above steps (2) to (3) to form a test unit in which the experimental test wafer has performed the corresponding number of interconnection processes. Among them, in the dark field mask, most areas are opaque, and only the pattern area that needs to be transferred to the wafer is translucent; during the exposure process, only these small translucent areas can allow ultraviolet light to irradiate the photoresist; in this way, the photoresist exposed to light undergoes chemical changes, while the remaining majority of areas remain unexposed. The bright field mask is just the opposite, and its design feature is that most areas are translucent. In the positive photoresist process, after the coating is exposed and developed during the photoresist process, the exposed part is dissolved and the unexposed part remains. In the negative photoresist process, after the coating is exposed and developed during the photoresist process, the exposed part is retained and the unexposed part is dissolved.

[0043] In some embodiments, the experimental test wafer has an ID, and the step of preparing the plurality of test units specifically includes providing a process tool and a process menu, wherein the process menu configures the process tool to execute the interconnection process after completing the current dielectric layer process and upon recognizing the ID of the experimental test wafer. Thus, the experimental test wafer only executes the interconnection process once between two adjacent dielectric layer processes.

[0044] In some embodiments, the dielectric layer materials deposited in two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers of different materials.

[0045] Regarding step S22 , a thickness difference between the top dielectric layer of the experimental test wafer and the top dielectric layer of the control test wafer in each test unit is obtained as a dishing defect value of the test unit.

[0046] Specifically, electron beam measurement can be used to measure the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer online, and the difference in film thickness between the two can be obtained as the dishing defect value of the test unit. For the control test wafer, electron beam measurement can be used with the dielectric layer material deposited in the previous dielectric layer process as the target point. For the experimental test wafer, electron beam measurement can be used with the metal layer formed in the interconnection process before the current dielectric layer process as the target point.

[0047] In some embodiments, the dielectric layer materials deposited in two consecutive dielectric layer processes are different, and the metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness (Thickness) of the top dielectric layer; the top dielectric layer is a single dielectric layer made of the corresponding material formed after the current dielectric layer process. The dielectric layer (IMD) material deposited in two consecutive dielectric layer processes can be selected from one of silicon oxide, silicon oxynitride, and silicon nitride; for example, the dielectric layer material deposited in the previous dielectric layer process can be silicon oxide, and the dielectric layer material deposited in the next dielectric layer process can be silicon oxynitride. For the control test wafer, since the dielectric layers formed by each dielectric layer process can be distinguished by material, the dielectric layer material deposited by the previous dielectric layer process can be used as the target point for electron beam measurement. For the experimental test wafer, the metal layer formed by the interconnection process before the current dielectric layer process can be used as the target point for electron beam measurement.

[0048] In some embodiments, all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers of different materials. The metal thickness after the corresponding metal grinding sub-process can be indirectly reflected by measuring the thickness of the top dielectric layer; the top dielectric layer is a multi-layer composite dielectric layer using different materials formed after the current dielectric layer process. For example, the dielectric layer (IMD) material deposited in each dielectric layer process can be a three-layer composite dielectric layer of silicon oxide, silicon oxynitride, and silicon nitride. For control test wafers, electron beam measurement can be used with the dielectric layer material corresponding to the topmost dielectric layer deposited by the previous dielectric layer process as the target point. For experimental test wafers, electron beam measurement can be used with the metal layer formed by the interconnection process before the current dielectric layer process as the target point.

[0049] Regarding step S23 , the minimum value among the dish-shaped defect values ​​of all test units with abnormalities on the experimental test wafers is obtained as the critical defect value.

[0050] In some embodiments, step S23 specifically includes: (1) performing a WAT ​​test or a CP test on the experimental test wafers of all the test units to screen out the test units with abnormal experimental test wafers; (2) obtaining the minimum value of the dish-shaped defect values ​​of the test units with abnormal experimental test wafers as the critical defect value. By setting the number of interconnection processes performed by the experimental test wafers of multiple test units to gradually change, the dish-shaped defect values ​​corresponding to the multiple test units gradually change; that is, the multiple test units reflect the layer-by-layer accumulation effect of the dish-shaped defect values. When the dish-shaped defect values ​​accumulate to the point where the experimental test wafer is abnormal, the minimum value of the dish-shaped defect values ​​of the test units with abnormal experimental test wafers can be obtained as the critical defect value. Specifically, the WAT test or the CP test can be performed on the experimental test wafers of all the test units to screen out the test units with abnormal experimental test wafers, and then the critical defect value can be obtained. WAT (Wafer Acceptance Test) is also called Process Control Monitor (PCM). WAT measures the electrical parameters of specific test structures after wafer product tape-out and before quality inspection. The purpose of WAT is to test the electrical parameters of specific test structures on the wafer to detect the process conditions of each wafer product, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specifications of the process technology platform. CP (Chip Probing) is located between wafer manufacturing and packaging in the entire chip production process and typically includes voltage, current, timing, and functional verification.

[0051] In some embodiments, the interconnection process may be a metal copper interconnection process for forming an embedded copper interconnection structure. The anomaly is a short circuit between conductors caused by a copper residual defect.

[0052] In this embodiment, the method further includes: S24, preparing multiple test unit groups with different metal line widths, each test unit group including multiple test units with the same metal line width; and S25, obtaining the critical defect value of each test unit group and establishing a comparison table between critical defect value and metal line width. Step S24 can be performed simultaneously with step S21.

[0053] For the metal copper interconnection process, the main reason for dishing defects is that during the CMP process, due to the different physical and chemical properties of copper and dielectric layer materials, the polishing rates of different materials are also inconsistent. The copper removal rate is too fast and the dielectric layer material removal is slow, which easily causes local over-polishing of the copper line and produces serious dishing defects. As the copper line width increases, the copper density (Density) also increases, and the dishing defects also tend to increase. By setting up multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, so that the critical defect value corresponding to each metal line width can be obtained. The critical defect value can be used to perform online card control of interconnection process defects.

[0054] Based on the same inventive concept, the present invention also provides a method for controlling interconnection process defects.

[0055] See also Figure 3 , which is a schematic diagram of the steps of the interconnection process defect control method provided by an embodiment of the present invention. Figure 3 As shown, in this embodiment, the method includes the following steps: S31, obtaining a target critical defect value for abnormal wafers corresponding to the current batch of wafers; S32, performing the same dielectric layer process on the current batch of wafers and the current control wafers, only the current batch of wafers performs an interconnection process between two adjacent dielectric layer processes; S33, obtaining a film thickness difference between the film thickness of the top dielectric layer of the current batch of wafers and the film thickness of the top dielectric layer of the current control wafer as a current dish-shaped defect value; S34, judging whether the current dish-shaped defect value is greater than or equal to the target critical defect value; if the current dish-shaped defect value is greater than or equal to the target critical defect value, it is determined that the current batch of wafers has an abnormality.

[0056] Regarding step S31, the target critical defect value of the wafers corresponding to the current batch of wafers is obtained. Figures 1 and 2 The interconnection process defect test structure and critical defect value acquisition method shown are used to obtain the target critical defect value of the wafer corresponding to the current batch of wafers that has an abnormality.

[0057] In some embodiments, step S31 specifically includes: (11) preparing multiple test units, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer have the same metal line width as the current batch of wafers, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of multiple test units gradually changes. Among them, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process. For details, please refer to Figures 1 and 2 (12) Obtain the difference in film thickness between the top dielectric layer of the experimental test wafer and the top dielectric layer of the control test wafer in each test unit as the dish defect value of the test unit. Figures 1 and 2 The electron beam measurement method is used for online measurement. (13) The minimum value of the dish-shaped defect values ​​of all test units with abnormalities in the experimental test wafers is obtained as the target critical defect value. Figures 1 and 2 The WAT test or CP test method screens out test units with abnormalities in the experimental test wafer.

[0058] In some embodiments, step S31 specifically includes: (21) preparing multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer perform the same dielectric layer process, only the experimental test wafer performs one interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed by the experimental test wafers of the multiple test units gradually changes. Among them, the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process and a metal grinding sub-process. For details, please refer to Figures 1 and 2 (22) Obtain the difference in film thickness between the top dielectric layer of the experimental test wafer and the top dielectric layer of the control test wafer in each test unit as the dish defect value of the test unit. Figures 1 and 2 The electron beam measurement method is used for online measurement. (23) The minimum value of the dish-shaped defect values ​​of all test units with abnormalities in the experimental test wafers is obtained as the critical defect value, and a comparison table of critical defect values ​​and metal line widths is established. Specifically, Figures 1 and 2The WAT test or CP test method screens out the test units with abnormalities in the experimental test wafer. (24) The comparison table is searched according to the metal line width of the current batch of wafers to obtain the corresponding critical defect value as the target critical defect value.

[0059] Regarding step S32, the same dielectric layer process is performed on the current batch of wafers and the current reference wafer, with only the current batch of wafers undergoing an interconnection process between two adjacent dielectric layer processes. The reference wafer can be set up in the same manner as the test unit described above to monitor dishing defect values.

[0060] Regarding step S33, the thickness difference between the top dielectric layer of the current batch of wafers and the top dielectric layer of the current reference wafer is obtained as the current dishing defect value. Figures 1 and 2 The electron beam measurement method is used for online measurement. The number of executions of the dielectric layer process can be set to start from 2 times, and the current dishing defect value is obtained once each time the dielectric layer process is executed.

[0061] Regarding step S34, determining whether the current dishing defect value is greater than or equal to the target critical defect value, if the current dishing defect value is greater than or equal to the target critical defect value, the current batch of wafers is determined to be abnormal. By comparing the current dishing defect value with the target critical defect value, it is possible to directly determine whether the current batch of wafers is abnormal without using complex test patterns (Test Keys) or waiting until the process is complete to perform WAT testing or CP testing. This allows for the timely detection of wafers with severe dishing defects, preventing short circuits between conductors that could result in substandard products.

[0062] In some embodiments, after determining that the current batch of wafers has an abnormality, the method further includes: re-performing the dielectric layer grinding process on the abnormal wafers and re-obtaining the current dishing defect value for judgment. In other words, for wafers that exceed the target critical defect value for the current batch of wafers, re-grinding (CMP rework) is performed to avoid short circuits between wires and resulting in low-quality products. Online inspections can also be performed to identify the causes of dishing defects (dishing) and process instability, and timely adjustments can be made to prevent more wafers from being affected.

[0063] From the above content, it can be seen that the present invention designs a test structure and method that can obtain the dish-shaped defects caused by the interconnection process and obtain the corresponding critical defect value. According to the critical defect value, the layer-by-layer cumulative effect of the dish-shaped defects can be monitored online; when the dish-shaped defects accumulate to the corresponding critical defect value, they can be discovered online in time for control and remediation to avoid the occurrence of low-quality products. It is also possible to achieve online control of wafers with different metal line widths by establishing a comparison table of critical defect values ​​and metal line widths. Since the short circuit between wires caused by dish-shaped defects is a layer-by-layer cumulative effect, compared with the existing technology, it cannot detect the abnormality in time, and it cannot be remedied by the WAT test / CP test, and the wafers in the batches (Lot) during the period may face the same problem. The present invention can timely control online according to the critical defect value and take remedial measures to avoid the occurrence of low-quality products and ensure stable product quality.

[0064] It should be noted that the terms "including," "having," and their variations, as used in this document, are intended to cover non-exclusive inclusions. Terms such as "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a specific order or precedence, unless the context clearly indicates otherwise. Such usage should be understood to be interchangeable where appropriate. The term "one or more" may be used to describe a feature, structure, or characteristic in the singular, or in the plural, depending at least in part on the context, to describe a feature, structure, or combination of features. The term "based on" should be understood as not necessarily intended to express an exclusive set of factors, but may alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, the embodiments of the present invention and the features therein may be combined with one another, unless there is a conflict. Furthermore, descriptions of well-known components and technologies have been omitted from the above description to avoid unnecessary confusion regarding the concepts of the present invention. In each of the above embodiments, each embodiment focuses on its differences from the other embodiments, and reference may be made to the same or similar parts between the embodiments.

[0065] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An interconnection process defect test structure, characterized in that: include: Multiple test units; Each of the test units includes an experimental test wafer and a control test wafer, wherein the experimental test wafer and the control test wafer are subjected to the same dielectric layer process, except that the experimental test wafer is subjected to an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer polishing sub-process, and the interconnection process includes a metal filling sub-process and a metal polishing sub-process; The number of interconnection processes performed on the experimental test wafers of the plurality of test units gradually changes, so that the dishing defect values ​​corresponding to the plurality of test units gradually change, the dishing defect value being the difference in film thickness between the film thickness of the top dielectric layer of the experimental test wafer and the film thickness of the top dielectric layer of the control test wafer in the test unit; The interconnection process defect test structure can be used to obtain the minimum value among the dish-shaped defect values ​​of all test units with abnormalities on the experimental test wafer as a critical defect value.

2. The interconnection process defect test structure according to claim 1, characterized in that: It comprises a plurality of test unit groups with different metal line widths, each of the test unit groups comprises a plurality of test units with the same metal line width, and the critical defect value corresponding to each metal line width can be obtained through the interconnection process defect test structure.

3. The interconnection process defect test structure according to claim 1, wherein: The experimental test wafer has an ID; The dielectric layer materials deposited in two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same, and each dielectric layer process forms at least two dielectric layers with different materials.

4. A method for obtaining a critical defect value of an interconnect process defect test structure, characterized in that: The steps include: Prepare multiple test units, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer undergo the same dielectric layer process, only the experimental test wafer undergoes an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed on the experimental test wafers of the multiple test units gradually changes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer polishing sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process, and a metal polishing sub-process; Obtaining a film thickness difference between a film thickness of a top dielectric layer of an experimental test wafer and a film thickness of a top dielectric layer of a control test wafer in each test unit as a dishing defect value of the test unit; The minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers is obtained as the critical defect value.

5. The method according to claim 4, characterized in that The method further comprises: preparing a plurality of test unit groups with different metal line widths, each of the test unit groups including a plurality of the test units with the same metal line width; The critical defect value of each test unit group is obtained, and a comparison table of critical defect value and metal line width is established.

6. The method according to claim 4, characterized in that The dielectric layer materials deposited in two consecutive dielectric layer processes are different, or all the dielectric layer processes are the same and each dielectric layer process forms at least two dielectric layers of different materials; the step of obtaining the film thickness difference between the film thickness of the top dielectric layer of the experimental test wafer and the film thickness of the top dielectric layer of the control test wafer in each test unit as the dishing defect value of the test unit specifically includes: The electron beam measurement method is used to measure the film thickness of the top dielectric layer of the experimental test wafer after the current dielectric layer process and the film thickness of the top dielectric layer of the control test wafer online, and the film thickness difference between the two is obtained as the dishing defect value of the test unit.

7. The method according to claim 4, characterized in that The step of obtaining the minimum value of the dish-shaped defect values ​​of all test units with abnormalities on the experimental test wafers as the critical defect value specifically includes: Performing a WAT ​​test or a CP test on the experimental test wafers of all the test units to screen out the test units with abnormal experimental test wafers; The minimum value among the dish-shaped defect values ​​of the test units in which abnormalities occur in all experimental test wafers is obtained as the critical defect value.

8. A method for controlling interconnection process defects, characterized in that: The steps include: Obtaining target critical defect values ​​corresponding to wafer anomalies of the current batch of wafers; Performing the same dielectric layer process on the current batch of wafers and the current control wafers, except that the current batch of wafers performs an interconnection process between two adjacent dielectric layer processes, wherein the dielectric layer process includes a dielectric layer deposition sub-process and a dielectric layer grinding sub-process, and the interconnection process includes a dielectric layer etching sub-process, a metal filling sub-process, and a metal grinding sub-process; Obtaining a film thickness difference between a film thickness of a top dielectric layer of a current batch of wafers and a film thickness of a top dielectric layer of a current reference wafer as a current dishing defect value; It is determined whether the current dishing defect value is greater than or equal to the target critical defect value. If the current dishing defect value is greater than or equal to the target critical defect value, it is determined that the current batch of wafers is abnormal.

9. The method according to claim 8, characterized in that The step of obtaining the target critical defect value of wafer abnormalities corresponding to the current batch of wafers specifically includes: Preparing a plurality of test units, each of the test units comprising an experimental test wafer and a control test wafer, wherein the experimental test wafer and the control test wafer have the same metal line width as the wafers in the current batch, the experimental test wafer and the control test wafer undergo the same dielectric layer process, only the experimental test wafer undergoes an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed on the experimental test wafers of the plurality of test units gradually changes; Obtaining a film thickness difference between a film thickness of a top dielectric layer of an experimental test wafer and a film thickness of a top dielectric layer of a control test wafer in each test unit as a dishing defect value of the test unit; The minimum value among the dish-shaped defect values ​​of the test units with abnormalities in all experimental test wafers is obtained as the target critical defect value.

10. The method according to claim 8, characterized in that The step of obtaining the target critical defect value of wafer abnormalities corresponding to the current batch of wafers specifically includes: Prepare multiple test unit groups with different metal line widths, each of the test unit groups includes multiple test units with the same metal line width, each of the test units includes an experimental test wafer and a control test wafer, the experimental test wafer and the control test wafer undergo the same dielectric layer process, only the experimental test wafer undergoes an interconnection process between two adjacent dielectric layer processes, and the number of interconnection processes performed on the experimental test wafers of the multiple test units gradually changes; Obtaining a film thickness difference between a film thickness of a top dielectric layer of an experimental test wafer and a film thickness of a top dielectric layer of a control test wafer in each test unit as a dishing defect value of the test unit; Obtain the minimum value of the dish-shaped defect values ​​of all test units with abnormalities on the experimental test wafers as the critical defect value, and establish a comparison table between the critical defect value and the metal line width; The comparison table is searched according to the metal line width of the current batch of wafers to obtain the corresponding critical defect value as the target critical defect value.

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