Clock frequency monitoring circuit and method

Abstract

The invention provides a clock frequency monitoring circuit and method, and the circuit comprises a first multiplexer which selects and outputs a first clock signal; the second multiplexer is used for selectively outputting a second clock signal; the first counter is triggered based on the first enable signal and is used for counting the first clock signal progressively until the first clock signal progressively decreases to 0; the second counter is triggered based on the second enable signal, performs incremental counting on the second clock signal and outputs a count value; the count value comparison module is used for comparing the count value with a target set value and outputting a state indication signal according to a comparison result; the counter heavy load controller is used for generating a first enable signal and a second enable signal according to the first clock signal and the second clock signal, and triggering the count value comparison module to start working after the counting of the second counter is finished; and determining whether to restart the next round of monitoring according to the state indication signal. By using the scheme of the invention, monitoring of any clock frequency to be measured can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of clock monitoring, and in particular to a clock frequency monitoring circuit and method. Background Art

[0002] The clock signal is an indispensable signal for digital integrated circuits and is regarded as the "heart" of the chip. The clock frequency not only affects the overall operating speed of the chip, but may also affect the correct transmission of data. If the clock frequency is unstable or the clock signal is lost, it may cause abnormal transmission of data inside the chip, or even serious consequences such as abnormal chip operation. Therefore, whether the chip clock frequency is normal or not is crucial, and clock calibration, measurement and other detection mechanisms need to be considered at the beginning of chip design. For this reason, a clock frequency monitoring circuit is usually designed to monitor in real time whether the frequency of the target clock meets the requirements.

[0003] Clock frequency monitoring circuits can usually be implemented by analog circuits or digital circuits. Analog circuits are generally designed as clock comparators, which detect whether the frequency of the clock to be tested meets the requirements by directly comparing the frequencies of the reference clock and the clock to be tested; digital circuits generally use a counter to count the reference clock and the clock to be tested for a period of time, and determine the clock frequency relationship by comparing the count values, thereby detecting whether the frequency of the clock to be tested meets the requirements. Existing clock frequency monitoring circuits mostly monitor a specific or a certain range of clock frequencies. Once the frequency of the clock to be tested changes, the circuit needs to be redesigned, and the versatility and flexibility of the monitoring circuit are poor. Summary of the invention

[0004] The embodiments of the present application provide a clock frequency monitoring circuit and method, which improve the versatility of the monitoring circuit and meet the monitoring requirements for a variety of different clock frequencies to be tested.

[0005] On the one hand, an embodiment of the present application provides a clock frequency monitoring circuit, the circuit comprising:

[0006] A first multiplexer, used for selecting a plurality of input first clock signal sources and outputting a first clock signal CLK0; the first clock signal CLK0 is used as a reference clock signal;

[0007] A second multiplexer, used for selecting a plurality of second clock signal sources inputted, and outputting a second clock signal CLK1; the second clock signal CLK1 is used as a monitored clock signal;

[0008] A first counter, configured to be triggered based on a first enable signal CLK0_ST, and to count down the first clock signal CLK0 starting from a loaded count initial value CLK0_CNT until it counts down to 0;

[0009] a second counter, configured to count up the second clock signal CLK1 based on the trigger of the second enable signal CLK1_ST, and output a count value cnt1 until the second enable signal CLK1_ST becomes invalid and the counting ends;

[0010] A count value comparison module, used for comparing the count value cnt1 with the target setting value CLK1_CNT, and outputting a state indication signal DCC_IF according to the comparison result to indicate the state of the monitored clock;

[0011] a counter reload controller, configured to generate the first enable signal CLK0_ST and the second enable signal CLK1_ST according to the first clock signal CLK0 and the second clock signal CLK1, and trigger the count value comparison module to start working after the second counter finishes counting; and to determine whether to restart the next round of monitoring according to the state indication signal DCC_IF;

[0012] The count initial value CLK0_CNT of the first counter and the target setting value CLK1_CNT are configured according to the frequencies of the first clock signal CLK0 and the second clock signal CLK1 based on the principle of consistent timing duration.

[0013] Optionally, the counter reload controller synchronizes the first enable signal CLK0_ST to the second clock domain through a trigger beat mode to generate the second enable signal CLK1_ST.

[0014] Optionally, the first enable signal CLK0_ST remains valid during the down-counting process of the first counter; and the second enable signal CLK1_ST remains valid during the up-counting process of the second counter.

[0015] Optionally, when the absolute value of the difference between the count value cnt1 and the target set value CLK1_CNT is less than or equal to a set threshold ACC_VLU, the status indication signal output by the count value comparison module is a low level; otherwise, the status indication signal output is a high level.

[0016] Optionally, the count value comparison module includes:

[0017] An adder, used for calculating the sum of the target setting value CLK1_CNT and the setting threshold ACC_VLU, and outputting the sum;

[0018] A subtractor, used for calculating the difference between the target setting value CLK1_CNT and the setting threshold ACC_VLU, and outputting the difference;

[0019] A first judgment unit, used for comparing the sum value with the count value cnt1, and outputting a first comparison result;

[0020] A second judgment unit, used for comparing the difference value with the count value cnt1, and outputting a second comparison result;

[0021] An OR gate, used for performing an OR logic operation on the first comparison result and the second comparison result, and outputting an operation result;

[0022] The D flip-flop is used to output the operation result as the state indication signal DCC_IF.

[0023] Optionally, the adder is further used to set the sum value to the current maximum value of the number of digits when the sum value is greater than the current maximum value of the number of digits; the subtractor is further used to set the difference value to 0 when the target setting value CLK1_CNT is less than the setting threshold ACC_VLU.

[0024] Optionally, the counter reload controller is implemented by a state machine, and the state machine operates in a first clock domain.

[0025] Optionally, the state machine includes the following states: idle state, loading state, waiting state for the first count to end, waiting state for the second count to end, detection state, and reloading state;

[0026] When the circuit system is reset, the state machine is in an idle state;

[0027] After the system enable signal is valid, the state of the state machine first jumps from idle state -> loading state -> waiting for the first count end state -> waiting for the second count end state -> detection state -> reloading state, and then cyclically jumps from waiting for the first count end state -> waiting for the second count end state -> detection state -> reloading state.

[0028] Optionally, the first clock signal source is provided by an on-chip clock, or provided by an external GPIO input clock.

[0029] Optionally, the circuit further comprises: an interrupt controller, configured to output an interrupt signal DCC_INT when the status indication signal DCC_IF indicates that the monitored clock is abnormal.

[0030] Optionally, the circuit further includes: a status register, used for storing the status indication signal DCC_IF.

[0031] On the other hand, an embodiment of the present application further provides a clock frequency monitoring method, the method comprising:

[0032] Acquire setting parameters, the parameters including: a first selection signal CLK0_SELECT, a second selection signal CLK1_SELECT, an initial count value CLK0_CNT of a first counter, a target set value CLK1_CNT, a set threshold ACC_VLU, and an interrupt enable signal DCC_IE; the first selection signal CLK0_SELECT is used to select a first clock signal as a reference clock signal; the second selection signal CLK1_SELECT is used to select a second clock signal as a monitored clock signal; the initial count value CLK0_CNT and the target set value CLK1_CNT of the first counter are configured according to the frequencies of the first clock signal CLK0 and the second clock signal CLK1 based on the principle of consistent timing duration;

[0033] Control the first counter to count down from the initial count value CLK0_CNT based on the first clock signal in the first clock domain through a first counter enable signal until the initial count value CLK0_CNT is reloaded to the first counter after the count is counted down to 0;

[0034] The second clock signal uses a trigger beat method to synchronize the first counter enable signal to the second clock domain to generate a second counter enable signal;

[0035] Control the second counter to count up from 0 based on the second clock signal through the second counter enable signal until the counting ends when the second counter enable signal is invalid, and maintain the current count value;

[0036] Compare the current count value output by the second counter with the target setting value CLK1_CNT in the first clock domain to obtain a comparison result;

[0037] Outputting a state indication signal according to the comparison result to indicate the state of the monitored clock;

[0038] If the status indication signal indicates that the status is normal, the next round of monitoring is restarted.

[0039] Optionally, outputting a status indication signal according to the comparison result includes: if the comparison result meets the set threshold ACC_VLU requirement, outputting a status indication signal indicating a normal status; otherwise, outputting a status indication signal indicating an abnormal status.

[0040] Optionally, the method further includes: outputting an interrupt signal if the status indication signal indicates that the status is abnormal.

[0041] Optionally, the method further includes: saving the status indication signal in a status register.

[0042] Optionally, the method further comprises:

[0043] Saving the current count value output by the second counter into a count value register;

[0044] If the status indication signal indicates that the status is abnormal, the monitoring is stopped, the count value stored in the count value register is read, and the clock abnormality is located according to the read count value;

[0045] After the status indication signal indicating the abnormal status is cleared, monitoring is continued.

[0046] The clock frequency monitoring circuit and method provided in the embodiment of the present application can realize the clock frequency monitoring function with controllable measurement duration, adjustable jitter tolerance, and no limit on the reference clock and monitored clock frequency by externally configuring the reference clock count value (i.e., the counting duration of the first counter is CLK0_CNT), the monitored clock count value (i.e., the target setting value CLK1_CNT), the counting tolerance value (i.e., the set threshold ACC_VLU) and other parameters. The scheme of the present application can realize the monitoring of any clock frequency to be measured.

[0047] Furthermore, when an abnormality occurs in the monitored clock, the abnormality can be indicated in a variety of ways, such as an interruption method or a register reading method, which can better meet different application requirements.

[0048] Furthermore, it is also possible to achieve that when an abnormality occurs, the circuit operation is suspended, and the current count value of the second counter is retained to quickly locate the cause of the abnormality. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide a clearer understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation to the present application. In the accompanying drawings:

[0050] Figure 1 is a structural schematic diagram of a clock frequency monitoring circuit provided in an embodiment of the present application;

[0051] Figure 2 is another structural schematic diagram of a clock frequency monitoring circuit provided in an embodiment of the present application;

[0052] Figure 3 is another structural schematic diagram of a clock frequency monitoring circuit provided in an embodiment of the present application;

[0053] Figure 4 is a state transition diagram of a state machine in a counter reload controller in an embodiment of the present application;

[0054] Figure 5It is a schematic diagram of the working timing of the clock frequency monitoring circuit in the embodiment of the present application;

[0055] Figure 6 This is a schematic diagram of the structure of the count value comparison module in the embodiment of the present application;

[0056] Figure 7 It is a flow chart of the clock frequency monitoring method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the above-mentioned purposes, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0058] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0059] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0060] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0061] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0062] In response to the problem that existing clock frequency monitoring circuits lack versatility and flexibility, the embodiments of the present application provide a clock frequency monitoring circuit and method, which uses a multiplexer to select a reference clock signal and a monitored clock signal with a plurality of different frequencies, so that the solution can adapt to a variety of different clock frequencies, and can configure a variety of measurement parameters according to actual needs to meet a variety of different measurement requirements.

[0063] like Figure 1, which is a schematic diagram of the structure of a clock frequency monitoring circuit provided in an embodiment of the present application.

[0064] In this embodiment, the clock frequency monitoring circuit includes: a first multiplexer MUX0, a second multiplexer MUX1, a counter reload controller 10, a first counter 21, a second counter 22, and a count value comparison module 30. Wherein:

[0065] The first multiplexer MUX0 is used to select multiple input first clock signal sources CLK0_SOURCE and output a first clock signal CLK0; the first clock signal CLK0 is used as a reference clock signal.

[0066] The second multiplexer MUX1 is used to select the input multiple second clock signal sources CLK1_SOURCE and output the second clock signal CLK1; the second clock signal CLK1 is used as the monitored clock signal.

[0067] The first clock signal source CLK0_SOURCE and the second clock signal source CLK1_SOURCE are a series of clocks to be selected. In specific implementation, the first clock signal source CLK0_SOURCE can be provided by an internal clock or an external GPIO (General Purpose Input / Output) input clock, which is not limited in this embodiment of the application.

[0068] The control signal of the first multiplexer MUX0 is CLK0_SELECT, and the control signal of the second multiplexer MUX1 is CLK1_SELECT. CLK0_SELECT and CLK1_SELECT are multi-bit signals and can be configured externally.

[0069] The first counter 21 is used to count down the first clock signal CLK0 when the first enable signal CLK0_ST becomes valid, until it counts down to 0; the initial count value of the first counter 21 is CLK0_CNT. CLK0_CNT is a multi-bit signal and can be configured externally.

[0070] The second counter 22 is used to count up the second clock signal CLK1 when the second enable signal CLK1_ST becomes valid, and output the count value cnt1 until the second enable signal CLK1_ST becomes invalid and the counting ends. If the count value cnt1 reaches the maximum value of the current bit when CLK1_ST is valid, cnt1 maintains the maximum value to avoid overflow of the count value. The use of the increment counting method is conducive to the direct use of the final count value.

[0071] Among them, the first enable signal CLK0_ST input to the first counter 21 and the second enable signal CLK1_ST input to the second counter 22 are generated by the counter reload controller 10. The counter reload controller 10 generates the first enable signal CLK0_ST and the second enable signal CLK1_ST according to the first clock signal CLK0 and the second clock signal CLK1. Specifically, the counter reload controller 10 generates the first enable signal CLK0_ST based on the first clock signal CLK0, and synchronizes the first enable signal CLK0_ST to the second clock domain through a trigger tapping method to generate the second enable signal CLK1_ST. The trigger tapping method is a commonly used synchronization method, also known as the delayed tapping method. By inserting a double-stage trigger between the two clock domains to ensure the stable transmission of the signal across the clock domain, the metastable signal can be effectively prevented from being transmitted to the next level circuit.

[0072] It should be noted that the first enable signal CLK0_ST remains valid during the count-down process of the first counter 21. For example, in some embodiments, CLK0_ST is valid when it is at a high level, and invalid when it is at a low level. Similarly, the second enable signal CLK1_ST remains valid during the count-up process of the second counter 22. For example, in some embodiments, CLK1_ST is valid when it is at a high level, and invalid when it is at a low level.

[0073] The counter reload controller 10 is further used to trigger the count value comparison module 30 to start working after the second counter 22 finishes counting, for example, by detecting the count of the counter check_cnt to trigger the count value comparison module 30 to start working.

[0074] Accordingly, the count value comparison module 30 compares the count value cnt1 output by the second counter 22 with the target setting value CLK1_CNT based on the triggering of the counter reload controller 10, and outputs a state indication signal DCC_IF according to the comparison result, and the state indication signal DCC_IF is used to indicate the state of the monitored clock. The target setting value CLK1_CNT is a multi-bit signal and can be set externally.

[0075] It should be noted that the initial count value CLK0_CNT and the target setting value CLK1_CNT of the first counter 21 can be configured externally, specifically according to the frequency of the first clock signal CLK0 and the second clock signal CLK1, based on the principle of consistent timing duration. For example, if the clock frequency of CLK0 is 25MHz and the clock frequency of CLK1 is 2MHz, then CLK0_CNT can be configured to 1250 and CLK1_CNT can be configured to 100. At this time, the counting time of CLK0 is the number of counting cycles × the clock cycle of CLK0, that is, 1250 × 40ns = 50us; the counting time of CLK1 is the number of counting cycles × the clock cycle of CLK1, that is, 100 × 500ns = 50us. Therefore, the counting values ​​of the two clocks at the same time can be used to determine whether the period of the clock signal to be measured meets the requirements, that is, whether the clock frequency meets the requirements.

[0076] The counter reload controller 10 is also used to determine whether to restart the next round of monitoring according to the state indication signal DCC_IF. When the monitored clock signal is normal, the clock frequency monitoring circuit is controlled to reload and start the next round of monitoring; when the monitored clock signal is abnormal, the monitoring work will be suspended, and the next round of monitoring work will be automatically started after the abnormality is eliminated.

[0077] For example, in some embodiments, when the absolute value of the difference between the count value cnt1 and the target set value CLK1_CNT is less than or equal to the set threshold ACC_VLU, the output state indication signal DCC_IF of the count value comparison module 30 is low level, indicating that the monitored clock signal is normal; otherwise, the output state indication signal DCC_IF is high level, indicating that the monitored clock signal is abnormal. The set threshold ACC_VLU can be set externally, and the size of the set threshold ACC_VLU can be adjusted according to the different requirements of the actual application accuracy of the monitored clock to better meet the requirements of clock accuracy in actual applications.

[0078] Correspondingly, when the status indication signal DCC_IF is at a low level, the counter reload controller 10 controls the clock frequency monitoring circuit to restart the monitoring work; when the status indication signal DCC_IF is at a high level, it indicates that the monitored clock signal is abnormal and needs to be processed first. After processing, DCC_IF is cleared through the flag clearing control signal DCC_IC, and the counter reload controller 10 controls the clock frequency monitoring circuit to restart the monitoring work.

[0079] The clearing of DCC_IF is completed by triggering the count value comparison module 30 with the flag clearing signal DCC_IC. The flag clearing signal DCC_IC can be configured according to the specific implementation of the count value comparison module 30, such as high level effective or low level effective, which is not limited in the embodiment of the present application.

[0080] for example, Figure 2 In another structural schematic diagram of the clock frequency monitoring circuit provided in the embodiment of the present application, the clock frequency monitoring circuit may further include: a status register 40.

[0081] In this embodiment, the count value comparison module 30 saves the state indication signal DCC_IF into the state register 40. The state register 40 is a read-only register, indicating the state of DCC_IF in real time. The value of DCC_IF can be obtained by accessing the address of the state register 40. The external device can obtain the state of the monitored clock signal by polling the state register 40. For example, when the flag bit in the state register 40 is read as 0, it indicates that the corresponding clock signal is normal; when the flag bit is 1, it indicates that the corresponding clock signal is abnormal.

[0082] In addition, the count value cnt1 of the second counter 22 can also be saved in a corresponding numerical register (not shown) at the same time. Similar to the status register 40, the numerical register is a read-only register that indicates the value of cnt1 in real time. By accessing the address of the numerical register, an external device can obtain the current value of cnt1. For ease of description, the count value saved in the numerical register is recorded as DCC_CNT1.

[0083] For example, Figure 3 In another structural diagram of the clock frequency monitoring circuit provided by the embodiment of the present application, the clock frequency monitoring circuit may also include: an interrupt controller 50, which is used to output an interrupt signal DCC_INT to quickly report abnormal information when the state indication signal DCC_IF indicates that the monitored clock is abnormal. The advantage of using interrupts to report abnormalities is that hardware feedback abnormalities is much faster than software polling to the abnormal flag bit, and interrupt events will be processed with priority, which can significantly improve the efficiency of handling abnormalities.

[0084] In some embodiments, in order to meet different application requirements, the clock frequency monitoring circuit can also be set Figure 2 Status register 40 and Figure 3 The interrupt controller 50 is configured in the embodiment of the present invention, and the interrupt controller 50 is controlled by the interrupt enable signal DCC_IE.

[0085] The interrupt enable signal DCC_IE can be configured by an external device, for example, using a 1-bit signal. When DCC_IE is configured to 1, the interrupt controller 50 is in an enabled state, and the interrupt controller 50 reports the clock abnormality information; when DCC_IE is configured to 0, the interrupt controller 50 is in a disabled state, and the abnormality information is stored in the status register 40. The external device obtains the clock abnormality information by reading the status register 40.

[0086] In some embodiments, the counter reload controller 10 can be implemented by a state machine.

[0087] Combine the following Figure 4 and Figure 5 The working process of the clock frequency monitoring circuit is further described in detail. Figure 4 is a state transition diagram of a state machine in a counter reload controller in an embodiment of the present application, Figure 5 It is a schematic diagram of the working timing of the clock frequency monitoring circuit in the embodiment of the present application.

[0088] like Figure 4 As shown, the state machine includes the following states: an idle state IDLE, a loading state LOAD_VLU, a waiting state WAIT_CLK0_END for the first counting, a waiting state WAIT_CLK1_END for the second counting, a checking state CHECK, and a reloading state RELOAD_VLU.

[0089] The state machine operates in a first clock domain.

[0090] When the circuit system is reset, that is, when the system reset signal RST_N is 0, the state machine is in the idle state IDLE.

[0091] When the circuit system is disabled, that is, when the system enable signal EN is 0, no matter what state the circuit is currently running in, it will return to the idle state IDLE.

[0092] After the system enable signal is valid, the state of the state machine first jumps from IDLE->LOAD_VLU->WAIT_CLK0_END->WAIT_CLK1_END->CHECK->RELOAD_VLU, and then loops from WAIT_CLK0_END to RELOAD_VLU. The specific process is as follows:

[0093] In the first clock domain of the circuit, a rising edge collector is used to sample the rising edge of the system enable signal EN. When the system enable signal EN changes from 0 to 1, a valid pulse signal en_puls is generated at the rising edge of the system enable signal EN. When en_puls is valid, the state machine switches from the idle state IDLE to the loading state LOAD_VLU.

[0094] The loading state LOAD_VLU stays for one CLK0 clock cycle and then switches to the waiting state for the first count to end WAIT_CLK0_END.

[0095] After the state machine enters the waiting state WAIT_CLK0_END for the first counting, the first counter enable signal CLK0_ST is generated, and the first counter is set to the set value CLK0_CNT (i.e., the counting time, corresponding to Figure 5 The first counter starts counting down based on the value n in the first counter until it is counted down to 0 and then reloads the set value CLK0_CNT. During the counting process, the first counter enable signal CLK0_ST is set to a high level state. When the count value of the first counter is counted down to 0, a pulse signal clk0_cnt_end is generated to indicate the end of the first count.

[0096] During the waiting period for the first counting end state WAIT_CLK0_END, the second clock signal CLK1 synchronizes the first counter enable signal CLK0_ST to the second clock domain by beating 2 times, thereby generating a second counter enable signal CLK1_ST. Figure 5 When CLK1_ST is equal to 1, the second counter starts counting from 0 until the second counter enable signal CLK1_ST is equal to 0, then the counting stops and the current count value is maintained (i.e. Figure 5 The final count value m in .

[0097] Reference Figure 5 , beat the second counter enable signal CLK1_ST 1-3 times in the second clock domain ( Figure 5 ), generating the second clock delay signal clk1_state_dly, which can ensure that when CLK0 samples the falling edge of the second counter enable signal CLK1_ST, CLK1 counting is completed and has been stable for at least one clock cycle.

[0098] Correspondingly, in the first clock domain, a falling edge collector is used to perform falling edge detection on the second clock delay signal clk1_state_dly, and when a falling edge occurs on the delay signal clk1_state_dly, a pulse signal clk1_cnt_neg is generated.

[0099] Continue to refer to Figure 4When the state machine reads the pulse signal clk0_cnt_end, the state machine jumps from the waiting state WAIT_CLK0_END for the first count to the waiting state WAIT_CLK1_END for the second count. In this state, the pulse signal clk1_cnt_neg is valid, indicating that the second counter has completed counting, and generates a pulse signal clk1_cnt_end for indicating the end of the second count.

[0100] Through the above-mentioned delayed signal clk1_state_dly and pulse signal clk1_cnt_neg, the stability of the count value of the second counter can be better guaranteed.

[0101] When the state machine reads the pulse signal clk1_cnt_end, the state machine jumps from the state WAIT_CLK1_END of waiting for the end of the second counter to the state CHECK.

[0102] Also refer to Figure 5 After entering the CHECK state, the 2-bit detection counter check_cnt starts counting from 0 to 3. After counting to 2, Figure 1 The count value comparison module 30 compares the count value output by the second counter 22 with the target setting value CLK1_CNT. When the condition is not met, the state indication signal DCC_IF starts to be set high; after counting to 3, a pulse signal check_end is generated to indicate the end of the detection.

[0103] It should be noted that the pulse signal check_end is generated only when the detection counter check_cnt is equal to 3 and DCC_IF is not 1. When DCC_IF is 1, the pulse signal check_end will not be generated until DCC_IF is cleared.

[0104] When the state machine reads the pulse signal check_end, the state machine jumps from the detection state CHECK to the reload state RELOAD_VLU.

[0105] After entering the reload state RELOAD_VLU, Figure 1 The first counter 21 in the reload_register is reassigned to n, and the second counter 22 is reassigned to 0. After the assignment is completed, a pulse signal reload_end is generated to indicate the end of reloading.

[0106] It should be noted that when the pulse signal check_end occurs, the corresponding level signal check_end_lvl (not shown in the figure) is set to 1, and when the pulse signal reload_end is valid, the level signal check_end_lvl is set to 0. The level signal check_end_lvl is used for signal synchronization in different clock domains. Specifically, the level signal check_end_lvl is synchronized with 3 beats in the second clock domain to generate a second clock reload synchronization signal clk1_reload_syn (not shown in the figure) to ensure sufficient reload time; then the second clock reload synchronization signal clk1_reload_syn is synchronized with 3 beats in the first clock domain, and an AND gate is used to generate a falling edge acquisition pulse signal reload_end.

[0107] When the state machine reads the pulse signal reload_end, the state machine jumps from the reload state RELOAD_VLU to the wait for the first count end state WAIT_CLK0_END, starting a new round of clock monitoring process.

[0108] Also refer to Figure 1 , in the above monitoring process, the use of state machine signals is as follows:

[0109] When the state machine is in the loading state LOAD_VLU and the reloading state RELOAD_VLU, CLK0_CNT (corresponding to Figure 5 The value n) in is assigned to the first counter 21 as its initial value.

[0110] When the state machine is in the waiting state WAIT_CLK0_END for the first counting, the first counter 21 is in a down counting state.

[0111] When the state machine is in the detection state CHECK, when the 2-bit detection counter check_cnt counts to 2, the count value comparison module 30 determines whether the count value cnt1 output by the second counter meets the requirements. The specific determination method is as follows:

[0112] When cnt1 is greater than or equal to (CLK1_CNT-ACC_VLU) and cnt1 is less than or equal to (CLK1_CNT+ACC_VLU), DCC_IF outputs 0; otherwise, DCC_IF outputs 1.

[0113] like Figure 6 , which is a structural diagram of a counting value comparison module in an embodiment of the present application.

[0114] The count value comparison module includes: an adder 101, a subtractor 102, a first judgment unit 111, a second judgment unit 112, an OR gate 121, and a D flip-flop 131. Among them:

[0115] The adder 101 is used to calculate the sum of the target setting value CLK1_CNT and the setting threshold ACC_VLU, and output a sum value SUM;

[0116] The subtractor 102 is used to calculate the difference between the target setting value CLK1_CNT and the setting threshold ACC_VLU, and output the difference SUB;

[0117] The first judgment unit 111 is used to compare the sum value SUM with the count value cnt1 and output a first comparison result;

[0118] The second judgment unit 112 is used to compare the difference SUB with the count value cnt1 and output a second comparison result;

[0119] The OR gate 121 is used to perform an OR logic operation on the first comparison result and the second comparison result, and output the operation result; specifically, when cnt1 is greater than the SUM output value or cnt1 is less than the SUB output value, it indicates that the count value exceeds the tolerance and outputs a high level; otherwise, outputs a low level.

[0120] The D flip-flop 131 is used to output the operation result as the state indication signal DCC_IF.

[0121] Specifically, when cnt1 is greater than the SUM output value or cnt1 is less than the SUB output value, it indicates that the count exceeds the tolerance. When the 2-bit detection counter check_cnt counts to 2, that is, check_cnt is equal to 2, the D flip-flop 131 outputs the comparison result, that is, the state indication signal DCC_IF.

[0122] Figure 6 In FIG. 1 , RST_N is a reset signal of the D flip-flop 131 , and DCC_IC is an output clear signal of the D flip-flop 131 .

[0123] like Figure 6 As shown, in some embodiments, the clock signal of the D flip-flop 131 can be generated by the AND gate 141 according to the count value output by the 2-bit detection counter check_cnt. Of course, it can also be generated in other ways, such as by Figure 1 The counter in the controller 10 is overloaded, which is not limited in this embodiment of the present application.

[0124] It should be noted that, since digital circuits have certain bit width limitations, when implementing the above-mentioned addition and subtraction using digital circuits, in order to avoid overflow caused by the calculated sum SUM and difference SUB exceeding the maximum number of bits, the above-mentioned adder 101 can also set the sum SUM to the maximum value corresponding to the current number of bits when the sum exceeds the maximum number of bits of the current number of bits; similarly, the subtractor 102 can also determine whether the target setting value CLK1_CNT is less than the set threshold ACC_VLU, and if so, set the difference SUB to 0.

[0125] The advantage of using adders and subtractors to generate upper and lower limits is that the data bit width for directly configuring the upper and lower limits through the input interface is reduced, and the amount of calculation involved in the system is also reduced.

[0126] The clock frequency monitoring circuit provided in the embodiment of the present application can be implemented by a digital circuit, avoiding the problem of too large area overhead of the analog circuit, and can monitor any clock frequency to be measured without modifying the circuit, and can be widely used in SOC systems.

[0127] In addition, the clock frequency monitoring circuit has the following advantages:

[0128] (1) The reference clock circuit does not need to be specially designed. The reference clock frequency does not depend on the clock frequency to be measured. In addition, a reliable on-chip clock or external GPIO input clock can be used, which can effectively reduce other circuit design overhead.

[0129] (2) The measurement duration is configurable and the measurement accuracy is adjustable.

[0130] (3) The allowable jitter tolerance of the clock frequency can be configured to meet different clock accuracy requirements, and the yield can be controlled.

[0131] (4) Multiple test clocks and reference clocks are available to better meet the needs of different applications.

[0132] Accordingly, the embodiment of the present application also provides a clock frequency monitoring method, such as Figure 7 As shown, it is a flow chart of the method, comprising the following steps:

[0133] Step 701, obtaining setting parameters.

[0134] The parameters include: a first selection signal CLK0_SELECT, a second selection signal CLK1_SELECT, an initial count value CLK0_CNT of a first counter, a target setting value CLK1_CNT, a set threshold ACC_VLU, and an interrupt enable signal DCC_IE; the first selection signal CLK0_SELECT is used to select a first clock signal as a reference clock signal; the second selection signal CLK1_SELECT is used to select a second clock signal as a monitored clock signal.

[0135] It should be noted that the initial count value CLK0_CNT of the first counter and the target setting value CLK1_CNT can be configured according to the frequencies of the first clock signal CLK0 and the second clock signal CLK1 based on the principle of consistency of timing duration.

[0136] Step 702 , control the first counter to count down from the initial count value CLK0_CNT based on the first clock signal in the first clock domain through a first counter enable signal until the initial count value CLK0_CNT is reloaded to the first counter after the count is counted down to 0.

[0137] Step 703: The second clock signal uses a trigger beat method to synchronize the first counter enable signal to the second clock domain to generate a second counter enable signal.

[0138] Step 704: Control the second counter to count upward from 0 based on the second clock signal through the second counter enable signal until the second counter enable signal is invalid and the counting ends, and the current count value is maintained.

[0139] Step 705 : Compare the current count value output by the second counter with the target setting value CLK1_CNT in the first clock domain to obtain a comparison result.

[0140] Step 706: output a state indication signal according to the comparison result to indicate the state of the monitored clock.

[0141] Specifically, if the comparison result meets the set threshold ACC_VLU requirement, that is, the absolute value of the difference between the current count value output by the second counter and the target set value CLK1_CNT is less than or equal to the set threshold ACC_VLU, it means that the monitored clock signal is normal, and a status indication signal indicating a normal state is output; otherwise, a status indication signal indicating an abnormal state is output.

[0142] Step 707: If the state indication signal indicates that the state is normal, the next round of monitoring is restarted. Otherwise, it indicates that the monitored clock signal is abnormal, so that the system can handle the abnormality in time. After the abnormality is handled and the abnormal state indication signal is cleared, the clock frequency monitoring is continued according to the process of the above steps 701 to 707.

[0143] In some embodiments, the clock abnormality information can also be reported by outputting an interrupt signal. Specifically, if the state indication signal indicates that the state is abnormal, an interrupt signal is output. Accordingly, when the external device receives the interrupt signal, it can determine that the monitored clock signal is abnormal.

[0144] In some embodiments, the status indication signal DCC_IF may also be stored in the status register, so that an external device can determine whether the monitored clock signal is abnormal by reading the status register.

[0145] In some embodiments, the current count value output by the second counter can also be saved in a count value register; if the status indication signal indicates an abnormal status, monitoring is stopped, and the count value saved in the count value register is read, and the clock abnormality is located based on the read count value.

[0146] The clock frequency monitoring method provided in the embodiment of the present application can realize the clock frequency monitoring function with controllable measurement duration, adjustable jitter tolerance, and no limit on the reference clock and the monitored clock frequency by externally configuring relevant parameters. The scheme of the present application can realize the monitoring of any clock frequency to be measured.

[0147] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A clock frequency monitoring circuit, characterized in that: The circuit comprises: A first multiplexer, used for selecting a plurality of input first clock signal sources and outputting a first clock signal CLK0; the first clock signal CLK0 is used as a reference clock signal; A second multiplexer, used for selecting a plurality of second clock signal sources inputted, and outputting a second clock signal CLK1; the second clock signal CLK1 is used as a monitored clock signal; A first counter, configured to be triggered based on a first enable signal CLK0_ST, and to count down the first clock signal CLK0 starting from a loaded count initial value CLK0_CNT until it counts down to 0; a second counter, configured to count up the second clock signal CLK1 based on the trigger of the second enable signal CLK1_ST, and output a count value cnt1 until the second enable signal CLK1_ST becomes invalid and the counting ends; A count value comparison module, used for comparing the count value cnt1 with the target setting value CLK1_CNT, and outputting a state indication signal DCC_IF according to the comparison result to indicate the state of the monitored clock; a counter reload controller, configured to generate the first enable signal CLK0_ST and the second enable signal CLK1_ST according to the first clock signal CLK0 and the second clock signal CLK1, and trigger the count value comparison module to start working after the second counter finishes counting; and to determine whether to restart the next round of monitoring according to the state indication signal DCC_IF; The count initial value CLK0_CNT of the first counter and the target setting value CLK1_CNT are configured according to the frequencies of the first clock signal CLK0 and the second clock signal CLK1 based on the principle of consistent timing duration.

2. The clock frequency monitoring circuit according to claim 1, characterized in that: The counter reload controller synchronizes the first enable signal CLK0_ST to the second clock domain through a trigger beat mode to generate the second enable signal CLK1_ST.

3. The clock frequency monitoring circuit according to claim 1, characterized in that: The first enable signal CLK0_ST remains valid during the down-counting process of the first counter; and the second enable signal CLK1_ST remains valid during the up-counting process of the second counter.

4. The clock frequency monitoring circuit according to claim 1, characterized in that: When the absolute value of the difference between the count value cnt1 and the target set value CLK1_CNT is less than or equal to the set threshold ACC_VLU, the state indication signal output by the count value comparison module is a low level; otherwise, the state indication signal output is a high level.

5. The clock frequency monitoring circuit according to claim 4, characterized in that: The count value comparison module comprises: An adder, used for calculating the sum of the target setting value CLK1_CNT and the setting threshold ACC_VLU, and outputting the sum; A subtractor, used for calculating the difference between the target setting value CLK1_CNT and the setting threshold ACC_VLU, and outputting the difference; A first judgment unit, used for comparing the sum value with the count value cnt1, and outputting a first comparison result; A second judgment unit, used for comparing the difference value with the count value cnt1, and outputting a second comparison result; An OR gate, used for performing an OR logic operation on the first comparison result and the second comparison result, and outputting an operation result; The D flip-flop is used to output the operation result as the state indication signal DCC_IF.

6. The clock frequency monitoring circuit according to claim 5, characterized in that: The adder is further used to set the sum value to the current maximum value of the number of digits when the sum value is greater than the current maximum value of the number of digits; The subtractor is further configured to set the difference value to 0 when the target setting value CLK1_CNT is less than the setting threshold ACC_VLU.

7. The clock frequency monitoring circuit according to claim 1, characterized in that: The counter reload controller is implemented by a state machine, and the state machine operates in a first clock domain.

8. The clock frequency monitoring circuit according to claim 7, characterized in that: The state machine includes the following states: idle state, loading state, waiting state for the first count to end, waiting state for the second count to end, detection state, and reloading state; When the circuit system is reset, the state machine is in an idle state; After the system enable signal is valid, the state of the state machine first jumps from idle state -> loading state -> waiting for the first count end state -> waiting for the second count end state -> detection state -> reloading state, and then cyclically jumps from waiting for the first count end state -> waiting for the second count end state -> detection state -> reloading state.

9. The clock frequency monitoring circuit according to claim 1, characterized in that: The first clock signal source is provided by an on-chip clock or an external GPIO input clock.

10. The clock frequency monitoring circuit according to any one of claims 1 to 9, characterized in that: The circuit further comprises: The interrupt controller is used to output an interrupt signal DCC_INT when the state indication signal DCC_IF indicates that the monitored clock is abnormal.

11. The clock frequency monitoring circuit according to any one of claims 1 to 9, characterized in that: The circuit further comprises: The status register is used to store the status indication signal DCC_IF.

12. A clock frequency monitoring method, characterized in that: The method comprises: Acquire setting parameters, the parameters including: a first selection signal CLK0_SELECT, a second selection signal CLK1_SELECT, an initial count value CLK0_CNT of a first counter, a target set value CLK1_CNT, a set threshold ACC_VLU, and an interrupt enable signal DCC_IE; the first selection signal CLK0_SELECT is used to select a first clock signal as a reference clock signal; the second selection signal CLK1_SELECT is used to select a second clock signal as a monitored clock signal; the initial count value CLK0_CNT and the target set value CLK1_CNT of the first counter are configured according to the frequencies of the first clock signal CLK0 and the second clock signal CLK1 based on the principle of consistent timing duration; Control the first counter to count down from the initial count value CLK0_CNT based on the first clock signal in the first clock domain through a first counter enable signal until the initial count value CLK0_CNT is reloaded to the first counter after the count is counted down to 0; The second clock signal uses a trigger beat method to synchronize the first counter enable signal to the second clock domain to generate a second counter enable signal; Control the second counter to count up from 0 based on the second clock signal through the second counter enable signal until the counting ends when the second counter enable signal is invalid, and maintain the current count value; Compare the current count value output by the second counter with the target setting value CLK1_CNT in the first clock domain to obtain a comparison result; Outputting a state indication signal according to the comparison result to indicate the state of the monitored clock; If the status indication signal indicates that the status is normal, the next round of monitoring is restarted.

13. The clock frequency monitoring method according to claim 12, characterized in that: Outputting a status indication signal according to the comparison result comprises: If the comparison result meets the requirement of the set threshold value ACC_VLU, a state indication signal indicating a normal state is output; otherwise, a state indication signal indicating an abnormal state is output.

14. The clock frequency monitoring method according to claim 13, characterized in that: The method further comprises: If the state indication signal indicates that the state is abnormal, an interrupt signal is output.

15. The clock frequency monitoring method according to claim 13, characterized in that: The method further comprises: The status indication signal is stored in a status register.

16. The clock frequency monitoring method according to any one of claims 12 to 15, characterized in that: The method further comprises: Saving the current count value output by the second counter into a count value register; If the status indication signal indicates that the status is abnormal, the monitoring is stopped, the count value stored in the count value register is read, and the clock abnormality is located according to the read count value; After the status indication signal indicating the abnormal status is cleared, monitoring continues.

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