Low-offset-voltage high-speed comparator

Abstract

The invention discloses a low-offset-voltage high-speed comparator. The low-offset-voltage high-speed comparator comprises a biasing circuit, a pre-amplifier, a post-comparator, a capacitive coupler and a driver, the biasing circuit is respectively connected with the pre-amplifier, the post-comparator and the capacitive coupler, the pre-amplifier is respectively connected with the post-comparator and the capacitive coupler, the capacitive coupler is connected with the post-comparator, and the post-comparator is connected with the capacitive coupler. The output end of the rear comparator is connected with the input end of the driver; by arranging the capacitive coupler, a rapid path is provided for an input signal, so that the change of the input signal can rapidly reach the rear comparator, and a comparison result is output, thereby realizing low offset voltage and high speed of the comparator.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low offset voltage high-speed comparator, which is applied to circuits requiring low offset voltage and high comparison speed. Background Art

[0002] Voltage comparators are commonly used circuit modules in integrated circuit design. They identify and compare input signals and convert analog voltage signals into high and low level signals. Offset voltage and speed are two important indicators of comparators. Offset voltage will cause the actual threshold of comparison to deviate from the theoretical design threshold, making it inaccurate when setting a specific comparison threshold, and producing erroneous output results when the input voltage difference is very small. Large-size design can reduce the offset voltage of the comparator. The speed of the comparator determines the response time of the comparator to changes in the input signal. Traditional comparators use large-size design to reduce the offset voltage of the comparator, but will generate large parasitic capacitance, reduce the speed of the comparator, and are not suitable for high-speed applications; or use self-calibration technology to reduce the offset voltage of the comparator, but in high-speed applications, a very high-frequency clock signal is required, which increases the complexity and power consumption of the circuit. Summary of the invention

[0003] The present invention aims to overcome the problems of low offset voltage comparator in the above-mentioned prior art, such as slow speed, complex circuit and high power consumption, and provide a low offset voltage high-speed comparator solution, which can not only achieve low offset voltage but also improve speed, reduce circuit complexity and power consumption.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] The embodiment of the present invention provides a low offset voltage high-speed comparator, comprising a bias circuit, a preamplifier, a post-comparator, a capacitive coupler and a driver;

[0006] The bias circuit is connected to the preamplifier, the post comparator and the capacitive coupler respectively, the preamplifier is connected to the post comparator and the capacitive coupler respectively, the capacitive coupler is connected to the post comparator, and the output end of the post comparator is connected to the input end of the driver;

[0007] The preamplifier is used to amplify the input signal to obtain an amplified signal;

[0008] The post comparator is used to compare the amplified signals;

[0009] The capacitive coupler is used to provide a second path for the input signal and couple the change of the input signal to the post comparator;

[0010] The driver is used to enhance the driving capability of the output signal of the post comparator.

[0011] Optionally, the preamplifier includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube, the gate of the first NMOS tube is connected to the first input end of the low offset voltage high-speed comparator, the source of the first NMOS tube is respectively connected to the source of the second NMOS tube and the drain of the third NMOS tube, the drain of the first NMOS tube is respectively connected to the first end of the first resistor and the gate of the fourth NMOS tube, the drain of the second NMOS tube is respectively connected to the first end of the second resistor and the gate of the fifth NMOS tube, the gate of the second NMOS tube is connected to the second input end of the low offset voltage high-speed comparator, the source of the fourth NMOS tube is respectively connected to the source of the fifth NMOS tube and the drain of the sixth NMOS tube, the drain of the fourth NMOS tube is respectively connected to the first end of the third resistor, The gate of the seventh NMOS tube is connected to the gate of the seventh NMOS tube, the drain of the fifth NMOS tube is respectively connected to the first end of the fourth resistor and the gate of the eighth NMOS tube, the source of the seventh NMOS tube is connected to the drain of the ninth NMOS tube, the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, the gate of the third NMOS tube is respectively connected to the gate of the sixth NMOS tube, the gate of the ninth NMOS tube, and the gate of the tenth NMOS tube, the source of the third NMOS tube, the gate of the sixth NMOS tube, and the gate of the ninth NMOS tube. The source of the S tube, the source of the ninth NMOS tube, and the source of the tenth NMOS tube are connected to the ground, the second end of the first resistor, the second end of the second resistor, the second end of the third resistor, the second end of the fourth resistor, the drain of the seventh NMOS tube, and the drain of the eighth NMOS tube are all connected to the power supply, the source of the seventh NMOS tube is connected to the first end of the post-comparator, the source of the eighth NMOS tube is connected to the second end of the post-comparator, and the gate of the third NMOS tube is connected to the bias circuit.

[0012] Optionally, the post-comparator includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a seventh resistor, and a third capacitor. The gate of the thirteenth NMOS tube is connected to the preamplifier, the source of the thirteenth NMOS tube is respectively connected to the source of the fourteenth NMOS tube and the drain of the fifteenth NMOS tube, the drain of the thirteenth NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the first PMOS tube, and the gate of the second PMOS tube, the gate of the fourteenth NMOS tube is connected to the preamplifier, the drain of the fourteenth NMOS tube is respectively connected to the drain of the second PMOS tube and the gate of the third PMOS tube, and the third The drain of the PMOS tube is connected to the drain of the lower sixteen NMOS tubes, the source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube are all connected to the power supply, the gate of the fifteenth NMOS is respectively connected to the first end of the seventh resistor and the first end of the third capacitor, the gate of the sixteenth NMOS tube is connected to the second end of the seventh resistor, the source of the fifteenth NMOS, the source of the sixteenth NMOS tube, and the second end of the third capacitor are all connected to the ground, the drain of the first PMOS tube is connected to the first end of the capacitive coupler, the drain of the second PMOS tube is connected to the second end of the capacitive coupler, the drain of the third PMOS tube is connected to the input end of the driver, and the gate of the fifteenth NMOS is connected to the bias circuit.

[0013] Optionally, the capacitive coupler includes an eleventh NMOS tube, a twelfth NMOS tube, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor, the source of the eleventh NMOS tube is respectively connected to the first end of the fifth resistor and the first end of the first capacitor, the drain of the eleventh NMOS tube is connected to the post-comparator, the source of the twelfth NMOS tube is connected to the first end of the sixth resistor, the gate of the eleventh NMOS tube is respectively connected to the gate of the twelfth NMOS tube and the bias circuit, the drain of the twelfth NMOS tube is connected to the post-comparator, the second end of the first capacitor is respectively connected to the second end of the second capacitor and the second input end of the low offset voltage high-speed comparator, and the second end of the fifth resistor and the second end of the sixth resistor are both connected to ground.

[0014] Optionally, the driver includes a Schmitt trigger and an inverter, the input end of the Schmitt trigger is connected to the output end of the post-comparator, the output end of the Schmitt trigger is connected to the input end of the inverter, and the output end of the inverter serves as the output end of the low offset voltage high-speed comparator.

[0015] Optionally, the bias circuit includes a first current source, a second current source, a seventeenth NMOS tube, an eighteenth NMOS tube and a fourth capacitor, the drain of the seventeenth NMOS tube is respectively connected to the gate of the seventeenth NMOS tube, the capacitive coupler, and the first end of the fourth capacitor, and the drain of the eighteenth NMOS tube is respectively connected to the gate of the eighteenth NMOS tube, the preamplifier and the post-comparator.

[0016] The beneficial effects of the present invention are:

[0017] A low offset voltage high speed comparator circuit of the present invention provides a fast path for an input signal by setting a capacitive coupler, so that the change of the input signal can quickly reach a post-comparator and output a comparison result, thereby achieving low offset voltage and high speed of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the schematic diagram of the traditional low offset voltage comparator circuit;

[0019] Figure 2 This is a principle block diagram of a low offset voltage high speed comparator of the present invention;

[0020] Figure 3 A circuit schematic diagram of an embodiment of a low offset voltage high speed comparator of the present invention;

[0021] Figure 4 This is the delay simulation waveform of the traditional low offset voltage comparator;

[0022] Figure 5 This is a delay simulation waveform diagram of the low offset voltage high-speed comparator of the present invention. DETAILED DESCRIPTION

[0023] The present invention and its beneficial effects will be further described in detail below in conjunction with specific implementations and the accompanying drawings, but the specific implementations of the present invention are not limited thereto.

[0024] refer to Figure 2 The principle block diagram of the low offset voltage high speed comparator of the present invention, the embodiment of the present invention provides a low offset voltage high speed comparator, including a bias circuit 100, a preamplifier 200, a post comparator 300, a capacitive coupler 400, and a driver 500;

[0025] The bias circuit 100 is connected to the preamplifier 200, the post comparator 300, and the capacitive coupler 400 respectively. The preamplifier 200 is connected to the post comparator 300 and the capacitive coupler 400 respectively. The capacitive coupler 400 is connected to the post comparator 300. The output end of the post comparator 300 is connected to the input end of the driver 500.

[0026] The preamplifier 200 is used to amplify the input signal to obtain an amplified signal and reduce the input offset voltage;

[0027] A post comparator 300, for comparing the amplified signals;

[0028] The capacitive coupler 400 is used to provide a second path for the input signal, and couple the change of the input signal to the post-comparator 300 to speed up the comparison;

[0029] The driver 500 is used to enhance the driving capability of the output signal of the post comparator 300 .

[0030] refer to Figure 3In this embodiment, the circuit schematic diagram of the low offset voltage high-speed comparator embodiment of the present invention, the preamplifier 200 includes a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, and a tenth NMOS tube NM10, the gate of the first NMOS tube NM1 is connected to the The first input terminal PIN of the low offset voltage high speed comparator is connected, the source of the first NMOS tube NM1 is connected to the source of the second NMOS tube NM2 and the drain of the third NMOS tube NM3, the drain of the first NMOS tube NM1 is connected to the first end of the first resistor R1 and the gate of the fourth NMOS tube NM4, the drain of the second NMOS tube NM2 is connected to the first end of the second resistor R2 and the gate of the fifth NMOS tube NM5, the gate of the second NMOS tube NM2 is connected to the second input terminal VIN of the low offset voltage high speed comparator, and the fourth NMOS tube NM4 is connected to the gate of the fifth NMOS tube NM5. The source of the S tube NM4 is connected to the source of the fifth NMOS tube NM5 and the drain of the sixth NMOS tube NM6, the drain of the fourth NMOS tube NM4 is connected to the first end of the third resistor R3 and the gate of the seventh NMOS tube NM7, the drain of the fifth NMOS tube NM5 is connected to the first end of the fourth resistor R4 and the gate of the eighth NMOS tube NM8, the source of the seventh NMOS tube NM7 is connected to the drain of the ninth NMOS tube NM9, the source of the eighth NMOS tube NM8 is connected to the drain of the ninth NMOS tube NM9, the third NMOS tube NM The gate of the first NMOS tube NM3 is connected to the gate of the sixth NMOS tube NM6, the gate of the ninth NMOS tube NM9, and the gate of the tenth NMOS tube NM10, the source of the third NMOS tube NM3, the source of the sixth NMOS tube NM6, the source of the ninth NMOS tube NM9, and the source of the tenth NMOS tube NM10 are connected to the ground, and the second end of the first resistor R1, the second end of the second resistor R2, the second end of the third resistor R3, the second end of the fourth resistor R4, the drain of the seventh NMOS tube NM7, and the drain of the eighth NMOS tube NM8 are connected to the power supply.

[0031] In one embodiment, the post comparator 300 includes a thirteenth NMOS tube NM13, a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a seventh resistor R7, and a third capacitor C3. The gate of the thirteenth NMOS tube NM13 is connected to the source of the seventh NMOS tube NM7 and the drain of the ninth NMOS tube NM9. The source of the thirteenth NMOS tube NM13 is connected to the source of the fourteenth NMOS tube NM14 and the drain of the fifteenth NMOS tube NM15. The drain of the thirteenth NMOS tube NM13 is connected to the drain of the first PMOS tube PM1, the gate of the first PMOS tube PM1, and the gate of the second PMOS tube PM2. The fourteenth NMOS tube NM14 is connected to the drain of the first PMOS tube PM1, the gate of the first PMOS tube PM1, and the gate of the second PMOS tube PM2. The gate of the S tube NM14 is connected to the source of the eighth NMOS tube NM8 and the drain of the tenth NMOS tube NM10, the drain of the fourteenth NMOS tube NM14 is connected to the drain of the second PMOS tube PM2 and the gate of the third PMOS tube PM3, the drain of the third PMOS tube PM3 is connected to the drain of the lower sixteen NMOS tubes, the source of the first PMOS tube PM1, the source of the second PMOS tube PM2, and the source of the third PMOS tube PM3 are connected to the power supply, the gate of the fifteenth NMOS tube NM15 is connected to the first end of the seventh resistor R7 and the first end of the third capacitor C3, the gate of the sixteenth NMOS tube NM16 is connected to the second end of the seventh resistor R7, and the source of the fifteenth NMOS, the source of the sixteenth NMOS tube NM16, and the second end of the third capacitor C3 are connected to the ground.

[0032] In one embodiment, the capacitive coupler 400 includes an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, and a second capacitor C2. The gate of the eleventh NMOS transistor NM11 is connected to the first end of the first capacitor C1, the source of the eleventh NMOS transistor NM11 is connected to the first end of the fifth resistor R5, the drain of the eleventh NMOS transistor NM11 is connected to the drain of the thirteenth NMOS transistor NM13, the drain of the first PMOS transistor PM1, the gate of the first PMOS transistor PM1, and the gate of the second PMOS transistor PM2. The gate of the twelfth NMOS tube PM12 is connected to the first end of the second capacitor C2, the source of the twelfth NMOS tube PM12 is connected to the second end of the sixth resistor R6, the drain of the twelfth NMOS tube PM12 is connected to the drain of the fourteenth NMOS tube NM14, the drain of the second PMOS tube PM2, and the gate of the third PMOS tube PM3, the second end of the first capacitor C1 is connected to the second end of the second capacitor C2, the gate of the first NMOS tube NM1, and the first input terminal PIN of the low offset voltage high speed comparator, and the second end of the fifth resistor R5 and the second end of the sixth resistor R6 are connected to the ground.

[0033] In one embodiment, the driver 500 includes a Schmitt trigger and an inverter, the input end of the Schmitt trigger is connected to the drain of the third PMOS tube PM3 and the drain of the sixteenth NMOS tube NM16, the output end of the Schmitt trigger is connected to the input end of the inverter, and the output end of the inverter serves as the output end of the low offset voltage of the present invention.

[0034] In one embodiment, the bias circuit 100 includes a seventeenth NMOS transistor NM17, an eighteenth NMOS transistor NM18, and a fourth capacitor C4. The drain of the seventeenth NMOS transistor NM17 is connected to the gate of the seventeenth NMOS transistor NM17, the gate of the eleventh NMOS transistor NM11, the gate of the twelfth NMOS transistor NM12, and the first end of the fourth capacitor C4, the drain of the eighteenth NMOS transistor NM18 is connected to the gate of the eighteenth NMOS transistor NM18, the gate of the third NMOS transistor NM3, the gate of the sixth NMOS transistor NM6, the gate of the ninth NMOS transistor NM9, the gate of the tenth NMOS transistor NM10, the gate of the fifteenth NMOS transistor NM15, the second end of the seventh resistor R7, and the first end of the third capacitor C3, and the source of the seventeenth NMOS transistor NM17, the source of the eighteenth NMOS transistor NM18, and the second end of the fourth capacitor C4 are connected to the ground.

[0035] The working principle of the present invention is as follows: the input terminal VIN is connected to the reference voltage. The preamplifier 200 is a differential amplifier with two-stage resistance load and a common-gate amplifier. The input differential pair tube adopts large-size devices and a reasonable static operating point to reduce the input voltage offset. The post-comparator 300 is a two-stage open-loop amplifier, which is used to compare the output of the preamplifier 200. Due to the large device size of the preamplifier 200, a large parasitic capacitance is generated, which makes the signal transmission delay large. The capacitive coupler 400 is introduced. When the input signal PIN changes, the changed signal is coupled to the drain of the eleventh NMOS tube NM11 through the first capacitor C1, and is output from the source of the eleventh NMOS tube NM11 to the gate of the PMOS tube PM3; the changed signal is coupled to the gate of the sixteenth NMOS tube NM16 through the second capacitor C2. At the rising edge of PIN, the voltage of the second end of the first capacitor C1 and the second end of the second capacitor C2 rises. Since the voltage across the capacitors cannot change suddenly, the voltage of the first end of the first capacitor C1 and the first end of the second capacitor C2 rises, the gate voltage of the third PMOS transistor PM3 and the gate voltage of the sixteenth NMOS transistor NM16 rises rapidly, and the voltage of the node connected to the drain of the third PMOS transistor PM3 and the drain of the sixteenth NMOS transistor NM16 drops rapidly, so that the output of the driver 500 is quickly converted from a high level to a low level, and then the change of PIN is transmitted to the output through the preamplifier 200, the post comparator 300 and the driver 500 to maintain the output stable. At the falling and rising edge of PIN, the voltage of the second end of the first capacitor C1 and the second end of the second capacitor C2 decreases. Since the voltage across the capacitors cannot change suddenly, the voltage of the first end of the first capacitor C1 and the first end of the second capacitor C2 decreases, and the gate voltage of the third PMOS transistor PM3 and the gate voltage of the sixteenth NMOS transistor NM16 decreases rapidly. The voltage of the node connected to the drain of the third PMOS transistor PM3 and the drain of the sixteenth NMOS transistor NM16 increases rapidly, so that the output of the driver 500 is quickly converted from a low level to a high level, and then the change of PIN is transmitted to the output through the preamplifier 200, the post comparator 300 and the driver 500 to maintain the output stable. The time for the change of PIN to reach the output through the capacitive coupler 400, the post comparator 300 and the driver 500 is faster than the time for the change of PIN to reach the output through the preamplifier 200, the post comparator 300 and the driver 500, thereby achieving low offset voltage and accelerating the comparison speed.

[0036] In this case, DB HiTek 0.18um 60V process is used to design and simulate a low offset voltage high-speed comparator of this embodiment, and the device used is a 5V device. Figure 4 This is the delay of a traditional low offset voltage comparator, with a rising edge delay of 21.64nS and a falling edge delay of 17.42nS. Figure 5The delay of the low offset voltage high-speed comparator of the present invention is 6.35nS for rising edge delay and 1.37nS for falling edge delay. The input offset voltage is 1mV.

[0037] The above are only preferred embodiments of the present invention. It should be pointed out that the above preferred embodiments should not be regarded as limitations of the present invention. For ordinary technicians in this technical field, several equivalent substitutions, improvements and modifications can be made without departing from the spirit and scope of the present invention. These equivalent substitutions, improvements and modifications should also be regarded as the protection scope of the present invention. The embodiments will not be repeated here. The protection scope of the present invention should be based on the scope defined by the claims.

Claims

1. A low offset voltage high speed comparator, characterized in that: The low offset voltage high-speed comparator comprises a bias circuit, a preamplifier, a post-comparator, a capacitive coupler and a driver; The bias circuit is connected to the preamplifier, the post comparator and the capacitive coupler respectively, the preamplifier is connected to the post comparator and the capacitive coupler respectively, the capacitive coupler is connected to the post comparator, and the output end of the post comparator is connected to the input end of the driver; The preamplifier is used to amplify the input signal to obtain an amplified signal; The post comparator is used to compare the amplified signals; The capacitive coupler is used to provide a second path for the input signal and couple the change of the input signal to the post comparator; The driver is used to enhance the driving capability of the output signal of the post comparator.

2. A low offset voltage high speed comparator according to claim 1, characterized in that: The preamplifier includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube. The gate of the first NMOS tube is connected to the first input end of the low offset voltage high-speed comparator. The source of the first NMOS tube is respectively connected to the source of the second NMOS tube and the drain of the third NMOS tube. The drain of the first NMOS tube is respectively connected to the first end of the first resistor and the gate of the fourth NMOS tube. The drain of the second NMOS tube is respectively connected to the first end of the second resistor and the gate of the fifth NMOS tube. The gate of the second NMOS tube is connected to the second input end of the low offset voltage high-speed comparator. The source of the fourth NMOS tube is respectively connected to the source of the fifth NMOS tube and the drain of the sixth NMOS tube. The drain of the fourth NMOS tube is respectively connected to the first end of the third resistor and the gate of the fifth NMOS tube. The gate of the seventh NMOS tube is connected to the gate of the seventh NMOS tube, the drain of the fifth NMOS tube is respectively connected to the first end of the fourth resistor and the gate of the eighth NMOS tube, the source of the seventh NMOS tube is connected to the drain of the ninth NMOS tube, the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, the gate of the third NMOS tube is respectively connected to the gate of the sixth NMOS tube, the gate of the ninth NMOS tube, and the gate of the tenth NMOS tube, the source of the third NMOS tube, the gate of the sixth NMOS tube, and the gate of the ninth NMOS tube. The source of the ninth NMOS tube, the source of the tenth NMOS tube are all connected to the ground, the second end of the first resistor, the second end of the second resistor, the second end of the third resistor, the second end of the fourth resistor, the drain of the seventh NMOS tube, and the drain of the eighth NMOS tube are all connected to the power supply, the source of the seventh NMOS tube is connected to the first end of the post comparator, the source of the eighth NMOS tube is connected to the second end of the post comparator, and the gate of the third NMOS tube is connected to the bias circuit.

3. A low offset voltage high speed comparator according to claim 1, characterized in that: The post comparator includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a seventh resistor, and a third capacitor. The gate of the thirteenth NMOS tube is connected to the preamplifier, the source of the thirteenth NMOS tube is respectively connected to the source of the fourteenth NMOS tube and the drain of the fifteenth NMOS tube, the drain of the thirteenth NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the first PMOS tube, and the gate of the second PMOS tube, the gate of the fourteenth NMOS tube is connected to the preamplifier, the drain of the fourteenth NMOS tube is respectively connected to the drain of the second PMOS tube and the gate of the third PMOS tube, and the third PMOS tube is connected to the preamplifier. The drain of the OS tube is connected to the drain of the sixteenth NMOS tube, the source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube are all connected to the power supply, the gate of the fifteenth NMOS is respectively connected to the first end of the seventh resistor and the first end of the third capacitor, the gate of the sixteenth NMOS tube is connected to the second end of the seventh resistor, the source of the fifteenth NMOS, the source of the sixteenth NMOS tube, and the second end of the third capacitor are all connected to the ground, the drain of the first PMOS tube is connected to the first end of the capacitive coupler, the drain of the second PMOS tube is connected to the second end of the capacitive coupler, the drain of the third PMOS tube is connected to the input end of the driver, and the gate of the fifteenth NMOS is connected to the bias circuit.

4. The low offset voltage high speed comparator according to claim 1, characterized in that: The capacitive coupler includes an eleventh NMOS tube, a twelfth NMOS tube, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor. The source of the eleventh NMOS tube is respectively connected to the first end of the fifth resistor and the first end of the first capacitor, the drain of the eleventh NMOS tube is connected to the post-comparator, the source of the twelfth NMOS tube is connected to the first end of the sixth resistor, the gate of the eleventh NMOS tube is respectively connected to the gate of the twelfth NMOS tube and the bias circuit, the drain of the twelfth NMOS tube is connected to the post-comparator, the second end of the first capacitor is respectively connected to the second end of the second capacitor and the second input end of the low offset voltage high-speed comparator, and the second end of the fifth resistor and the second end of the sixth resistor are both connected to the ground.

5. The low offset voltage high speed comparator according to claim 1, characterized in that: The driver includes a Schmitt trigger and an inverter, the input end of the Schmitt trigger is connected to the output end of the post comparator, the output end of the Schmitt trigger is connected to the input end of the inverter, and the output end of the inverter serves as the output end of the low offset voltage high-speed comparator.

6. The low offset voltage high speed comparator according to claim 1, characterized in that: The bias circuit includes a first current source, a second current source, a seventeenth NMOS tube, an eighteenth NMOS tube and a fourth capacitor. The drain of the seventeenth NMOS tube is respectively connected to the gate of the seventeenth NMOS tube, the capacitive coupler and the first end of the fourth capacitor. The drain of the eighteenth NMOS tube is respectively connected to the gate of the eighteenth NMOS tube, the preamplifier and the post-comparator.

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