Background digital calibration method for Pipeline SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)

Abstract

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a Pipeline SAR ADC background digital calibration method, which comprises the following steps: in a first-stage sub-ADC sampling stage, sampling an analog input signal by adopting a capacitor lower-stage board of a first-stage capacitor array; after the sampling is finished, the first-stage SAR ADC performs SAR conversion; obtaining a corresponding residual voltage and a pseudo-random PN sequence after SAR conversion; the residual voltage and the generated pseudo-random PN sequence are input into the amplifier, the output of the amplifier is obtained and serves as a second-stage input signal for sampling, and in the same way, each sub-ADC can generate a digital code; and inputting the digital codes output by all the sub-ADCs into a digital calibration module for digital calibration, and finally obtaining an output result. Compared with the traditional digital calibration technology, the method has the advantages that the non-linear error calibration is added, the convergence speed is increased, the calibration precision is improved, and the ADC performance is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital converters, and in particular relates to a pipeline SAR ADC background digital calibration method. Background Art

[0002] With the continuous development of the semiconductor industry, integrated circuits have quickly entered the public's field of vision, not only providing convenience for people, but also measuring the country's scientific and technological development level and military strength. Since the signals in daily life are continuous analog signals, they cannot be directly processed by the microprocessor or digital signal processor in modern electronic devices. Therefore, it is particularly important to use a high-performance analog to digital converter (ADC) to convert analog signals into digital signals. As a type of integrated circuit, the demand for high-speed, high-precision, and low-power ADCs is also gradually increasing.

[0003] The Pipeline Successive Approximation Register Analog to Digital Converter (hereinafter referred to as Pipeline SAR ADC) has the advantages of high sampling rate and low power consumption, and is one of the focuses of the research field of digital-to-analog converter design in recent years. In the actual production process of the chip, affected by the process conditions and working environment, the structure of the Pipeline SAR ADC will be affected by errors such as capacitor mismatch, comparator offset, and inter-stage gain amplifier gain error, resulting in a decrease in ADC accuracy. Digital calibration technology is the main technology to improve the accuracy of Pipeline SAR ADC and reduce power consumption. It transfers the difficulty of analog circuit design to digital circuits, and is an important means to improve the accuracy and dynamic range of analog-to-digital converters in current integrated circuit design and manufacturing.

[0004] Compared with the foreground calibration algorithm, the background calibration technology can measure the calibration parameters without interrupting the normal data conversion of the analog-to-digital converter, and can update the calibration parameters in real time, so that the output signal can be calibrated continuously. The use of background calibration technology can reduce the design complexity of analog circuits. However, since most current calibration technologies only consider the linear error of inter-stage gain, the calibration of nonlinear errors is less considered, and the pseudo-random injection calibration technology generally uses a statistical calibration algorithm, which requires multiple iterations to achieve convergence, resulting in a long convergence time and a long calibration cycle. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a Pipeline SAR ADC background digital calibration method, comprising:

[0006] Step 1: In the first-stage sub-ADC sampling stage of the Pipeline SAR ADC, the analog input signal is sampled using the capacitor lower-stage board of the first-stage capacitor array;

[0007] Step 2: After sampling, the first-stage SAR ADC uses a binary search algorithm to perform SAR conversion, converting the sampled input signal into a digital code D1, completing the first-stage SAR ADC conversion;

[0008] Step 3: After the first-stage SAR ADC conversion is completed, the residual voltage generation stage is entered. In this stage, the digital code D1 quantized in the first stage is converted by DAC to generate the corresponding residual voltage and pseudo-random PN sequence, and the pseudo-random PN sequence is added to the first-stage process of Pipeline SAR ADC;

[0009] Step 4: The output residual voltage of the first-stage SAR ADC plus the generated pseudo-random PN sequence is input into the amplifier to obtain the output of the amplifier, and the output of the amplifier is sampled as the input signal of the second stage, and so on, each sub-ADC will generate a digital code;

[0010] Step 5: Input the digital codes output by all sub-ADCs into the digital calibration module, and use the dynamic measurement noise elimination algorithm and the least mean square algorithm to extract the inter-stage linear and nonlinear errors of the Pipeline SAR ADC, perform digital calibration, and finally obtain the output result.

[0011] Beneficial effects of the present invention:

[0012] The present invention adopts a 1.5-bit sub-SAR ADC per level, so that the output results are all within [-1 / 2V ref , 1 / 2V ref ], the threshold voltage offset of the residual transfer curve caused by the offset of the sub-ADC comparator is improved, resulting in erroneous digital output near the threshold voltage, causing the accuracy of the ADC output to decrease.

[0013] The present invention adopts a dynamic measurement noise elimination algorithm and a least mean square algorithm, and can achieve a convergence effect of pseudo-random injection calibration at a faster convergence speed.

[0014] Compared with the traditional digital calibration technology, the present invention increases the calibration of nonlinear errors, accelerates the convergence speed of the algorithm, increases the calibration accuracy, and improves the performance of ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of the Pipeline SAR ADC of the present invention;

[0016] Figure 2 It is a schematic diagram of the kbit SAR ADC quantization setting process of the present invention;

[0017] Figure 3 It is a pseudo-random sequence structure block diagram of the present invention;

[0018] Figure 4 This is a schematic diagram of PN sequence injection into ADC of the present invention;

[0019] Figure 5 is a first-order error calibration flow chart of the present invention;

[0020] Figure 6 is a flow chart of the third-order error calibration of the present invention;

[0021] Figure 7 This is the FFT analysis diagram of the 12-bit Pipeline SAR ADC before calibration of the present invention;

[0022] Figure 8 This is the FFT analysis diagram of the 12-bit Pipeline SAR ADC after calibration of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] A pipeline SAR ADC background digital calibration method, the overall workflow is as follows:

[0025] Step 1: In the first-stage sub-ADC sampling stage of the Pipeline SAR ADC, the analog input signal is sampled using the capacitor lower-stage board of the first-stage capacitor array;

[0026] Step 2: After sampling, the first-stage SAR ADC uses a binary search algorithm to perform SAR conversion, converting the sampled input signal into a digital code D1, completing the first-stage SAR ADC conversion;

[0027] Step 3: After the first-stage SAR ADC conversion is completed, the residual voltage generation stage is entered. In this stage, the digital code D1 quantized in the first stage is converted by DAC to generate the corresponding residual voltage and pseudo-random PN sequence, and the pseudo-random PN sequence is added to the first-stage process of Pipeline SAR ADC;

[0028] Step 4: The output residual voltage of the first-stage SAR ADC plus the generated pseudo-random PN sequence is input into the amplifier to obtain the output of the amplifier, and the output of the amplifier is sampled as the input signal of the second stage, and so on, each sub-ADC will generate a digital code;

[0029] Step 5: Input the digital codes output by all sub-ADCs into the digital calibration module, and use the dynamic measurement noise elimination algorithm and the least mean square algorithm to extract the inter-stage linear and nonlinear errors of the Pipeline SAR ADC, perform digital calibration, and finally obtain the output result.

[0030] The implementation method of the present invention will be described below in conjunction with the accompanying drawings.

[0031] The present invention aims at the existing calibration technology based on pseudo-random injection, which needs to go through multiple iterations to achieve convergence, and is affected by high-order nonlinear gain, resulting in long convergence time, inaccurate calibration and other problems. A Pipeline SARADC calibration algorithm is proposed for improvement. This calibration technology reduces the convergence time by dynamically measuring noise elimination, and extracts high-order errors through the output of the post-stage ADC to improve the calibration accuracy under the influence of high-order nonlinearity. This calibration method can effectively reduce the overall quantization noise of the analog-to-digital converter, thereby improving the calibration accuracy of the inter-stage gain and improving the performance of the analog-to-digital converter.

[0032] A pipeline SAR ADC background digital calibration method, such as Figure 1 As shown, the method includes: a PN sequence injection module, a Pipeline SAR ADC module and a calibration circuit; the PN sequence injection module is used to generate a PN pseudo-random sequence, and input the PN sequence into the Pipeline SAR ADC module; the Pipeline SAR ADC is composed of a plurality of SAR ADC sub-modules, each ADC sub-module is connected in series, and the PN sequence generates a corresponding analog signal according to the ADC sub-module; the digital signal output by each ADC sub-module is input into the calibration circuit, and the signal is calibrated by using the least mean square algorithm and the dynamic measurement noise elimination algorithm to obtain the final digital signal.

[0033] The architecture of Pipeline SAR ADC is similar to that of Pipeline ADC. The high precision required by the system is allocated to each stage of the pipeline, and then the digital code of each stage is combined and restored to the final system output code. The N-stage Pipeline SAR ADC consists of N SAR ADCs and N-1 interstage gain operational amplifiers. Each sub-stage component module of Pipeline SAR ADC includes CDAC capacitor array, SAR control logic, comparator and interstage gain operational amplifier. The circulation mode of input data is consistent with Pipeline ADC. The input data enters the first sub-stage to participate in quantization to obtain the digital output code string D1. The residual analog voltage Vres left by quantization is amplified by the interstage operational amplifier RA1 as the input data to be quantized in the second stage. The quantization process performed by the second stage is the same as that of the first stage. By analogy, the final system digital output can be obtained. After several cycles, when the initial system input reaches the last stage, the analog-to-digital conversion process of the system input is completed. The digital output of each stage is integrated and restored to obtain the final quantized output. As the number of stages of Pipeline SAD ADC increases, the digital code weight of the pipeline output becomes lower and the quantization becomes more detailed.

[0034] The basic component module of the sub-ADC is the SAR ADC. In order to reduce the threshold voltage offset of the residual transfer curve, the erroneous digital output is generated near the threshold voltage. The present invention adopts a redundant calibration algorithm in the top-level design. The output results of the next level are all within the range of [-1 / 2V ref , 1 / 2V ref ], which is equivalent to 1 redundant bit, and the interleaved bits are added between the two levels, which increases the linearity of the entire system.

[0035] The components of the sub-SAR ADC mainly include the sampling and holding circuit, comparator, CDAC capacitor array and SAR logic control array. The SAR ADC uses a binary search algorithm to digitize the input signal into an N-bit digital codeword through continuous comparison. After passing through the sampling and holding circuit, the input signal is compared with the voltage generated by the N-bit DAC, where the voltage generated by the DAC is controlled by the SAR logic array. The switching of the DAC in the SAR ADC is determined by the result of the comparator. After the switching is completed, the comparator will perform the next comparison until the quantization is completed. Usually, this process requires 1 cycle to sample the input and N comparator cycles to convert, with a total cycle of N+1. The SAR ADC quantization setting process is as follows Figure 2 shown.

[0036] The PN injection module generates a pseudo-random sequence through a linear feedback shift register network composed of a shift pulse generator and a modulo-2 adder. A pseudo-random sequence is a deterministic sequence that has a certain random sequence in statistical laws. The correlation function is close to white noise, with good randomness, predetermined determinism and repeatability. For an n-level LFSR, there is feedback in the system. Under the action of the shift pulse, the internal state of the shift register will continue to change. The end of the shift register is used as the output sequence, and the output sequence is the pseudo-random sequence.

[0037] Implementation of pseudo-random PN sequence, the pseudo-random PN sequence is generated by a linear feedback shift register. The six LFSRs use the same characteristic polynomial, and the initial values ​​inside the registers are set to different initial values. According to the characteristics of the pseudo-random series autocorrelation function, five of the pseudo-random sequences can be considered to be the result of shifting another pseudo-random sequence. Figure 3 This is a pseudo-random sequence generation structure diagram, where a i are the values ​​inside the shift registers whose serial numbers are all n in the figure, {a k} is the output pseudo-random sequence, c i is the feedback coefficient. c i is 0 or 1. i 1 means that the i-th register is connected to the feedback loop, and 0 means it is not connected. The feedback path is determined by selecting the value of the feedback coefficient. The feedback connection state of the linear feedback shift register is described by the characteristic polynomial f(x), which is recorded as:

[0038]

[0039] When there are n characteristic polynomials of LSFR, the pseudo-random sequence generated has (2n-1) states, which is the maximum length of the pseudo-random sequence. In one cycle of this sequence, since the probability of the code elements "0" and "1" appearing is the same, it is approximately random. Since the M sequence stores a single-bit sequence of 0 and 1 in the register, and the required PN sequence is a sequence of 1 and -1, 0 and 1 need to be represented as a sequence of 1 and -1 in the form of binary complement.

[0040] In this implementation case, the calibration coefficient of the ADC digital output is extracted by injecting pseudo-random noise into the ADC. The pseudo-random PN sequence is added, and the output is quantized by the post-stage pipeline, multiplied by the injected pseudo-random PN sequence itself, and the average is taken after accumulation. The calibration coefficient is obtained by using the autocorrelation characteristics of the pseudo-random sequence itself. The same PN sequence is injected into the output end of the pipeline, and the linear and nonlinear calibration of the inter-stage gain error is realized by the least mean square algorithm. The PN sequence is injected into the ADC as shown in FIG. Figure 4 shown.

[0041] When the PN sequence is injected into the Pipeline SAR ADC, the PN sequence flows into the subsequent sub-ADC along with the residual signal until the last sub-ADC conversion is completed. The output digital codeword is input into the calibration circuit, and the digital codeword Dres of the output residual is obtained by adding the corresponding weights. The output residual contains the inter-stage gain error and storage error. Use Dres to calibrate. When the calibration is completed, the final digital output is completed.

[0042] Figure 4 In the equation, δ is the capacitor mismatch parameter, a1 is the gain error caused by the limited gain of the amplifier, and a3 is the third-order gain error caused by the nonlinearity of the amplifier and the switch. Ignoring the pseudo-random PN sequence added during correction, the amplified residual voltage can be expressed as:

[0043]

[0044] V res =(2+δ)V in -D1(1+δ)V res

[0045] Where D1 is the digital output of the first stage of ADC, V ref is the reference level, δ is the capacitance mismatch parameter, and the ideal value is 0. The processing method of the residual voltage of the subsequent ADC is the same as the above method.

[0046] Considering only the linear error, the voltage of the DAC after adding the PN sequence is:

[0047] V DAC1 =(D1V ref -PN)(1+δ)

[0048] The imported pseudo-random PN sequence can only take "+VPN" or "-VPN", and the voltage of the subsequent ADC is obtained:

[0049] V BE =a1(V in (2+δ)-(D1V ref -PN)(1+δ)

[0050] After adding the PN sequence, the output is equivalent to the original residual signal of this stage superimposed with a noise signal related to the PN sequence and error. Assuming that the subsequent ADC is ideal, the expression of the subsequent ADC is:

[0051] D B1 =a1(D in (2+δ)-(D1-D PN )(1+δ))

[0052] Divide both sides of the above equation by D PN / Vref2 gives D BE ':

[0053]

[0054] Because (D PN / V ref )2 is always 1, so the last term on the right side of the above equation is equal to the ideal gain error coefficient A1:

[0055] D′ BE [n] = e PN,1 [n]+A1

[0056] From the above, we can know that the actual value of A1 is A1(1+δ). Since there is no correlation between the input signal and the PN signal, the desired A1 can be obtained by taking an appropriate average value of the above formula:

[0057]

[0058] For the third-order error, consider V at the transition point BE ,

[0059]

[0060] Simplifying the above formula we can get di,i+1.

[0061] Ignoring the higher order of a3 and δ and their products, the ideal value of di,i+1 is A1V ref , so by using the iterations where A1-di,i+1 approaches 0, A3 will move towards the theoretical value.

[0062]

[0063] As shown above, the output of the post-ADC is composed of measurement noise and expected error, which decreases as the average or iteration cycle increases. and The pseudo-random nature of the algorithm takes a long time to converge.

[0064] In order to shorten the convergence time, a dynamic measurement noise cancellation technology (Dynamic Measurement Noise Cancelation, DMNC) is proposed, such as Figure 5 As shown. The conversion samples required for calibration are reduced by DMNC technology. For gain error, the output of each subsequent ADC is divided into two different sets by another pseudo-random sequence PN2. In this example, the pseudo-random sequences PN and PN2 are two unrelated sequences.

[0065] DBE were randomly divided into11 and S 12 , from the above formula we can get S 11 [n] and S 12 The average value of [n] is:

[0066] S 11 [n] = D BE ×0.5×(1+PN2[n])

[0067] S 12 [n] = D BE ×0.5×(1+PN2[n])

[0068] Where S 11 [n] and S 12 [n] is uncorrelated and specifies the average of the differences between the partitioned DBE sets, from which we can see that:

[0069]

[0070] e 11 [n] and e 12 The value of [n] represents D BE The average value of the difference between the partition sets. Therefore, the change in each sampling period can be expressed as:

[0071]

[0072]

[0073] In the above formula, M1[n] is e 11 [n] and e 12 [n] is the differential part of the error. The value of M1[n] is ES 11 [n] and ES 12 The convergence of A1 is achieved by eliminating the measurement noise. Got it.

[0074] The convergence calculation of A1 and A3 is performed by using DMNC technology and LMS algorithm. S is obtained by using PN2 and DBE. 11 and S 12 , subtract the two values ​​to get M1[n], the sign of M1[n] depends on D BE And PN. Through the above process, we get D cal1 [n] D cal1 [n] is input into LMS for iteration to finally obtain the value of A1.

[0075] D cal1 [n] = D BE [n]-sign(M1[n])×|M1[n]|

[0076] A1[n]=A1[n-1]+μ1e LMS1 [n-1]

[0077]

[0078] μ1 is the step size of the LMS algorithm, e LMS1 [n] is D cal1 Results of autocorrelation of [n] and PN[n].

[0079] Similarly, for the third-order error compensation coefficient A3, it is only necessary to replace the above D BE [n] Replace di.i+1 with Figure 6 As shown. The first-order compensation coefficient A1 and the third-order compensation coefficient A3 are calculated by the above algorithm. The first-order compensation coefficient and the third-order compensation coefficient are used to calibrate the digital output of the ADC:

[0080]

[0081] This example is a 12-bit Pipeline SAR ADC. Use MATLAB to model the above algorithm and Pipeline SAR ADC. The FFT after adding the error is as follows: Figure 7 The FFT analysis after adding the digital calibration algorithm is shown in Figure 8 shown.

[0082] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A Pipeline SAR ADC background digital calibration method, characterized in that: include: Step 1: In the first-stage sub-ADC sampling stage of the Pipeline SAR ADC, the analog input signal is sampled using the capacitor lower-stage board of the first-stage capacitor array; Step 2: After sampling, the first-stage SAR ADC uses a binary search algorithm to perform SAR conversion, converting the sampled input signal into a digital code D1, completing the first-stage SAR ADC conversion; Step 3: After the first-stage SAR ADC conversion is completed, the residual voltage generation stage is entered. In this stage, the digital code D1 quantized in the first stage is converted by DAC to generate the corresponding residual voltage and pseudo-random PN sequence, and the pseudo-random PN sequence is added to the first-stage process of Pipeline SAR ADC; Step 4: The output residual voltage of the first-stage SAR ADC plus the generated pseudo-random PN sequence is input into the amplifier to obtain the output of the amplifier, and the output of the amplifier is sampled as the input signal of the second stage, and so on, each sub-ADC will generate a digital code; Step 5: Input the digital codes output by all sub-ADCs into the digital calibration module, and use the dynamic measurement noise elimination algorithm and the least mean square algorithm to extract the inter-stage linear and nonlinear errors of the Pipeline SAR ADC, perform digital calibration, and finally obtain the output result.

2. A Pipeline SAR ADC background digital calibration method according to claim 1, characterized in that: After sampling, the first-stage SAR ADC uses a binary search algorithm to perform SAR conversion, converting the sampled input signal into a digital code D1, generating the corresponding residual voltage and pseudo-random PN sequence, including: During the sampling phase, the switch connects the upper plate of the capacitor array to ground and connects the lower plate to the input signal V in Thus sampling is carried out; In the quantization stage, the SAR logic controls the switch of the capacitor lower board to connect to the reference voltage or ground, and compares the signal sampled by the SAR ADC with the reference voltage 1 / 2V. ref Compare and generate the first digital code. If it is less than 1 / 2V ref , then the output is 0, and the next digit is 1 / 4V ref Compare; if greater than 1 / 2V ref , then output 1, the next bit is 3 / 4V ref Compare, and so on, and finally generate digital output; this process makes the DAC voltage of the upper plate gradually approach the input signal V in each cycle. in ,The comparator performs comparison in each cycle, and the SAR logic determines whether the approximation is correct based on the binary signal output by the comparator and forms the output of the SAR ADC; The pseudo-random PN sequence is generated by a linear feedback shift register. The six LFSRs use the same characteristic polynomial, and the initial values ​​inside the registers are set to different initial values. According to the characteristics of the pseudo-random series autocorrelation function, five of the pseudo-random sequences can be considered to be the result of shifting another pseudo-random sequence.

3. A Pipeline SAR ADC background digital calibration method according to claim 1, characterized in that: The output residual voltage of the first-stage SAR ADC and the generated pseudo-random PN sequence are input into the amplifier to obtain the output of the amplifier, including: The pseudo-random PN sequence is injected into the CDAC capacitor array of the first-stage SAR ADC, and is input into the amplifier together with the residual voltage output by the SAR ADC. The output of the amplifier is used as the input of the next-stage SAR ADC. When the PN sequence is injected into the Pipeline SAR ADC, the PN sequence flows into the subsequent sub-ADC along with the residual signal until the last sub-ADC conversion is completed.

4. The Pipeline SAR ADC background digital calibration method according to claim 1, characterized in that: The dynamic measurement noise elimination algorithm and the least mean square algorithm are combined to extract the inter-stage linear and nonlinear errors of the Pipeline SAR ADC, perform digital calibration, and finally obtain the output results, including: The output D of the subsequent ADC BE , the difference between the transition points d i，i+1 And the first pseudo-random sequence PN1 and the second pseudo-random sequence PN2 are input into the ADC digital calibration module; The ADC digital calibration module converts D BE Divide into two unrelated sets according to the second pseudo-random sequence PN2, and obtain M1 by using the difference between the two sets; Use D BE Subtract the product of the absolute value and the sign of M1 to obtain the parameter D used for iteration cal1 ; D cal1 Iterate the first-order compensation coefficient A1 with the value obtained by autocorrelating with the first pseudo-random sequence PN1, and finally obtain the calibrated A1; D BE The difference between the transition points d i，i+1 , and obtain the third-order compensation coefficient A3; The digital output of the Pipeline SAR ADC is calibrated using the compensation coefficient. The first-order compensation coefficient A1 is multiplied by the first-stage digital output D1 of the Pipeline SAR ADC and then added to the output D1 of the subsequent ADC. BE The cubic and third-order compensation coefficients A3 and D BE The product of , finally the calibrated output result can be obtained.

5. A Pipeline SAR ADC background digital calibration method according to claim 4, characterized in that: Use D BE Subtract the product of the absolute value and the sign of M1 to obtain the parameter D used for iteration cal1 ,include: D cal [n]=D BE [n]-sign(M1[n])×|M1[n]| Among them, D cal1 represents the parameters used for iteration, D cal [n] represents the nth iteration parameter, D BE [n] represents the digital output of the subsequent ADC, M1[n] represents D BE The difference between two unrelated sub-levels divided by PN2, sign() means extracting the sign value.

6. A Pipeline SAR ADC background digital calibration method according to claim 4, characterized in that: D cal1 The first-order compensation coefficient A1 is iterated by the value obtained by autocorrelating with the first pseudo-random sequence PN1, and finally the calibrated A1 is obtained, including: a1[n]=A1[n-1]+μ1e LMS [n-1] Among them, A1[n] represents the first-order calibration coefficient obtained by the nth iteration, A1[n-1] represents the error coefficient obtained by the n-1th iteration, μ1 represents the iteration step size of the first-order compensation coefficient, and e LMS [n-1] represents the value obtained by the n-1th least mean square algorithm iteration, e LMS [n] represents the value obtained by the nth iteration of the least mean square algorithm, D cal [n] represents the nth iteration parameter, PN1[n] represents the nth pseudo-random sequence number, Represents autocorrelation.

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