Pseudo-differential lower polar plate sampling circuit and sampling method

Abstract

The invention relates to a pseudo-differential lower polar plate sampling circuit and a sampling method, which are used for designing an ADC (Analog to Digital Converter) sampling capacitor circuit, matching with a specifically designed common-mode level generation circuit and efficiently realizing signal sampling through switching of different stages under the control of each switch, and have the characteristic of direct comparison after sampling of an upper polar plate of a sampling capacitor. The conversion rate same as that of upper pole plate sampling can be achieved, the defects of upper pole plate charge injection, clock feed-through and other traditional upper pole plate sampling can be overcome, and the SDNR and SFDR performance is improved; and aiming at a high-swing input signal, the sampling capacitor array can perform level shift on the input signal, so that the function of processing the high-swing signal by a low-voltage device is realized, and the conversion rate of the SAR is effectively improved.

Description

Technical Field

[0001] The invention relates to a pseudo-differential lower plate sampling circuit and a sampling method, belonging to the technical field of ADC sampling. Background Art

[0002] In high-speed ADC circuits, especially SAR-ADC circuits, in order to maximize the sampling rate of the ADC circuit, its sampling capacitor usually uses upper-level board sampling. The advantage is that the comparison is made directly after the sampling is completed, which reduces the voltage change process by one time compared with the lower-level board sampling. However, the inherent non-ideal effects of upper-level board sampling, such as clock feedthrough and charge injection, limit the improvement of the signal-to-noise ratio and spurious-free dynamic range of the upper-level board sampling circuit. In addition, the withstand voltage of devices with advanced process technology continues to decrease. For 22nm / 28nm process, the withstand voltage of core devices is about 0.9V. The input signal amplitude and the withstand voltage of SAR core circuit constitute a pair of contradictions: the use of core devices in the SAR core circuit will maximize the conversion speed of the SAR-ADC circuit, but will limit the amplitude of the input signal and deteriorate the signal-to-noise ratio; if the SAR core circuit uses high-voltage devices, it will limit the conversion rate of the ADC.

[0003] like Figure 3 The figure shows a sampling circuit of an upper board applied to SAR-ADC in the literature "Liu CC, Kuo CH, Lin YZ. A 10 bit 320 MS / s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2015, 50(11): 2645-2654." This sampling method uses the upper board of the sampling capacitor to sample the input signal, and directly compares it after sampling, thereby improving the conversion rate of the ADC circuit. However, due to the existence of non-ideal effects such as clock feedthrough and charge injection, the SNDR and SFDR of the circuit are deteriorated. At a sampling rate of 320 MS / s, only 56.79 dB SNDR is achieved under an input signal of 19.9 MHz; and if the subsequent circuit uses core devices, the circuit cannot process high-amplitude input signals. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a pseudo-differential lower plate sampling circuit, which overcomes the defects of the prior art, achieves the same conversion rate as the upper plate sampling, and can level shift the input signal, thereby realizing the function of low-voltage devices processing high-swing signals, and effectively improving the conversion rate of SAR.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a pseudo-differential lower plate sampling circuit, including an ADC sampling capacitor circuit, the ADC sampling capacitor circuit includes a sampling capacitor Cs, a first switch S1, and a second switch S2, wherein the lower plate of the sampling capacitor Cs is connected to the differential signal VI to be sampled via the first switch S1, and the upper plate of the sampling capacitor Cs is connected to the common mode voltage VCM via the second switch S2, and the common mode voltage VCM is composed of a first voltage and a second voltage switched alternately, and the first voltage is greater than the second voltage; based on the switching of the first voltage and the second voltage, and the on-off control of the first switch S1 and the second switch S2, the sampling capacitor Cs realizes the sampling of the differential signal VI to be sampled.

[0006] As a preferred technical solution of the present invention: it also includes a common-mode level generating circuit, which selectively switches the first voltage and the second voltage to form a common-mode voltage VCM and outputs it. The common-mode level generating circuit includes a broadband operational amplifier I1, a source follower NMOS tube M1, a common-mode switching switch S3, and a source follower resistor R1, wherein the first voltage is formed by the power supply voltage VDD, the positive input end of the broadband operational amplifier I1 is connected to the reference voltage VREF, the output end of the broadband operational amplifier I1 is connected to the gate of the source follower NMOS tube M1, the drain of the source follower NMOS tube M1 is connected to the power supply voltage VDD, and the source output of the source follower NMOS tube M1 constitutes the second voltage, the active end of the common-mode switching switch S3 selectively switches to connect the first voltage and the second voltage, the fixed end of the common-mode switching switch S3, the negative input end of the broadband operational amplifier I1, and one end of the source follower resistor R1 are connected, and the connected position constitutes the output end of the common-mode level generating circuit, which is used to output the common-mode voltage VCM to the ADC sampling capacitor circuit, and the other end of the source follower resistor R1 is grounded.

[0007] As a preferred technical solution of the present invention: the ADC sampling capacitor circuit also includes an input voltage REF, a fixed end of the second switch S2 is connected to the upper plate of the sampling capacitor Cs, and an active end of the second switch S2 is switched between the three states of connecting to the common mode voltage VCM, connecting to the input voltage REF, and disconnecting, and based on the connection between the active end of the second switch S2 and the input voltage REF, the signal collected by the sampling capacitor Cs is compared.

[0008] Corresponding to the above, the technical problem that the present invention needs to solve is to provide a sampling method based on a pseudo-differential lower plate sampling circuit, based on the different stage switching under the control of each switch in the designed circuit, to efficiently realize signal sampling.

[0009] In order to solve the above technical problems, the present invention adopts the following technical solution: the present invention designs a sampling method of a pseudo-differential lower plate sampling circuit, performs the following steps A to D, and samples the differential signal VI to be sampled by the sampling capacitor Cs: Step A. Execute the first stage, control the mobile end of the common mode switch S3 to connect to the first voltage, i.e., the power supply voltage VDD, and control the first switch S1 to close and connect to the differential signal VI to be sampled, and control the second switch S2 to close and connect to the common mode voltage VCM, and use the sampling capacitor Cs to sample the differential signal VI to complete the collection of the charge amount of (VDD - VI) * Cs; Step B. executing the second stage, keeping the mobile end of the common mode switch S3 connected to the first voltage, i.e., the power supply voltage VDD, and keeping the first switch S1 closed to access the differential signal VI to be sampled, and controlling the second switch S2 to be opened; Step C. Execute the third stage, control the mobile end of the common mode switch S3 to be connected to the second voltage, and control the first switch S1 and the second switch S2 to be disconnected; Step D: Execute the fourth stage, keep the common mode switch S3 connected to the second voltage, keep the first switch S1 open, control the second switch S2 to close and connect the common mode voltage VCM, and the lower plate potential of the sampling capacitor Cs becomes VI -VDD+VCM, completing the level shift.

[0010] The pseudo-differential lower plate sampling circuit and sampling method of the present invention, using the above technical solution, has the following technical effects compared with the prior art: The present invention designs a pseudo-differential lower plate sampling circuit and a sampling method, designs an ADC sampling capacitor circuit, matches a specifically designed common-mode level generating circuit, and realizes signal sampling efficiently by switching at different stages under the control of various switches. The circuit has the characteristic of directly comparing after sampling on the upper plate of the sampling capacitor, and can not only achieve the same conversion rate as that of the upper plate sampling, but also overcome the defects of the traditional upper plate sampling such as the upper plate charge injection and clock feedthrough, and improve the SDNR and SFDR performances. Moreover, for high-swing input signals, the sampling capacitor array can level-shift the input signals, realize the function of low-voltage devices processing high-swing signals, and effectively improve the conversion rate of SAR. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of a pseudo-differential lower plate sampling circuit of the present invention; Figure 2 A schematic diagram of a sampling method process of a pseudo-differential lower plate sampling circuit of the present invention; Figure 3 This is a schematic diagram of a sampling circuit of an upper board described in the document JSSC2015. DETAILED DESCRIPTION

[0012] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0013] The present invention designs a pseudo-differential lower plate sampling circuit. In practical applications, Figure 1 As shown, it includes a common-mode level generating circuit and an ADC sampling capacitor circuit. The common-mode level generating circuit includes a broadband operational amplifier I1, a source follower NMOS tube M1, a common-mode switching switch S3, and a source follower resistor R1. The power supply voltage VDD constitutes a first voltage, the positive input terminal of the broadband operational amplifier I1 is connected to the reference voltage VREF, the output terminal of the broadband operational amplifier I1 is connected to the gate of the source follower NMOS tube M1, the drain of the source follower NMOS tube M1 is connected to the power supply voltage VDD, and the source output of the source follower NMOS tube M1 constitutes a second voltage. The active end of the common-mode switching switch S3 selectively switches to connect the first voltage and the second voltage. The fixed end of the common-mode switching switch S3, the negative input terminal of the broadband operational amplifier I1, and one end of the source follower resistor R1 are connected, and the connected position constitutes the output end of the common-mode level generating circuit to output the common-mode voltage VCM, that is, the common-mode level generating circuit selectively switches the first voltage and the second voltage to form the common-mode voltage VCM and outputs it to the ADC sampling capacitor circuit. The other end of the source follower resistor R1 is grounded, and the first voltage is greater than the second voltage.

[0014] The ADC sampling capacitor circuit includes a sampling capacitor Cs, a first switch S1, and a second switch S2, wherein the lower plate of the sampling capacitor Cs is connected to the differential signal VI to be sampled via the first switch S1, the fixed end of the second switch S2 is connected to the upper plate of the sampling capacitor Cs, and the active end of the second switch S2 is used to selectively switch between the three states of connecting to the common mode voltage VCM, connecting to the input voltage REF, and disconnecting. Based on the selective switching between the first voltage and the second voltage, and the on-off control of the first switch S1 and the second switch S2, the sampling capacitor Cs is used to sample the differential signal VI to be sampled, and based on the connection between the active end of the second switch S2 and the input voltage REF, the signal collected by the sampling capacitor Cs is compared. Figure 1 As shown, VIP and VIN respectively represent the positive signal of the differential signal VI to be sampled and the negative signal of the differential signal VI to be sampled, and REFP and REFN respectively represent the positive voltage of the input voltage REF and the negative voltage of the input voltage REF.

[0015] According to the above-mentioned pseudo-differential lower plate sampling circuit structure, in practical application, the corresponding sampling method is further designed, such as Figure 2 As shown, the specific design performs the following steps A to D, and the sampling capacitor Cs samples the differential signal VI to be sampled.

[0016] Step A. Execute the first stage, control the mobile end of the common-mode switching switch S3 to connect to the first voltage, that is, the power supply voltage VDD, and control the first switch S1 to close and connect to the differential signal VI to be sampled, and control the second switch S2 to close and connect to the common-mode voltage VCM, and use the sampling capacitor Cs to sample the differential signal VI to complete the collection of the charge amount of (VDD - VI) * Cs.

[0017] Step B: Execute the second stage, keep the mobile end of the common mode switch S3 connected to the first voltage, ie, the power supply voltage VDD, keep the first switch S1 closed to access the differential signal VI to be sampled, and control the second switch S2 to be opened.

[0018] Step C: Execute the third stage, control the mobile end of the common mode switch S3 to be connected to the second voltage, and control the first switch S1 and the second switch S2 to be disconnected.

[0019] Step D. Execute the fourth stage, keep the common mode switch S3 mobile end connected to the second voltage, and keep the first switch S1 open, control the second switch S2 to close and connect the common mode voltage VCM, the lower plate potential of the sampling capacitor Cs becomes VI-VDD+VCM, complete the level shift, and the input higher swing signal is level shifted to a voltage range that can be directly processed by the low voltage core device. In addition, the voltage will be directly sent to the comparator for comparison, which improves the conversion rate of the SAR circuit; VI represents the difference between the positive signal VIP of the differential signal VI to be sampled and the negative signal VIN of the differential signal VI to be sampled.

[0020] The sampling and comparison method designed and proposed by the above technical solution is different from the lower plate sampling in that it is not limited by the common mode and amplitude of the input signal. In the actual application of the design of the present invention, the SAR logic unused capacitor array switches can use low-voltage devices, which can show faster speed.

[0021] The pseudo-differential lower plate sampling circuit and sampling method designed in the above technical solution are used to design an ADC sampling capacitor circuit, which is matched with a specifically designed common-mode level generating circuit. By switching at different stages under the control of each switch, signal sampling is efficiently realized. It has the characteristic of directly comparing after sampling on the upper plate of the sampling capacitor, and can not only achieve the same conversion rate as that of the upper plate sampling, but also overcome the defects of traditional upper plate sampling such as upper plate charge injection and clock feedthrough, thereby improving the SDNR and SFDR performance. Moreover, for high-swing input signals, the sampling capacitor array can level-shift the input signal, thereby realizing the function of low-voltage devices to process high-swing signals, and effectively improving the conversion rate of SAR.

[0022] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A pseudo-differential lower plate sampling circuit, characterized in that: The ADC sampling capacitor circuit includes a sampling capacitor Cs, a first switch S1, and a second switch S2, wherein the lower plate of the sampling capacitor Cs is connected to the differential signal VI to be sampled via the first switch S1, and the upper plate of the sampling capacitor Cs is connected to the common mode voltage VCM via the second switch S2, and the common mode voltage VCM is composed of a first voltage and a second voltage switched alternately, and the first voltage is greater than the second voltage; based on the switching of the first voltage and the second voltage, and the on-off control of the first switch S1 and the second switch S2, the sampling capacitor Cs realizes the sampling of the differential signal VI to be sampled.

2. A pseudo-differential lower plate sampling circuit according to claim 1, characterized in that: It also includes a common-mode level generating circuit, which selectively switches a first voltage and a second voltage to form a common-mode voltage VCM and outputs it. The common-mode level generating circuit includes a broadband operational amplifier I1, a source follower NMOS tube M1, a common-mode switching switch S3, and a source follower resistor R1, wherein the first voltage is formed by a power supply voltage VDD, the positive input terminal of the broadband operational amplifier I1 is connected to the reference voltage VREF, the output terminal of the broadband operational amplifier I1 is connected to the gate of the source follower NMOS tube M1, the drain of the source follower NMOS tube M1 is connected to the power supply voltage VDD, the source output of the source follower NMOS tube M1 forms the second voltage, the active end of the common-mode switching switch S3 selectively switches to connect the first voltage and the second voltage, the fixed end of the common-mode switching switch S3, the negative input terminal of the broadband operational amplifier I1, and one end of the source follower resistor R1 are connected, and the connected position constitutes the output end of the common-mode level generating circuit, which is used to output the common-mode voltage VCM to the ADC sampling capacitor circuit, and the other end of the source follower resistor R1 is grounded.

3. A pseudo-differential lower plate sampling circuit according to claim 1 or 2, characterized in that: The ADC sampling capacitor circuit also includes an input voltage REF, a fixed end of the second switch S2 is connected to the upper plate of the sampling capacitor Cs, and an active end of the second switch S2 is switched between the three states of connecting to the common mode voltage VCM, connecting to the input voltage REF, and disconnecting. Based on the connection between the active end of the second switch S2 and the input voltage REF, the signal collected by the sampling capacitor Cs is compared.

4. A sampling method based on the pseudo-differential lower plate sampling circuit according to claim 2 or 3, characterized in that: Perform the following steps A to D to sample the differential signal VI by the sampling capacitor Cs: Step A. Execute the first stage, control the mobile end of the common mode switch S3 to connect to the first voltage, i.e., the power supply voltage VDD, and control the first switch S1 to close and connect to the differential signal VI to be sampled, and control the second switch S2 to close and connect to the common mode voltage VCM, and use the sampling capacitor Cs to sample the differential signal VI to complete the collection of the charge amount of (VDD - VI) * Cs; Step B. executing the second stage, keeping the mobile end of the common mode switch S3 connected to the first voltage, i.e., the power supply voltage VDD, and keeping the first switch S1 closed to access the differential signal VI to be sampled, and controlling the second switch S2 to be opened; Step C. Execute the third stage, control the mobile end of the common mode switch S3 to be connected to the second voltage, and control the first switch S1 and the second switch S2 to be disconnected; Step D: Execute the fourth stage, keep the common mode switch S3 connected to the second voltage, keep the first switch S1 open, control the second switch S2 to close and connect the common mode voltage VCM, and the lower plate potential of the sampling capacitor Cs becomes VI -VDD+VCM, completing the level shift.

Images