MEMS bimorph structure and preparation method thereof, and MEMS piezoelectric microphone

Abstract

The invention relates to the technical field of novel electroacoustic element manufacturing, microelectronic devices and the like, in particular to an MEMS bimorph structure, a preparation method thereof and an MEMS piezoelectric microphone. The MEMS bimorph structure comprises: a support structure, which comprises an outer ring body; the back cavity is formed on the inner side of the outer ring body; the composite vibration layer comprises a lower piezoelectric layer formed above the outer ring body and the back cavity from bottom to top; the middle layer is formed on the lower piezoelectric layer and comprises a middle electrode layer on the inner side and a second dielectric layer on the periphery, and a middle electrode is flush with the upper surface and the lower surface of the second dielectric layer; the upper piezoelectric layer is formed above the middle layer; the lower electrode layer is formed below the lower piezoelectric layer; and the upper electrode layer is formed above the upper piezoelectric layer. The second dielectric layer is deposited on the periphery of the middle electrode layer, so that a step surface is eliminated, the plane quality of the middle layer is greatly improved through the CMP process, and the quality of a piezoelectric layer film grown on the flat surface is better.

Description

Technical Field

[0001] The present invention relates to the technical fields of novel electroacoustic component manufacturing and microelectronic devices, and in particular to a MEMS double-chip structure and a preparation method thereof, and a MEMS piezoelectric microphone. Background Art

[0002] MEMS (Micro-Electro-Mechanical System) microphone is a new type of electroacoustic component made by micromachining technology, which has the characteristics of small size, good frequency response characteristics, low noise, etc. With the development of smart electronic devices becoming smaller and thinner, MEMS microphones are increasingly widely used in these devices.

[0003] MEMS microphones mainly include capacitive and piezoelectric types. MEMS piezoelectric microphones are microphones made using micro-electromechanical system technology and piezoelectric film technology. Due to the use of semiconductor planar technology and bulk silicon processing technology, they are small in size, small in volume, and have good consistency. At the same time, compared with capacitive microphones, they also have the advantages of not requiring bias voltage, a wide operating temperature range, dustproof and waterproof, but their sensitivity is relatively low, which restricts the development of MEMS piezoelectric microphones. Residual stress is a major factor restricting the improvement of the sensitivity of MEMS piezoelectric microphones, which is particularly significant in circular piezoelectric MEMS dual-chip structures.

[0004] Figure 1 FIG. 1 is a cross-sectional view of a dual-chip MEMS dual-chip structure of the prior art. Figure 1 As shown, since both the lower electrode layer and the middle electrode layer protrude upward, the two subsequently grown piezoelectric layers have poor coverage at the step gradient, the size and direction of the crystal columns are dispersed, and the poor material quality affects the signal output; at the same time, the upward protruding part of the composite vibration layer will produce additional resistance, affecting the vibration amplitude in the vibration direction, resulting in poor signal output quality. Summary of the invention

[0005] 1. Technical issues to be solved

[0006] The present invention is expected to at least partially solve one of the above technical problems.

[0007] 2. Technical Solution

[0008] The first aspect of the present invention provides a MEMS dual-chip structure. The MEMS dual-chip structure includes: a support structure, including: an outer ring body; a back cavity formed inside the outer ring body; a composite vibration layer, from bottom to top, including: a lower piezoelectric layer, formed above the outer ring body and the back cavity; an intermediate layer, formed on the lower piezoelectric layer, including: an inner middle electrode layer, a second dielectric layer on the periphery, wherein the upper and lower surfaces of the middle electrode and the second dielectric layer are flush; an upper piezoelectric layer, formed above the intermediate layer; a lower electrode layer, formed below the lower piezoelectric layer; and an upper electrode layer, formed above the upper piezoelectric layer.

[0009] A second aspect of the present invention provides a method for preparing a MEMS dual-wafer structure. The method for preparing a MEMS dual-wafer structure is used to prepare the above MEMS dual-wafer structure, comprising:

[0010] Step A, growing a sacrificial material film on a substrate, depositing an electrode film on the sacrificial material film, and patterning the electrode film to form a lower electrode layer;

[0011] Step B, depositing a first dielectric film on the lower electrode layer and the sacrificial material film;

[0012] Step C, planarizing the first dielectric film until the lower electrode layer is exposed, and the first dielectric film retained around the lower electrode layer forms a first dielectric layer;

[0013] Step D, depositing a lower piezoelectric layer on the lower electrode layer and the first dielectric layer;

[0014] Step E, depositing an electrode film on the lower piezoelectric layer, and patterning the electrode film to form a middle electrode layer;

[0015] Step F, depositing a second dielectric film on the middle electrode layer and the lower piezoelectric layer;

[0016] Step G, planarizing the second dielectric film until the middle electrode layer is exposed, and the second dielectric film retained outside the middle electrode layer forms a second dielectric layer;

[0017] Step H, depositing an upper piezoelectric layer on the middle electrode layer and the second dielectric layer;

[0018] Step I, depositing an electrode film on the upper piezoelectric layer, and patterning the electrode film to form an upper electrode layer;

[0019] Step J, performing deep etching on the back side of the substrate to form a back side cavity on the inner side, exposing the sacrificial material film;

[0020] Step K, continuing etching on the back side of the substrate to remove the sacrificial layer material and the first dielectric layer in the back side cavity, so that the lower electrode is exposed in the back side cavity to form a back side cavity.

[0021] 3. Beneficial Effects

[0022] It can be seen from the above technical solution that the present invention has at least one of the following beneficial effects compared with the prior art:

[0023] (1) Forming a better quality piezoelectric layer film on a flat surface

[0024] In the prior art MEMS dual-chip structure, an upper piezoelectric layer is grown on the stepped surfaces of the lower piezoelectric layer and the middle electrode layer. As a result, both the upper piezoelectric layer and the lower piezoelectric layer are distorted, and the material growth quality is affected.

[0025] In the present invention, the step surface is eliminated by depositing the second dielectric layer on the periphery of the middle electrode layer, and the plane quality of the middle layer is greatly improved after the CMP process. The grain size of the piezoelectric layer film grown on the flat surface will be larger, with better orientation and better crystallization performance. The surface morphology of the prepared piezoelectric layer film is smoother and more uniform without cracks, thereby improving the signal quality of MEMS.

[0026] (2) Symmetrical composite vibration layer increases vibration amplitude

[0027] The composite vibration layer formed by the prior art has one layer of the membrane being flat, while the other layer of the membrane being an irregular plane protruding upward. The asymmetry of the diaphragm in the vertical direction (ie, the vibration direction) affects the mechanical vibration amplitude of the diaphragm.

[0028] Compared with the asymmetric vibration composite film, the composite vibration layer of the present invention is symmetrical in the vibration direction. During the vibration process, the deformation of the upper piezoelectric layer and the lower piezoelectric layer is synchronized and consistent, and double equal signal output can be integrated. At the same time, the flat vibration composite film eliminates the additional resistance caused by the irregular protrusions of the composite vibration layer in the prior art, maximizes the vibration amplitude, and improves the signal strength of the MEMS. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a cross-sectional view of a dual-chip MEMS dual-chip structure in the prior art.

[0030] Figure 2 It is a cross-sectional view of a MEMS dual-chip structure according to an embodiment of the present invention.

[0031] Figure 3 Flow chart of a method for preparing a MEMS dual-chip structure according to an embodiment of the present invention.

[0032] Figure 4 for Figure 3 The cross-sectional view of the middle component of the MEMS dual-chip structure preparation method after each step is completed. DETAILED DESCRIPTION

[0033] The inventive concept of the present invention is to eliminate the steps of the middle layer so that the upper piezoelectric layer grows on a flat plane, thereby improving the quality of the upper piezoelectric layer and the lower piezoelectric layer, thereby improving the signal quality of the MEMS.

[0034] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific implementation methods and with reference to the accompanying drawings.

[0035] A first aspect of the present invention provides a MEMS dual-chip structure. Figure 2 FIG. 2 is a cross-sectional view of a MEMS dual-chip structure according to an embodiment of the present invention. Figure 2 As shown, the MEMS dual-chip structure of this embodiment includes:

[0036] The supporting structure includes: an outer ring body 11; a back cavity 12 formed inside the outer ring body;

[0037] The composite vibration layer 20 comprises, from bottom to top:

[0038] A lower piezoelectric layer 21 is formed above the outer ring body and the back cavity;

[0039] The middle layer is formed above the lower piezoelectric layer, and includes: an inner middle electrode layer 22A and an outer second dielectric layer 22B, wherein the upper surfaces of the middle electrode and the second dielectric layer are flush;

[0040] an upper piezoelectric layer 23 formed above the middle layer;

[0041] A lower electrode layer 31 is formed below the lower piezoelectric layer;

[0042] The upper electrode layer 32 is formed on the upper piezoelectric layer.

[0043] The various components of the MEMS dual-chip structure of this embodiment are described in detail below.

[0044] like Figure 2 As shown, in this embodiment, the outer ring body 11 includes: a substrate outer ring body 11A; a sacrificial layer outer ring body 11B, formed above the substrate outer ring body; and a first dielectric layer outer ring body 11C, formed above the sacrificial layer outer ring body. The substrate outer ring body, the sacrificial layer outer ring body, and the first dielectric layer outer ring body together surround a back cavity 12.

[0045] The outer ring of the sacrificial layer is formed by etching the sacrificial layer, and the purpose of setting the sacrificial layer is to etch the back cavity. The outer ring of the first dielectric layer is formed by etching the first dielectric layer, and the purpose of setting the first dielectric layer is to form a growth plane flush with the lower electrode layer for the growth of the lower piezoelectric layer 21. The specific content will be described in detail in the subsequent MEMS dual-chip structure preparation method.

[0046] In this embodiment, the upper piezoelectric layer 23 is grown on a flat intermediate layer plane, and its grain size will be larger, with better orientation and better crystallization performance. The surface morphology of the prepared piezoelectric layer film will be smoother and more uniform without cracks, thereby improving the signal quality of MEMS.

[0047] In this embodiment, the lower piezoelectric layer and the upper piezoelectric layer are symmetrical about the middle layer; the lower electrode layer and the upper electrode layer are symmetrical about the middle layer, and the horizontal plane projections of the lower electrode layer, the middle electrode layer, and the upper electrode layer overlap and fall within the horizontal plane projection of the back cavity. Through such an arrangement, this embodiment provides a MEMS dual-chip structure with a fully symmetrical structure, which is a symmetrical structure in both vertical and horizontal directions, thereby avoiding the influence of the asymmetric structure on the energy output, and the signal quality is greatly improved.

[0048] In this embodiment, the material of the outer ring body of the substrate is: silicon or silicon-based compounds; the material of the sacrificial layer outer ring body and the second dielectric layer is: silicon oxide; the material of the lower piezoelectric layer and the upper piezoelectric layer is selected from one or more of the following materials: aluminum nitride, scandium-doped aluminum nitride, zinc oxide, lead zirconate titanate; the material of the lower electrode layer, the middle electrode layer, and the upper electrode layer is selected from one or more of the following materials: molybdenum, gold, aluminum, chromium, platinum, titanium, tungsten, titanium nitride.

[0049] Those skilled in the art should understand that the above material selections are only examples, and in actual scenarios, suitable materials can be selected as needed, all of which can implement the present invention and are within the protection scope of the present invention.

[0050] So far, the introduction of the MEMS dual-chip structure of the embodiment of the present invention is completed.

[0051] A second aspect of the present invention provides a method for preparing a MEMS dual-chip structure, which is used to prepare the MEMS dual-chip structure in the above embodiment. Figure 3 Flow chart of a method for preparing a MEMS dual-chip structure according to an embodiment of the present invention. Figure 4 for Figure 3 The cross-sectional view of the middle part of the MEMS dual-chip structure preparation method after each step is completed. Figure 3 and Figure 4 The preparation method of the MEMS dual-wafer structure of this embodiment includes:

[0052] Step A, growing a sacrificial material film on a substrate, depositing an electrode film on the sacrificial material film, and patterning the electrode film to form a lower electrode layer;

[0053] Specifically, a silicon oxide film is grown on the surface of the silicon substrate, the thickness of the silicon oxide film is H0, and an electrode film is grown on the silicon oxide film, the thickness of the electrode film is H a, coating the surface with photoresist, and using dry etching to form the electrode film to form the lower electrode layer, such as Figure 4 As shown in (a).

[0054] Step B, depositing a first dielectric film on the lower electrode layer and the sacrificial material film;

[0055] Specifically, a silicon oxide film is deposited on the surface of the lower electrode layer and the sacrificial material film not covered by the lower electrode layer. The thickness of the silicon oxide film is H1. Figure 4 As shown in (b).

[0056] After this step, in the non-lower electrode layer area, the silicon oxide film as a sacrificial layer is connected to the subsequently deposited silicon oxide film. Due to the existence of the lower electrode layer pattern, the pattern transfer continues during the material deposition process, and the surface of the silicon oxide film after deposition is not a flat surface.

[0057] Step C, planarizing the first dielectric film until the lower electrode layer is exposed, and the first dielectric film retained around the lower electrode layer forms a first dielectric layer;

[0058] Specifically, the silicon oxide film is planarized until the lower electrode layer pattern is exposed, such as Figure 4 As shown in (c).

[0059] In actual operation, the CMP process can be used to reduce the thickness of the silicon oxide film from H1 to H a Or slightly smaller. Thickness H a The thickness H can be adjusted by adjusting the grinding liquid ratio and grinding time to adjust the grinding speed and select the end node time of the CMP process. a , exposing the lower electrode material.

[0060] Preferably, regarding the thickness of each film layer, the thickness of the electrode film deposited in step A is H a The thickness of the first dielectric film in step B is H1, and the thickness of the lower electrode layer and the first dielectric layer after planarization in step C is H a ', then: H1≥1.1H a , 0.6H a ≤H a '≤0.9H a .

[0061] Step D, depositing a lower piezoelectric layer on the lower electrode layer and the first dielectric layer;

[0062] Specifically, after the planarization process, the lower electrode layer and the first dielectric layer form a flat plane, and the first piezoelectric layer is further deposited on the flat plane with a thickness of H.b ,like Figure 4 As shown in (d).

[0063] As mentioned above, the material of the first piezoelectric layer is selected from one or more of the following materials: aluminum nitride, scandium-doped aluminum nitride, zinc oxide, and lead zirconate titanate.

[0064] In the prior art, the upper piezoelectric layer is grown on the step surface of the lower piezoelectric layer and the middle electrode layer, which results in the upper and lower piezoelectric layers being distorted and deformed, and the material growth quality is affected. Compared with the piezoelectric layer film grown on the step surface and the rough surface, the present invention eliminates the step surface by depositing the second dielectric layer on the periphery of the middle electrode layer, and after the CMP process, the plane quality of the middle layer is greatly improved. The grain size of the piezoelectric layer film grown on the flat surface will be larger, with better orientation and better crystallization performance. The surface morphology of the prepared piezoelectric layer film is smoother and more uniform, without cracks, and the signal of MEMS is improved.

[0065] Step E, depositing an electrode film on the lower piezoelectric layer, and patterning the electrode film to form a middle electrode layer;

[0066] Specifically, an electrode film is deposited on the first piezoelectric layer, and the thickness of the electrode film is H. c , the same as the electrode patterning method in step A, coating the surface of the electrode film with photoresist, and using dry etching patterning to form the middle electrode layer pattern, such as Figure 4 As shown in (e);

[0067] Step F, depositing a second dielectric film on the middle electrode layer and the lower piezoelectric layer;

[0068] Specifically, a second dielectric film, a silicon oxide film, is continuously deposited on the surface of the middle electrode layer and the lower piezoelectric layer not covered by the middle electrode layer. The thickness of the silicon oxide film is H2. Figure 4 As shown in (f).

[0069] It is understood by those skilled in the art that, due to the presence of the middle electrode layer pattern, the pattern transfer continues during the material deposition process, and the silicon oxide film after deposition is not a flat surface;

[0070] Step G, planarizing the second dielectric film until the middle electrode layer is exposed, and the second dielectric film retained outside the middle electrode layer forms a second dielectric layer;

[0071] Specifically, the second dielectric film is planarized until the middle electrode layer pattern is exposed. The CMP process can be used to reduce the thickness of the second dielectric film from H2 to H c Or slightly smaller. Thickness H c The thickness may be 0.1-5 μm, preferably 0.1 to 0.5 μm, and the intermediate electrode material may be exposed after planarization, such as Figure 4 As shown in (g).

[0072] Regarding the thickness of each film layer, the thickness of the electrode film deposited in step E is H c The thickness of the second dielectric film in step F is H2, and the thickness of the electrode layer and the second dielectric layer after planarization in step G is H c ', then: H2≥1.1H c , 0.6H c ≤H c '≤0.9H c .

[0073] Step H, depositing an upper piezoelectric layer on the middle electrode layer and the second dielectric layer;

[0074] Specifically, a second piezoelectric layer is deposited on the flat second dielectric layer and the middle electrode layer, with a thickness of H. d ,like Figure 4 As shown in (h).

[0075] Similarly, a flat surface will improve the growth quality of the piezoelectric layer material, allowing for the production of a better piezoelectric layer and improving the MEMS signal.

[0076] Step I, depositing an electrode film on the upper piezoelectric layer, and patterning the electrode film to form an upper electrode layer;

[0077] Specifically, a growth electrode film is formed on the upper piezoelectric layer, and the thickness of the electrode film is H e , the same as the electrode patterning method in step B, coating the surface of the upper electrode with photoresist, and using dry etching to pattern the upper electrode layer, such as Figure 4 As shown in (i);

[0078] Step J, etching is performed on the back side of the substrate until the sacrificial material film is exposed.

[0079] Specifically, deep silicon etching is performed on the back side of the silicon substrate to form a back side cavity on the inner side, exposing the sacrificial material film, such as Figure 4 As shown in (j).

[0080] Step K, continuing etching on the back side of the substrate to remove the sacrificial layer material and the first dielectric layer in the back side cavity, so that the lower electrode is exposed in the back side cavity, thereby forming the back side cavity in the final form.

[0081] Specifically, wet etching is continued on the back side of the substrate to remove the silicon oxide-based material in the cavity portion, so that the lower electrode pattern is exposed in the lower cavity, forming the final back cavity, and the back cavity is larger than the bottom electrode, and the bottom electrode is completely exposed on the back side. Figure 4 As shown in (k).

[0082] So far, the introduction of the method for preparing the MEMS dual-chip structure according to the embodiment of the present invention has been completed.

[0083] The third aspect of the present invention provides a MEMS piezoelectric microphone. In an exemplary embodiment of the present invention, the MEMS piezoelectric microphone includes: a MEMS dual-chip structure as in the above embodiment, wherein the lower electrode layer and the upper electrode layer are connected to the output end of the MEMS piezoelectric microphone; wherein the composite vibration layer vibrates by sensing sound waves, and the lower piezoelectric layer and the upper piezoelectric layer sense the electrical signals generated by the strain, and output them to the outside through the lower electrode layer and the upper electrode layer.

[0084] At this point, the various embodiments of the present invention have been introduced. According to the above description, those skilled in the art should have a clear understanding of the present invention.

[0085] It should be noted that, unless explicitly indicated to the contrary, the numerical parameters in the specification and claims of the present invention may be approximate values ​​and may be changed according to the content of the present invention. Specifically, all the numbers indicating the content of the composition, reaction conditions, etc. recorded in the specification and claims should be understood to be modified by the term "about" in all cases, and the meaning of the expression is to include a change of ±10% from a specific number in some embodiments.

[0086] The ordinal numbers used in the specification and claims, such as "first", "second", "third", "primary", "secondary", as well as Arabic numerals, letters, etc., to modify the corresponding elements (or steps), are intended only to make a component (or step) with a certain name clearly distinguishable from another component (or step) with the same name, and do not mean that the element (or step) has any ordinal number, nor do they represent the order of one element (or step) and another element (or step). At the same time, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design.

[0087] Those skilled in the art should understand that in the claims and description of the present invention, the word "comprising" does not exclude the existence of elements (or steps) not listed in the claims. The word "a" or "an" preceding an element (or step) does not exclude the existence of multiple such elements (or steps).

[0088] For certain implementations, if they are not the key content of the present invention and are well known to ordinary technicians in the relevant technical field, they are not described in detail in the drawings or text of the specification due to space limitations. In this case, reference can be made to relevant existing technologies for understanding.

[0089] Furthermore, the above embodiments are provided merely to enable the present invention to satisfy legal requirements, and the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0090] Similarly, it should be understood that in order to simplify the present invention, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the invention should not be interpreted as reflecting the following intention: the claimed invention requires more features than the features explicitly stated in each claim. More specifically, as reflected in the claims, each inventive aspect lies in less than all the features of the previous single embodiment. Moreover, the embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present invention.

[0091] The above specific embodiments provide a detailed description of the objectives, technical means and beneficial effects of the present invention. It should be understood that the purpose of the detailed description is to enable those skilled in the art to understand the present invention more clearly, and it is not used to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A MEMS dual-chip structure, characterized in that: include: The support structure includes: an outer ring body; a back cavity formed inside the outer ring body; The composite vibration layer, from bottom to top, includes: A lower piezoelectric layer is formed above the outer ring body and the back cavity; An intermediate layer is formed on the lower piezoelectric layer, comprising: an inner middle electrode layer and an outer second dielectric layer, wherein the upper and lower surfaces of the intermediate electrode and the second dielectric layer are flush; an upper piezoelectric layer formed above the middle layer; A lower electrode layer, formed below the lower piezoelectric layer; An upper electrode layer is formed above the upper piezoelectric layer.

2. The MEMS dual-chip structure according to claim 1, characterized in that: The lower piezoelectric layer and the upper piezoelectric layer are symmetrical about the middle layer; And / or, the lower electrode layer and the upper electrode layer are symmetrical with respect to the middle layer.

3. The MEMS dual-chip structure according to claim 2, characterized in that: The horizontal plane projections of the lower electrode layer, the middle electrode layer and the upper electrode layer overlap and all fall within the horizontal plane projection of the back cavity.

4. The MEMS dual-chip structure according to claim 1, characterized in that: The outer ring body comprises: Substrate outer ring body; A sacrificial layer outer ring body, formed above the substrate outer ring body; A first dielectric layer outer ring body is formed above the sacrificial layer outer ring body; The substrate outer ring body, the sacrificial layer outer ring body and the first dielectric layer outer ring body together surround the back cavity, and the lower electrode layer is exposed in the back cavity.

5. The MEMS dual-chip structure according to claim 4, characterized in that: The material of the substrate outer ring body is: silicon or silicon-based compound; And / or, the material of the sacrificial layer outer ring body and the second dielectric layer is: silicon oxide; And / or, the material of the lower piezoelectric layer and the upper piezoelectric layer is selected from one or more of the following materials: aluminum nitride, scandium-doped aluminum nitride, zinc oxide, lead zirconate titanate; And / or, the materials of the lower electrode layer, the middle electrode layer and the upper electrode layer are selected from one or more of the following materials: molybdenum, gold, aluminum, chromium, platinum, titanium, tungsten and titanium nitride.

6. A method for preparing a MEMS dual-chip structure, characterized in that: For preparing a MEMS dual-chip structure as claimed in any one of claims 1 to 4, the preparation method comprises: Step A, growing a sacrificial material film on a substrate, depositing an electrode film on the sacrificial material film, and patterning the electrode film to form a lower electrode layer; Step B, depositing a first dielectric film on the lower electrode layer and the sacrificial material film; Step C, planarizing the first dielectric film until the lower electrode layer is exposed, and the first dielectric film retained around the lower electrode layer forms a first dielectric layer; Step D, depositing a lower piezoelectric layer on the lower electrode layer and the first dielectric layer; Step E, depositing an electrode film on the lower piezoelectric layer, and patterning the electrode film to form a middle electrode layer; Step F, depositing a second dielectric film on the middle electrode layer and the lower piezoelectric layer; Step G, planarizing the second dielectric film until the middle electrode layer is exposed, and the second dielectric film retained outside the middle electrode layer forms a second dielectric layer; Step H, depositing an upper piezoelectric layer on the middle electrode layer and the second dielectric layer; Step I, depositing an electrode film on the upper piezoelectric layer, and patterning the electrode film to form an upper electrode layer; Step J, performing deep etching on the back side of the substrate to form a back side cavity on the inner side, exposing the sacrificial material film; Step K, continuing etching on the back side of the substrate to remove the sacrificial layer material and the first dielectric layer in the back side cavity, so that the lower electrode is exposed in the back side cavity to form a back side cavity.

7. The method for preparing a MEMS dual-chip structure according to claim 6, characterized in that: The thickness of the electrode film deposited in step B is H a The thickness of the first dielectric film in step C is H1, and the thickness of the lower electrode layer and the first dielectric layer after planarization in step D is H a ', then: H1≥1.1H a , 0.6H a ≤H a '≤0.9H a ; And / or, the thickness of the electrode film deposited in step F is H c The thickness of the second dielectric film in step G is H2, and the thickness of the electrode layer and the second dielectric layer after planarization in step H is H c ', then: H2≥1.1H c , 0.6H c ≤H c '≤0.9H c .

8. The method for preparing a MEMS dual-chip structure according to claim 7, characterized in that: The planarization in step C and step G is achieved by a CMP process.

9. The method for preparing a MEMS dual-chip structure according to claim 6, characterized in that: In the step J, a dry etching process is used to perform deep etching. In the step K, the etching is continued by using a wet etching process.

10. A MEMS piezoelectric microphone, characterized in that: include: The MEMS dual-chip structure according to any one of claims 1 to 5, wherein the lower electrode layer and the upper electrode layer are connected to an output end of the MEMS piezoelectric microphone; The composite vibration layer vibrates in response to sound waves, and the lower piezoelectric layer and the upper piezoelectric layer sense the electrical signals generated by the strain, which are output to the outside through the lower electrode layer and the upper electrode layer.

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