Multi-layer three-dimensional stacked circuit board and preparation method thereof

Abstract

The present invention discloses a multi-layer three-dimensional stacked circuit board and a method for preparing the same. The method specifically comprises: obtaining a single-sided conductive substrate, spraying a stress buffer layer on the conductive surface of the substrate; covering the stress buffer layer with an insulating material, and forming a patterned insulating layer by photolithography; performing pulse electroplating on the exposed patterned portion of the patterned insulating layer to obtain a first circuit board; silk-screening a flexible connection layer on the patterned pad layer of the first circuit board, and performing a three-dimensional stacking process on the flexible connection layer to obtain a second circuit board; assembling a circuit protection layer on the second circuit board, and machining a stress relief groove between the second circuit board and the circuit protection layer to obtain a multi-layer three-dimensional stacked circuit board. The design of the stress buffer layer and the stress relief groove can reduce interlayer stress, avoid circuit board breakage or cracking caused by excessive interlayer stress, and solve the technical problem of generating large interlayer stress during circuit board preparation in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board preparation, and in particular to a multi-layer three-dimensional stacked circuit board and a preparation method thereof. Background Art

[0002] As electronic devices become increasingly miniaturized and performant, demand for multi-layer, three-dimensional stacked circuit boards (PCBs) is increasing. These boards are a key technology in high-end electronic products, offering higher levels of integration and more compact designs. These boards are widely used in high-speed, high-frequency, and precision electronic devices such as smartphones, computers, and automotive electronics.

[0003] In the prior art, in a multi-layer, three-dimensional stacked circuit board structure, surface layers, signal layers, power layers, ground layers, and dielectric layers are alternately stacked and connected via through-holes, resulting in a three-dimensional circuit board with high density, high integration, and excellent electrical performance. However, during the preparation of these multi-layer, three-dimensional stacked circuit boards, significant interlayer stress is generated due to the varying thermal expansion coefficients of the materials in each layer and the temperature fluctuations involved in the production process. This interlayer stress not only affects the mechanical properties of the circuit board but can also cause electrical connection failure, thereby affecting the reliability of the entire electronic product. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-layer three-dimensional stacked circuit board and a preparation method thereof, which solves the technical problem of large interlayer stress generated during the preparation process of the circuit board in the prior art.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] According to a first aspect, the present invention discloses a method for preparing a multi-layer three-dimensional stacked circuit board, comprising: step S1, obtaining a single-sided conductive substrate, and spraying a stress buffer layer on the conductive surface of the substrate; the stress buffer layer is made of a polymer material;

[0007] Step S2, covering the stress buffer layer with a layer of insulating material and forming a patterned insulating layer by photolithography;

[0008] Step S3, performing pulse electroplating on the exposed pattern of the patterned insulating layer to obtain a first circuit board; wherein the first circuit board includes a substrate, a stress buffer layer and a patterned pad layer, and the patterned pad layer includes a patterned insulating layer and a low-stress metal pattern;

[0009] Step S4, screen-printing a flexible connection layer on the pattern pad layer of the first circuit board, and performing a three-dimensional stacking process on the flexible connection layer to obtain a second circuit board; the second circuit board includes the first circuit board, the flexible connection layer, and at least one stacked three-dimensional circuit layer;

[0010] Step S5: assembling a circuit protection layer on the second circuit board, and processing a stress relief groove between the second circuit board and the circuit protection layer to obtain a multi-layer three-dimensional stacked circuit board.

[0011] Optionally, step S1 includes:

[0012] Step S11, selecting an aluminum-based composite material or a copper-based composite material as a single-sided conductive substrate;

[0013] Step S12, performing surface activation treatment on the conductive surface of the substrate; the surface activation treatment includes ultrasonic cleaning treatment and plasma treatment;

[0014] Step S13, electrostatically spraying the substrate after surface activation treatment to obtain a stress buffer layer by gradient spraying;

[0015] Step S14, placing the electrostatically sprayed substrate in a curing furnace for segmented curing;

[0016] Step S15 , performing laser micro-etching on the fixed stress buffer layer to form a grid micro-structure on the surface of the stress buffer layer.

[0017] Optionally, step S12 includes:

[0018] Step S121, ultrasonically cleaning the substrate using a cleaning solution containing a surfactant for 5 to 15 minutes;

[0019] Step S122, after the ultrasonic cleaning of the substrate, rinsing the substrate with deionized water and drying it with nitrogen or hot air;

[0020] Step S123 , performing plasma treatment on the substrate after the drying treatment, wherein the plasma is any combination of oxygen, argon and nitrogen, and the treatment time is 30 seconds to 120 seconds.

[0021] Optionally, the stress buffer layer includes a first layer, a second layer, and a third layer sprayed sequentially, wherein the first layer is sprayed on the conductive surface of the substrate; and step S13 includes:

[0022] Step S131, placing the substrate in an electrostatic spraying device for initial spraying, wherein the spraying flow rate of the initial spraying stage is set to 5 mL / min to 15 mL / min, the spraying angle is 30° to 60°, and the first layer is sprayed to form a thin layer; the thickness of the first layer is 0.2 μm to 1 μm;

[0023] Step S132: After the first layer is formed, the intermediate spraying stage is entered, and the spraying flow rate is set to 15 mL / min to 30 mL / min, the spraying angle is 45° to 75°, and the second layer is sprayed to form a thickness of 1 μm to 7 μm.

[0024] Step S133, after obtaining the second layer, entering the later spraying stage, setting the spraying flow rate to 8 mL / min~20 mL / min, spraying to form a third layer, the thickness of the third layer is 0.5 μm~2 μm, and obtaining a stress buffer layer.

[0025] Optionally, after step S133, the method further includes:

[0026] Step S134 , placing the substrate sprayed with the stress buffer layer into a preheating zone for pre-curing treatment; wherein the pre-curing temperature is 60° C. to 80° C., and the pre-curing time is 5 min to 15 min.

[0027] Optionally, step S14 includes:

[0028] Step S141 , placing the substrate sprayed with the stress buffer layer in a curing furnace for preliminary curing treatment, with the preliminary curing temperature being 80° C. to 120° C. and the preliminary curing time being 10 min to 30 min;

[0029] Step S142 , performing deep curing treatment on the substrate sprayed with the stress buffer layer, wherein the deep curing temperature is 150° C. to 200° C., the deep curing time is 30 min to 60 min, and the heating rate is 2° C. / min to 5° C. / min;

[0030] Step S143 , after the stress buffer layer is deeply cured, the substrate is cooled until the temperature of the curing furnace is reduced to room temperature of 20° C. to 30° C., with a cooling rate of 1° C. / min to 5° C. / min.

[0031] Optionally, step S2 includes:

[0032] Step S21, coating a selected insulating material on the surface of the stress buffer layer; the insulating material is photoresist, epoxy resin or polyimide;

[0033] Step S22, pre-baking the coated insulating material, the pre-baking temperature is 90° C. to 120° C., and the pre-baking time is 10 min to 20 min;

[0034] Step S23, projecting the pattern onto the insulating material coating through a mask of an ultraviolet light exposure system, and removing the coating area not irradiated by the ultraviolet light from the exposed substrate through a developer;

[0035] Step S24 , performing hardening and baking on the exposed substrate to obtain a patterned insulating layer; wherein the hardening and baking temperature is 150° C. to 180° C., and the hardening and baking time is 20 min to 30 min.

[0036] Optionally, step S3 includes:

[0037] Step S31, setting the current of the pulse plating equipment, the pulse frequency is 0.5Hz to 5Hz;

[0038] Step S32, depositing the metal in the electroplating solution on the exposed pattern of the patterned insulating layer through a preset current pulse to form a patterned pad layer, thereby obtaining a first circuit board; the pH value of the electroplating solution is 4.5 to 5.5;

[0039] Step S33: performing deplating treatment on the first circuit board.

[0040] Optionally, step S4 includes:

[0041] Step S41: Selecting polyimide or silicone-based polymer material as a flexible connection layer material, screen-printing the flexible connection layer material onto the pattern pad layer of the first circuit board, and performing a preliminary shaping process on the coated flexible connection layer material; the preliminary shaping temperature is 80° C. to 100° C., and the preliminary shaping time is 3 to 5 minutes;

[0042] Step S42, covering the surface of the flexible connection layer with a photosensitive insulating medium, and preparing micropores by laser direct writing exposure technology;

[0043] Step S43, depositing a copper layer in the microhole to form a vertical conductive structure, and electroplating a copper circuit to obtain a three-dimensional circuit layer;

[0044] Step S44 , stacking the three-dimensional circuit layers through a hot pressing bonding process to obtain a second circuit board; the hot pressing temperature is 180° C. to 200° C., the pressure is 0.5 to 1.0 MPa, and the time is 30 seconds to 60 seconds.

[0045] According to a second aspect, the present invention discloses a multi-layer stereoscopic stacked circuit board, which is manufactured using the method for manufacturing a multi-layer stereoscopic stacked circuit board as described in the first aspect, comprising: a substrate, a stress buffer layer sprayed on a conductive surface of the substrate, the stress buffer layer being covered with a pattern pad layer, the pattern pad layer comprising a patterned insulating layer and a low-stress metal pattern;

[0046] Among them, a flexible connection layer is silk-screened on the pattern pad layer, and several three-dimensional circuit layers are stacked on the flexible connection layer. A circuit protection layer is assembled on the second circuit board, and a stress relief groove is processed between the three-dimensional circuit layer and the circuit protection layer.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] The present invention provides a multi-layer three-dimensional stacked circuit board and its preparation method, which uses polymer material spraying to form a stress buffer layer with good buffering performance, which helps to reduce the stress accumulation caused by the difference in thermal expansion coefficient between different layers and prevent interlayer separation. In addition, the provision of stress release grooves further disperses stress concentration, avoiding the breakage or cracking of the circuit board caused by excessive interlayer stress. By using a multi-layer three-dimensional circuit layer and a flexible connection layer, the circuit board can achieve a higher integration in a smaller volume, meeting the requirements of modern electronic equipment for miniaturization, high integration and diversified functions. By using a flexible connection layer, a multi-layer three-dimensional circuit layer and a circuit protection layer, the stability and durability of the circuit board during long-term use are significantly enhanced, especially in high temperature, high pressure or external force impact environments, the circuit board can still maintain high performance. Through fine lithography and pulse electroplating technology, the pattern formation and metal plating processing can be carried out with high precision, ensuring the consistency and reliability of the circuit board in different batches. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which the present invention can be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention.

[0051] Figure 1 The present invention is a flowchart of a method for preparing a multi-layer three-dimensional stacked circuit board disclosed in the first embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0053] In the description of the present invention, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the present invention and simplify the description. They are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0054] The technical solution of the present invention will be further described below with reference to the accompanying drawings and through specific implementation methods.

[0055] Example 1:

[0056] The embodiment of the present invention provides a method for preparing a multi-layer three-dimensional stacked circuit board, such as Figure 1 Shown, including:

[0057] Step S1, obtaining a single-sided conductive substrate, and spraying a stress buffer layer on the conductive surface of the substrate; the stress buffer layer is made of a polymer material;

[0058] Step S2, covering the stress buffer layer with a layer of insulating material and forming a patterned insulating layer by photolithography;

[0059] Step S3: performing pulse electroplating on the exposed pattern of the patterned insulating layer to obtain a first circuit board; wherein the first circuit board includes a substrate, a stress buffer layer, and a pattern pad layer, and the pattern pad layer includes a patterned insulating layer and a low-stress metal pattern; in this embodiment, the low-stress metal pattern uses a metal material with good mechanical properties and a low thermal expansion coefficient, such as copper-plated gold, nickel-chromium alloy, or other low-expansion alloy; the low-stress metal pattern can be drawn using computer-aided design (CAD) software, and the pattern can be transferred by photolithography;

[0060] Step S4, screen-printing a flexible connection layer on the pattern pad layer of the first circuit board, and performing a three-dimensional stacking process on the flexible connection layer to obtain a second circuit board; the second circuit board includes the first circuit board, the flexible connection layer, and at least one stacked three-dimensional circuit layer;

[0061] Step S5: assembling a circuit protection layer on the second circuit board, and processing a stress relief groove between the second circuit board and the circuit protection layer to obtain a multi-layer three-dimensional stacked circuit board.

[0062] It should be noted that the present invention provides a method for preparing a multi-layer three-dimensional stacked circuit board, which forms a stress buffer layer with good buffering performance by spraying a polymer material, thereby helping to reduce the stress accumulation caused by the difference in thermal expansion coefficient between different layers and prevent separation between layers. In addition, by setting the stress release groove, the stress concentration is further dispersed, and the circuit board breakage or cracking caused by excessive interlayer stress is avoided. By using a multi-layer three-dimensional circuit layer and a flexible connection layer, the circuit board can achieve a higher integration in a smaller volume, meeting the requirements of modern electronic equipment for miniaturization, high integration and diversified functions. By applying a flexible connection layer, a multi-layer three-dimensional circuit layer and a circuit protection layer, the stability and durability of the circuit board during long-term use are significantly enhanced, especially in high temperature, high pressure or external force impact environments, the circuit board can still maintain high performance. Through fine lithography and pulse electroplating technology, the pattern formation and metal plating processing can be carried out with high precision, ensuring the consistency and reliability of the circuit board in different batches.

[0063] In an optional embodiment, step S1 specifically includes:

[0064] In step S11, an aluminum-based composite material or a copper-based composite material is selected as a single-sided conductive substrate. In this embodiment, the aluminum-based composite material has a lower density, which helps reduce the weight of the entire circuit board and is particularly suitable for lightweight electronic products. The copper-based composite material has excellent thermal conductivity, which can effectively reduce the heat generated during operation and help improve the thermal stability of the circuit board in high-frequency and high-power environments.

[0065] Step S12, performing surface activation treatment on the conductive surface of the substrate; the surface activation treatment includes ultrasonic cleaning treatment and plasma treatment;

[0066] In step S13, the surface-activated substrate is electrostatically sprayed to form a stress buffer layer using a gradient spraying method. In practice, electrostatic spraying ensures uniform adhesion of the stress buffer material to the substrate surface, avoiding performance inconsistencies caused by uneven coatings. By controlling the thickness and density of different layers through gradient spraying, the stress buffer layer can better absorb and disperse stress, reducing interlayer stress caused by differences in thermal expansion coefficients, thereby improving the stability and compressive strength of the multi-layer stacked circuit board.

[0067] In step S14, the electrostatically sprayed substrate is placed in a curing furnace for segmented curing. In this embodiment, the segmented curing process ensures that the sprayed solvent evaporates gradually, avoiding bubbles, defects, and uneven coating. It also reduces stress accumulation in the stress buffer layer, avoids cracking or interlayer delamination of the stress buffer layer, and improves the uniformity and stability of the entire stress buffer layer.

[0068] In step S15, the immobilized stress buffer layer is laser micro-etched to form a grid microstructure on the surface of the stress buffer layer. In the specific implementation process, high-precision laser equipment is selected for laser micro-etching, such as a CO2 laser or a fiber laser. The laser wavelength of the CO2 laser is 10.6μm and the laser wavelength of the fiber laser is 1μm to ensure accurate etching effect on the surface of the polymer material. According to the material and micro-etching requirements, the laser power is set to 10W~50W and the pulse frequency is set to 20kHz~50kHz to ensure that the etching depth and the clarity of the microstructure can be accurately controlled.

[0069] Specifically, the laser scanning speed is 100mm / s~500mm / s. During each laser scan, the etching depth is controlled between 0.2μm~1μm according to the required depth requirement of the grid microstructure to ensure the stability of the grid microstructure and not affect the overall performance of the coating.

[0070] It should be noted that the combination of surface activation treatment and gradient spraying significantly improves the adhesion between the stress buffer and the substrate, avoiding the risk of stress buffer shedding or peeling. Through electrostatic spraying and segmented curing treatment, stress concentration within the stress buffer layer is effectively reduced, enabling the stress buffer layer to better absorb and disperse the forces generated by thermal expansion or mechanical stress, thereby improving the reliability of multi-layer three-dimensional stacked circuit boards. The grid microstructure formed by laser micro-etching enhances the stability, wear resistance, and impact resistance of the stress buffer layer, allowing the circuit board to maintain high performance during long-term use.

[0071] In an optional embodiment, step S12 specifically includes:

[0072] In step S121, the substrate is ultrasonically cleaned using a cleaning solution containing a surfactant for a cleaning time of 5 to 15 minutes. In this embodiment, a common ultrasonic cleaning machine in the art is used, and its working principle is not described in detail here. The frequency is set in the range of 40 kHz to 120 kHz, and the surfactant is isopropyl alcohol, acetone, or citric acid solution.

[0073] In step S122, after the ultrasonic cleaning treatment of the substrate, the substrate is rinsed with deionized water and dried with nitrogen or hot air. In this embodiment, the substrate is rinsed in a deionized water rinsing tank to completely remove the surfactants and chemicals in the cleaning solution, thereby preventing the surfactants and chemicals from interfering with the subsequent stress buffer layer and plasma treatment.

[0074] In step S123 , the dried substrate is subjected to plasma treatment, wherein the plasma is any combination of oxygen, argon and nitrogen, and the treatment time is 30 seconds to 120 seconds.

[0075] It should be noted that plasma treatment effectively removes residual contaminants, oxide layers, and organic matter from the substrate surface. It also alters the substrate's surface chemistry, making it more hydrophilic and providing good adhesion for the subsequent stress buffer layer. Ultrasonic cleaning and deionized water rinsing thoroughly remove surface contaminants, ensuring surface cleanliness and uniformity, which provides a foundation for uniform coating and long-term stability of the stress buffer layer.

[0076] In an optional embodiment, the stress buffer layer includes a first layer, a second layer, and a third layer sprayed sequentially, wherein the first layer is sprayed on the conductive surface of the substrate; step S13 includes:

[0077] In step S131, the substrate is placed in an electrostatic spraying device for initial spraying. The spraying flow rate of the initial spraying stage is set to 5 mL / min~15 mL / min, the spraying angle is 30°~60°, and the first layer of the thin layer is sprayed; the thickness of the first layer is 0.2 μm~1 μm; in this embodiment, the electrostatic spraying equipment is a common equipment in this field, and its working principle is not repeated here; the first layer, as the thinnest layer, can be tightly adhered to the surface of the substrate, effectively eliminating the initial stress caused by the thermal expansion difference between the substrate and the coating; due to the thin layer characteristics of the first layer, the metal in step S32 can start to be deposited faster, and a preliminary electroplating structure is established.

[0078] Step S132, after obtaining the first layer, enter the mid-term spraying stage, set the spraying flow rate to 15mL / min~30mL / min, the spraying angle to 45°~75°, and spray to form the second layer; the thickness of the second layer is 1μm~7μm; in this embodiment, the thicker design of the second layer increases the overall buffering capacity and can effectively absorb stress changes caused by external forces or thermal expansion; the second layer has a moderate thickness, so that the electroplating solution of step S32 can penetrate better and is not easily blocked, thereby achieving higher biocompatibility and better metal deposition quality.

[0079] Step S133, after obtaining the second layer, enters the post-spraying stage, sets the spraying flow rate to 8mL / min~20mL / min, and sprays to form a third layer with a thickness of 0.5μm~2μm, thereby obtaining a stress buffer layer. In this embodiment, the third layer serves as the outermost layer, further uniformly distributing the stress and preventing the impact of internal stress on the overall structure. The third layer has an appropriate thickness, which can further enhance the coverage of the electroplating layer in step S32 and reduce cracks or peeling that may occur during the electroplating process.

[0080] It should be noted that by using a phased spraying method to form a stress buffer layer layer by layer, this process significantly improves the uniformity, adhesion, buffering performance and mechanical strength of the coating. Each layer is controlled by different spray flow rates, spray angles and coating thicknesses. The layer-by-layer spraying optimizes the bonding strength between the stress buffer layer and the substrate, effectively preventing peeling or shedding. The layered design can better disperse stress, avoid stress concentration or crack formation between layers, and effectively enhance the coating's compressive, impact and wear resistance. The smooth and uniform surface improves the adaptability of subsequent processes.

[0081] After step S133, the method further includes:

[0082] In step S134, the substrate coated with the stress buffer layer is placed in a preheating zone for pre-curing. The pre-curing temperature is 60°C to 80°C, and the pre-curing time is 5 to 15 minutes. In this embodiment, the pre-curing time can be fine-tuned based on the actual coating thickness and the volatilization rate of the material. Keeping the pre-curing temperature within a low range effectively prevents changes in the coating's fluidity during initial heating and maintains coating uniformity.

[0083] It's important to note that the pre-curing process helps gradually remove solvent from the coating, preventing bubbles and uneven coating during subsequent curing. Pre-curing also facilitates initial cross-linking of the first, second, and third layers, imparting mechanical strength and stability to the stress buffer layer, thereby maintaining a good structure during subsequent processes such as deep curing and laser micro-etching.

[0084] In an optional embodiment, step S14 includes:

[0085] Step S141 , placing the substrate sprayed with the stress buffer layer in a curing furnace for preliminary curing treatment, with the preliminary curing temperature being 80° C. to 120° C. and the preliminary curing time being 10 min to 30 min;

[0086] Step S142 , performing deep curing treatment on the substrate sprayed with the stress buffer layer, wherein the deep curing temperature is 150° C. to 200° C., the deep curing time is 30 min to 60 min, and the heating rate is 2° C. / min to 5° C. / min;

[0087] Step S143 , after the stress buffer layer is deeply cured, the substrate is cooled until the temperature of the curing furnace is reduced to room temperature of 20° C. to 30° C., with a cooling rate of 1° C. / min to 5° C. / min.

[0088] It should be noted that through a multi-stage approach of initial curing, deep curing, and cooling treatment, the stress buffer layer is ensured to gradually transition to a stable state under different temperature conditions, thereby improving the uniformity, durability, and thermal shock resistance of the stress buffer layer. The adhesion, hardness, and wear resistance of the stress buffer layer have been significantly improved, and it can effectively adapt to the use requirements of electronic equipment in complex environments such as high temperature, humidity changes, and mechanical shock. This multi-stage curing method provides a solid physical foundation for multi-layer three-dimensional stacked circuit boards, greatly enhancing the reliability and durability of the circuit boards in various environments, and meeting the high reliability and high performance requirements of modern electronic products.

[0089] In an optional embodiment, step S2 includes:

[0090] Step S21: Coating the surface of the stress buffer layer with a selected insulating material; the insulating material can be photoresist, epoxy resin, or polyimide. The epoxy resin is selected to ensure photolithographic and thermal performance, while the polyimide is selected to achieve excellent electrical insulation. This is done using a spin coating process commonly used in the art, with a spin coating time of 30 to 60 seconds and a coating thickness of 2 to 20 μm.

[0091] In step S22, the coated insulating material is pre-baked at a temperature of 90°C to 120°C for a time of 10 to 20 minutes. The pre-baking step can remove the solvent in the coating, enhance the adhesion of the film layer, and provide better optical properties for the subsequent exposure step.

[0092] In step S23, the pattern is projected onto the insulating material coating through the mask of the ultraviolet exposure system, and the exposed substrate is subjected to a developer to remove the coating area not irradiated by the ultraviolet light. In this embodiment, the ultraviolet exposure system uses an ultraviolet exposure machine with an ultraviolet light wavelength of 365nm, an exposure time of 5 seconds to 60 seconds, and a power density of 100mW / cm 2 Up to 1000mW / cm 2 .

[0093] In step S24, the exposed substrate is hardened and baked to form a patterned insulating layer. The hardening bake temperature is 150°C to 180°C, and the hardening bake time is 20 minutes to 30 minutes. Step S24 further crosslinks and solidifies the insulating material to improve its heat resistance, mechanical properties, and chemical stability, thereby obtaining a high-resolution, high-adhesion patterned insulating layer.

[0094] It should be noted that the use of high-performance insulating materials ensures that the resulting insulating layer possesses excellent electrical insulation properties, meeting the requirements of high-frequency, high-voltage applications. The pre-bake process effectively removes bubbles and solvents, improving adhesion between the insulating layer and the stress buffer layer and reducing the risk of delamination during subsequent use. The hardened and baked insulating layer not only exhibits excellent heat resistance but also high mechanical strength, ensuring long-term stability under operating conditions. Precise exposure and development ensure that the pattern of the insulating layer has excellent clarity and edge sharpness, suitable for the needs of high-precision microelectronic devices.

[0095] In an optional embodiment, step S3 includes:

[0096] Step S31, set the current of the pulse plating equipment, the pulse frequency is 0.5Hz to 5Hz; in the specific implementation process, the time ratio of high current and low current can be adjusted according to the design requirements, and the high pulse current density is 5A / dm 2 Up to 30A / dm 2 , high current pulse time is 10ms to 100ms; low pulse current density is 0.5A / dm 2 Up to 5A / dm 2 , low current pulse time is 50ms to 500ms. For copper electroplating, set the high current pulse time to 50ms and the low current pulse time to 200ms.

[0097] In step S32, the metal in the electroplating solution is deposited on the exposed pattern of the patterned insulating layer through a preset current pulse to form a patterned pad layer, and a first circuit board is obtained; the pH value of the electroplating solution is 4.5 to 5.5; the deposition time is 5 minutes to 30 minutes, and the main components of the electroplating solution are copper sulfate and sulfuric acid; in order to improve the gloss and uniformity of the deposition, polyvinyl alcohol can be added to the electroplating solution; in order to reduce bubbles and improve the deposition quality, a surfactant such as hexadecyltrimethylammonium bromide can be added.

[0098] Step S33 deplating the first circuit board. In this specific implementation, the first circuit board is removed and gently shaken to remove excess plating solution from the surface. An appropriate chemical (such as dilute sulfuric acid or ammonia) is then used to clean the first circuit board to remove any undeposited metal and dirt. After cleaning, the first circuit board is thoroughly rinsed with deionized water to ensure no chemical residue remains. The cleaned substrate is then dried under dry conditions to obtain the desired first circuit board. The cleaning and drying procedures in step S33 are common techniques in the art, and the specific operating conditions are not detailed here.

[0099] It should be noted that by precisely controlling the current and pulse frequency, the uniformity and consistency of metal deposition on the patterned insulating layer are effectively improved, ensuring the electrical properties and good conductivity of the patterned pad layer. The use of low-stress metal material deposition can reduce the internal stress of the patterned pad layer while maintaining conductive properties, reduce the risk of breakage and peeling, and improve the mechanical stability of the first circuit board. Through stripping treatment, undeposited metal and chemical residues can be effectively removed to ensure the purity and electrical properties of the product while reducing the risk of environmental pollution. This pulse plating solution can be flexibly adapted to different materials and plating solution formulas, and can meet the diverse needs of multi-layer three-dimensional stacked circuit boards.

[0100] In an optional embodiment, step S4 includes:

[0101] Step S41: Selecting polyimide or silicone-based polymer material as the flexible connection layer material, screen-printing the flexible connection layer material onto the pattern pad layer of the first circuit board, and performing a preliminary shaping process on the coated flexible connection layer material; the preliminary shaping temperature is 80°C to 100°C, and the preliminary shaping time is 3 minutes to 5 minutes; the thickness of the flexible connection layer is 5 to 20 μm; the screen printing technology is common in the art and will not be described in detail here;

[0102] In step S42, the surface of the flexible connection layer is coated with a photosensitive insulating medium and micropores are formed using laser direct writing exposure technology. In this embodiment, the photosensitive insulating medium is a photosensitive polymer, such as a photosensitive resin. The micropores have a diameter of less than 20 μm. A UV laser with a wavelength of 355 nm is used, with an exposure power of 10 to 200 mW and an exposure time of 3 to 10 seconds.

[0103] In step S43, a copper layer is chemically deposited within the micropores to form a vertical conductive structure. Copper circuits are simultaneously electroplated to produce a three-dimensional circuit layer. In this embodiment, the vertical conductive structure is three-dimensionally interconnected with the low-stress metal pattern, thereby achieving complete electrical conductivity. The electroless plating solution for the copper layer is 5-20 g / L CuSO4 (copper sulfate) or CuCl2 (copper chloride), and the deposition time is 15-30 minutes. The copper layer thickness is 1-5 μm. The electroplating solution for the copper circuits is 15-30 g / L CuSO4 or CuCl2. The electroplating current density is 1.5-2.5 A / dm², and the pulse frequency is 50-100 Hz. The electroless deposition and electroplating processes are common techniques in the art, and their operating principles are not detailed here.

[0104] In step S44, the three-dimensional circuit layers are stacked using a hot pressing process to obtain a second circuit board. The hot pressing process is performed at a temperature of 180°C to 200°C, a pressure of 0.5 MPa to 1.0 MPa, and a time of 30 to 60 seconds. In this embodiment, the hot pressing process is a common technique in the art, and its working principle is not further described here.

[0105] It should be noted that the use of polyimide or silicone-based polymer materials as flexible connection layers ensures that the final circuit board has excellent thermal stability and physical strength, enabling the circuit board to operate stably for a long time under dynamic loads and environmental changes. The use of laser direct writing technology to prepare micropores allows greater flexibility in the arrangement and shape of the micropores, meeting the design requirements of complex circuits. The three-dimensional circuit layers are stacked through a thermal compression bonding process to quickly achieve physical adhesion and electrical conductivity between layers.

[0106] After step S44, the method further includes:

[0107] In step S45, steps S41, S42, S43, and S44 are repeated according to the number of layers of the three-dimensional circuit board to obtain a second circuit board with multiple layers of three-dimensional circuit layers. In this embodiment, step S45 can be processed according to the processing requirements of the circuit board; the circuit board with multiple layers of three-dimensional circuit layers can be processed to meet actual product requirements.

[0108] Specifically, step S5 includes:

[0109] Step S51, select polyimide (PI) or epoxy resin as the protective material, spray the protective material on the second circuit board, and cure it through ultraviolet light to obtain a circuit protection layer; in this embodiment, polyimide is suitable for high-end flexible circuits, and epoxy resin is suitable for rigid-flexible structures. The protective material is prepared in the form of a solution or slurry, and an appropriate amount of diluent is added to optimize fluidity. Use common spraying equipment in this field to evenly apply the protective material to ensure that a uniform covering layer is formed on the surface of the circuit board. The thickness of the circuit protection layer is 5~50μm. After spraying is completed, ultraviolet light (UV) is used for curing, with a wavelength of 365nm~405nm and an energy density of 800~1500mJ / cm 2 , the curing time is 20~60 seconds.

[0110] In step S52, a stress release groove is laser-etched between the second circuit board and the circuit protection layer to obtain a multi-layer three-dimensional stacked circuit board with high performance. In this embodiment, a UV laser etching device commonly used in the field is used to process the stress release groove. The laser wavelength is 355nm and the scanning speed is 100~300mm / s. The depth of the stress release groove is 10~30μm and the width of the stress release groove is 50~200μm. The stress release groove is distributed in a grid, line or dot matrix to release stress evenly. The grid-shaped stress release groove is suitable for large-area circuit areas to evenly disperse stress. The linear stress release groove is suitable for high-density wiring areas to avoid excessive local stress concentration. The dot matrix stress release groove is suitable for precision device connection areas to reduce local rigidity and improve flexible durability.

[0111] It should be noted that the design of the circuit protection layer enhances overall mechanical strength, effectively preventing the effects of moisture, dust, and chemical corrosion on the circuit, and improving the long-term stability of the product. Laser-etched stress relief grooves can reduce stress concentration between multilayer structures, improve thermal shock resistance, and enable the circuit board to adapt to a wider range of temperature variations. The use of spray coating and UV curing can quickly form the protective layer, avoiding the long baking required by traditional thermal curing and improving production efficiency. Due to the precise laser etching process, stress relief grooves can be processed in batches, avoiding damage to the circuit board caused by mechanical processing and improving product consistency.

[0112] Example 2:

[0113] An embodiment of the present invention provides a multi-layer three-dimensional stacked circuit board, which is manufactured using the method for manufacturing a multi-layer three-dimensional stacked circuit board as described in Example 1, comprising: a substrate, a stress buffer layer sprayed on a conductive surface of the substrate, the stress buffer layer being covered with a pattern pad layer, the pattern pad layer including a patterned insulating layer and a low-stress metal pattern;

[0114] A flexible connection layer is silkscreened on the pattern pad layer, upon which several three-dimensional circuit layers are stacked. A circuit protection layer is mounted on the second circuit board, with stress relief grooves machined between the three-dimensional circuit layers. In this embodiment, stacking multiple three-dimensional circuit layers achieves a higher level of functional integration, improving the circuit board's signal processing capabilities and transmission efficiency while also providing greater flexibility for complex circuit design.

[0115] It should be noted that by spraying a stress buffer layer on the conductive surface of the substrate, the internal stress caused by temperature changes and mechanical stress can be effectively absorbed and dispersed, reducing the risk of damage to the circuit board due to deformation or bending. The silk-screened flexible connection layer provides a certain degree of elasticity, allowing the circuit board to adapt to complex shapes and deformation under external forces during use, increasing overall durability. The low-stress metal pattern used in the pattern pad layer can ensure the reliability of the solder joints under thermal cycles and mechanical stress; reduce welding defects and improve the stability of the overall electrical connection. The stress relief groove can effectively alleviate the thermal expansion stress caused by temperature changes, reduce heat-induced failures such as delamination, cracking and welding failure, and enable the circuit to maintain stability during long-term operation.

[0116] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a multi-layer three-dimensional stacked circuit board, characterized in that: include: Step S1: obtaining a single-sided conductive substrate, and forming a stress buffer layer on the conductive surface of the substrate by a gradient electrostatic spraying process; the stress buffer layer is made of a polymer elastic material; the surface of the stress buffer layer has a grid microstructure formed by laser microetching, and the depth of the grid microstructure is 0.2 μm to 1 μm; the stress buffer layer includes a first layer, a second layer, and a third layer sprayed in sequence, the first layer being sprayed on the conductive surface of the substrate; the thickness of the first layer is 0.2 μm to 1 μm; the thickness of the second layer is 1 μm to 7 μm; and the thickness of the third layer is 0.5 μm to 2 μm. Step S2, covering the stress buffer layer with a layer of insulating material and forming a patterned insulating layer by photolithography; Step S3, performing pulse electroplating on the exposed pattern of the patterned insulating layer, with a pulse frequency of 0.5 Hz to 5 Hz and a plating solution pH of 4.5 to 5.5, to obtain a first circuit board; wherein the first circuit board includes a substrate, a stress buffer layer, and a pattern pad layer, and the pattern pad layer includes a patterned insulating layer and a low-stress metal pattern; Step S4, screen-printing a flexible connection layer on the pattern pad layer of the first circuit board, and performing a three-dimensional stacking process on the flexible connection layer to obtain a second circuit board; the second circuit board includes the first circuit board, the flexible connection layer, and at least one stacked three-dimensional circuit layer; Step S5: assemble a circuit protection layer on the second circuit board, and laser-etch a grid-shaped stress relief groove between the second circuit board and the circuit protection layer to obtain a multi-layer three-dimensional stacked circuit board; the depth of the stress relief groove is 10~30μm, and the width of the stress relief groove is 50~200μm.

2. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 1, wherein: The step S1 comprises: Step S11, selecting an aluminum-based composite material or a copper-based composite material as a single-sided conductive substrate; Step S12, performing surface activation treatment on the conductive surface of the substrate; the surface activation treatment includes ultrasonic cleaning treatment and plasma treatment; Step S13, electrostatically spraying the substrate after surface activation treatment to obtain a stress buffer layer by gradient spraying; Step S14, placing the electrostatically sprayed substrate in a curing furnace for segmented curing; Step S15 , performing laser micro-etching on the fixed stress buffer layer to form a grid micro-structure on the surface of the stress buffer layer.

3. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 2, wherein: The step S12 includes: Step S121, ultrasonically cleaning the substrate using a cleaning solution containing a surfactant for 5 to 15 minutes; Step S122, after the ultrasonic cleaning of the substrate, rinsing the substrate with deionized water and drying it with nitrogen or hot air; Step S123 , performing plasma treatment on the substrate after the drying treatment, wherein the plasma is any combination of oxygen, argon and nitrogen, and the treatment time is 30 seconds to 120 seconds.

4. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 2, wherein: The step S13 includes: Step S131, placing the substrate in an electrostatic spraying device for initial spraying, wherein the spraying flow rate of the initial spraying stage is set to 5 mL / min to 15 mL / min, the spraying angle is 30° to 60°, and the first layer of the thin layer is sprayed; Step S132, after the first layer is obtained, the mid-term spraying stage is entered, the spraying flow rate is set to 15 mL / min to 30 mL / min, the spraying angle is 45° to 75°, and the second layer is sprayed; Step S133 , after the second layer is obtained, the subsequent spraying stage is entered, the spraying flow rate is set to 8 mL / min to 20 mL / min, and the third layer is sprayed to obtain a stress buffer layer.

5. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 4, characterized in that: After step S133, the method further includes: Step S134 , placing the substrate sprayed with the stress buffer layer into a preheating zone for pre-curing treatment; wherein the pre-curing temperature is 60° C. to 80° C., and the pre-curing time is 5 min to 15 min.

6. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 2, wherein: The step S14 includes: Step S141 , placing the substrate sprayed with the stress buffer layer in a curing furnace for preliminary curing treatment, with the preliminary curing temperature being 80° C. to 120° C. and the preliminary curing time being 10 min to 30 min; Step S142 , performing deep curing treatment on the substrate sprayed with the stress buffer layer, wherein the deep curing temperature is 150° C. to 200° C., the deep curing time is 30 min to 60 min, and the heating rate is 2° C. / min to 5° C. / min; Step S143 , after the stress buffer layer is deeply cured, the substrate is cooled until the temperature of the curing furnace is reduced to room temperature of 20° C. to 30° C., with a cooling rate of 1° C. / min to 5° C. / min.

7. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 1, wherein: The step S2 comprises: Step S21, coating a selected insulating material on the surface of the stress buffer layer; the insulating material is photoresist, epoxy resin or polyimide; Step S22, pre-baking the coated insulating material, the pre-baking temperature is 90° C. to 120° C., and the pre-baking time is 10 min to 20 min; Step S23, projecting the pattern onto the insulating material coating through a mask of an ultraviolet light exposure system, and removing the coating area not irradiated by the ultraviolet light from the exposed substrate through a developer; Step S24 , performing hardening and baking on the exposed substrate to obtain a patterned insulating layer; wherein the hardening and baking temperature is 150° C. to 180° C., and the hardening and baking time is 20 min to 30 min.

8. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 1, wherein: The step S3 comprises: Step S31, setting the current of the pulse plating equipment, the pulse frequency is 0.5Hz to 5Hz; Step S32, depositing the metal in the electroplating solution on the exposed pattern of the patterned insulating layer through a preset current pulse to form a patterned pad layer, thereby obtaining a first circuit board; the pH value of the electroplating solution is 4.5 to 5.5; Step S33: performing deplating treatment on the first circuit board.

9. The method for preparing a multi-layer three-dimensional stacked circuit board according to claim 1, wherein: The step S4 comprises: Step S41: Selecting polyimide or silicone-based polymer material as a flexible connection layer material, screen-printing the flexible connection layer material onto the pattern pad layer of the first circuit board, and performing a preliminary shaping process on the coated flexible connection layer material; the preliminary shaping temperature is 80° C. to 100° C., and the preliminary shaping time is 3 to 5 minutes; Step S42, covering the surface of the flexible connection layer with a photosensitive insulating medium, and preparing micropores by laser direct writing exposure technology; Step S43, depositing a copper layer in the microhole to form a vertical conductive structure, and electroplating a copper circuit to obtain a three-dimensional circuit layer; Step S44 , stacking the three-dimensional circuit layers through a hot pressing bonding process to obtain a second circuit board; the hot pressing temperature is 180° C. to 200° C., the pressure is 0.5 to 1.0 MPa, and the time is 30 seconds to 60 seconds.

10. A multi-layer stereoscopic stacked circuit board, produced by the method for producing a multi-layer stereoscopic stacked circuit board according to any one of claims 1 to 9, characterized in that: include: A substrate, wherein a stress buffer layer is sprayed on the conductive surface of the substrate, the stress buffer layer is covered with a pattern pad layer, the pattern pad layer includes a pattern insulation layer and a low-stress metal pattern; the surface of the stress buffer layer has a grid microstructure formed by laser microetching, and the depth of the grid microstructure is 0.2μm to 1μm; the stress buffer layer includes a first layer, a second layer, and a third layer sprayed in sequence, the first layer is sprayed on the conductive surface of the substrate; the thickness of the first layer is 0.2μm to 1μm; the thickness of the second layer is 1μm to 7μm; and the thickness of the third layer is 0.5μm to 2μm; Among them, a flexible connection layer is silk-screened on the pattern pad layer, and several three-dimensional circuit layers are stacked on the flexible connection layer. A circuit protection layer is assembled on the second circuit board, and a grid-shaped stress relief groove is processed between the three-dimensional circuit layer and the circuit protection layer.

Images