Memcapacitor, preparation method, neural network parallel computing chip and application method of neural network parallel computing chip

Abstract

The invention discloses a memcapacitor, a preparation method, a neural network parallel computing chip and an application method of the neural network parallel computing chip. The memcapacitor comprises a top gate electrode, a top dielectric layer, a shielding layer and a readout electrode which are sequentially arranged from top to bottom. Wherein the top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode is provided with an input end connected with an external input circuit; the top dielectric layer covers a partial region of the upper surface of the shielding layer; the shielding layer is located between the top dielectric layer and the readout electrode, and the lower surface of the shielding layer completely covers the upper surface of the readout electrode; and the lower surface of the reading electrode is provided with an output end electrically connected with an external output circuit. The invention relates to the technical field of semiconductors. The shielding layer is introduced between the electrodes, and capacitance change in a high dynamic range is realized by utilizing a charge shielding effect, so that power consumption is remarkably reduced while high precision is kept.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically to a memory container, a preparation method, a neural network parallel computing chip and an application method thereof. Background Art

[0002] With the rapid development of artificial intelligence technology, data-intensive computing operations such as training neural networks are crucial in artificial intelligence applications, but they are also accompanied by huge energy consumption problems. Traditional computer architectures often require a lot of energy consumption when performing these computing tasks, limiting the further development of artificial intelligence technology.

[0003] To solve this problem, researchers proposed the concept of neuromorphic computing. Neuromorphic computing is a computing paradigm that simulates the structure and function of human brain neuron networks. It realizes information processing by simulating the connection and signal transmission process between neurons. Compared with traditional computer architecture, neuromorphic computing has higher computing efficiency and lower energy consumption, so it is considered to be an important direction for the future development of artificial intelligence.

[0004] However, the existing neuromorphic computing technology solutions mainly include memristors. Memristors are a new type of electronic device with nonlinear resistance characteristics. They can simulate the plasticity of synapses and are therefore widely used in neuromorphic computing. Memristors can be used to build cross-array structures, and the storage and update of synaptic weights can be achieved by changing the resistance value at the intersection. However, memristors still have some limitations, such as high energy consumption and poor scalability.

[0005] Therefore, providing new ideas for the development of neuromorphic computing technology in order to solve at least one of the above-mentioned technical problems is an issue that technical personnel in this field urgently need to solve. Summary of the invention

[0006] In view of this, the present invention provides a memcapacitor, a preparation method, a neural network parallel computing chip and an application method thereof. The memcapacitor uses the charge shielding principle to control the capacitance value by adjusting the shielding effect of the shielding layer on the electric field to achieve multiplication and accumulation operations.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a memcapacitor, comprising: a top gate electrode, a top dielectric layer, a shielding layer, and a readout electrode arranged in sequence from top to bottom;

[0009] in:

[0010] The top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input terminal connected to an external input circuit;

[0011] The top dielectric layer covers a portion of the upper surface of the shielding layer;

[0012] The shielding layer is located between the top dielectric layer and the readout electrode, and the lower surface of the shielding layer completely covers the upper surface of the readout electrode;

[0013] The bottom surface of the readout electrode has an output terminal electrically connected to an external output circuit.

[0014] Furthermore, the top dielectric layer is made of high-k material hafnium-zirconium co-doped oxide.

[0015] Furthermore, the top gate electrode is made of titanium nitride material.

[0016] Furthermore, the shielding layer is made of SiO2 material;

[0017] The shielding layer includes one side of p + doped region, formed by implanting boron ions; the other side includes n + Doped regions are formed by implanting phosphorus ions.

[0018] In a second aspect, the present invention provides a neural network parallel computing chip, comprising a plurality of memcapacitors as described in any one of the first aspects; the plurality of memcapacitors are arranged in horizontal and vertical directions respectively to form a crossbar switch array;

[0019] Among them, in all the memory containers:

[0020] The top gate electrode is used as a word line to receive input signals; the shielding layer is used as a shielding line, which is perpendicular to the word line, dynamically adjusts the electric field shielding efficiency, and controls the capacitance value of the memcapporat; the readout electrode is used as a bit line, which is parallel to the shielding line, and is used to output parallel calculation results.

[0021] In a third aspect, the present invention provides an application method of a neural network parallel computing chip as described in the second aspect, characterized in that highly parallel multiplication and accumulation calculations are performed in image classification or recognition scenarios;

[0022] The highly parallel multiplication-accumulation calculation includes differential weight operation and four-quadrant multiplication.

[0023] Furthermore, the differential weight calculation specifically includes:

[0024] The positive or negative weight of the memory container is stored in two storage units respectively, and the bit lines of the storage units are divided into positive bit lines and negative bit lines according to the positive and negative values ​​of the storage weights;

[0025] When the weight is greater than 0, the charge value is written into the memcapacitor corresponding to the positive bit line, and the memcapacitor corresponding to the negative bit line remains zero;

[0026] When the weight is less than 0, the charge value is written into the memcapacitor corresponding to the negative bit line, and the memcapacitor corresponding to the positive bit line remains at zero;

[0027] The charge values ​​of the positive bit line and the negative bit line are subtracted to obtain a weighted calculation result.

[0028] Furthermore, the four-quadrant multiplication specifically includes:

[0029] Using clock signals to control the switched capacitor circuit and adjust the connection mode of the capacitor;

[0030] In the clock high level stage, when the product of the input signal and the weight is greater than 0, the positive bit line is grounded and the negative bit line is connected to the integral capacitor amplifier; when the product of the input signal and the weight is less than 0, the negative bit line is grounded and the positive bit line is connected to the integral capacitor amplifier;

[0031] The charge difference is accumulated through the integrating capacitor amplifier to obtain the accumulated product of the input signal and the weight.

[0032] In a fourth aspect, the present invention provides a method for preparing a memory container as described in any one of the first aspects, comprising the following steps:

[0033] S1, preparing a composite substrate; the composite substrate is divided into a device layer, a buried oxide layer, a P-doped epitaxial layer and an epitaxial layer from top to bottom;

[0034] S2, pre-etching alignment marks on the upper surface of the device layer, and forming p + Doped regions and n + a doped region, which acts as a shielding layer;

[0035] S3, performing oxidation treatment on the upper surface of the device layer to prepare a top dielectric layer, and covering it with a titanium nitride capping layer as a top gate electrode;

[0036] S4, preparing a first metallization layer in the top dielectric layer by sputtering deposition; and longitudinally penetrating the P-doped epitaxial layer by etching according to the alignment mark to form two deep trenches, and using the P-doped epitaxial layer between the two deep trenches as a readout electrode.

[0037] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a memory container, a preparation method, a neural network parallel computing chip and an application method thereof, which have at least the following beneficial effects:

[0038] 1. The present invention introduces a shielding layer between electrodes and utilizes the charge shielding effect to achieve capacitance changes in a high dynamic range, thereby achieving high precision; at the same time, the memristor device can operate at a lower voltage, reducing energy consumption.

[0039] 2. The present invention organizes the memory container into a cross array structure, which can realize highly parallel multiplication and accumulation operations. The input signal is applied to the word line, the shielding layer serves as the shielding line, and the readout electrode serves as the bit line, so that the accumulation multiplication operation at each intersection can be highly parallelized. The present invention adopts a readout method based on an AC signal, that is, using a bias voltage to adjust the readout window, a global clock signal combined with a switch capacitor. Through the dynamic voltage response, the high linearity of the multiplication and accumulation operation is guaranteed, ensuring the stability and consistency of the signal between the input and output.

[0040] 3. The memcapacitor of the present invention has strong scalability in lateral dimensions. By optimizing the thickness of each layer, the memcapacitor can be miniaturized while maintaining a high dynamic range. This scalability makes the memcapacitor device more suitable for large-scale parallel computing systems.

[0041] 4. The memory container computing chip also performs well in programming speed and durability; without sacrificing performance, it improves the energy efficiency of the computing system and is suitable for large-scale parallel computing and artificial intelligence applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0043] Figure 1 A schematic diagram of the hierarchical structure of a memory container provided by the present invention.

[0044] Figure 2 A complete structural cross-sectional view of a memory container provided by the present invention.

[0045] Figure 3 A schematic diagram of a detailed shielding layer structure of a memcapacitor provided by the present invention.

[0046] Figure 4 The present invention provides a flow chart of a method for preparing a memory container.

[0047] Figure 5 A schematic diagram of the structure of a neural network parallel computing chip provided by the present invention.

[0048] Figure 6 A schematic diagram of a chip manufacturing process with a bonding pad provided by the present invention and an enlarged diagram thereof.

[0049] Figure 7 A diagram of the neuromorphic system layout provided by the present invention. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Example 1

[0052] The embodiment of the present invention discloses a memory container, referring to Figure 1 As shown, it includes: a top gate electrode, a top dielectric layer, a shielding layer and a readout electrode arranged in sequence from top to bottom;

[0053] in:

[0054] A top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input terminal connected to an external input circuit;

[0055] A top dielectric layer covering a portion of the upper surface of the shielding layer;

[0056] A shielding layer, located between the top dielectric layer and the readout electrode, with a lower surface completely covering the upper surface of the readout electrode;

[0057] The bottom surface of the readout electrode has an output terminal electrically connected to an external output circuit.

[0058] The memristor of the present invention can operate at a lower voltage by utilizing the charge shielding principle, thereby reducing energy consumption. This low power consumption characteristic makes the memristor device more advantageous in high-performance computing. Not only does it improve the energy efficiency of the device, but it also shows its potential advantages in large-scale applications through simulation. In addition, the design of the memristor device allows for higher parallel processing capabilities while maintaining high precision, and the scalability of the memristor device in lateral dimensions is superior to that of traditional memristors. By optimizing the thickness of each layer, the memristor device can be miniaturized while maintaining a high dynamic range. This scalability makes the memristor device more suitable for large-scale parallel computing systems.

[0059] Ordinary memristors rely on changes in resistance states for calculations, and require the application of voltage or current, resulting in high static power consumption, and scalability is limited by material properties. The present invention utilizes the charge shielding principle, controls the capacitance value by adjusting the shielding effect of the shielding layer on the electric field, and realizes multiplication and accumulation operations. This method does not require changing the resistance state, avoids the shortcomings of memristors, and has lower power consumption and higher scalability. At the same time, traditional ordinary neuron functional circuit units are usually connected using silicon through holes, which are not scalable and have no significant parallel computing capabilities. The present invention organizes memristor devices into a cross array structure, which can realize highly parallel multiplication and accumulation operations. At the same time, the scalability of memristor devices in lateral dimensions is better than that of traditional memristors. By optimizing the thickness of each layer, memristor devices can be miniaturized while maintaining a high dynamic range. This scalability makes memristor devices more suitable for large-scale parallel computing systems.

[0060] The embodiment of the present invention mainly consists of the following parts: a top gate electrode, a top dielectric layer, a shielding layer with contacts and a back readout electrode, and each component is separated by a dielectric layer. Figure 2 As shown, the internal structure and material of the memory container are intuitively displayed.

[0061] The memory container structure of the present invention is described in detail below:

[0062] The top gate electrode is located at the top of the entire structure.

[0063] Different from the gate of traditional transistors, the top gate electrode is covered on the dielectric layer with titanium nitride (TiN). Its function is to receive external applied electrical signals and regulate the charge distribution in the shielding layer below through the electric field effect. Due to the excellent conductivity of titanium nitride, it can effectively ensure the rapid transmission of electrical signals and improve the overall performance of the circuit. The specific structural position of the top gate electrode is shown in Figure 1. Figure 2 TiN is shown in orange.

[0064] At the same time, titanium nitride also has good compatibility with dielectrics, especially high-k materials, and can be well combined with the dielectric layer in the present invention to improve the gate leakage performance.

[0065] In this embodiment, the top gate electrode is directly converted into a word line (WL) for applying an input signal for calculation, and other positions are filled with SU-8 resist to form an insulating layer.

[0066] The top dielectric layer is made of high-k material hafnium zirconium co-doped oxide instead of traditional silicon dioxide (SiO2). Its core function is to isolate the top gate electrode from the shielding layer below, while allowing the electric field to penetrate to affect the charge in the shielding layer. Its specific structural position refers to Figure 2 Hafnium zirconium oxide is shown in medium to dark blue.

[0067] Since the hafnium-zirconium co-doped oxide itself has a high dielectric constant, it is easier to capture electrons, so that the top dielectric layer of the memristor obtains a memory effect. Based on the principle of charge shielding, the shielding efficiency can be adjusted by changing the gate voltage or the charge stored in the memory dielectric, thereby controlling the capacitive coupling between the gate electrode and the readout electrode. Under high shielding efficiency, the electric field is almost completely blocked, resulting in a very low capacitance value; while under low shielding efficiency, the electric field penetrates the shielding layer, resulting in a higher capacitance value. Therefore, different weight values ​​can be encoded by adjusting the state of the shielding layer and used for multiplication and accumulation operations.

[0068] The shielding layer further includes a p+ doped region and an n+ doped region. The specific structural position is as shown in Figure 2 The red p+ and dark green n+ are shown as reservoirs for holes and electrons respectively. Figure 3 As shown, specifically red p+ and dark green p+.

[0069] These regions are formed by ion implantation technology, which allows different types of carriers to be injected into the shielding layer according to actual needs, so as to optimize the charge distribution to adjust the electric field coupling efficiency, and then adjust the shielding effect of the shielding layer on the gate electric field. The p+ doped region of this embodiment is rich in holes (positive carriers) and is formed by injecting trivalent elements such as boron (B) to store and regulate the distribution of positive charges. The p+ doped region is rich in electrons (negative charge carriers) and is formed by injecting pentavalent elements such as phosphorus (P) to store and regulate the distribution of negative charges.

[0070] When used for cross array calculations, the shielding layer acts as a shielding line (SL) in a direction perpendicular to the WL.

[0071] In addition, this embodiment ensures that the device can produce a symmetrical response under positive and negative gate voltages. This symmetry is one of the most important characteristics in neuromorphic computing. During the neural network training process, any asymmetry in the weight update process may cause signal distortion, thereby affecting the accuracy of the model. The symmetrical response mechanism provided by the present invention ensures that there will be no distortion when the weight is updated, greatly improving the accuracy and reliability of training.

[0072] Silicon dioxide (SiO2) is used as a dielectric layer between the shielding layer and the readout electrode.

[0073] The readout electrodes are formed from a base wafer of highly n-type doped epitaxial layers and are used to detect and transmit charge state changes accumulated in the shielding layer or other sensitive areas.

[0074] In addition, an additional epitaxial layer structure is grown below the readout electrode as a substrate, mainly to improve carrier mobility and make the transmission of electrical signals faster and more efficient.

[0075] When used in crossbar array computing, the readout electrode acts as a bit line (BL) and is arranged in parallel with the SL.

[0076] This embodiment is based on the design of a high dynamic range memristor device based on the charge shielding principle. The shielding layer of the memristor device uses a material with a memory effect. Through the charge shielding effect, the device can switch between high electric field coupling and low electric field coupling, thereby achieving a high dynamic range of capacitance. This design significantly reduces static power consumption and improves energy efficiency.

[0077] Example 2

[0078] The embodiment of the present invention discloses a method for preparing a memory container, referring to Figure 4 As shown, steps S1-S4 are included;

[0079] In step S1, a composite substrate is prepared; the composite substrate is divided into a device layer, a buried oxide layer, a P-doped epitaxial layer and an epitaxial layer from top to bottom; specifically comprising:

[0080] Preparation of composite substrate: This embodiment uses a lightly doped P-type (doping concentration is about 3×10^15 cm^-3) silicon wafer with an oxide layer as the first substrate, and a lightly doped P-type (doping concentration is about 1×10^20 cm^-3) silicon wafer without an oxide layer as the second substrate. Through a bonding process, the oxide layer of the first substrate is bonded to the surface with a higher doping concentration in the second substrate, and a composite silicon wafer is successfully prepared as a composite substrate.

[0081] In this embodiment, the wafer consists of a device layer, a buried oxide layer (BOX) and an epitaxial layer from top to bottom, and the thickness of each layer is 88nm, 190nm and 3.5μm, respectively, providing a positioning reference for subsequent processes.

[0082] In step S2, an alignment mark is pre-etched on the upper surface of the device layer, and a p + Doped regions and n + The doped region serves as a shielding layer; specifically includes:

[0083] First, alignment marks are etched on the upper surface of the device layer, and boron and phosphorus ions are implanted. After the implantation is completed, the device is heat treated using rapid annealing technology in a temperature range of 350°C to 600°C to activate the implanted impurities and repair damage in the crystal structure.

[0084] In step S3, the upper surface of the device layer is oxidized to prepare a top dielectric layer, and covered with a titanium nitride cap layer as a top gate electrode; specifically comprising:

[0085] The device layer surface was cleaned with Standard Clean 1 solution to remove surface impurities and contaminants, and then oxidized in an oxygen environment at 750°C to chemically grow interface oxides to improve interface quality and stability.

[0086] Subsequently, Hf was prepared on the interfacial oxide using atomic layer deposition. 0.5 Zr 0.5 O2 ferroelectric material is used as a top dielectric layer; a TiN capping layer is covered on its surface as a top gate electrode; and an annealing treatment is performed at 600°C.

[0087] In step S4, a first metallization layer is prepared in the top dielectric layer by sputtering deposition; and two deep trenches are formed by longitudinally penetrating the P-doped epitaxial layer according to the alignment mark by etching, and the P-doped epitaxial layer between the two deep trenches is used as a readout electrode; specifically comprising:

[0088] Hf 0.5 Zr 0.5 The O2 ferroelectric layer is patterned, and the first aluminum metallization layer is prepared by sputtering deposition to form the contact holes and electrode structure of the device to achieve electrical connection.

[0089] This embodiment uses a 7 μm deep trench reactive etching method to separate the bit lines, and achieves separation and isolation of different functional layers through a precise etching process, thereby ensuring the structural integrity and performance stability of the device.

[0090] When preparing the memcapacitors arranged in a crossbar switch array, this embodiment further includes step S5;

[0091] Specifically include:

[0092] When preparing memcachors arranged in a crossbar array,

[0093] Etching shielding lines on the surface of the shielding layer by using an ion beam sputtering etching method;

[0094] Etching a bit line on the surface of the readout electrode; the bit line is parallel to the shield line;

[0095] SU-8 resist is filled inside the inner trench and above the first metallization layer; after forming the insulating layer, a second metallization layer is prepared to directly contact the top gate electrode as a word line and perpendicular to the bit line.

[0096] In this embodiment, a shielding line is etched on the surface of the shielding layer by an ion beam sputtering etching method, and the shielding layer is used as the shielding line; a bit line is etched on the surface of the readout electrode; the readout electrode is used as the bit line; SU-8 resist is used to fill the inside of the groove etched in step S4 to form an insulating layer; and another patterned SU-8 layer is applied above the first metallization layer to insulate it from the first metallization layer, and a second metallization layer is prepared, which is in direct contact with the top gate electrode and serves as a word line.

[0097] Example 3

[0098] The embodiment of the present invention discloses a neural network parallel computing chip, referring to Figure 5 As shown, it includes a plurality of memcapacitors as described in Embodiment 1; the plurality of memcapacitors are arranged in horizontal and vertical directions respectively to form a crossbar switch array;

[0099] Among them, in all the memory containers:

[0100] The top gate electrode is used as a word line to receive input signals; the shielding layer is used as a shielding line, which is perpendicular to the word line, dynamically adjusts the electric field shielding efficiency, and controls the capacitance value of the memcapporat; the readout electrode is used as a bit line, which is parallel to the shielding line, and is used to output parallel calculation results.

[0101] This embodiment is a multi-row and multi-column cross switch array, which can be set to (25+1)*3 memcapacitors as needed. The (25+1)*3 memcapacitors are arranged into a cross switch array to achieve highly parallel multiplication and accumulation calculations. The amount of charge accumulated from a single bit line BL represents the result of the multiplication and accumulation operation at each intersection. This means that it can process 25-dimensional input data (including bias terms) and output a 3-dimensional result. Specifically, the multiplication operation occurs between the input signal applied to the word line WL and the shielding layer adjusted by the state of the storage material, where the state of the storage material corresponds to the weight value of each intersection and is encoded by the capacitance of the point.

[0102] Example 4

[0103] The embodiment of the present invention discloses an application method of a neural network parallel computing chip as described in Example 3, which performs highly parallel multiplication and accumulation calculations in image classification or recognition scenarios;

[0104] The highly parallel multiplication-accumulation calculation includes differential weight operation and four-quadrant multiplication.

[0105] Specifically, the chip of this embodiment can realize the function of a single-layer perceptron and complete image classification tasks;

[0106] This embodiment implements a (25+1)*3 single-layer perceptron function through a cross array of memory containers. This means that it can process 25-dimensional input data (including bias terms) and output 3-dimensional results. At the same time, the chip successfully completed the three-classification task of a 5*5 image, that is, identifying letters in the image such as M, P, or I. This task demonstrates the potential of the chip in the field of image recognition. Figure 6 Figure 2 shows an image of a fabricated chip with bonding pads, a magnified micrograph of the crossbar array, and a scanning electron microscope image. Each memory cell has a size of 50×50 μm^2.

[0107] The crossbar matrix in the chip of this embodiment includes 26 word lines WLs and 6 bit lines BLs. Figure 7 As shown in the figure, a (25+1)*3 single-layer perceptron (25 is the input dimension, 1 is the bias, and 3 is the output dimension) is parallelized using a memcpy cross array. For the input 5×5 image, black is 1 and white is -1. The image is flattened into a 25-dimensional vector at input, corresponding to WL1~WL25, and the input value of the bias is always -1, which is equivalent to a fixed 26th-dimensional input. The output of the array is V1, V2, and V3 below, and the output signal is an analog voltage value.

[0108] In this embodiment, the chip uses a method based on differential weight topology to perform computing tasks. Specifically, in a memcapped crossbar switch array system, the weight is represented by the state of the memcapped. The memcapped state at each intersection corresponds to a weight value and is encoded by the capacitance at that point. The weight determines the contribution of the input signal to the output result after the multiplication operation.

[0109] The positive and negative values ​​of each weight are stored in two independent storage units, and the corresponding bit lines of the memcpu are positive bit lines and negative bit lines. When the weight is greater than 0, the memcpu on the positive bit line (PBL) is written with a specific charge value, while the memcpu on the negative bit line (NBL) remains zero; conversely, if the weight is less than 0, the memcpu on the NBL is written with a value, and the memcpu on the PBL remains zero. The final calculation result is obtained by subtracting the values ​​read from the PBL and NBL.

[0110] Among them, i is used for bit line, j is used for index word line, represents the positive potential line charge value, Indicates negative bit line charge value.

[0111] Since the differential pair can cancel out the common-mode signal, that is, the same signal that appears at both input ends, this topology exhibits good linearity for situations where only the signal difference rather than the absolute value is of interest. This makes it very suitable for applications that require high-precision signal processing. In addition, the differential signal transmission method itself has strong noise immunity. Since environmental noise usually affects the PBL and NBL in a similar way, these noises can cancel each other out in the final calculation process, which not only improves the accuracy of the calculation, but also significantly improves the signal-to-noise ratio (SNR), ensuring the quality and reliability of the signal.

[0112]

[0113] SNR stands for Signal-to-Noise Ratio and is measured in decibels (dB) and is a measure of signal quality.

[0114] RMS stands for root mean square; , RMS) is the RMS voltage value of the signal. The RMS value is an effective measure of the magnitude of the changing voltage (or current), especially for AC signals. , RMS) is the RMS voltage value of the noise. Similar to the RMS value of the signal, it is used to measure the effective value of the noise component.

[0115] For a periodic continuous-time signal , its RMS value can be calculated by the following integral formula:

[0116] Where T is the length of time for one complete cycle of the signal; is a time-varying function of the signal voltage.

[0117] For discrete data points, the following formula can be used:

[0118]

[0119] Where N is the number of sampling points. represents the voltage value of the i-th sampling point.

[0120] Similarly, for a continuous-time noise signal:

[0121]

[0122] For discrete data points:

[0123]

[0124] At the same time, in order to achieve the required four-quadrant multiplication (input × weight), a global clock signal is combined with a switched capacitor method. The circuit connection method is adjusted according to the polarity of the input signal and the state of the weight value. When the clock signal is high, the input signal is positive and the weight is also positive. At this time, the positive bit line is grounded, and the negative bit line is connected to the amplifier with an integrating capacitor to transfer the charge corresponding to the positive weight value. The input signal is positive, but the weight is negative. At this time, the negative bit line is grounded, and the positive bit line is connected to the integrating capacitor to transfer the charge corresponding to the negative weight value. The same is true in reverse; the input signal is negative and the weight is also negative. At this time, the positive bit line is grounded, and the negative bit line is connected to the amplifier with an integrating capacitor to transfer the charge corresponding to the negative weight value. The input signal is negative, but the weight is positive. At this time, the negative bit line is grounded, and the positive bit line is connected to the integrating capacitor to transfer the charge corresponding to the positive weight value.

[0125] Using this switched capacitor approach, the capacitances can be subtracted and “four-quadrant multiplication” can be achieved without the use of a differential amplifier.

[0126] Compared to memristors, memristors only respond to dynamic voltage or current signals; therefore, during the reading process, an AC voltage needs to be applied to the WL to ensure accurate data reading. In addition, the writing process of the storage material is achieved by applying a specific voltage difference between the SL and the WL, thereby changing the state of the storage cell and updating its weight value. This design not only improves the speed and efficiency of data processing, but also enhances the reliability and stability of the system. It is particularly suitable for application scenarios that require highly parallel computing capabilities, such as neural network accelerators.

[0127] The present invention is based on a high-performance capacitor computing structure design based on adiabatic charging; by adopting adiabatic charging, most of the charging energy of the capacitor can be recovered, thereby achieving higher energy efficiency. Combined with neuromorphic computing, the memcapacitor device can achieve high-performance computing while maintaining high energy efficiency, while greatly reducing energy consumption.

[0128] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0129] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory container, characterized in that: include: A top gate electrode, a top dielectric layer, a shielding layer and a readout electrode are sequentially arranged from top to bottom; in: The top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input terminal connected to an external input circuit; The top dielectric layer covers a portion of the upper surface of the shielding layer; The shielding layer is located between the top dielectric layer and the readout electrode, and the lower surface of the shielding layer completely covers the upper surface of the readout electrode; The bottom surface of the readout electrode has an output terminal electrically connected to an external output circuit.

2. A memory container as claimed in claim 1, characterized in that: The top dielectric layer is made of high-k material hafnium-zirconium co-doped oxide.

3. A memory container as claimed in claim 2, characterized in that: The top gate electrode is made of titanium nitride material.

4. A memory container as claimed in claim 1, characterized in that: The shielding layer is made of SiO2 material; The shielding layer includes one side of p + doped region, formed by implanting boron ions; the other side includes n + Doped regions are formed by implanting phosphorus ions.

5. A neural network parallel computing chip, characterized in that: The method comprises a plurality of memcapacitors as claimed in any one of claims 1 to 4; the plurality of memcapacitors are arranged in horizontal and vertical directions to form a crossbar switch array; Among them, in all the memory containers: The top gate electrode is used as a word line to receive input signals; the shielding layer is used as a shielding line, which is perpendicular to the word line, dynamically adjusts the electric field shielding efficiency, and controls the capacitance value of the memcapporat; the readout electrode is used as a bit line, which is parallel to the shielding line, and is used to output parallel calculation results.

6. An application method of a neural network parallel computing chip as claimed in claim 5, characterized in that: Perform highly parallel multiplication and accumulation calculations in image classification or recognition scenarios; The highly parallel multiplication-accumulation calculation includes differential weight operation and four-quadrant multiplication.

7. The application method of a neural network parallel computing chip as claimed in claim 6, characterized in that: The differential weight operation specifically includes: The positive or negative weight of the memory container is stored in two storage units respectively, and the bit lines of the storage units are divided into positive bit lines and negative bit lines according to the positive and negative values ​​of the storage weights; When the weight is greater than 0, the charge value is written into the memcapacitor corresponding to the positive bit line, and the memcapacitor corresponding to the negative bit line remains zero; When the weight is less than 0, the charge value is written into the memcapacitor corresponding to the negative bit line, and the memcapacitor corresponding to the positive bit line remains at zero; The charge values ​​of the positive bit line and the negative bit line are subtracted to obtain a weighted calculation result.

8. The application method of a neural network parallel computing chip as claimed in claim 6, characterized in that: The four-quadrant multiplication method specifically includes: Using clock signals to control the switched capacitor circuit and adjust the connection mode of the capacitor; In the clock high level stage, when the product of the input signal and the weight is greater than 0, the positive bit line is grounded and the negative bit line is connected to the integral capacitor amplifier; when the product of the input signal and the weight is less than 0, the negative bit line is grounded and the positive bit line is connected to the integral capacitor amplifier; The charge difference is accumulated through the integrating capacitor amplifier to obtain the accumulated product of the input signal and the weight.

9. A method for preparing a memory container according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1, preparing a composite substrate; the composite substrate is divided into a device layer, a buried oxide layer, a P-doped epitaxial layer and an epitaxial layer from top to bottom; S2, pre-etching alignment marks on the upper surface of the device layer, and forming p + Doped regions and n + a doped region, which acts as a shielding layer; S3, performing oxidation treatment on the upper surface of the device layer to prepare a top dielectric layer, and covering it with a titanium nitride capping layer as a top gate electrode; S4, preparing a first metallization layer in the top dielectric layer by sputtering deposition; and longitudinally penetrating the P-doped epitaxial layer by etching according to the alignment mark to form two deep trenches, and using the P-doped epitaxial layer between the two deep trenches as a readout electrode.

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