A memristor, a preparation method, a neural network parallel computing chip, and an application method thereof

Abstract

The present invention discloses a memcapacitor, a preparation method, a neural network parallel computing chip and an application method thereof. The memcapacitor includes: a top gate electrode, a top dielectric layer, a shielding layer and a readout electrode which are sequentially arranged from top to bottom; wherein: the top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input end connected to an external input circuit; the top dielectric layer covers a partial area of the upper surface of the shielding layer; the shielding layer is located between the top dielectric layer and the readout electrode, and the lower surface completely covers the upper surface of the readout electrode; the lower surface of the readout electrode has an output end electrically connected to an external output circuit. The present invention relates to the technical field of semiconductors; by introducing a shielding layer between electrodes, a high-dynamic-range capacitance change is achieved by using the charge shielding effect, thereby significantly reducing power consumption while maintaining high precision.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a memcapacitor, a preparation method, a neural network parallel computing chip and an application method thereof. Background Art

[0002] With the rapid development of artificial intelligence technology, data-intensive computing operations such as training neural networks are crucial in artificial intelligence applications, but at the same time are accompanied by huge energy consumption problems. When traditional computer architectures execute these computing tasks, they often require a large amount of energy consumption, which limits the further development of artificial intelligence technology.

[0003] To solve this problem, researchers have proposed the concept of neuromorphic computing. Neuromorphic computing is a computing paradigm that mimics the structure and function of the human brain neuron network. It realizes information processing by simulating the connection and signal transmission process between neurons. Compared with traditional computer architectures, neuromorphic computing has higher computing efficiency and lower energy consumption, so it is considered an important direction for the future development of artificial intelligence.

[0004] However, the existing neuromorphic computing technology solutions mainly include memristors. A memristor is a new type of electronic device with non-linear resistance characteristics. It can simulate the plasticity of synapses and is therefore widely used in neuromorphic computing. Memristors can be used to construct a crossbar array structure, and the storage and update of synaptic weights are realized by changing the resistance value at the cross point. However, memristors still have some limitations, such as higher energy consumption and poor scalability, etc.

[0005] Therefore, providing new ideas for the development of neuromorphic computing technology in order to solve at least one of the above technical problems is an urgent problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a memcapacitor, a preparation method, a neural network parallel computing chip and an application method thereof. This memcapacitor utilizes the charge shielding principle to control the capacitance value by adjusting the shielding effect of the shielding layer on the electric field, and realizes multiply-accumulate operations.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a memcapacitor, comprising: a top gate electrode, a top dielectric layer, a shielding layer and a readout electrode which are sequentially arranged from top to bottom;

[0009] Wherein:

[0010] The top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input end connected to an external input circuit;

[0011] The top dielectric layer covers a partial area on the upper surface of the shielding layer;

[0012] The shielding layer is located between the top dielectric layer and the readout electrode, and its lower surface completely covers the upper surface of the readout electrode;

[0013] The lower surface of the readout electrode has an output terminal electrically connected to an external output circuit.

[0014] Furthermore, the top dielectric layer is composed of a high-k material, hafnium zirconium co-doped oxide.

[0015] Furthermore, the top gate electrode is made of titanium nitride material.

[0016] Furthermore, the shielding layer is made of SiO2 material;

[0017] One side of the shielding layer includes a p + doped region formed by implanting boron ions; the other side includes an n + doped region formed by implanting phosphorus ions.

[0018] In a second aspect, the present invention provides a neural network parallel computing chip, including a plurality of memristors as described in any item of the first aspect; the plurality of memristors are respectively arranged in horizontal and vertical directions to form a crossbar switch array;

[0019] Among them, in all of the memristors:

[0020] The top gate electrode is used as a word line to receive an input signal; the shielding layer is used as a shielding line, perpendicular to the word line, dynamically adjusting the electric field shielding efficiency to control the capacitance value of the memristor; the readout electrode is used as a bit line, parallel to the shielding line, for outputting the parallel computing result.

[0021] In a third aspect, the present invention provides an application method of a neural network parallel computing chip as described in the second aspect, characterized in that highly parallel multiply-accumulate calculations are performed in an image classification or recognition scenario;

[0022] Among them, the highly parallel multiply-accumulate calculations include differential weight operations and four-quadrant multiplications.

[0023] Furthermore, the differential weight operation specifically includes:

[0024] Storing the positive or negative weights of the memristor in two storage units respectively, and the bit lines of the storage units are correspondingly divided into positive bit lines and negative bit lines according to the positive or negative nature of the stored weights;

[0025] When the weight is greater than 0, the memristor corresponding to the positive bit line is written with a charge value, and the memristor corresponding to the negative bit line remains zero;

[0026] When the weight is less than 0, the memristor corresponding to the negative bit line is written with a charge value, and the memristor corresponding to the positive bit line remains zero;

[0027] The charge values of the positive bit line and the negative bit line are subtracted to obtain the weight operation result.

[0028] Further, the four-quadrant multiplication specifically includes:

[0029] Using a clock signal to control a switched-capacitor circuit to adjust the connection mode of the capacitors;

[0030] In the high level stage of the clock, when the product of the input signal and the weight is greater than 0, the positive bit line is grounded, and the negative bit line is connected to the integrating capacitor amplifier; when the product of the input signal and the weight is less than 0, the negative bit line is grounded, and the positive bit line is connected to the integrating capacitor amplifier;

[0031] Accumulating the charge difference through the integrating capacitor amplifier to obtain the accumulated product of the input signal and the weight.

[0032] In a fourth aspect, the present invention provides a method for manufacturing a memristor according to any one of the first aspects, including the following steps:

[0033] S1. Prepare a composite substrate; the composite substrate is sequentially divided into a device layer, a buried oxide layer, a P-doped epitaxial layer, and an epitaxial layer from top to bottom;

[0034] S2. Pre-etch alignment marks on the upper surface of the device layer, and form a p + doped region and an n + doped region by ion implantation and rapid annealing processes as a shielding layer;

[0035] S3. Perform an oxidation treatment on the upper surface of the device layer to prepare a top dielectric layer and cover it with a titanium nitride capping layer as a top gate electrode;

[0036] S4. Prepare a first metallization layer in the top dielectric layer by sputtering deposition; and longitudinally penetrate the P-doped epitaxial layer through the etching method according to the alignment marks to form two deep trenches, and use the P-doped epitaxial layer between the two deep trenches as a readout electrode.

[0037] Through the above technical solutions, compared with the prior art, the present invention discloses a memristor, a manufacturing method, a neural network parallel computing chip and an application method thereof, and at least has the following beneficial effects:

[0038] 1. By introducing a shielding layer between the electrodes, the present invention uses the charge shielding effect to achieve a high dynamic range of capacitance change, thereby achieving high precision; at the same time, the memristor device can operate at a lower voltage, reducing energy consumption.

[0039] 2. The memristors of the present invention are organized into a crossbar array structure, enabling highly parallel multiply-accumulate operations. The input signals are applied to the word lines, the shielding layer serves as the shielding lines, and the read electrodes serve as the bit lines, allowing the cumulative multiplication operations at each cross point to be executed in a highly parallel manner. The present invention employs a readout method based on alternating current signals, that is, using a bias voltage to adjust the readout window, a global clock signal combined with switched capacitors. Through dynamic voltage response, a high degree of linearity in the multiply-accumulate operation is ensured, guaranteeing the stability and consistency of the signals between the input and output.

[0040] 3. The memristors of the present invention have strong scalability in the lateral dimension. By optimizing the thickness of each layer, the memristors can be miniaturized while maintaining a high dynamic range. This scalability makes the memristor devices more suitable for large-scale parallel computing systems.

[0041] 4. The memristor computing chips also perform excellently in terms of programming speed and durability; without sacrificing performance, the energy efficiency of the computing system is improved, making them suitable for large-scale parallel computing and artificial intelligence applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0043] Figure 1 It is a schematic diagram of the hierarchical structure of a memristor provided by the present invention.

[0044] Figure 2 It is a complete structure cross-sectional view of a memristor provided by the present invention.

[0045] Figure 3 It is a schematic diagram of the refined structure of the shielding layer of a memristor provided by the present invention.

[0046] Figure 4 It is a flowchart of the manufacturing method of a memristor provided by the present invention.

[0047] Figure 5 It is a schematic diagram of the structure of a neural network parallel computing chip provided by the present invention.

[0048] Figure 6 It is a schematic diagram of a manufacturing chip with bonding pads provided by the present invention and its enlarged view.

[0049] Figure 7 It is a layout diagram of a neuromorphic system provided by the present invention. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] Embodiment 1

[0052] An embodiment of the present invention discloses a memcapacitor. Referring to Figure 1 as shown, it includes: a top gate electrode, a top dielectric layer, a shielding layer, and a readout electrode, which are sequentially arranged from top to bottom;

[0053] Wherein:

[0054] The top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input end connected to an external input circuit;

[0055] The top dielectric layer covers a partial area of the upper surface of the shielding layer;

[0056] The shielding layer is located between the top dielectric layer and the readout electrode, and its lower surface completely covers the upper surface of the readout electrode;

[0057] The lower surface of the readout electrode has an output end electrically connected to an external output circuit.

[0058] The memcapacitor of the present invention can operate at a lower voltage by utilizing the charge shielding principle, reducing energy consumption. This low-power consumption characteristic makes the memcapacitor device more advantageous in high-performance computing. It not only improves the energy efficiency of the device but also shows its potential advantages in large-scale applications through simulation. In addition, the design of the memcapacitor device allows for higher parallel processing capabilities while maintaining high precision, and the memcapacitor device has better scalability in the lateral dimension than traditional memristors. By optimizing the thickness of each layer, the memcapacitor device can be miniaturized while maintaining a high dynamic range. This scalability makes the memcapacitor device more suitable for large-scale parallel computing systems.

[0059] Ordinary memristors rely on changes in resistance state for computing, require the application of voltage or current, resulting in high static power consumption, and their scalability is limited by material properties. The present invention utilizes the principle of charge shielding to control the capacitance value by adjusting the shielding effect of the shielding layer on the electric field, thereby realizing multiply-accumulate operations. This method does not require changing the resistance state, avoiding the disadvantages of memristors, and having lower power consumption and higher scalability. At the same time, traditional ordinary neuron functional circuit units usually use through-silicon vias for connection, with poor scalability and insignificant parallel computing ability. The present invention organizes memcapacitor devices into a crossbar array structure, which can achieve highly parallel multiply-accumulate operations. At the same time, the memcapacitor devices have better scalability in the lateral dimension than traditional memristors. By optimizing the thickness of each layer, the memcapacitor devices can be miniaturized while maintaining a high dynamic range. This scalability makes memcapacitor devices more suitable for large-scale parallel computing systems.

[0060] The embodiment of the present invention mainly consists of the following parts: a top gate electrode, a top dielectric layer, a shielding layer with contacts, and a backside readout electrode. All components are separated by dielectric layers. Refer to Figure 2 As shown, it intuitively displays the internal structure and materials of the memcapacitor.

[0061] The following details the memcapacitor structure of the present invention:

[0062] The top gate electrode is located at the uppermost part of the entire structure.

[0063] Different from the gate of traditional transistors, the top gate electrode uses titanium nitride (TiN) to cover the dielectric layer. Its function is to receive externally applied electrical signals and regulate the charge distribution in the underlying shielding layer through the electric field effect. Also, due to the excellent electrical conductivity of titanium nitride, it can effectively ensure the rapid transmission of electrical signals and improve the overall performance of the circuit. The specific structural position of the top gate electrode refers to Figure 2 the TiN shown in orange in

[0064] At the same time, titanium nitride also has good compatibility with the dielectric, especially high-k materials, and can well combine with the dielectric layer in the present invention to improve the gate leakage performance.

[0065] In this embodiment, the top gate electrode is directly converted into a word line (WL) for applying input signals for computing, and other positions are filled with SU-8 resist to form an insulating layer.

[0066] The top dielectric layer is made of a hafnium-zirconium co-doped oxide, a high-k material, to replace traditional silicon dioxide (SiO2). Its core function is to isolate the top gate electrode from the underlying shielding layer, while allowing the electric field to penetrate to affect the charges in the shielding layer. The specific structural position refers to Figure 2 the hafnium-zirconium oxide shown in dark blue in

[0067] Due to the relatively high dielectric constant of the hafnium-zirconium co-doped oxide itself, it is easier to capture electrons, enabling the top dielectric layer of the memcapacitor to obtain a memory effect. Based on the principle of charge shielding, the shielding efficiency can be adjusted by changing the gate voltage or the charge stored in the memory dielectric, thereby controlling the capacitive coupling between the gate electrode and the readout electrode. At high shielding efficiency, the electric field is almost completely blocked, resulting in a very low capacitance value; while at low shielding efficiency, the electric field penetrates the shielding layer, generating a higher capacitance value. Thus, different weight values can be encoded by adjusting the state of the shielding layer and used for multiply-accumulate operations.

[0068] The shielding layer further includes a p+-doped region and an n+-doped region, and the specific structural positions are referred to Figure 2 as shown by the red p+ and dark green n+ in Figure 3 respectively, serving as repositories for holes and electrons. The detailed schematic diagram of its structure is referred to

[0069] These regions are formed by ion implantation technology, allowing different types of carriers to be implanted into the shielding layer according to actual needs, thereby optimizing the charge distribution to adjust the electric field coupling efficiency, and further adjusting the shielding effect of the shielding layer on the gate electric field. The p+-doped region in this embodiment is rich in holes (positive carriers), formed by implanting trivalent elements such as boron (B), and is used to store and regulate the positive charge distribution. The n+-doped region is rich in electrons (negative carriers), formed by implanting pentavalent elements such as phosphorus (P), and is used to store and regulate the negative charge distribution.

[0070] When used for crossbar array computing, the shielding layer serves as a shielding line (shielding layer, SL) in the direction perpendicular to the WL.

[0071] In addition, this embodiment ensures that the device can generate symmetric responses under positive and negative gate voltages. This symmetry is one of the extremely important characteristics in neuromorphic computing. During the neural network training process, any asymmetry in the weight update process may lead to signal distortion, thereby affecting the accuracy of the model. The symmetric response mechanism provided by the present invention ensures that there will be no distortion phenomenon during weight update, greatly improving the accuracy and reliability of training.

[0072] A dielectric layer of silicon dioxide (SiO2) is provided between the shielding layer and the readout electrode.

[0073] The readout electrode is composed of a substrate wafer with a highly n-type doped epitaxial layer, and is used to detect and transfer the change in the charge state accumulated in the shielding layer or other sensitive regions.

[0074] In addition, an epitaxial layer structure is additionally epitaxially grown below the readout electrode as a substrate, mainly to improve the carrier mobility and make the transmission of electrical signals faster and more efficient.

[0075] When used for crossbar array computing, the readout electrode acts as a bit line (BL) and is arranged in parallel with the SL.

[0076] This embodiment designs a high-dynamic-range memcapacitor device based on the charge shielding principle. The shielding layer of the memcapacitor device uses a material with a memory effect. Through the charge shielding effect, the device can switch between high-field coupling and low-field coupling, thereby achieving a high dynamic range of capacitance. This design significantly reduces the static power consumption and improves the energy efficiency.

[0077] Embodiment 2

[0078] An embodiment of the present invention discloses a preparation method of a memcapacitor. Referring to Figure 4 as shown, it includes steps S1 - S4;

[0079] In step S1, a composite substrate is prepared; the composite substrate is divided into a device layer, a buried oxide layer, a P-doped epitaxial layer, and an epitaxial layer from top to bottom in sequence; specifically including:

[0080] Preparing the composite substrate: In this embodiment, a lightly doped P-type (doping concentration is about 3×10^15 cm^-3) silicon wafer with an oxide layer is used as the first substrate, and a lightly doped P-type (doping concentration is about 1×10^20 cm^-3) silicon wafer without an oxide layer is used as the second substrate. Through the bonding process, the oxide layer of the first substrate is bonded to the surface with a higher doping concentration in the second substrate, and a composite silicon wafer is successfully prepared as the composite substrate.

[0081] In this embodiment, the wafer is composed of a device layer, a buried oxide layer (BOX), and an epitaxial layer from top to bottom in sequence, and the thicknesses of each layer are 88nm, 190nm, and 3.5μm respectively, providing a positioning reference for subsequent processes.

[0082] In step S2, alignment marks are pre-etched on the upper surface of the device layer, and p + -doped regions and n + -doped regions are formed as the shielding layer through ion implantation and rapid annealing processes; specifically including:

[0083] First, alignment marks are etched on the upper surface of the device layer, boron ions and phosphorus ions are implanted, and after the implantation, the device is heat-treated in the temperature range of 350°C to 600°C using rapid annealing technology to activate the implanted impurities and repair the damage in the crystal structure.

[0084] In step S3, the upper surface of the device layer is oxidized to prepare a top dielectric layer, and a titanium nitride capping layer is covered as the top gate electrode; specifically including:

[0085] The surface of the device layer is cleaned with Standard Clean 1 solution to remove surface impurities and contaminants, and then oxidized in an oxygen environment at 750 °C to chemically grow an interfacial oxide to improve the interface quality and stability.

[0086] Subsequently, Hf 0.5 Zr 0.5 O2 ferroelectric material is prepared on the interfacial oxide by atomic layer deposition as the top dielectric layer; and a TiN capping layer is covered on its surface as the top gate electrode; and annealing treatment is carried out at 600 °C.

[0087] In step S4, a first metallization layer is prepared in the top dielectric layer by sputter deposition; and two deep trenches are longitudinally penetrated through the P-doped epitaxial layer according to the alignment marks, and the P-doped epitaxial layer between the two deep trenches is used as the readout electrode; specifically including:

[0088] The Hf 0.5 Zr 0.5 O2 ferroelectric layer is patterned, and a first aluminum metallization layer is prepared by sputter deposition to form contact holes and electrode structures of the device, realizing electrical connection.

[0089] In this embodiment, a 7-μm deep trench reactive etching method is used to separate the bit lines, and different functional layers are separated and isolated through precise etching processes to ensure the structural integrity and performance stability of the device.

[0090] When preparing the memristors arranged in a crossbar switch array, this embodiment further includes step S5;

[0091] Specifically including:

[0092] When preparing the memristors arranged in a crossbar switch array,

[0093] The shielding lines are etched on the surface of the shielding layer by ion beam sputter etching method;

[0094] The bit lines are etched on the surface of the readout electrode; the bit lines are parallel to the shielding lines;

[0095] SU-8 resist is filled inside the internal trenches and above the first metallization layer; after forming an insulating layer, a second metallization layer is prepared, which is in direct contact with the top gate electrode as the word line and is perpendicular to the bit lines.

[0096] In this embodiment, a shielding line is etched on the surface of the shielding layer by ion beam sputtering etching, and the shielding layer is used as the shielding line; a bit line is etched on the surface of the readout electrode; the readout electrode is used as the bit line; SU-8 resist is used to fill the inside of the groove etched in step S4 to form an insulating layer; and another patterned SU-8 layer is applied above the first metallization layer to insulate it from the first metallization layer, and a second metallization layer is prepared, which is in direct contact with the top gate electrode and serves as a word line.

[0097] Example 3

[0098] The embodiment of the present invention discloses a neural network parallel computing chip, referring to Figure 5 As shown, it includes multiple memcapacitors as described in Example 1; the multiple memcapacitors are arranged in the horizontal and vertical directions respectively to form a crossbar switch array;

[0099] Among them, in all the memory containers:

[0100] The top gate electrode serves as a word line for receiving input signals; the shielding layer serves as a shielding line, which is perpendicular to the word line, dynamically adjusts the electric field shielding efficiency, and controls the capacitance value of the memcappator; the readout electrode serves as a bit line, which is parallel to the shielding line, and is used to output parallel calculation results.

[0101] This embodiment features a multi-row, multi-column crossbar array, which can be configured as (25+1)*3 memcapacitors as needed. Arranging these (25+1)*3 memcapacitors into a crossbar array enables highly parallel multiplication and accumulation. The charge accumulated from a single bit line BL represents the result of the multiplication and accumulation operation at each intersection. This means it can process 25-dimensional input data (including bias terms) and output a 3-dimensional result. Specifically, the multiplication operation occurs between the input signal applied to the word line WL and a shielding layer adjusted by the state of the storage material. The state of the storage material corresponds to the weight value of each intersection and is encoded by the capacitance at that intersection.

[0102] Example 4

[0103] The embodiment of the present invention discloses an application method of a neural network parallel computing chip as described in Example 3, which performs highly parallel multiplication and accumulation calculations in image classification or recognition scenarios;

[0104] The highly parallel multiplication-accumulation calculation includes differential weight operation and four-quadrant multiplication.

[0105] Specifically, the chip of this embodiment can realize the function of a single-layer perceptron and complete image classification tasks;

[0106] In this embodiment, a single-layer perceptron function of (25 + 1) * 3 is realized through a memristor cross array. This means that it can process 25-dimensional input data (including the bias term) and output 3-dimensional results. At the same time, the chip successfully completed the three-classification task of a 5 * 5 image, that is, to identify the letters in the image, such as M, P, or I. This task demonstrates the potential of the chip in the field of image recognition. Refer to Figure 6 As shown, it shows an image of the fabricated chip with bonding pads, an enlarged microscopic image of the cross array, and a scanning electron microscope image. The size of each memory cell is 50 × 50 μm^2.

[0107] The cross matrix in the chip of this embodiment contains 26 word lines WLs and 6 bit lines BLs. Refer to Figure 7 As shown, a parallel calculation of a single-layer perceptron of (25 + 1) * 3 (25 is the input dimension, 1 is the bias, and 3 is the output dimension) is realized using a memristor cross array. For the input 5 × 5 image, black is 1 and white is -1. The image is flattened into a 25-dimensional vector when input, corresponding to WL1 to WL25, and the input value of the bias Bias is always -1, which is equivalent to the 26th-dimensional input with a fixed value. The output of the array is V1, V2, V3 below, and the output signal is an analog voltage value.

[0108] In this embodiment, the chip adopts a method based on differential weight topology to perform arithmetic tasks. Specifically, in a memristor-based crossbar array system, the weights are represented by the states of the memristors. The state of the memristor at each cross point corresponds to a weight value and is encoded by the capacitance at that point. The weights determine the contribution of the input signal to the output result after multiplication.

[0109] The positive and negative values of each weight are stored in two independent memory cells respectively. The bit lines corresponding to the memristors are the positive bit line and the negative bit line respectively. When the weight is greater than 0, the memristor on the positive bit line (Positive Bit Line, PBL) is written with a specific charge value, while the memristor on the negative bit line (Negative Bit Line, NBL) remains zero; conversely, if the weight is less than 0, the memristor on the NBL is written with a value and the memristor on the PBL remains zero. The final arithmetic result is obtained by subtracting the values read from the PBL and the NBL.

[0110] Among them, i is used for the bit line and j is used for indexing the word line. represents the positive bit line charge value. represents the negative bit line charge value.

[0111] Since a differential pair can cancel out common-mode signals, i.e., the same signals that appear simultaneously at both input terminals, this topology exhibits good linear characteristics for situations where only the signal differences rather than the absolute values are of concern. This makes it very suitable for applications that require high-precision signal processing. Additionally, the differential signal transmission method itself has strong noise immunity. Since environmental noise generally affects the PBL and NBL in a similar manner, these noises cancel each other out during the final calculation process, which not only improves the accuracy of the operation but also significantly increases the signal-to-noise ratio (SNR), ensuring the quality and reliability of the signal.

[0112]

[0113] SNR stands for signal-to-noise ratio, with the unit of decibels (dB), and is used to measure the signal quality.

[0114] RMS stands for root mean square; ( , RMS) is the RMS voltage value of the signal. The RMS value is an effective way to measure the magnitude of the varying voltage (or current), especially suitable for AC signals. ( , RMS) is the RMS voltage value of the noise. Similar to the RMS value of the signal, it is used to measure the effective value of the noise component.

[0115] For a periodic continuous-time signal , its RMS value can be calculated by the following integral formula:

[0116] where T is the time length of a complete cycle of the signal; is the signal voltage function that varies with time.

[0117] For discrete data points, the following formula can be used:

[0118]

[0119] where N is the number of sampling points. represents the voltage value of the i-th sampling point.

[0120] Similarly, for a continuous-time noise signal:

[0121]

[0122] For discrete data points:

[0123]

[0124] Meanwhile, to achieve the required four-quadrant multiplication (input × weight), a combination of a global clock signal and a switched-capacitor method is adopted. The circuit connection is adjusted according to the polarity of the input signal and the state of the weight value. When the clock signal is high, if the input signal is positive and the weight is also positive, the positive bit line is grounded, while the negative bit line is connected to an amplifier with an integrating capacitor to transfer the charge corresponding to the positive weight value. If the input signal is positive but the weight is negative, the negative bit line is grounded and the positive bit line is connected to the integrating capacitor to transfer the charge corresponding to the negative weight value. Vice versa; if the input signal is negative and the weight is also negative, the positive bit line is grounded, while the negative bit line is connected to an amplifier with an integrating capacitor to transfer the charge corresponding to the negative weight value. If the input signal is negative but the weight is positive, the negative bit line is grounded and the positive bit line is connected to the integrating capacitor to transfer the charge corresponding to the positive weight value.

[0125] By using this switched-capacitor method, subtraction operations can be performed on capacitors, and "four-quadrant multiplication" can be achieved without using a differential amplifier.

[0126] Compared with memristors, due to the characteristic that memcapacitors only respond to dynamic voltage or current signals; therefore, during the reading process, an AC voltage needs to be applied to the WL to ensure accurate data reading. In addition, the writing process of the storage material is achieved by applying a specific voltage difference between the SL and the WL, thereby changing the state of the storage unit and updating its weight value. This design not only improves the speed and efficiency of data processing but also enhances the reliability and stability of the system, and is particularly suitable for application scenarios that require high parallel computing capabilities, such as neural network accelerators, etc.

[0127] The present invention is based on the design of a high-performance capacitive computing structure with adiabatic charging; by adopting adiabatic charging, the charging energy of most capacitors can be recovered, thereby achieving higher energy efficiency. Combining neuromorphic computing, memcapacitor devices can achieve high-performance computing while maintaining high energy efficiency, and at the same time greatly reducing energy consumption.

[0128] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0129] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memristor, characterized in that, Comprising: A top gate electrode, a top dielectric layer, a shielding layer, and a readout electrode arranged successively from top to bottom; Wherein: The top gate electrode completely covers the upper surface of the top dielectric layer; the top surface of the top gate electrode has an input end connected to an external input circuit; The top dielectric layer covers a partial area of the upper surface of the shielding layer; The shielding layer is located between the top dielectric layer and the readout electrode, and its lower surface completely covers the upper surface of the readout electrode; The lower surface of the readout electrode has an output end electrically connected to an external output circuit; A preparation method of a memcapacitor, comprising the following steps: S1. Prepare a composite substrate; the composite substrate is successively divided into a device layer, a buried oxide layer, a P-doped epitaxial layer, and an epitaxial layer from top to bottom; S2. Pre-etch alignment marks on the upper surface of the device layer, and form a p+-doped region and an n+-doped region through ion implantation and rapid annealing processes as the shielding layer; S3. Perform an oxidation treatment on the upper surface of the device layer to prepare the top dielectric layer, and cover it with a titanium nitride capping layer as the top gate electrode; S4. Prepare a first metallization layer in the top dielectric layer by sputtering deposition; and form two deep trenches longitudinally penetrating the P-doped epitaxial layer according to the alignment marks, and use the P-doped epitaxial layer between the two deep trenches as the readout electrode.

2. The memristor according to claim 1, characterized in that, The top dielectric layer is composed of a high-k material, hafnium zirconium co-doped oxide.

3. A memcontainer according to claim 2, characterized in that, The top gate electrode is made of titanium nitride material.

4. A memcontainer according to claim 1, characterized in that, The shielding layer is made of SiO2 material; One side of the shielding layer includes a p+-doped region formed by implanting boron ions; the other side includes an n+-doped region formed by implanting phosphorus ions.

5. A neural network parallel computing chip, characterized in that, Comprising a plurality of memcapacitors as described in any one of claims 1-4; the plurality of memcapacitors are respectively arranged in horizontal and vertical directions to form a crossbar switch array; Wherein, among all the memcapacitors: The top gate electrode serves as a word line for receiving an input signal; the shielding layer serves as a shielding line, perpendicular to the word line, dynamically adjusts the electric field shielding efficiency, and controls the capacitance value of the memcapacitor; the readout electrode serves as a bit line, parallel to the shielding line, and is used to output parallel calculation results.

6. An application method of a neural network parallel computing chip as described in claim 5, characterized in that, Perform highly parallel multiply-accumulate calculations in an image classification or recognition scenario; Wherein, the highly parallel multiply-accumulate calculation includes differential weight operation and four-quadrant multiplication.

7. The application method of a neural network parallel computing chip according to claim 6, characterized in that, The differential weight operation specifically includes: Store the positive or negative weight values of the memcapacitor in two storage units respectively, and the bit lines of the storage units are correspondingly divided into positive bit lines and negative bit lines according to the positive or negative nature of the stored weights; When the weight is greater than 0, the memcapacitor corresponding to the positive bit line is written with a charge value, and the memcapacitor corresponding to the negative bit line remains zero; When the weight is less than 0, the memcapacitor corresponding to the negative bit line is written with a charge value, and the memcapacitor corresponding to the positive bit line remains zero; The charge values of the positive bit line and the negative bit line are subtracted to obtain the weight operation result.

8. The application method of a neural network parallel computing chip as described in claim 6, wherein The four-quadrant multiplication specifically includes: Use a clock signal to control a switched-capacitor circuit and adjust the connection mode of the capacitors; During the high level stage of the clock, when the product of the input signal and the weight is greater than 0, the positive bit line is grounded and the negative bit line is connected to the integrating capacitor amplifier; when the product of the input signal and the weight is less than 0, the negative bit line is grounded and the positive bit line is connected to the integrating capacitor amplifier; The integrating capacitor amplifier accumulates the charge difference to obtain the accumulated product of the input signal and the weight.

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