Layout structure capable of improving latch-up resistance

Abstract

The invention provides a layout structure for improving latch-up resistance, which comprises an NWELL region, a PWELL region, a first P + contact region, a second P + contact region, a first N + contact region, a second N + contact region, a first active region, a second active region, a first polycrystalline grid, a second polycrystalline grid, a third polycrystalline grid, a contact hole, a first metal, a second metal, a third metal and a fourth metal, according to the invention, the layout structure of the existing PMOS + NMOS driving transistor is improved, the latch-up resistance is improved by using the close design of substrate contact and source region contact from the angle of reducing the base resistance of the parasitic transistor, and the robustness of the driving circuit is improved from the angle of layout design.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices and relates to a layout structure for improving anti-latch capability. Background Art

[0002] Latch up is the latch effect, which often occurs in driving circuits containing larger PMOS and NMOS in CMOS integrated circuits. The latch effect is a condition that generates a low-impedance path between the power pin and the ground of the device. This low-impedance path may cause system turbulence or catastrophic damage due to excessive current levels. When the external trigger causes the emitter of the parasitic transistor inside the driving circuit to be forward biased and generate a sufficiently large current, so that the other parasitic transistor is also forward biased and forward-conducted, and the product of the common emitter current amplification factor β of the two parasitic transistors is greater than 1, the circuit will generate a low-resistance channel to double the current after triggering. At this time, if the power supply can provide the current to maintain the trigger, the device will remain in the latched state and cannot be turned off, and the chip will burn out.

[0003] The most direct means of anti-latching is to make the current amplification factor of the parasitic transistor small enough; in the layout design, the distance between the source and drain regions of the MOS tube and the well boundary is generally increased, or the contact between the substrate and the well potential is reasonably distributed to minimize the equivalent resistance Rsub and Rwell of the substrate and the well. Under current technology, the engineering design rules will leave a large gap between the substrate contact and the source contact. From the perspective of anti-latching, there is a large well resistance between the substrate contact and the source contact, which undoubtedly makes the latch effect more likely to occur. In order to solve this problem, the present invention breaks through engineering common sense, from the perspective of eliminating the large resistance of the well region and the substrate region, and uses the design of the substrate contact and the source contact close to provide anti-latching, which improves the robustness of the transistor of the driving circuit from the perspective of layout design. Summary of the invention

[0004] The problem to be solved by the present invention is to improve the anti-latch capability of the circuit by changing the layout structure without changing the working performance of the driving circuit.

[0005] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0006] An anti-latch layout structure comprises part A: an NWELL region (100), a first P+ contact region (201) located inside the NWELL region (100), a second N+ contact region (102) adjacent to the first P+ contact region (201), and a first active region (401) located inside the first P+ contact region (201) and the second N+ contact region (102), and further comprises a first polycrystalline gate (001), a first metal (301), and a contact hole (501) located in the first active region (401), wherein the first P+ contact region (201) and the second N+ contact region (102) are adjacent to each other and in contact, and the first P+ contact region (201) and the second N+ contact region (102) on the left side of the first polycrystalline gate (001) are connected to VDD through the first metal (301);

[0007] The invention also includes part B: a PWELL region (200), an N+ contact region (101) located inside the PWELL region (200), a second P+ contact region (202) adjacent to the first N+ contact region (101), and a second active region (402) located inside the first N+ contact region (101) and the second P+ contact region (202). The invention also includes a second polycrystalline gate (002), a fourth metal (304), and a contact hole (501) located in the second active region (402), wherein the first N+ contact region (101) is adjacent to and in contact with the second P+ contact region (202), and is connected to GND through the second metal (302); and the first N+ contact region (101) on the left side of the second polycrystalline gate (002) is connected to the second P+ contact region (202) through the second metal (302).

[0008] The invention also includes a portion C: a third N+ contact region (103) is provided inside the NWELL region (100), and the third N+ contact region (103) surrounds the portion A; the third N+ contact region (103), the second N+ contact region (102), and the first P+ contact region (201) on the left side of the first polycrystalline gate (001) are all connected to VDD through the first metal (301) and the sixth metal (306).

[0009] The device further comprises a portion D: a third P+ contact region (203) is disposed inside the PWELL (200), the third P+ contact region (203) surrounds the portion B, and the third P+ contact region (203), the second P+ contact region (202), and the first N+ contact region (101) on the left side of the second polycrystalline gate (002) are all connected to GND via the second metal (302) and the seventh metal (307).

[0010] As a preferred embodiment, a fourth N+ contact region (104) and a fourth P+ contact region (204) are provided inside the PWELL region (200), wherein the fourth N+ contact region (104) is located inside the fourth P+ contact region (204) and surrounds the D portion; wherein the fourth N+ contact region (104) is connected to the tenth metal (310) through the eighth metal (308) and the through hole (502), and the tenth metal (310) is connected to VDD through the through hole (502); the fourth P+ contact region (204) is connected to the ninth metal (309) through the eleventh metal (311) and the through hole (502), and the ninth metal (309) is connected to GND through the through hole (502).

[0011] The beneficial effects of the present invention are: breaking through the existing common layout scheme, from the perspective of reducing the base resistance of the parasitic transistor, using the design of close substrate contact and source contact to provide an anti-latch layout structure scheme, thereby improving the robustness of PMOS+NMOS driving circuits from the perspective of layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is an equivalent circuit diagram of the parasitic latch-up effect of a traditional PMOS+NMOS drive circuit.

[0013] FIG2 is the layout structure of Example 1.

[0014] 001 is the first polycrystalline gate, 002 is the second polycrystalline gate, 003 is the third polycrystalline gate, 100 is the NWELL region, 101 is the first N+ contact region, 102 is the second N+ contact region, 103 is the third N+ contact region, 104 is the fourth N+ contact region, 200 is the PWELL region, 201 is the first P+ contact region, 202 is the second P+ contact region, 203 is the third P+ contact region, 204 is the fourth P+ contact region, 301 is the first metal, 302 is the second metal, 303 is the third metal, 304 is the fourth metal, 305 is the fifth metal, 306 is the sixth metal, 307 is the seventh metal, 308 is the eighth metal, 309 is the ninth metal, 310 is the tenth metal, 311 is the eleventh metal, 401 is the first active region, 402 is the is the second active area, 403 is the third active area, 404 is the fourth active area, 405 is the fifth active area, 406 is the sixth active area, 501 is the contact hole, and 502 is the through hole. DETAILED DESCRIPTION

[0015] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. Example 1

[0016] As shown in FIG. 2 , the device structure of this embodiment includes part A: an NWELL region (100), a first P+ contact region (201) located inside the NWELL region (100), a second N+ contact region (102) adjacent to the first P+ contact region (201), and a first active region (401) located inside the first P+ contact region (201) and the second N+ contact region (102), and also includes a first polycrystalline gate (001), a first metal (301), and a contact hole (501) located in the first active region (401), wherein the first P+ contact region (201) and the second N+ contact region (102) are adjacent to each other and in contact, and the first P+ contact region (201) and the second N+ contact region (102) on the left side of the first polycrystalline gate (001) are connected to VDD through the first metal (301).

[0017] The invention also includes part B: a PWELL region (200), an N+ contact region (101) located inside the PWELL region (200), a second P+ contact region (202) adjacent to the first N+ contact region (101), and a second active region (402) located inside the first N+ contact region (101) and the second P+ contact region (202). The invention also includes a second polycrystalline gate (002), a fourth metal (304), and a contact hole (501) located in the second active region (402), wherein the first N+ contact region (101) is adjacent to and in contact with the second P+ contact region (202), and is connected to GND through the second metal (302); and the first N+ contact region (101) on the left side of the second polycrystalline gate (002) is connected to the second P+ contact region (202) through the second metal (302).

[0018] The invention also includes a portion C: a third N+ contact region (103) is provided inside the NWELL region (100), and the third N+ contact region (103) surrounds the portion A; the third N+ contact region (103), the second N+ contact region (102), and the first P+ contact region (201) on the left side of the first polycrystalline gate (001) are all connected to VDD through the first metal (301) and the sixth metal (306).

[0019] The device further comprises a portion D: a third P+ contact region (203) is disposed inside the PWELL (200), the third P+ contact region (203) surrounds the portion B, and the third P+ contact region (203), the second P+ contact region (202), and the first N+ contact region (101) on the left side of the second polycrystalline gate (002) are all connected to GND via the second metal (302) and the seventh metal (307).

[0020] A fourth N+ contact region (104) and a fourth P+ contact region (204) are provided inside the PWELL region (200), wherein the fourth N+ contact region (104) is located inside the fourth P+ contact region (204) and surrounds the D portion; wherein the fourth N+ contact region (104) is connected to the tenth metal (310) through the eighth metal (308) and the through hole (502), and the tenth metal (310) is connected to VDD through the through hole (502); the fourth P+ contact region (204) is connected to the ninth metal (309) through the eleventh metal (311) and the through hole (502), and the ninth metal (309) is connected to GND through the through hole (502).

[0021] The working principle of this example is as follows: in the existing commonly used PMOS+NMOS driving circuit, according to the process design rules, there is generally a certain distance between the P+ contact area and the N+ contact area. However, there is a certain distance between the substrate contact and the source contact of the MOS tube, which will cause a large resistance in the well area between the substrate contact and the source contact. If the resistance generates a voltage drop due to the current flowing through it, there will undoubtedly be a potential difference between the source area and the substrate. This potential difference is the emitter bias of the parasitic transistor. When the potential difference reaches a certain voltage value, the internal parasitic transistor will be turned on, causing the circuit to latch. In Example 1, the layout layout in which the source area and the substrate are cross-tangent and close to each other is applied, which significantly reduces the size of the well resistance, that is, reduces the emitter bias of the parasitic transistor and improves the anti-latch capability of the circuit. In addition, by adding an additional isolation ring, the current flowing through the substrate parasitic resistance is reduced, and the effect of reducing the emitter bias of the parasitic transistor is also achieved, thereby further improving the anti-latch capability of the circuit.

[0022] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An anti-latch layout structure, characterized in that: The invention comprises a part A: an NWELL region (100), a first P+ contact region (201) located inside the NWELL region (100), a second N+ contact region (102) adjacent to the first P+ contact region (201), and a first active region (401) located inside the first P+ contact region (201) and the second N+ contact region (102), and also comprises a first polycrystalline gate (001), a first metal (301), and a contact hole (501) located in the first active region (401), wherein the first P+ contact region (201) and the second N+ contact region (102) are adjacent to each other and contact each other, and the first P+ contact region (201) and the second N+ contact region (102) on the left side of the first polycrystalline gate (001) are connected to VDD through the first metal (301); and a part B: a PWELL region (200), a first metal (301) located inside the PWELL The invention further comprises an N+ contact region (101) inside the NWELL region (200), a second P+ contact region (202) adjacent to the first N+ contact region (101), and a second active region (402) located inside the first N+ contact region (101) and the second P+ contact region (202), and further comprises a second polycrystalline gate (002), a fourth metal (304), and a contact hole (501) located in the second active region (402), wherein the first N+ contact region (101) is adjacent to and in contact with the second P+ contact region (202), and is connected to GND through the second metal (302); the first N+ contact region (101) on the left side of the second polycrystalline gate (002) is connected to the second P+ contact region (202) through the second metal (302); and further comprises a C part: a third N+ contact region (103) is provided inside the NWELL region (100), and the third N+ contact region (103) surrounds the A The invention also comprises a portion D: a third N+ contact region (103), a second N+ contact region (102), and a first P+ contact region (201) on the left side of the first polycrystalline gate (001) are all connected to VDD through a first metal (301) and a sixth metal (306); and a portion D: a third P+ contact region (203) is provided inside the PWELL (200), and the third P+ contact region (203) surrounds the portion B, and the third P+ contact region (203), the second P+ contact region (202), and the first N+ contact region (101) on the left side of the second polycrystalline gate (002) are all connected to GND through a second metal (302) and a seventh metal (307).

2. The anti-latch layout structure according to claim 1, characterized in that: A fourth N+ contact region (104) and a fourth P+ contact region (204) are provided inside the PWELL region (200), wherein the fourth N+ contact region (104) is located inside the fourth P+ contact region (204) and surrounds the D portion; wherein the fourth N+ contact region (104) is connected to the tenth metal (310) through the eighth metal (308) and the through hole (502), and the tenth metal (310) is connected to VDD through the through hole (502); the fourth P+ contact region (204) is connected to the ninth metal (309) through the eleventh metal (311) and the through hole (502), and the ninth metal (309) is connected to GND through the through hole (502).

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