Display panel and electronic equipment

Abstract

The invention provides a display panel and electronic equipment, the display panel comprises a display area and a non-display area, and the display panel comprises a substrate; the circuit function layer is located on one side of the substrate and comprises a pixel driving circuit located in the display area and a gate driving circuit located in the display area; the first insulating layer is positioned on one side, far away from the substrate, of the circuit function layer; the connecting circuit layer is located on the side, away from the substrate, of the first insulating layer and comprises a connecting wire, and the connecting wire is connected with the gate drive circuit and the pixel drive circuit; the orthographic projection of the connecting wire on the substrate coincides with the orthographic projection of at least part of the gate drive circuit on the substrate. According to the embodiment of the invention, the connecting wire connected with the gate driving circuit in the frame region is at least partially overlapped with the gate driving circuit, so that the total occupied area of the gate driving circuit and the connecting wire can be reduced, and the frame size, especially the frame size of the arc angle region, is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the invention

[0004] In order to overcome the above-mentioned deficiencies in the prior art, the object of the present application is to provide a display panel, the display panel comprising a display area and a non-display area surrounding at least a portion of the display area, the display panel comprising:

[0005] substrate;

[0006] A circuit function layer located on one side of the substrate, the circuit function layer comprising a pixel driving circuit located in a display area and a gate driving circuit located in a non-display area;

[0007] A first insulating layer located on a side of the circuit function layer away from the substrate;

[0008] A connection circuit layer is located on a side of the first insulating layer away from the substrate, the connection circuit layer includes a connection line, the connection line connects the gate drive circuit and the pixel drive circuit; the orthographic projection of the connection line on the substrate coincides with the orthographic projection of at least part of the gate drive circuit on the substrate.

[0009] In some possible implementations, the gate driving circuit includes at least two sub-circuits, and the at least two sub-circuits are arranged in a direction away from the display area; the connection circuit layer includes at least two connection traces; the at least two sub-circuits are connected to the pixel driving circuit through the corresponding connection traces; the orthographic projection of the connection trace on the substrate at least partially overlaps with the orthographic projection of at least one of the sub-circuits on the substrate;

[0010] Preferably, different connecting wires are respectively connected to different sub-circuits through through holes penetrating the first insulating layer; the orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of at least one sub-circuit on the substrate away from the display area;

[0011] Preferably, the orthographic projection of the through hole on the substrate is located between the orthographic projections of two adjacent sub-circuits on the substrate;

[0012] Preferably, the sub-circuit comprises an active layer; the orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of the active layer of at least one of the sub-circuit on the substrate away from the display area;

[0013] Preferably, the orthographic projection of the through hole on the substrate is located between the orthographic projections of the active layers of two adjacent sub-circuits on the substrate.

[0014] In some possible implementations, the sub-circuit of the gate driving circuit includes a first scanning driving circuit, a second scanning driving circuit, and a light emitting control driving circuit arranged in a direction away from the display area;

[0015] The orthographic projection of the through hole on the substrate is located between the orthographic projections of the first scan driving circuit and the second scan driving circuit on the substrate, and the orthographic projection of the connecting wire on the substrate coincides with the orthographic projection of the first scan driving circuit on the substrate;

[0016] Preferably, the sub-circuit comprises an active layer; and an orthographic projection of the through hole on the substrate is located between an orthographic projection of the active layer of the first scan driving circuit and an orthographic projection of the active layer of the second scan driving circuit on the substrate.

[0017] In some possible implementations, the sub-circuit of the gate driving circuit includes a first scanning driving circuit, a second scanning driving circuit, and a light emitting control driving circuit arranged in a direction away from the display area;

[0018] The orthographic projection of the through hole on the substrate is located between the orthographic projections of the second scan drive circuit and the light emitting control drive circuit on the substrate, and the orthographic projection of the connecting wire on the substrate coincides with the orthographic projections of the first scan drive circuit and the second scan drive circuit on the substrate;

[0019] Preferably, the sub-circuit comprises an active layer; and an orthographic projection of the through hole on the substrate is located between an orthographic projection of the active layer of the second scanning driving circuit and an orthographic projection of the active layer of the light emitting control driving circuit on the substrate.

[0020] In some possible implementations, the sub-circuit of the gate driving circuit includes a first scanning driving circuit, a second scanning driving circuit, and a light emitting control driving circuit arranged in a direction away from the display area;

[0021] The orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of the light emitting control driving circuit on the substrate away from the display area, and the orthographic projection of the connecting wire on the substrate coincides with the orthographic projections of the first scanning driving circuit, the second scanning driving circuit and the light emitting control driving circuit on the substrate;

[0022] Preferably, the sub-circuit comprises an active layer; and the orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of the active layer of the light emitting control driving circuit on the substrate away from the display area.

[0023] In some possible implementations, the display panel further includes:

[0024] An isolation structure located on a side of the connection line layer away from the substrate; the isolation structure is located in the display area, and the isolation structure includes an isolation opening;

[0025] The display panel further includes a light emitting device at least partially located within the isolation opening;

[0026] The light-emitting device includes a first electrode, a light-emitting unit and a second electrode stacked in a direction away from the substrate; the first electrode is electrically connected to the pixel driving circuit; at least part of the isolation structure is conductive, and the second electrode is electrically connected to the isolation structure.

[0027] In some possible implementations, the display panel also includes a shielding structure disposed on the same layer as the isolation structure, the shielding structure is located in the non-display area, and the orthographic projection of the gate drive circuit on the substrate at least partially overlaps with the orthographic projection of the shielding structure on the substrate.

[0028] In some possible implementations, the display panel further includes a touch function film layer located on a side of the isolation structure and the shielding structure away from the substrate;

[0029] Preferably, an orthographic projection of the touch-sensitive functional film layer on the substrate at least partially overlaps with an orthographic projection of the shielding structure on the substrate.

[0030] In some possible implementations, the display panel further includes an encapsulation unit located on a side of the light-emitting device away from the substrate, and at least a portion of the encapsulation unit extends from within the isolation opening to a side of the isolation structure away from the substrate;

[0031] Preferably, there is a gap between the packaging units corresponding to at least some of the adjacent isolation openings, and the gap is located on a side of the isolation structure away from the substrate;

[0032] Preferably, the display panel further comprises a first encapsulation layer and a second encapsulation layer which are located on a side of the encapsulation unit and the isolation structure away from the substrate and are stacked in a direction away from the substrate;

[0033] The materials of the encapsulation unit and the second encapsulation layer include inorganic materials, and the material of the first encapsulation layer includes organic materials.

[0034] In some possible implementations, the isolation structure includes a supporting portion and a shielding portion located on a side of the supporting portion away from the substrate, and an orthographic projection of the supporting portion on the substrate is located within an orthographic projection of the shielding portion on the substrate;

[0035] Preferably, the etching resistance of the supporting portion is less than that of the shielding portion;

[0036] Preferably, the material of the support portion includes aluminum, and / or the material of the shielding portion includes titanium;

[0037] Preferably, the isolation structure further comprises a connecting portion located between the supporting portion and the substrate, and an orthographic projection of the supporting portion on the substrate is located within an orthographic projection of the connecting portion on the substrate;

[0038] Preferably, the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the shielding portion on the substrate;

[0039] Preferably, the material of the connecting portion includes molybdenum.

[0040] In some possible implementations, the non-display area includes an arc angle area, and an orthographic projection of the connection trace located in the arc angle area on the substrate coincides with an orthographic projection of the gate driving circuit at least partially located in the arc angle area on the substrate;

[0041] Preferably, the non-display area also includes a straight edge area adjacent to the arc angle area, and the orthographic projection of the connecting line located in the straight edge area on the substrate coincides with the orthographic projection of the gate driving circuit at least partially located in the straight edge area on the substrate.

[0042] In some possible implementations, the display panel includes a data signal line connected to the pixel driving circuit, and the data signal line and the connection line are arranged on the same layer;

[0043] Preferably, along a direction away from the substrate, the display panel comprises a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence, and the connecting wire is located in the fifth conductive layer;

[0044] Preferably, the first insulating layer is located between the fourth conductive layer and the fifth conductive layer.

[0045] Another object of the present application is to provide a display panel, the display panel comprising a display area and a non-display area surrounding at least a portion of the display area, the display panel comprising:

[0046] substrate;

[0047] A pixel driving circuit located in the display area and a gate driving circuit located in the non-display area;

[0048] A connection circuit layer located on one side of the substrate, the connection circuit layer comprising connection wires, and the connection wires are connected to the gate driving circuit and the pixel driving circuit;

[0049] The orthographic projection of the connecting wire on the substrate coincides with the orthographic projection of at least part of the gate driving circuit on the substrate; and / or a partial area of ​​the connecting wire is located within the display area.

[0050] In some possible implementations, the display panel further includes:

[0051] The first insulating layer is located on a side of the pixel driving circuit and the gate driving circuit away from the substrate; the connecting wire is located on a side of the first insulating layer away from the substrate.

[0052] In some possible implementations, the connection line layer includes a fourth conductive layer and a fifth conductive layer stacked in a direction away from the substrate; at least a portion of the connection line located in the display area is located in the fourth conductive layer, and at least a portion of the connection line is located in the fifth conductive layer;

[0053] Preferably, the connection line is located in the display area and the portion extending along the first direction is located in the fourth conductive layer, and the connection line is located in the display area and the portion extending along the second direction is located in the fifth conductive layer;

[0054] Preferably, the pixel driving circuits in the same row arranged along the first direction are connected to the same gate driving circuit;

[0055] Preferably, the first direction is perpendicular to the second direction;

[0056] Preferably, the first direction is a row direction, and the second direction is a column direction;

[0057] Preferably, the non-display area includes an arc-angle area and a straight-edge area adjacent to the arc-angle area, the display area includes a first display area and a second display area in the second direction, the first display area is adjacent to the straight-edge area, and the second display area is adjacent to the arc-angle area; a partial area of ​​the connection line connected to the pixel driving circuit located in the second display area is located in the display area;

[0058] Preferably, the second display area includes an n-th row of pixel driving circuits and an (n+1)-th row of pixel driving circuits, the number of pixel driving circuits in the (n+1)-th row of pixel driving circuits is less than the number of pixel driving circuits in the n-th row of pixel driving circuits, and a portion of the connecting wire connected to the n-th row of pixel driving circuits located in the fifth conductive layer and a portion of the connecting wire connected to the (n+1)-th row of pixel driving circuits located in the fourth conductive layer are cross-arranged.

[0059] The present application also provides an electronic device, which includes the display panel provided in the present application, or includes a display panel manufactured by the manufacturing method of the display panel provided in the present application.

[0060] Compared with the prior art, this application has the following beneficial effects:

[0061] The display panel and electronic device provided in the present application can reduce the overall area occupied by the gate drive circuit and the connecting lines by setting the connecting lines connected to the gate drive circuit in the border area to at least partially overlap with the gate drive circuit, thereby reducing the border size, especially the border size in the arc corner area. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0063] Figure 1 is a schematic diagram of a conventional display panel;

[0064] Figure 2 A schematic diagram of a region of a display panel provided in this embodiment;

[0065] Figure 3 One of the cross-sectional schematic diagrams of the display panel provided in this embodiment;

[0066] Figure 4a One of the schematic diagrams of the GIP circuit and connection wiring provided in this embodiment;

[0067] Figure 4b The second schematic diagram of the GIP circuit and connection wiring provided in this embodiment;

[0068] Figure 5 The third schematic diagram of the GIP circuit and connection wiring provided in this embodiment;

[0069] Figure 6 The fourth schematic diagram of the GIP circuit and connection wiring provided in this embodiment;

[0070] Figure 7 The fifth schematic diagram of the GIP circuit and connection wiring provided in this embodiment;

[0071] Figure 8 A second cross-sectional schematic diagram of a display panel provided in this embodiment;

[0072] Fig. 9 The third cross-sectional schematic diagram of the display panel provided in this embodiment;

[0073] Fig.10 A fourth cross-sectional schematic diagram of the display panel provided in this embodiment;

[0074] Fig.11 One of the schematic diagrams of the isolation structure provided in this embodiment;

[0075] Fig.12 A second schematic diagram of the isolation structure provided in this embodiment;

[0076] Fig.13 The sixth schematic diagram of the GIP circuit and connection wiring provided in this embodiment;

[0077] Fig.14 A schematic flow chart of the steps of the method for manufacturing a display panel provided in this embodiment.

[0078] Icon: 111-substrate; 112-circuit function layer; 1121-pixel driving circuit; 1122-gate driving circuit; 113-first insulating layer; 114-connecting wiring; 1141-first part; 1142-second part; 901-first scanning driving circuit; 902-second scanning driving circuit; 903-light-emitting control driving circuit; 800-through hole; 120-first electrode; 130-pixel defining layer; 140-isolation structure; 141-supporting part; 142-shielding part; 143-connecting part; 150-light-emitting unit; 160-second electrode; 170-packaging unit; 180-first packaging layer; 190-second packaging layer; 540-shielding structure; 900-touch function layer; AA-display area; NA-non-display area. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0080] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0081] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0082] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0083] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0084] In some display panels, Gate In Panel (GIP) technology is used, and the gate driving circuit (e.g., the circuit for generating scanning signals and the circuit for generating light-emitting control signals) is set in the border area outside the display area, and the gate driving circuit is connected to the pixel driving circuit in the display area through connecting wiring.

[0085] The inventor has found that, please see Figure 1In a display panel using the GIP technology and having an arc angle in the display area AA, the gate driving circuit 1122 in the arc angle area will be arranged in an arc shape. Since the arrangement of the gate driving circuit 1122 and the pixel driving circuit 1121 in the display area AA in the arc angle area is inconsistent, the connecting wire 114 needs to have a larger extension distance to connect the gate driving circuit 1122 and the pixel driving circuit 1121, resulting in an increase in the space occupied by the connecting wire 114, which affects the frame size of the display panel.

[0086] In view of this, the present embodiment provides a solution that can reduce the size of the border of the display panel. The solution provided by the present embodiment is described in detail below.

[0087] See also Figure 2 , Figure 2 A schematic diagram of a region of a display panel provided in this embodiment. The display panel may include a display area AA and a non-display area NA. The non-display area NA at least partially surrounds the display area AA.

[0088] See also Figure 3 The display panel provided in this embodiment may include a substrate 111, a circuit function layer 112, a first insulating layer 113 and a connecting line layer.

[0089] In this embodiment, the material of the substrate 111 may include a rigid material, such as glass; or, the material of the substrate 111 may include a flexible material, such as polyimide (Polyimide, Pi).

[0090] The circuit function layer 112 is located on one side of the substrate 111. The circuit function layer 112 may be composed of multiple film layers. For example, the multiple film layers may include a buffer layer, an active layer, multiple conductive layers, multiple array insulating layers, and a planarization layer. The multiple film layers may form multiple thin film transistors (TFT) at different positions. The thin film transistors cooperate with each other to form multiple pixel driving circuits 1121 or gate driving circuits 1122. The pixel driving circuit 1121 is located in the display area AA and is used to drive the light-emitting device to emit light; the gate driving circuit 1122 is located in the non-display area NA and is used to provide a scanning signal (SCAN) or a light-emitting control signal (EM) for the pixel driving circuit 1121.

[0091] The first insulating layer 113 is located on a side of the circuit function layer 112 away from the substrate 111. The material of the first insulating layer 113 may include an organic material or an inorganic material. Optionally, in some possible implementations, the first insulating layer 113 may be formed of an organic material having a certain fluidity during the manufacturing process, that is, the first insulating layer 113 may achieve planarization while achieving an insulating function.

[0092] The connection line layer is located on a side of the first insulating layer 113 away from the substrate 111, and the connection line layer includes a connection line 114, and the connection line 114 connects the gate driving circuit 1122 and the pixel driving circuit 1121. For example, the connection line 114 is electrically connected to the line in the gate driving circuit 1122 through a through hole 800 that penetrates the first insulating layer 113. The orthographic projection of the connection line 114 on the substrate 111 coincides with the orthographic projection of at least part of the gate driving circuit 1122 on the substrate 111.

[0093] As such, referring to FIG. 4 , by setting the connecting trace 114 connected to the gate driving circuit 1122 in the border area to at least partially overlap with the gate driving circuit 1122, the overall area occupied by the gate driving circuit 1122 and the connecting trace 114 can be reduced, thereby reducing the border size, especially the border size in the arc corner area.

[0094] In this embodiment, the outer contour of the display area AA may include straight edges and arc-angle edges, the non-display area includes an arc-angle area corresponding to the arc-angle edge, and the orthographic projection of the connecting line 114 located in the arc-angle area on the substrate 111 coincides with the orthographic projection of the gate driving circuit 1122 at least partially located in the arc-angle area on the substrate 111.

[0095] Optionally, the non-display area NA further includes a straight edge area adjacent to the arc corner area, and the orthographic projection of the connection trace 114 located in the straight edge area on the substrate 111 coincides with the orthographic projection of the gate driving circuit 1122 located at least partially in the straight edge area on the substrate.

[0096] For example, at least part of the gate driver circuit 1122 may be arranged along a straight edge. For this part of the gate driver circuit 1122, the orthographic projection of the connection trace 114 connecting the gate driver circuit 1122 on the substrate 111 may at least partially overlap with the orthographic projection of the gate driver circuit 1122 itself on the substrate 111.

[0097] In addition, at least part of the gate driving circuits 1122 may be arranged along the arc angle edge. For this part of the gate driving circuits 1122, the orthographic projection of the connection traces 114 connecting the gate circuits on the substrate 111 may at least partially overlap with the orthographic projection of at least one other gate driving circuit 1122 on the substrate 111.

[0098] In some possible implementations, the gate driving circuit 1122 includes at least two sub-circuits, and the at least two sub-circuits are arranged in a direction away from the display area AA.

[0099] The connection line layer includes at least two connection traces 114, and at least two sub-circuits are connected to the pixel driving circuit 1121 via corresponding connection traces 114. The orthographic projection of the connection trace 114 on the substrate 111 at least partially overlaps with the orthographic projection of at least one sub-circuit on the substrate 111.

[0100] Optionally, different connection traces 114 are respectively connected to different sub-circuits through through holes 800 penetrating the first insulating layer 113. The orthographic projection of the through hole 800 on the substrate 111 is located on a side of the substrate 111 away from the display area AA of at least one sub-circuit.

[0101] Optionally, the sub-circuit includes an active layer, and the orthographic projection of the through hole 800 on the substrate 111 is located on a side of the orthographic projection of the active layer of at least one sub-circuit on the substrate 111 away from the display area AA.

[0102] For example, the subcircuit includes a transistor formed by an active layer and a conductive layer, and the orthographic projection of the through hole 800 on the substrate 111 is located on the side of the orthographic projection of the active layer of the thin film transistor forming the subcircuit on the substrate 111 away from the display area AA.

[0103] Optionally, the orthographic projection of the through hole 800 on the substrate 111 is located between the orthographic projections of the active layers of two adjacent sub-circuits on the substrate 111 .

[0104] Optionally, see Figure 5 In a possible implementation, the sub-circuit of the gate driving circuit 1122 includes a first scanning driving circuit 901, a second scanning driving circuit 902 and a light emitting control driving circuit 903 arranged in a direction away from the display area AA.

[0105] The orthographic projection of the through hole 800 on the substrate 111 is located between the orthographic projections of the first scan driving circuit 901 and the second scan driving circuit 902 on the substrate 111 , and the orthographic projection of the connecting trace 114 on the substrate 111 coincides with the orthographic projection of the first scan driving circuit 901 on the substrate 111 .

[0106] Optionally, the orthographic projection of the through hole 800 on the substrate 111 is located between the orthographic projection of the active layer of the first scan driving circuit 901 and the orthographic projection of the active layer of the second scan driving circuit 902 on the substrate 111 .

[0107] See also Figure 6 In another possible implementation, the sub-circuit of the gate driving circuit 1122 includes a first scanning driving circuit 901, a second scanning driving circuit 902 and a light emitting control driving circuit 903 arranged in a direction away from the display area AA.

[0108] The orthographic projection of the through hole 800 on the substrate 111 is located between the orthographic projections of the second scan drive circuit 902 and the light emitting control drive circuit 903 on the substrate 111 , and the orthographic projection of the connecting trace 114 on the substrate 111 coincides with the orthographic projections of the first scan drive circuit 901 and the second scan drive circuit 902 on the substrate 111 .

[0109] Optionally, the orthographic projection of the through hole 800 on the substrate 111 is located between the orthographic projections of the active layer of the second scan driving circuit 902 and the active layer of the light emitting control driving circuit 903 on the substrate 111 .

[0110] See also Figure 7 In another possible implementation, the sub-circuit of the gate driving circuit 1122 includes a first scanning driving circuit 901, a second scanning driving circuit 902 and a light emitting control driving circuit 903 arranged in a direction away from the display area AA.

[0111] The orthographic projection of the through hole 800 on the substrate 111 is located on the side of the orthographic projection of the light-emitting control driving circuit 903 on the substrate 111 away from the display area AA, and the orthographic projection of the connecting trace 114 on the substrate 111 coincides with the orthographic projections of the first scanning driving circuit 901, the second scanning driving circuit 902 and the light-emitting control driving circuit 903 on the substrate 111.

[0112] Optionally, the orthographic projection of the through hole 800 on the substrate 111 is located on a side of the orthographic projection of the active layer of the light emitting control driving circuit 903 on the substrate 111 away from the display area AA.

[0113] For some possible implementations, see Figure 8 The display panel may further include an isolation structure 140 located on a side of the connection line layer away from the substrate 111 .

[0114] The isolation structure 140 is located in the display area AA, and the isolation structure 140 includes an isolation opening.

[0115] Optionally, the display panel further includes a light emitting device at least partially located in the isolation opening. The light emitting device includes a first electrode 120, a light emitting unit 150, and a second electrode 160 stacked in a direction away from the substrate 111; the first electrode 120 is electrically connected to the pixel driving circuit 1121; at least a portion of the isolation structure 140 is conductive, and the second electrode 160 is electrically connected to the isolation structure 140.

[0116] Among them, patent applications PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 record relevant technical solutions of the isolation structure 140, and their contents are incorporated into this application by reference for reference.

[0117] Please see again Figure 8 The display panel further includes a shielding structure 540 disposed in the same layer as the isolation structure 140. That is, the isolation structure 140 and the shielding structure 540 can be formed in the same manufacturing step. The isolation structure 140 and the shielding structure 540 can be disposed at intervals.

[0118] The shielding structure 540 is located in the non-display area NA, and the orthographic projection of the gate driving circuit 1122 on the substrate 111 at least partially overlaps with the orthographic projection of the shielding structure 540 on the substrate 111. For example, the orthographic projection of the gate driving circuit 1122 on the substrate 111 is located within the orthographic projection of the shielding structure 540 on the substrate 111.

[0119] In this way, the shielding structure 540 manufactured on the same layer as the isolation structure 140 can serve as a shielding layer for the gate driving circuit 1122 to shield the gate driving circuit 1122 from the influence of other circuits.

[0120] Optionally, see some possible implementations. Fig. 9 The display panel further includes a touch function layer 900 located on a side of the isolation structure 140 and the shielding structure 540 away from the substrate 111. Optionally, the orthographic projection of the touch function layer 900 on the substrate 111 at least partially overlaps with the orthographic projection of the shielding structure 540 on the substrate 111.

[0121] That is, in this embodiment, the shielding structure 540 is located between the touch function layer 900 and the gate driving circuit 1122. In this way, the shielding structure 540 can reduce the signal coupling between the touch function layer 900 and the gate driving circuit 1122, avoid signal interference, and thus improve the display effect and touch detection effect.

[0122] For some possible implementations, see Fig.10 The display panel provided in this embodiment may further include a packaging unit 170 located on a side of the light-emitting device away from the substrate 111 , and at least a portion of the packaging unit 170 extends from the isolation opening to a side of the isolation structure 140 away from the substrate 111 .

[0123] Optionally, there is a gap between the packaging units 170 corresponding to at least some of the adjacent isolation openings, and the gap is located on a side of the isolation structure 140 away from the substrate 111 .

[0124] In some possible implementations, the display panel provided in this embodiment further includes a first encapsulation layer 180 and a second encapsulation layer 190 which are located on a side of the encapsulation unit 170 and the isolation structure 140 away from the substrate 111 and are stacked in a direction away from the substrate 111 .

[0125] Optionally, the materials of the encapsulation unit 170 and the second encapsulation layer 190 include inorganic materials, and the material of the first encapsulation layer 180 includes organic materials. For example, the encapsulation unit 170 and the second encapsulation layer 190 can be formed by chemical vapor deposition (CVD), and the first encapsulation layer 180 can be formed by inkjet printing (IJP).

[0126] For some possible implementations, see Fig.11 The isolation structure 140 includes a support portion 141 and a shielding portion 142 located on a side of the support portion 141 away from the substrate 111, and the orthographic projection of the support portion 141 on the substrate 111 is located within the orthographic projection of the shielding portion 142 on the substrate 111. That is, the support portion 141 is retracted relative to the shielding portion 142 to form an undercut structure.

[0127] Optionally, the etching resistance of the support portion 141 is smaller than the etching resistance of the shielding portion 142 .

[0128] Optionally, the material of the support portion 141 includes aluminum, and / or the material of the shielding portion 142 includes titanium.

[0129] For some possible implementations, see Fig.12 The isolation structure 140 further includes a connecting portion 143 located between the supporting portion 141 and the substrate 111 , and an orthographic projection of the supporting portion 141 on the substrate 111 is located within an orthographic projection of the connecting portion 143 on the substrate 111 .

[0130] Optionally, the orthographic projection of the connecting portion 143 on the substrate 111 is located within the orthographic projection of the shielding portion 142 on the substrate 111 .

[0131] Optionally, the material of the connection portion 143 includes molybdenum.

[0132] In some possible implementations, the display panel includes a data signal line connected to the pixel driving circuit 1121 , the data signal line and the connecting line are arranged on the same layer, and the data signal line is used to provide a data signal Data to the pixel driving circuit 1121 .

[0133] Optionally, along the direction away from the substrate 1111, the display panel includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence, and the connecting line is located in the fifth conductive layer. An insulating layer or a planarization layer may also be provided between adjacent conductive layers. Among them, the first insulating layer 113 is located between the fourth conductive layer and the fifth conductive layer. Among them, the display panel can be an LTPO display panel, and the pixel driving circuit 1121 of the display panel has both oxide transistors and low-temperature polysilicon transistors.

[0134] The present embodiment further provides a display panel, wherein the display panel may include a display area AA and a non-display area NA, wherein the non-display area NA at least partially surrounds the display area AA.

[0135] The display panel provided in this embodiment may include a substrate 111 , a pixel driving circuit 1121 , a gate driving circuit 1122 , and a connection circuit layer.

[0136] The pixel driving circuit 1121 and the gate driving circuit 1122 are located on one side of the substrate 111 , the pixel driving circuit 1121 is located in the display area AA, and the gate driving circuit 1122 is located in the non-display area.

[0137] The connection circuit layer is located on one side of the substrate 111 . The connection circuit layer includes connection traces 114 . The connection traces 114 connect the gate driving circuit 1122 and the pixel driving circuit 1121 .

[0138] The orthographic projection of the connection line 114 on the substrate 111 coincides with the orthographic projection of at least a portion of the gate driving circuit 1122 on the substrate 111 ; and / or, a portion of the connection line 504 is located within the display area AA.

[0139] In some possible implementations, the display panel further includes a first insulating layer 113 , which is located on a side of the pixel driving circuit 1121 and the gate driving circuit 1122 away from the substrate 111 , and the connecting trace 301 is located on a side of the first insulating layer 113 away from the substrate.

[0140] In this way, the connecting line 301 and the gate driving circuit 1122 are on different layers, so the connecting line 301 and the gate driving circuit 1122 can be overlapped, that is, the orthographic projection of the connecting line 114 on the substrate 111 can coincide with the orthographic projection of at least part of the gate driving circuit 1122 on the substrate 111.

[0141] In some other possible implementations, a portion of the connection trace 504 is located in the display area AA. The connection line layer includes a fourth conductive layer and a fifth conductive layer stacked in a direction away from the substrate 111. At least a portion of the connection trace 114 located in the display area AA is located in the fourth conductive layer, and at least a portion of the connection trace 114 is located in the fifth conductive layer.

[0142] Optionally, the gate driving circuit 1122 may also include traces or electrodes located in the fourth conductive layer.

[0143] Optionally, see Fig.13 , the portion of the connecting wire 114 located in the display area AA and extending along the first direction D1 (e.g., the first portion 1141) is located in the fourth conductive layer, and the portion of the connecting wire 114 located in the display area AA and extending along the second direction D2 (e.g., the second portion 1142) is located in the fifth conductive layer. In this way, the second portion 1142 of the connecting wire 114 located in the fifth conductive layer can avoid other wires extending along the first direction D1 in the display area AA to prevent short circuit of the wires.

[0144] Optionally, the pixel driving circuits 1121 in the same row arranged along the first direction D1 are connected to the same gate driving circuit 1122. Optionally, the first direction D1 is perpendicular to the second direction D2. That is, the first direction D1 may be the direction in which the scan line extends, and the second direction D2 may be the direction in which the data line extends.

[0145] In this embodiment, the connecting line 114 led out from the gate driving circuit 1122 can first extend to the vicinity of a row of pixel driving circuits 1122 located in the display area AA, and then the fourth conductive layer extends along the first direction D2 and overlaps with at least part of the gate driving circuit 1122, and then switches to the fifth conductive layer to extend along the second direction D2 to avoid the signal line extending along the first direction D1 in the display area AA until it extends to the corresponding gate driving circuit 1122.

[0146] In this way, at least a portion of the connection line 114 overlaps with the pixel driving circuit 1122 located in the display area AA, which can reduce the occupied area of ​​the connection line 114, thereby reducing the frame size, especially the frame size of the arc corner area.

[0147] Optionally, the non-display area NA includes an arc angle area and a straight edge area adjacent to the arc angle area, and the display area AA includes a first display area and a second display area in the second direction D2, the first display area is adjacent to the straight edge area, and the second display area is adjacent to the arc angle area. Part of the connection line 114 connected to the pixel driving circuit 1121 located in the second display area is located in the display area AA.

[0148] For example, the shape of the first display area may be a rectangle, and the second display area may be located on at least one side of the first display area in the second direction D2, and the number of pixel driving circuits in each row of pixel driving circuits in the second display area decreases along the direction away from the first display area, thereby forming an arc contour at the position corresponding to the arc corner area.

[0149] Optionally, the second display area includes an n-th row of pixel driving circuits and an (n+1)-th row of pixel driving circuits, the number of pixel driving circuits 1121 in the (n+1)-th row of pixel driving circuits is less than the number of pixel driving circuits 1121 in the n-th row of pixel driving circuits, and a portion of a connecting wire 114 connected to the n-th row of pixel driving circuits located in the fifth conductive layer and a portion of a connecting wire 114 connected to the (n+1)-th row of pixel driving circuits located in the fourth conductive layer are cross-arranged.

[0150] The (n+1)th row of pixel driving circuits is located on a side of the nth row of pixel driving circuits away from the center of the display area AA.

[0151] In this way, it is possible to avoid the connection wires 114 corresponding to the pixel driving circuits in different rows from crossing each other on the same layer to cause a short circuit.

[0152] See also Fig.14 This embodiment also provides a method for manufacturing a display panel. The display panel includes a display area AA and a non-display area NA surrounding at least a portion of the display area AA. The method may include the following steps.

[0153] Step S110 , providing a substrate 111 .

[0154] In step S120 , a circuit function layer 112 is disposed on one side of the substrate 111 . The circuit function layer 112 includes a pixel driving circuit 1121 located in the display area AA and a gate driving circuit 1122 located in the display area AA.

[0155] Step S130 , disposing a first insulating layer 113 on a side of the circuit function layer 112 away from the substrate 111 .

[0156] In step S140, a connecting circuit layer is provided on a side of the first insulating layer 113 away from the substrate 111, wherein the connecting circuit layer includes a connecting wire 114, and the connecting wire 114 connects the gate driving circuit 1122 and the pixel driving circuit 1121; the orthographic projection of the connecting wire 114 on the substrate 111 coincides with the orthographic projection of at least part of the gate driving circuit 1122 on the substrate 111.

[0157] Optionally, in this embodiment, the connection trace 114 may be electrically connected to the gate driving circuit 1122 through a through hole 800 penetrating the first insulating layer 113 .

[0158] The present application also provides an electronic device, which includes the display panel provided in the present application, or includes a display panel manufactured by the method for manufacturing a display panel provided in the present application. The electronic device may include a mobile phone, a tablet computer, a smart wearable device, a television, a laptop computer, a monitor, and other devices with a display function.

[0159] In summary, the display panel and electronic device provided by the present application can reduce the overall area occupied by the gate driving circuit and the connecting lines by setting the connecting lines connected to the gate driving circuit in the border area to at least partially overlap with the gate driving circuit, thereby reducing the border size, especially the border size in the arc corner area.

[0160] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a non-display area surrounding at least a portion of the display area, and the display panel comprises: substrate; A circuit function layer located on one side of the substrate, the circuit function layer comprising a pixel driving circuit located in a display area and a gate driving circuit located in a non-display area; A first insulating layer located on a side of the circuit function layer away from the substrate; A connection circuit layer is located on a side of the first insulating layer away from the substrate, the connection circuit layer includes a connection line, the connection line connects the gate drive circuit and the pixel drive circuit; the orthographic projection of the connection line on the substrate coincides with the orthographic projection of at least part of the gate drive circuit on the substrate.

2. The display panel according to claim 1, characterized in that: The gate driving circuit comprises at least two sub-circuits, and the at least two sub-circuits are arranged in a direction away from the display area; the connecting circuit layer comprises at least two connecting wires; the at least two sub-circuits are connected to the pixel driving circuit through the corresponding connecting wires; the orthographic projection of the connecting wire on the substrate at least partially overlaps with the orthographic projection of at least one of the sub-circuits on the substrate; Preferably, different connecting wires are respectively connected to different sub-circuits through through holes penetrating the first insulating layer; the orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of at least one sub-circuit on the substrate away from the display area; Preferably, the orthographic projection of the through hole on the substrate is located between the orthographic projections of two adjacent sub-circuits on the substrate; Preferably, the sub-circuit comprises an active layer; the orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of the active layer of at least one of the sub-circuit on the substrate away from the display area; Preferably, the orthographic projection of the through hole on the substrate is located between the orthographic projections of the active layers of two adjacent sub-circuits on the substrate.

3. The display panel according to claim 2, characterized in that: The sub-circuit of the gate driving circuit includes a first scanning driving circuit, a second scanning driving circuit and a light emitting control driving circuit arranged in a direction away from the display area; The orthographic projection of the through hole on the substrate is located between the orthographic projections of the first scan driving circuit and the second scan driving circuit on the substrate, and the orthographic projection of the connecting wire on the substrate coincides with the orthographic projection of the first scan driving circuit on the substrate; Preferably, the sub-circuit comprises an active layer; and an orthographic projection of the through hole on the substrate is located between an orthographic projection of the active layer of the first scan driving circuit and an orthographic projection of the active layer of the second scan driving circuit on the substrate.

4. The display panel according to claim 2, characterized in that: The sub-circuit of the gate driving circuit includes a first scanning driving circuit, a second scanning driving circuit and a light emitting control driving circuit arranged in a direction away from the display area; The orthographic projection of the through hole on the substrate is located between the orthographic projections of the second scan drive circuit and the light emitting control drive circuit on the substrate, and the orthographic projection of the connecting wire on the substrate coincides with the orthographic projections of the first scan drive circuit and the second scan drive circuit on the substrate; Preferably, the sub-circuit comprises an active layer; and an orthographic projection of the through hole on the substrate is located between an orthographic projection of the active layer of the second scanning driving circuit and an orthographic projection of the active layer of the light emitting control driving circuit on the substrate.

5. The display panel according to claim 2, characterized in that: The sub-circuit of the gate driving circuit includes a first scanning driving circuit, a second scanning driving circuit and a light emitting control driving circuit arranged in a direction away from the display area; The orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of the light emitting control driving circuit on the substrate away from the display area, and the orthographic projection of the connecting wire on the substrate coincides with the orthographic projections of the first scanning driving circuit, the second scanning driving circuit and the light emitting control driving circuit on the substrate; Preferably, the sub-circuit comprises an active layer; and the orthographic projection of the through hole on the substrate is located on a side of the orthographic projection of the active layer of the light emitting control driving circuit on the substrate away from the display area.

6. The display panel according to claim 1, characterized in that: The display panel further includes: An isolation structure located on a side of the connection line layer away from the substrate; the isolation structure is located in the display area, and the isolation structure includes an isolation opening; The display panel further includes a light emitting device at least partially located within the isolation opening; The light emitting device comprises a first electrode, a light emitting unit and a second electrode which are stacked and arranged in a direction away from the substrate; the first electrode is electrically connected to the pixel driving circuit.

7. The display panel according to claim 6, characterized in that: The display panel further includes a shielding structure disposed on the same layer as the isolation structure, the shielding structure being located in the non-display area, and the orthographic projection of the gate driving circuit on the substrate at least partially overlaps with the orthographic projection of the shielding structure on the substrate.

8. The display panel according to claim 7, characterized in that: The display panel further comprises a touch function film layer located on a side of the isolation structure and the shielding structure away from the substrate; Preferably, an orthographic projection of the touch-sensitive functional film layer on the substrate at least partially overlaps with an orthographic projection of the shielding structure on the substrate.

9. The display panel according to claim 6, characterized in that: The display panel further comprises an encapsulation unit located at a side of the light emitting device away from the substrate, wherein at least a portion of the encapsulation unit extends from the isolation opening to a side of the isolation structure away from the substrate; Preferably, there is a gap between the packaging units corresponding to at least some of the adjacent isolation openings, and the gap is located on a side of the isolation structure away from the substrate; Preferably, the display panel further comprises a first encapsulation layer and a second encapsulation layer which are located on a side of the encapsulation unit and the isolation structure away from the substrate and are stacked in a direction away from the substrate; The materials of the encapsulation unit and the second encapsulation layer include inorganic materials, and the material of the first encapsulation layer includes organic materials.

10. The display panel according to claim 6, characterized in that: The isolation structure comprises a supporting portion and a shielding portion located on a side of the supporting portion away from the substrate, wherein an orthographic projection of the supporting portion on the substrate is located within an orthographic projection of the shielding portion on the substrate; Preferably, the etching resistance of the supporting portion is less than that of the shielding portion; Preferably, the material of the support portion includes aluminum, and / or the material of the shielding portion includes titanium; Preferably, the isolation structure further comprises a connecting portion located between the supporting portion and the substrate, and an orthographic projection of the supporting portion on the substrate is located within an orthographic projection of the connecting portion on the substrate; Preferably, the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the shielding portion on the substrate; Preferably, the material of the connecting portion includes molybdenum.

11. The display panel according to claim 1, characterized in that: The non-display area includes an arc angle area, and an orthographic projection of the connection line located in the arc angle area on the substrate coincides with an orthographic projection of the gate driving circuit at least partially located in the arc angle area on the substrate; Preferably, the non-display area also includes a straight edge area adjacent to the arc angle area, and the orthographic projection of the connecting line located in the straight edge area on the substrate coincides with the orthographic projection of the gate driving circuit at least partially located in the straight edge area on the substrate.

12. The display panel according to claim 1, characterized in that: The display panel comprises a data signal line connected to the pixel driving circuit, wherein the data signal line and the connection line are arranged in the same layer; Preferably, along a direction away from the substrate, the display panel comprises a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence, and the connecting wire is located in the fifth conductive layer; Preferably, the first insulating layer is located between the fourth conductive layer and the fifth conductive layer.

13. A display panel, characterized in that: The display panel comprises a display area and a non-display area surrounding at least a portion of the display area, and the display panel comprises: substrate; A pixel driving circuit located in the display area and a gate driving circuit located in the non-display area; A connection circuit layer located on one side of the substrate, the connection circuit layer comprising connection wires, and the connection wires are connected to the gate driving circuit and the pixel driving circuit; The orthographic projection of the connecting wire on the substrate coincides with the orthographic projection of at least part of the gate driving circuit on the substrate; and / or a partial area of ​​the connecting wire is located within the display area.

14. The display panel according to claim 13, characterized in that: The display panel further includes: The first insulating layer is located on a side of the pixel driving circuit and the gate driving circuit away from the substrate; the connecting wire is located on a side of the first insulating layer away from the substrate.

15. The display panel according to claim 13, characterized in that: The connection line layer includes a fourth conductive layer and a fifth conductive layer stacked in a direction away from the substrate; at least part of the connection line located in the display area is located in the fourth conductive layer, and at least part of the connection line is located in the fifth conductive layer; Preferably, the portion of the connecting wire located in the display area and extending along the first direction is located in the fourth conductive layer, and the portion of the connecting wire located in the display area and extending along the second direction is located in the fifth conductive layer; Preferably, the pixel driving circuits in the same row arranged along the first direction are connected to the same gate driving circuit; Preferably, the first direction is perpendicular to the second direction; Preferably, the first direction is a row direction, and the second direction is a column direction; Preferably, the non-display area includes an arc-angle area and a straight-edge area adjacent to the arc-angle area, the display area includes a first display area and a second display area in the second direction, the first display area is adjacent to the straight-edge area, and the second display area is adjacent to the arc-angle area; a partial area of ​​the connection line connected to the pixel driving circuit located in the second display area is located in the display area; Preferably, the second display area includes an n-th row of pixel driving circuits and an (n+1)-th row of pixel driving circuits, the number of pixel driving circuits in the (n+1)-th row of pixel driving circuits is less than the number of pixel driving circuits in the n-th row of pixel driving circuits, and a portion of the connecting wire connected to the n-th row of pixel driving circuits located in the fifth conductive layer and a portion of the connecting wire connected to the (n+1)-th row of pixel driving circuits located in the fourth conductive layer are cross-arranged.

16. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1-15.

Images