Multi-chip IGBT module chip open-circuit failure monitoring method and system

Abstract

The present invention relates to the technical field of IGBT module monitoring, and specifically discloses a method and system for monitoring chip open-circuit failure of a multi-chip IGBT module. First, the health-sensitive parameters for monitoring chip open-circuit failure of the multi-chip IGBT module are determined. Then, the values of the health-sensitive parameters of the multi-chip IGBT module are measured and converted into an analog voltage signal V<subgt;PG< / subgt>. Next, the failure threshold V<subgt;REF3< / subgt> of the analog voltage signal V<subgt;PG< / subgt> for determining chip open-circuit failure of the multi-chip IGBT module is determined. Finally, the measured analog voltage signal V<subgt;PG< / subgt> is compared with the failure threshold V<subgt;REF3< / subgt> to determine whether chip open-circuit failure occurs in the multi-chip IGBT module. Without unsealing the package of the multi-chip IGBT module, the present invention realizes the monitoring of chip open-circuit failure of the multi-chip IGBT module, and only needs to collect the gate voltage signal, with few influencing factors, easy to measure, non-invasive, can be plug-and-play or integrated in the drive circuit, and is easy to realize in-situ monitoring of chip open-circuit failure of the multi-chip IGBT module.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBT module monitoring, and in particular to a method and system for monitoring chip open circuit failure in a multi-chip IGBT module. Background Art

[0002] Insulated gate bipolar transistor (IGBT) modules are widely used in industrial fields such as rail transit, electric vehicles, and renewable energy generation. In high-power power electronic converters, multi-chip IGBT modules, consisting of multiple IGBT and diode chips connected in parallel, are often used to improve the current-carrying capacity of the power module. Safety and long-term reliability remain key concerns in power electronic converter design. However, surveys have shown that IGBT modules have the highest probability of failure in power electronic converters. Bond wire failure is the primary failure mode in IGBT modules. In multi-chip IGBT modules, due to differences in chip characteristics and package layout, the bond wires on the chip subject to greater electrothermal stress fail first, accelerating the failure of the remaining bond wires on the chip, ultimately leading to chip open-circuit failure. Therefore, introducing condition monitoring technology to identify chip open-circuit failures in multi-chip IGBT modules has become a cost-effective method for improving the reliability of high-power power electronic converters.

[0003] Extensive research has been conducted on monitoring chip open-circuit failures in multi-chip IGBT modules. Existing methods can be divided into sensor methods and health-sensitive parameter methods. The sensor method requires the installation of additional sensors within the module, significantly increasing monitoring costs and device operational risks. The health-sensitive parameter method, on the other hand, is widely used due to its fast response speed and low invasiveness. Depending on the influencing mechanism of bond wire failure, the health-sensitive parameter method can be further divided into resistance- and inductance-based monitoring methods and capacitance-based monitoring methods. While the resistance- and inductance-based monitoring method can identify chip open-circuit failures, its discrimination is low and it is easily affected by partial bond wire failures. In contrast, the capacitance-based monitoring method can avoid the interference of partial bond wire failures and has a high discrimination, making it the most promising method for monitoring chip open-circuit failures.

[0004] At present, the main monitoring methods based on capacitance are: opening delay time t don , turn-off delay time t doff , front threshold voltage V GE(pre-th) , gate charge Q G , crosstalk voltage V GEB , turn-off voltage change rate dV CE / dt, gate voltage fall time t gfetc. However, the above methods have disadvantages such as many influencing factors, high invasiveness, susceptibility to power circuit interference, and difficulty in measurement, which are not conducive to realizing in-situ monitoring of chip open-circuit failure of multi-chip IGBT modules. Summary of the Invention

[0005] The present invention provides a method and system for monitoring chip open-circuit failure of a multi-chip IGBT module, and the technical problem to be solved is that the existing methods for monitoring chip open-circuit failure of a multi-chip IGBT module have many influencing factors, high invasiveness, susceptibility to interference, small discrimination, and difficulty in measurement.

[0006] To solve the above technical problems, the present invention provides a method for monitoring chip open-circuit failure of a multi-chip IGBT module, including the steps of:

[0007] Determine a health-sensitive parameter for monitoring chip open-circuit failure of the multi-chip IGBT module, which is related to the number n of effective chip branches in the multi-chip IGBT module and is at least not affected by the bus voltage and load current;

[0008] Measure the value of the health-sensitive parameter of the multi-chip IGBT module and convert it into an analog voltage signal V PG ;

[0009] Determine a failure threshold V PG of the analog voltage signal V REF3 for determining that the multi-chip IGBT module has a chip open-circuit failure;

[0010] Based on the measured analog voltage signal V PG and the failure threshold V REF3 determine whether the multi-chip IGBT module has a chip open-circuit failure.

[0011] Further, the health-sensitive parameter is determined as the time when the gate voltage of the multi-chip IGBT module rises from 0 to a set voltage V SET , that is, the gate voltage pre-charge time t PG , and the set voltage V SET is set below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module.

[0012] Further, by comparing the measured analog voltage signal V PG with the failure threshold V REF3 , if V PG is lower than the failure threshold V REF3 , it is determined that the multi-chip IGBT module has a chip open-circuit failure; if V PG is higher than the failure threshold V REF3 , it is determined that the multi-chip IGBT module has not had a chip open-circuit failure.

[0013] Further, measure the health - sensitive parameter values of the multi - chip IGBT module and convert them into an analog voltage signal V PG Specifically, it includes the steps of:

[0014] Capture the equivalent pulses of the gate voltage signal during the turn - on and turn - off processes of the multi - chip IGBT module;

[0015] Obtain a digital pulse representing the gate voltage pre - charging time t PG based on the captured equivalent pulses of the turn - on and turn - off processes of the multi - chip IGBT module;

[0016] Eliminate the pulses during the turn - off process in the digital pulse of the gate voltage pre - charging time t PG and convert the obtained pulse into an analog voltage signal V PG with an amplitude representing t PG .

[0017] Further, the capturing of the equivalent pulses of the gate voltage signal during the turn - on and turn - off processes of the multi - chip IGBT module specifically includes the steps of:

[0018] Perform voltage matching on the collected gate voltage signal of the multi - chip IGBT module through a voltage divider composed of voltage - dividing resistors R1 and R2;

[0019] Lift the output voltage V ge of the voltage divider by a DC voltage E C to ensure that the output signal V gep of the non - inverting summing amplifier is within the allowable input voltage range of the window comparator;

[0020] Input the output signal V gep of the non - inverting summing amplifier to the window comparator, and compare it with the input reference voltages V REF1 and V REF2 respectively, and output the corresponding comparison results V a and V b , V REF2 i.e., the set voltage V SET ;

[0021] The comparison results V a and V b are respectively output to the logic sub - circuit through digital isolators U4 and U5 to obtain the equivalent pulses of the turn - on and turn - off processes of the multi - chip IGBT module.

[0022] Further, the obtaining of the digital pulse representing the gate voltage pre - charging time t PG based on the captured equivalent pulses of the turn - on and turn - off processes of the multi - chip IGBT module specifically includes the steps of:

[0023] Input the output signal Va and V b The corresponding equivalent pulses are input into the logic AND gate U6 to obtain the digital pulse V represented by the pulse width gg ;

[0024] The output signal V of the window comparator b The corresponding equivalent pulses are input into the RC delay circuit, and the output signal of the RC delay circuit and the equivalent pulses corresponding to V b are input into the logic AND gate U7 together to obtain the enable signal OE.

[0025] Furthermore, the pulses in the off process of the digital pulses for eliminating the gate voltage pre-charge time t PG are eliminated, and the obtained pulses are converted into an analog voltage signal V whose amplitude represents t PG Specifically, it includes the steps: PG

[0026] The output signal V of the logic AND gate U6 gg is input into the signal input terminal of the tri-state buffer U8, and the output signal OE of the logic AND gate U7 is input into the enable terminal of the tri-state buffer U8;

[0027] The output signal V of the tri-state buffer U8 buf is input into the RC integration circuit composed of the resistor R8 and the capacitor C3 to obtain an analog voltage signal V whose amplitude represents t PG PG .

[0028] Furthermore, determining whether the multi-chip IGBT module has a chip open-circuit failure based on the measured analog voltage signal V PG and the failure threshold V REF3 Specifically, it includes the steps:

[0029] The enable signal OE passes through the RC delay circuit and the logic NOT gate U 10 to obtain the clock signal CLK of the D flip-flop U 11 ;

[0030] The output signal V PG and the input reference voltage V REF3 are input into the high-speed comparator U9 for comparison;

[0031] The output signal of the high-speed comparator U9 is input into the data input terminal of the D flip-flop U 11 ;

[0032] The D flip-flop U 11 outputs a voltage signal V characterizing the health state of the chip branch of the multi-chip IGBT module dia ;

[0033] If the output voltage V​​dia If it is at a low level, the multi-chip IGBT module is in a healthy state;

[0034] If the output voltage V dia is at a high level, a chip open-circuit failure occurs in the multi-chip IGBT module.

[0035] The present invention also provides a monitoring system for chip open-circuit failure of a multi-chip IGBT module, which applies the monitoring method for chip open-circuit failure of the multi-chip IGBT module. The key lies in that: the system includes a health-sensitive parameter determination module, a measurement module, a failure threshold determination module, and a diagnosis module. The health-sensitive parameter determination module is used to determine the health-sensitive parameters for monitoring the chip open-circuit failure of the multi-chip IGBT module. The measurement module is used to measure the values of the health-sensitive parameters of the multi-chip IGBT module and convert them into an analog voltage signal V PG , the failure threshold determination module is used to determine the failure threshold V PG of the analog voltage signal V REF3 for determining that a chip open-circuit failure occurs in the multi-chip IGBT module. The diagnosis module determines whether a chip open-circuit failure occurs in the multi-chip IGBT module based on the measured analog voltage signal V PG and the failure threshold V REF3 .

[0036] Preferably, the measurement module adopts a measurement circuit, and the measurement circuit includes a signal processing sub-circuit, a logic sub-circuit, and a signal conversion sub-circuit;

[0037] The signal processing sub-circuit includes a resistor voltage divider composed of voltage-dividing resistors R1 and R2, a non-inverting adder composed of a high-speed operational amplifier U1, resistors R3, R4, R5, R6, and a capacitor C1, a window comparator composed of high-speed comparators U2 and U3, digital isolators U4 and U5, input reference voltages V REF1 , V REF2 , a DC voltage E C ; the voltage-dividing resistors R1 and R2 are connected in series and then coupled between the gate G and the auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the series connection of the voltage-dividing resistors R1 and R2 is coupled to the non-inverting input terminal of the high-speed operational amplifier U1 through the resistor R4. The DC voltage E C is coupled to the non-inverting terminal of the high-speed operational amplifier U1 through the resistor R5. The resistor R3 is coupled between the inverting input terminal of the high-speed operational amplifier U1 and the reference ground. The resistor R6 and the capacitor C1 are connected in parallel and then coupled between the inverting input terminal and the output terminal of the high-speed operational amplifier U1. The output terminal of the high-speed operational amplifier U1 is respectively coupled to the non-inverting input terminal of the high-speed comparator U2 and the inverting input terminal of the high-speed comparator U3. The input reference voltages V REF1 , V REF2They are respectively coupled to the inverting input terminal of the high-speed comparator U2 and the non-inverting input terminal of the high-speed comparator U3, and the outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the input terminals of the digital isolators U4 and U5;

[0038] The logic sub-circuit includes an RC delay circuit composed of a resistor R7 and a capacitor C2 and two logic AND gates U6 and U7; the resistor R7 and the capacitor C2 are connected in series and then coupled between the output terminal of the digital isolator U4 and the digital reference ground. The input terminals of the logic AND gate U6 are respectively coupled to the midpoint of the RC delay circuit and the output terminal of the digital isolator U4, and the input terminals of the logic AND gate U7 are respectively coupled to the output terminal of the digital isolator U4 and the output terminal of the digital isolator U5;

[0039] The signal conversion sub-circuit includes a tri-state buffer U8 and an RC integration circuit composed of a resistor R8 and a capacitor C3; the enable terminal of the tri-state buffer U8 is coupled to the output terminal of the logic AND gate U6, the signal input terminal of the tri-state buffer U8 is coupled to the output terminal of the logic AND gate U7, the resistor R8 and the capacitor C3 are connected in series and then coupled between the output terminal of the tri-state buffer U8 and the digital reference ground, and the output voltage at the midpoint of the series connection of the resistor R8 and the capacitor C3 is V which characterizes the pre-charge time of the gate voltage PG .

[0040] For the multi-chip IGBT module chip open-circuit failure monitoring method and system provided by the present invention, first, the health-sensitive parameters for monitoring the chip open-circuit failure of the multi-chip IGBT module are determined, then the values of the health-sensitive parameters of the multi-chip IGBT module are measured and converted into an analog voltage signal V PG , and then the analog voltage signal V PG for determining that the multi-chip IGBT module has a chip open-circuit failure is determined, and the failure threshold V REF3 is obtained. Finally, the measured analog voltage signal V PG is compared with the failure threshold V REF3 to determine whether the multi-chip IGBT module has a chip open-circuit failure. Without unpacking the package of the multi-chip IGBT module, the present invention realizes the monitoring of the chip open-circuit failure of the multi-chip IGBT module, and only needs to collect the gate voltage signal. It has few influencing factors, is easy to measure, is non-invasive, can be plug-and-play or integrated into the drive circuit, and is easy to realize the in-situ monitoring of the chip open-circuit failure of the multi-chip IGBT module, having strong practical application value. Description of the Drawings

[0041] Figure 1 is a flowchart of the multi-chip IGBT module chip open-circuit failure monitoring method provided by an embodiment of the present invention;

[0042] Figure 2 is the structure and circuit diagram of the multi-chip IGBT module provided by an embodiment of the present invention;

[0043] Figure 3 is the waveform diagram of the collector-emitter voltage v CE , collector current i C , gate voltage v GE , and gate current i G during the turn-on process of the multi-chip IGBT module provided by the embodiment of the present invention;

[0044] Figure 4 is the circuit diagram of the measurement circuit provided by the embodiment of the present invention;

[0045] Figure 5 is the ideal waveform diagram of the key nodes of the gate voltage pre-charge time measurement circuit of the multi-chip IGBT module provided by the embodiment of the present invention;

[0046] Figure 6 is the double-pulse test circuit diagram of the multi-chip IGBT module provided by the embodiment of the present invention;

[0047] Figure 7 is the V DC result diagram of the multi-chip IGBT module under two working conditions at different bus voltages V PG ;

[0048] Figure 8 is the V L result diagram of the multi-chip IGBT module under two working conditions at different load currents I PG ;

[0049] Figure 9 is the V j result diagram of the multi-chip IGBT module under two working conditions at different junction temperatures T PG ;

[0050] Figure 10 is the circuit diagram of the diagnostic circuit provided by the embodiment of the present invention;

[0051] Figure 11 is the waveform diagram of the intermediate node and output signal of the diagnostic circuit under different working conditions provided by the embodiment of the present invention. Detailed implementation manners

[0052] The following specifically illustrates the implementation manners of the present invention in conjunction with the accompanying drawings. The given embodiments are only for illustrative purposes and should not be construed as limitations on the present invention. The accompanying drawings are only for reference and illustration and do not constitute a limitation on the protection scope of the present invention patent. Because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0053] The multi-chip IGBT module chip open-circuit failure monitoring method provided by the embodiment of the present invention, such asFigure 1 As shown in the flowchart, it includes the steps:

[0054] Determine the health-sensitive parameters for monitoring the open-circuit failure of chips in a multi-chip IGBT module. These health-sensitive parameters are related to the number n of effective chip branches in the multi-chip IGBT module and are at least not affected by the bus voltage and load current;

[0055] Measure the values of the health-sensitive parameters of the multi-chip IGBT module and convert them into an analog voltage signal V PG ;

[0056] Determine the failure threshold V PG of the analog voltage signal V REF3 for determining the occurrence of open-circuit failure of chips in the multi-chip IGBT module;

[0057] Based on the measured analog voltage signal V PG and the failure threshold V REF3 judge whether the multi-chip IGBT module has an open-circuit failure of chips.

[0058] The structure and circuit of a specific multi-chip IGBT module are as Figure 2 shown. This module is a welded IGBT module FF150R12ME3G. Figure 2 Figure (a) of Figure 2 shows the internal structure of the welded IGBT module FF150R12ME3G, and figure (b) of Figure 2 shows the equivalent circuit of the welded IGBT module FF150R12ME3G. The welded IGBT module FF150R12ME3G contains two switches, which are connected in series to form a half-bridge structure. Each switch consists of three chip branches, and each branch consists of an IGBT chip and a FWD chip. Figure 2 In figure (a) of gint , the meaning of the first capital letter in the parameter label is: Q represents the IGBT chip, D represents the diode chip, G represents the gate, AE represents the auxiliary emitter, C represents the collector, and E represents the emitter. The meaning of the first subscript in the parameter label is: T represents the top, and B represents the bottom. And the second subscript (if any) specifies the chip number. Figure 2 In figure (b) of gint , R g , L GC , C GE , C CE and C T are the internal gate resistance, gate-loop parasitic inductance, gate-collector capacitance, gate-emitter capacitance, and collector-emitter capacitance of each chip branch respectively. L C is the parasitic inductance of the upper-tube power terminal, L B is the parasitic inductance of the midpoint power terminal, and L

[0059] During the turn-on process of a multi-chip IGBT module, the collector-emitter voltage v CE , collector current i C , gate voltage v GE , and gate current i G are shown in the waveform diagram as Figure 3 shown, where V DC , I L , V PO , V FB , V TH , V GP , V GON , V GOFF , and I GP are the DC bus voltage, load current, gate spike voltage, flat-band voltage, threshold voltage, Miller plateau voltage, turn-on gate voltage, turn-off gate voltage, and Miller plateau current, respectively. According to the characteristics of the collector current, the turn-on process of the multi-chip IGBT module in the present invention is divided into two stages:

[0060] (1) Pre-charge stage (t0~t3): During this stage, the gate control signal flips from 0 to 1, and the gate voltage v GE starts to rise from the moment t0 and rises to V PO , V FB , and V TH at the moments t1, t2, and t3, respectively. In the pre-charge stage, the conductive channel has not been formally formed, and the collector current i C and the collector-emitter voltage v CE will not change significantly.

[0061] (2) Fast turn-on stage (t>t3): When v GE exceeds the threshold voltage V TH , the conductive channel is formally formed, and the multi-chip IGBT module officially enters the fast turn-on stage. The collector current i C starts to rise rapidly, and the collector-emitter voltage v CE starts to drop rapidly.

[0062] The expression of the gate voltage in the pre-charge stage is:

[0063]

[0064] where n is the number of effective chip branches in the multi-chip IGBT module, R gint is the internal gate resistance of a single chip branch, R gext is the external gate resistance, R gint is the internal gate resistance of a single chip branch, C GE is the gate-emitter capacitance of a single chip, and V GONFor the turn-on gate voltage, V GOFF For the turn-off gate voltage, V SET To define t PG The voltage at the end time, where t represents time and e represents the natural base.

[0065] The time to increase the gate voltage from 0 to the set voltage V SET is defined as the pre-charge time t PG , then the pre-charge time t PG The relationship with the number n of parallel chip branches can be expressed as:

[0066]

[0067] When a chip open-circuit failure occurs, the number n of parallel chip branches inside the module decreases, and the gate voltage pre-charge time t PG decreases. Therefore, t PG can be used as a health-sensitive parameter for monitoring chip open-circuit failures.

[0068] Furthermore, it is necessary to analyze the relationship between t PG and the bus voltage, load current, and junction temperature.

[0069] (1) The relationship between t PG and the bus voltage V DC : During the switching process, the expression for the gate-emitter capacitance C GE is:

[0070]

[0071] Among them, C OXD is the gate oxide capacitance and is independent of the bus voltage. C dep is the depletion layer capacitance and is inversely proportional to the bus voltage. Therefore, by setting the end voltage V PG of t SET below the flat-band voltage V FB , the influence of the bus voltage change can be eliminated. Furthermore, the flat-band voltage V FB is affected by the bus voltage. Due to the existence of the short-channel effect, as the bus voltage rises, V FB decreases. Therefore, the present invention sets V SET below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module, thereby eliminating the influence of the bus voltage change.

[0072] (2) The relationship between t PG and the load current I L : During the pre-charge stage, the conductive channel in the IGBT gate region is not formally formed. Regardless of how the load current changes, the collector current i flowing through the multi-chip IGBT module CThe currents are all 0. Therefore, t PG is independent of the load current I L .

[0073] (3) The relationship between t PG and the junction temperature T j : In the expression of t PG , only R gint is affected by the change in the junction temperature. Differentiating t PG with respect to R gint yields:

[0074]

[0075] wherein, the temperature sensitivity of R gint is very small, only 1 - 2 mV / °C. In addition, the presence of the external gate resistance R gext further suppresses the influence of the change in R gint . Therefore, the change in the junction temperature has only a weak influence on t PG .

[0076] Therefore, in this embodiment, the health - sensitive parameter is determined as the gate - voltage pre - charging time t PG of the multi - chip IGBT module. The health - sensitive parameter can also be set to other parameters, but this parameter needs to be related to the number n of effective chip branches in the multi - chip IGBT module and at least not affected by the bus voltage and the load current.

[0077] In order to effectively measure the value of the health - sensitive parameter (gate - voltage pre - charging time t PG ) of the multi - chip IGBT module and convert it into an analog voltage signal V PG , this embodiment specifically adopts the steps:

[0078] Capture the equivalent pulse of the gate - voltage signal during the turn - on and turn - off processes of the multi - chip IGBT module;

[0079] Based on the captured equivalent pulse of the turn - on and turn - off processes of the multi - chip IGBT module, obtain the digital pulse representing the gate - voltage pre - charging time t PG ;

[0080] Eliminate the pulses during the turn - off process in the digital pulse of the gate - voltage pre - charging time t PG , and convert the obtained pulse into an analog voltage signal V PG whose amplitude represents t PG .

[0081] This embodiment designs a measurement circuit to implement the above three steps. As Figure 4As shown in the circuit diagram of the provided measurement circuit, the measurement circuit specifically includes a signal processing sub-circuit, a logic sub-circuit, and a signal conversion sub-circuit, which are respectively used to implement the above three steps.

[0082] The main function of the signal processing sub-circuit is to capture the start and end moments of t PG . As Figure 4 shown, the signal processing sub-circuit includes a resistor voltage divider composed of voltage dividing resistors R1 and R2, a non-inverting adder composed of a high-speed operational amplifier (OPA) U1, resistors R3, R4, R5, R6, and a capacitor C1, a window comparator composed of high-speed comparators (CMP) U2 and U3, digital isolators (ISO) U4 and U5, input reference voltages V REF1 、V REF2 (the input reference voltage V REF2 represents V SET ), and a DC voltage E C . The voltage dividing resistors R1 and R2 are connected in series and then coupled between the gate G of the multi-chip IGBT module and the auxiliary emitter AE. The midpoint of the series connection of the voltage dividing resistors R1 and R2 is coupled to the non-inverting input terminal of the high-speed operational amplifier U1 through a resistor R4. The DC voltage E C is coupled to the non-inverting terminal of the high-speed operational amplifier U1 through a resistor R5. The resistor R3 is coupled between the inverting input terminal of the high-speed operational amplifier U1 and the reference ground. The resistor R6 and the capacitor C1 are connected in parallel and then coupled between the inverting input terminal and the output terminal of the high-speed operational amplifier U1. The output terminal of the high-speed operational amplifier U1 is respectively coupled to the non-inverting input terminal of the high-speed comparator U2 and the inverting input terminal of the high-speed comparator U3. The input reference voltages V REF1 、V REF2 are respectively coupled to the inverting input terminal of the high-speed comparator U2 and the non-inverting input terminal of the high-speed comparator U3. The outputs of the high-speed comparator U2 and the high-speed comparator U3 are respectively coupled to the input terminals of the digital isolators U4 and U5.

[0083] The working process of the signal processing sub-circuit is as follows:

[0084] Perform voltage matching on the collected gate voltage signal of the multi-chip IGBT module through the resistor voltage divider composed of the voltage dividing resistors R1 and R2;

[0085] Lift the output voltage V ge of the resistor voltage divider by a DC voltage E C to ensure that the output signal V gep of the non-inverting adder is within the allowable input voltage range of the window comparator and suppress the interference of the gate spike voltage V PO ;

[0086] Input the output signal V gep of the non-inverting adder to the window comparator and respectively compare it with the input reference voltage VREF1 and V REF2 Compare with V, and output the corresponding comparison result V a and V b ;

[0087] Output the comparison result V a and V b to the logic sub - circuit through digital isolators U4 and U5 respectively, and obtain the equivalent pulses during the turn - on and turn - off processes of the multi - chip IGBT module respectively.

[0088] It should be noted that a capacitor C1 is connected in parallel in the feedback loop of the non - inverting adder. Its main function is to perform phase compensation and form a low - pass filter to suppress the interference of the gate spike voltage V PO to the measurement. The design principle of its capacitance value is:

[0089]

[0090] where t r_PG is the duration of the gate voltage pre - charging stage.

[0091] The main function of the logic sub - circuit is to convert the comparison result of the window comparator into a digital pulse whose pulse width represents t PG and generate the enable signal of the signal conversion sub - circuit. As Figure 4 shown, the logic sub - circuit includes an RC delay circuit composed of a resistor R7 and a capacitor C2, and two logic AND gates U6 and U7. The resistor R7 and the capacitor C2 are connected in series and coupled between the output terminal of the digital isolator U4 and the digital reference ground. The input terminals of the logic AND gate U6 are respectively coupled to the mid - point of the RC delay circuit and the output terminal of the digital isolator U4. The input terminals of the logic AND gate U7 are respectively coupled to the output terminal of the digital isolator U4 and the output terminal of the digital isolator U5.

[0092] The working process of the logic sub - circuit is as follows:

[0093] Input the equivalent pulses corresponding to the output signals V a and V b of the window comparator to the logic AND gate U6, and obtain the digital pulse V whose pulse width represents gg ;

[0094] Input the equivalent pulse corresponding to the output signal V b of the window comparator to the RC delay circuit. The output signal of the RC delay circuit and the equivalent pulse corresponding to V b are input to the logic AND gate U7 together to obtain the enable signal OE.

[0095] The main function of the signal conversion sub - circuit is to eliminate the pulses during the turn - off process and convert t PG into an analog voltage signal V PG . AsFigure 4 As shown, the signal conversion sub-circuit includes a tri-state buffer (3S-buf) U8 and an RC integrating circuit composed of a resistor R8 and a capacitor C3. The enable terminal of the tri-state buffer U8 is coupled to the output terminal of the logic AND gate U6, the signal input terminal of the tri-state buffer U8 is coupled to the output terminal of the logic AND gate U7, the resistor R8 and the capacitor C3 are connected in series and then coupled between the output terminal of the tri-state buffer U8 and the digital reference ground, and the voltage output at the midpoint of the series connection of the resistor R8 and the capacitor C3 is V which characterizes the pre-charge time of the gate voltage PG .

[0096] The working process of the signal conversion sub-circuit is as follows:

[0097] Input the output signal V of the logic AND gate U6 gg to the signal input terminal of the tri-state buffer U8, and input the output signal OE of the logic AND gate U7 to the enable terminal of the tri-state buffer U8;

[0098] Input the output signal V of the tri-state buffer U8 buf to the RC integrating circuit composed of the resistor R8 and the capacitor C3 to obtain an analog voltage signal V whose amplitude represents t PG . PG .

[0099] The design principle of the RC integrating circuit in the signal conversion sub-circuit is: based on the allowable input voltage range of the microprocessor ADC. Taking a microprocessor with an allowable input voltage range of 3.3V as an example in the present invention, and under the condition of ensuring a 20% safety margin, the value-taking principle of the RC integrating circuit is:

[0100]

[0101] Figure 5 is the ideal waveform diagram of the key node of the gate voltage pre-charge time measurement circuit for the multi-chip IGBT module, where t delay is the delay time introduced by the RC delay circuit in the logic sub-circuit, and HI-Z is the high impedance state. The gate voltage of the multi-chip IGBT module passes through the signal processing and logic sub-circuits to obtain a digital pulse V with a pulse width of t PG and the enable signal OE. In the range of t gg (t0 to t1), OE is at a high level, and the output signal V of U8 PG flips from a low level to a high level at the moment of t0 and starts to charge the capacitor C3, and the voltage V on C3 buf rises exponentially from 0. In the stage of t1 to t5, OE flips to a low level, V PG is in a high impedance state, and V buf remains at the value at the moment of t1. This state lasts until the moment of t5, when OE flips to a high level again, V PG ... PGDischarge starts to 0. It should be noted that the t1-t5 stage includes the turn-off process of the multi-chip IGBT module, thus eliminating the influence of digital pulses during the turn-off process.

[0102] In this embodiment, by building a double-pulse test circuit for the multi-chip IGBT module as shown in Figure 6 , full-condition tests are respectively carried out on the multi-chip IGBT module in a healthy state and the multi-chip IGBT module with an open-circuit failure in one chip branch, and the V PG under all working conditions is recorded, and the failure threshold V REF3 for determining the occurrence of chip open-circuit failure in the multi-chip IGBT module is set according to the experimental results. Figure 6 In load , the upper IGBT device is always in the off state, the lower IGBT device is in the normal switching state, the load inductor L DC is connected in parallel across the upper IGBT device, V DC is the DC power supply voltage, C gext is the DC-side support capacitor, R GG is the external gate resistor, and V

[0103] In a specific experiment, the embodiment of the present invention uses the multi-chip IGBT module FF150R12ME3G with three parallel chip branches as shown in Figure 2 to conduct tests under healthy conditions and open-circuit failure conditions where one chip branch has an open-circuit failure. The constructed experimental circuit is set according to Figure 6 . The relevant parameters of the experimental circuit are set as shown in Table 1 below. The chip open-circuit failure of the multi-chip IGBT module is simulated by cutting off all the emitter bonding wires of Q Figure 2 as shown in B1 .

[0104] Table 1

[0105]

[0106] Figure 7 are the V DC results diagrams of the multi-chip IGBT module under two working conditions at different bus voltages V PG . Among them, (a) is the time-domain waveform diagram, and (b) is the overview diagram of V DC under different bus voltages V PG . It can be seen from Figure 7 that the V PG under healthy conditions and open-circuit failure conditions is independent of the bus voltage V DC , the V PG under the two working conditions remains basically unchanged, and the V PG under healthy conditionsThe average value is approximately 2.669V, the maximum value is 2.675V, the minimum value is 2.655V, and V under the open - circuit failure condition PG The average value is approximately 1.733V, the maximum value is 1.738V, and the minimum value is 1.729V.

[0107] Figure 8 For the multi - chip IGBT module under two working conditions at different load currents I L of V PG Result graphs, where (a) is the time - domain waveform graph and (b) is the overview graph of V DC at different bus voltages V PG From Figure 8 it can be seen that V under the healthy working condition and the open - circuit failure condition PG has nothing to do with the load current I L , and V under the two working conditions PG basically remains unchanged. The average value of V under the healthy working condition PG is approximately 2.672V, the maximum value is 2.675V, the minimum value is 2.671V, and the average value of V under the open - circuit failure condition PG is approximately 1.732V, the maximum value is 1.735V, and the minimum value is 1.729V.

[0108] Figure 9 For the multi - chip IGBT module under two working conditions at different junction temperatures T j of V PG Result graphs, where (a) is the time - domain waveform graph and (b) is the overview graph of V j at different junction temperatures T PG From Figure 9 it can be seen that V under the healthy working condition and the open - circuit failure condition PG has little correlation with the junction temperature T j , and the changes in V under the two working conditions PG are not significant. The average value of V under the healthy working condition PG is approximately 2.675V, the maximum value is 2.707V, the minimum value is 2.643V, and the average value of V under the open - circuit failure condition PG is approximately 1.729V, the maximum value is 1.783V, and the minimum value is 1.673V.

[0109] From Figures 7 to 9 it can be seen that V under the two working conditions PG is relatively stable, and there are obvious differences in V under the two working conditions PG . Using the rounding - off method, then under different bus voltages V DC , different load currents I L , different junction temperatures T j of V under the healthy working condition PGBoth are 2.7V (V He ), while the V PG under the open - circuit failure condition are both 1.7V (V Fa ). In order to accurately distinguish between these two conditions, the failure threshold V REF3 for determining the chip open - circuit failure of the multi - chip IGBT module in this embodiment is set as:

[0110] V REF3 ∈[V Fa +α(V He -V Fa ),V Fa -α(V He -V Fa )](7)

[0111] The value of the coefficient factor α should satisfy that V Fa +α(V He -V Fa ) is greater than the maximum value of all V PG under the open - circuit failure conditions, and V Fa -α(V He -V Fa ) is less than the minimum value of all V PG under the healthy conditions.

[0112] In order to accurately distinguish between the healthy condition and the open - circuit failure condition, α should not be too small. In this embodiment, α is selected in the range of (0.1, 0.5]. Finally, α is determined to be equal to 0.4 in this embodiment, and the failure threshold V REF3 is selected in [2.1, 2.3]V. In this example, the failure threshold V REF3 is selected as 2.3V.

[0113] By comparing the measured analog voltage signal V PG with the failure threshold V REF3 , if V PG is lower than the failure threshold V REF3 , it is determined that the multi - chip IGBT module has a chip open - circuit failure. If V PG is higher than the failure threshold V REF3 , it is determined that the multi - chip IGBT module has not had a chip open - circuit failure.

[0114] In addition to testing the multi - chip IGBT module with an open - circuit failure in one chip branch, it is also possible to test the multi - chip IGBT module with open - circuit failures in two or more chip branches. By setting the failure thresholds for the n conditions that can sufficiently distinguish between the healthy condition and the open - circuit failure conditions of one chip branch, two chip branches up to n - 1 chip branches having open - circuit failures under the conditions of one chip branch, two chip branches up to n - 1 chip branches having open - circuit failures, the number of chip branches with open - circuit failures can be obtained.

[0115] To compare the measured analog voltage signal V PG with the failure threshold V REF3 and obtain the diagnostic result, an embodiment of the present invention designs a diagnostic circuit, as shown in the circuit diagram of Figure 10 . The diagnostic circuit mainly includes a high-speed comparator U9, an RC delay circuit composed of a resistor R9 and a capacitor C4, a logic NOT gate U 10 , a D flip-flop U 11 , and an input reference voltage V REF3 (failure threshold). The input terminals of the high-speed comparator U9 are respectively coupled to the input reference voltage V REF3 and the output V PG of the measurement circuit. The resistor R9 and the capacitor C4 are connected in series and then coupled between the output terminal of the logic AND gate U6 and the digital reference ground. The input terminal of the logic NOT gate U 10 is coupled to the series midpoint of the resistor R9 and the capacitor C4. The input terminals of the D flip-flop U 11 are respectively coupled to the output terminal of the high-speed comparator U9 and the output terminal of the logic NOT gate U 10 . The output terminal of the D flip-flop U 11 is a voltage signal V dia representing the health state of the chip branch of the multi-chip IGBT module.

[0116] The working process of the diagnostic circuit is as follows:

[0117] The enable signal OE passes through the RC delay circuit and the logic NOT gate U 10 to obtain the clock signal CLK of the D flip-flop U 11 ;

[0118] The output signal V PG of the measurement circuit and the input reference voltage V REF3 are input to the high-speed comparator U9 for comparison;

[0119] The output signal of the high-speed comparator U9 is input to the data input terminal of the D flip-flop U 11 ;

[0120] The D flip-flop U 11 outputs a voltage signal V dia representing the health state of the chip branch of the multi-chip IGBT module.

[0121] If the output voltage V dia of the diagnostic circuit is at a low level, the multi-chip IGBT module is in a healthy state;

[0122] If the output voltage V dia of the diagnostic circuit is at a high level, the multi-chip IGBT module has a chip open failure.

[0123] Figure 11 Waveform diagrams of the intermediate node and output signal of the diagnostic circuit under different working conditions, where (a) is the healthy working condition and (b) is the open-circuit failure working condition. From Figure 11 it can be seen that when there is no chip open-circuit failure in the multi-chip IGBT module, the output signal V 11 of the D flip-flop U dia is at a low level. When there is a chip open-circuit failure in the multi-chip IGBT module, the output signal V 11 of the D flip-flop U dia is at a high level, which verifies the effectiveness of the diagnostic circuit.

[0124] It should also be noted that the above measurement circuit and diagnostic circuit are only a preferred implementation manner, and other circuits and implementation manners that can achieve the same function can also be adopted.

[0125] The embodiment of the present invention also provides a multi-chip IGBT module chip open-circuit failure monitoring system, which applies the above multi-chip IGBT module chip open-circuit failure monitoring method. The system includes a health-sensitive parameter determination module, a measurement module, a failure threshold determination module, and a diagnostic module. The health-sensitive parameter determination module is used to determine the health-sensitive parameters for monitoring the chip open-circuit failure of the multi-chip IGBT module. The measurement module is used to measure the health-sensitive parameter values of the multi-chip IGBT module and convert them into an analog voltage signal V PG , the failure threshold determination module is used to determine the failure threshold V PG of the analog voltage signal V REF3 for determining that the multi-chip IGBT module has a chip open-circuit failure. The diagnostic module determines whether the multi-chip IGBT module has a chip open-circuit failure based on the measured analog voltage signal V PG and the failure threshold V REF3 . These modules are electronic modules that can achieve the corresponding functions. The measurement module and the diagnostic module can adopt the above measurement circuit and diagnostic circuit.

[0126] In summary, for the multi-chip IGBT module chip open-circuit failure monitoring method and system provided by the embodiment of the present invention, first, the health-sensitive parameters for monitoring the chip open-circuit failure of the multi-chip IGBT module are determined, then the health-sensitive parameter values of the multi-chip IGBT module are measured and converted into an analog voltage signal V PG , then the failure threshold V PG of the analog voltage signal V REF3 for determining that the multi-chip IGBT module has a chip open-circuit failure is determined, and finally the measured analog voltage signal V PG and the failure threshold V REF3Compare to determine whether there is a chip open - circuit failure in the multi - chip IGBT module. Without unpacking the package of the multi - chip IGBT module, the present invention realizes the monitoring of chip open - circuit failure of the multi - chip IGBT module. And only the gate voltage signal needs to be collected. There are few influencing factors, it is easy to measure, has non - invasiveness, can be plug - and - play or integrated into the drive circuit, and is easy to realize in - situ monitoring of chip open - circuit failure of the multi - chip IGBT module, having strong practical application value.

[0127] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A method for monitoring open - circuit failure of chips in a multi - chip IGBT module, characterized in that, Including the steps: Determine the health-sensitive parameter for monitoring the chip open-circuit failure of a multi-chip IGBT module, where the health-sensitive parameter is related to the number of effective chip branches in the multi-chip IGBT module n and is at least not affected by the bus voltage and load current; the health-sensitive parameter is determined as the time when the gate voltage of the multi-chip IGBT module rises from 0 to the set voltage V SET i.e., the gate voltage pre-charge time t PG , and the set voltage V SET is set below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module; Measure the health-sensitive parameter values of a multi-chip IGBT module and convert them into an analog voltage signal V PG ; Determine the analog voltage signal for judging the occurrence of chip open - circuit failure in a multi - chip IGBT module V PG of the failure threshold V REF3 ; Based on the measured analog voltage signal V PG and the failure threshold V REF3 Determine whether a chip open - circuit failure occurs in the multi - chip IGBT module.

2. The multi-chip IGBT module chip open circuit failure monitoring method according to claim 1, characterized in that: By comparing the measured analog voltage signal V PG with the failure threshold V REF3 if V PG it is lower than the failure threshold V REF3 it is determined that the multi-chip IGBT module has a chip open-circuit failure. If V PG it is higher than the failure threshold V REF3 it is determined that the multi-chip IGBT module has not had a chip open-circuit failure.

3. The method for monitoring chip open-circuit failure of the multi-chip IGBT module according to claim 2, characterized in that Measuring the health-sensitive parameter values of the multi-chip IGBT module and converting them into analog voltage signals V PG Specifically including the steps: Capturing the equivalent pulses of the gate voltage signals during the turn-on and turn-off processes of the multi-chip IGBT module; Obtaining a digital pulse representing the gate voltage pre-charge time based on the equivalent pulse during the turn-on and turn-off processes of a captured multi-chip IGBT module t PG ; Eliminate the gate voltage pre-charge time t PG the pulse during the turn-off process in the digital pulse, and convert the obtained pulse into an analog voltage signal with an amplitude representing t PG V PG .​ 4. The multi-chip IGBT module chip open-circuit failure monitoring method according to claim 3, characterized in that The capturing of the equivalent pulses of the gate voltage signals during the turn-on and turn-off processes of the multi-chip IGBT module specifically includes the steps: Through a voltage-dividing resistor R 1 and R 2 form a resistor voltage divider to perform voltage matching on the collected gate voltage signals of the multi-chip IGBT module; The output voltage of the resistor divider is lifted by an in-phase adder V ge to raise a DC voltage E C , ensuring that the output signal of the in-phase adder V gep is within the input voltage range allowed by the window comparator; The output signal of the non-inverting summer V gep is input to the window comparator and compared with the input reference voltages V REF1 and V REF2 respectively, and the corresponding comparison results V a and V b , V REF2 i.e., the set voltage V SET ; Comparison result V a and V b are respectively output to a logic sub-circuit through digital isolators U 4 and U 5 to respectively obtain equivalent pulses during the turn-on and turn-off processes of the multi-chip IGBT module.

5. The multi-chip IGBT module chip open-circuit failure monitoring method according to claim 4, characterized in that, The equivalent pulse acquisition representing the gate voltage pre-charge time during the turn-on and turn-off processes of the capture-based multi-chip IGBT module t PG of the digital pulse, specifically including the steps: The output signal of the window comparator V a and V b The corresponding equivalent pulses are input to the logic AND gate U 7 to obtain a digital pulse represented by the pulse width V gg ; The output signal of the window comparator V b The corresponding equivalent pulse is input to RC the delay circuit, RC The output signal of the delay circuit and V b the corresponding equivalent pulse are input to the logic AND gate U 6 to obtain the enable signal OE .

6. The method for monitoring the chip open-circuit failure of the multi-chip IGBT module according to claim 5, characterized in that, The gate voltage pre-charge time elimination t PG the pulse in the turn-off process of the digital pulse, and convert the obtained pulse into an analog voltage signal whose amplitude represents t PG and specifically includes the steps of: V PG ​ The output signal of the logical AND gate U of 7 V gg is input to the tri-state buffer U at the signal input terminal of 8. The output signal of the logical AND gate U of 6 OE is input to the tri-state buffer U at the enable terminal of 8; The output signal of the tri-state buffer U 8 V buf is input to the resistor R 8 and the capacitor C 3 to form RC an integrating circuit to obtain an analog voltage signal whose amplitude represents t PG . V PG .

7. The method for monitoring the chip open-circuit failure of the multi-chip IGBT module according to claim 6, wherein The measured analog voltage signal V PG and the failure threshold V REF3 to determine whether a chip open - circuit failure occurs in the multi - chip IGBT module, specifically including the steps: The enable signal OE passes through RC a delay circuit and a logic NOT gate U 10 to obtain the clock signal U 11 for the D flip-flop CLK ; The output signal V PG is compared with the failure threshold V REF3 by inputting it to a high-speed comparator U 9; High-speed comparator U The output signal of 9 is input to the D flip-flop U 11 data input terminal; D flip-flop U 11 Output a voltage signal characterizing the health status of the chip branch of the multi-chip IGBT module V dia ; If the output voltage V dia is at a low level, the multi-chip IGBT module is in a healthy state; If the output voltage V dia is at a high level, the multi-chip IGBT module experiences a chip open-circuit failure.

8. A multi-chip IGBT module chip open-circuit failure monitoring system, which applies the multi-chip IGBT module chip open-circuit failure monitoring method according to any one of claims 1 to 7, characterized in that: The system includes a health-sensitive parameter determination module, a measurement module, a failure threshold determination module, and a diagnosis module. The health-sensitive parameter determination module is used to determine the health-sensitive parameters for monitoring the chip open-circuit failure of a multi-chip IGBT module. The health-sensitive parameters are determined as the time when the gate voltage of the multi-chip IGBT module rises from 0 to a set voltage V SET , that is, the gate voltage pre-charge time t PG , and the set voltage V SET is set below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module; the measurement module is used to measure the value of the health-sensitive parameters of the multi-chip IGBT module and convert it into an analog voltage signal V PG , and the failure threshold determination module is used to determine the analog voltage signal for determining the occurrence of chip open-circuit failure in the multi-chip IGBT module V PG 's failure threshold V REF3 , and the diagnosis module determines whether the multi-chip IGBT module has a chip open-circuit failure based on the measured analog voltage signal V PG and the failure threshold V REF3 .

9. The multi-chip IGBT module chip open-circuit failure monitoring system according to claim 8, characterized in that: The measurement module adopts a measurement circuit, and the measurement circuit includes a signal processing sub-circuit, a logic sub-circuit, and a signal conversion sub-circuit; The signal processing sub - circuit includes a resistor voltage divider composed of voltage - dividing resistors R 1 and R 2, a non - inverting adder composed of high - speed operational amplifier U 1, resistor R 3, R 4, R 5, R 6 and capacitor C 1, a window comparator composed of high - speed comparators U 2 and U 3, digital isolators U 4 and U 5, input reference voltages V REF1 , V REF2 , a DC voltage E C ; the voltage - dividing resistors R 1 and R 2 are connected in series and coupled between the gate G and the auxiliary emitter AE of the multi - chip IGBT module. The mid - point of the series connection of the voltage - dividing resistors R 1 and R 2 is coupled to the non - inverting input terminal of the high - speed operational amplifier R 4 through resistor U 1. The DC voltage E C is coupled to the non - inverting terminal of the high - speed operational amplifier R 5 through resistor U 1. Resistor R 3 is coupled between the inverting input terminal of the high - speed operational amplifier U 1 and the reference ground. Resistor R 6 and capacitor C 1 are connected in parallel and then coupled between the inverting input terminal and the output terminal of the high - speed operational amplifier U 1. The output terminal of the high - speed operational amplifier U 1 is respectively coupled to the non - inverting input terminal of the high - speed comparator U 2 and the inverting input terminal of the high - speed comparator U 3. The input reference voltages V REF1 , V REF2 are respectively coupled to the inverting input terminal of the high - speed comparator U 2 and the non - inverting input terminal of the high - speed comparator U 3. The outputs of the high - speed comparator U 2 and the high - speed comparator U 3 are respectively coupled to the input terminals of the digital isolators U 4 and U 5; The logic subcircuit includes a resistor R 7 and capacitor C 2 RC Delay circuit and two logic AND gates U 6 and U 7. Resistance R 7 and capacitor C 2 are connected in series and then coupled to the digital isolator U 4 Between the output terminal and the digital reference ground, the logic AND gate U 6 input terminals are respectively RC Midpoint of delay circuit and digital isolator U 4 output coupling, logic AND gate U 7 input terminals are connected to the digital isolator U 4 outputs and digital isolators U 5 output terminal coupling; The signal conversion sub-circuit includes a tri-state buffer U 8 and a resistor R 8 and a capacitor C 3 to form a RC integrating circuit; the enable terminal of the tri-state buffer U 8 is coupled to the output terminal of the logic AND gate U 6, the signal input terminal of the tri-state buffer U 8 is coupled to the output terminal of the logic AND gate U 7, the resistor R 8 and the capacitor C 3 are connected in series and then coupled between the output terminal of the tri-state buffer U 8 and the digital reference ground, and the midpoint output voltage of the series connection of the resistor R 8 and the capacitor C 3 is the V PG。

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