Compensation of photoinduced current in integrated circuits

Abstract

The invention provides a circuit for compensating an exposure effect. The circuit includes a first circuit and a light compensation circuit. The first circuit has an output for providing a first current, wherein at least a portion of the first current varies with a first photosensitive circuit component. The compensation circuit has a current mirror and a second photosensitive circuit component. The current mirror has an input coupled to receive a second current mirrored from the first current and an output coupled to provide a third current in response to the second current. The second photosensitive circuit component is configured to be similar to the first photosensitive circuit component and compensate for a photoinduced current provided by the first photosensitive circuit component such that the third current is provided without a photoinduced current component.

Description

Technical Field

[0001] The present disclosure relates generally to electronic circuits, and more particularly to compensation of light-induced current in integrated circuits. Background Art

[0002] Radio frequency identification (RFID) tags, commonly referred to as RFID inlays, tags or transponders, are widely used to identify the objects to which the tags are attached. The most common application examples of RFID tags are retail, supply chain management, shipping services, airline luggage tracking, laundry services, etc. RFID tags typically include an antenna and an integrated circuit (IC) (commonly referred to as a "chip" in this article). In some RFID tags, the chip is not packaged or covered, so the chip is exposed to light. When the tag is exposed to different types of light sources such as sunlight, halogen light, light-emitting diode (LED) light, the RFID tag operation can be significantly reduced. In the semiconductor material of the unpackaged chip, photons can generate electron-hole pairs, thereby generating charge carriers. The photogenerated charge carriers can diffuse through the back side of the semiconductor substrate, and a portion of the photogenerated charge carriers can reach the pn junction, thereby generating a reverse current (or photocurrent), which may interfere with the operation of some low-power circuits on the chip.

[0003] Many circuits on an IC require a constant bias voltage and / or bias current in order to operate properly, and the ability of the bias circuit to provide a constant bias voltage and / or bias current may be adversely affected by light exposure. Figure 1 A bias circuit 100 is shown as an example of the above-mentioned interference caused by exposure. The bias circuit 100 includes two P-channel metal oxide semiconductor (PMOS) transistors 102 and 103, two N-channel metal oxide semiconductor (NMOS) transistors 104 and 105, and an N-well resistor 106. The output circuit 101 includes a plurality of output transistors 107 to deliver a plurality of bias currents to different circuits of the chip. The bias current present in the bias circuit 100 is generated by the gate-source voltage difference between the transistors 104 and 105, and the gate-source voltage difference is applied to the N-well resistor 106. The bias current generated in the bias circuit 100 is mirrored to the output circuit 101 through a current mirror formed by the transistor 102 and any one of the output transistors 107. The generated bias current is a resistive current, which is marked as I R .

[0004] Since the N-well resistor 106 is formed of the N-well material in the P-substrate, a parasitic pn junction device created by the N-well and P-substrate semiconductor materials exists in the resistor 106. This means that when the N-well resistor is exposed to light, a parallel current may appear at the N-well resistor 106 due to the reverse current across the pn junction. This parallel current at the N-well resistor 106 is the light-induced photocurrent, labeled I L , and once generated by the light source, will be added to the current I R , thus generating a value of 1 at 107 R Plus I L The output current at Figure 1 Marked as I R +I L .

[0005] The additional current I flowing from the output device 107 to the different circuits of the chip L This may increase the overall current consumption of the chip and interfere with the operation of the circuit receiving current from transistor 107, which will also receive the light-induced current I L . Summary of the invention

[0006] According to a first aspect of the present disclosure, a circuit implemented on an integrated circuit is provided, the circuit comprising: a first circuit having a first photosensitive circuit component and an output terminal for providing a first current, wherein at least a portion of the first current varies with the first photosensitive circuit component; and a compensation circuit having a current mirror and a second photosensitive circuit component, the current mirror having an input terminal and an output terminal, the input terminal being coupled to receive a second current mirrored from the first current, the output terminal being coupled to provide a third current in response to the second current, the second photosensitive circuit component being configured to match the first photosensitive circuit component and compensate for the light-induced current provided by the first photosensitive circuit component, thereby providing the third current without a light-induced current component caused by the first photosensitive circuit component.

[0007] In one or more embodiments, the first photosensitive component and the second photosensitive component each include an N-well resistor.

[0008] In one or more embodiments, the N-well resistor is formed in a P-substrate, wherein the P-substrate is grounded.

[0009] In one or more embodiments, one or both of an area and a resistance value of the second photosensitive component are proportional to one or both of an area and a resistance value of the first photosensitive component.

[0010] In one or more embodiments, the current mirror of the compensation circuit includes: a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground.

[0011] In one or more embodiments, the second light-sensitive circuit component has a first end and a second end, and wherein both the first end and the second end are coupled to both the control electrodes of the first transistor and the second transistor.

[0012] In one or more embodiments, the circuit further includes: a third transistor having a first current electrode coupled to a power supply voltage, a control electrode coupled to receive a first bias voltage from the first circuit, and a second current electrode coupled to the first current electrode of the first transistor; and a fourth transistor having a first current electrode coupled to the power supply voltage, and a control electrode and a second current electrode both coupled to the first current electrode of the second transistor.

[0013] In one or more embodiments, the circuit further includes one or more additional circuits coupled to the first current electrode and the control electrode of the fourth transistor to receive the bias voltage generated by the first circuit.

[0014] In one or more embodiments, the first circuit includes: a first transistor having a first current electrode, a second current electrode and a control electrode, the second current electrode being coupled to the first end of the first photosensitive component; a second transistor having a first current electrode, a second current electrode coupled to ground, a control electrode and a second current electrode both coupled to the control electrode of the first transistor; and a third transistor having a first current electrode coupled to receive a power supply voltage, a control electrode and a second current electrode both coupled to the first current electrode of the first transistor for providing the first current, the first current being mirrored to form the second current.

[0015] In one or more embodiments, the first circuit is implemented in an unpackaged integrated circuit for a radio frequency identification tag.

[0016] According to a second aspect of the present disclosure, a circuit for compensating for a light-induced current in an unpackaged integrated circuit is provided, the circuit comprising: a first circuit having a first photosensitive N-well resistor and an output terminal for providing a first current, wherein at least a portion of the first current varies with the first photosensitive N-well resistor; and a compensation circuit having a current mirror and a second photosensitive N-well resistor, the current mirror having an input terminal and an output terminal, the input terminal being coupled to receive a second current mirrored from the first current, the output terminal being coupled to provide a third current in response to the second current, the second photosensitive N-well resistor being configured to match the first photosensitive N-well resistor and compensate for the light-induced current component provided by the first photosensitive N-well resistor, wherein the third current is provided without a photogenerated current component.

[0017] In one or more embodiments, one or both of an area and a resistance value of the photosensitive N-well resistor are proportional to one or both of an area and a resistance value of the first photosensitive N-well resistor.

[0018] In one or more embodiments, the current mirror of the compensation circuit includes: a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground.

[0019] In one or more embodiments, the second photosensitive N-well resistor has a first end and a second end, and wherein both the first end and the second end are coupled to both the control electrodes of the first transistor and the second transistor.

[0020] In one or more embodiments, the circuit is implemented in an unpackaged integrated circuit that is exposed to light during use.

[0021] According to a third aspect of the present disclosure, a bias circuit for compensating for light-induced current in an unpackaged integrated circuit is provided, the bias circuit comprising: a first circuit, comprising: a first transistor, having a first current electrode coupled to a power supply voltage, and a second current electrode and a control electrode coupled together; a second transistor, having a first current electrode coupled to the power supply voltage, a second current electrode, and a control electrode coupled to both the control electrode of the first transistor and the second current electrode, and a second current electrode; and a third transistor, having a first current electrode, a control electrode, and a second current electrode, the first current electrode being coupled to the second current electrode of the first transistor; a fourth transistor, having a first current electrode and a control electrode coupled to both the second current electrode of the second transistor and the control electrode of the third transistor, and a second current electrode coupled to a ground terminal; a photosensitive component having a first current electrode coupled to the third transistor; a first end of the second end of the tube, and a second end coupled to ground; a compensation circuit, which includes: a fifth transistor, which has a first current electrode coupled to the power supply terminal, a control electrode coupled to the current electrode of the first transistor, and a second current electrode; a sixth transistor, which has a first current electrode coupled to the power supply terminal, and a second current electrode and a control electrode coupled together; a seventh transistor, which has a first current electrode and a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the ground; and an eighth transistor, which has a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the ground terminal; and a second photosensitive component, which has a first end and a second end, both of which are coupled to the second current electrode of the fifth transistor.

[0022] In one or more embodiments, the first photosensitive component and the second photosensitive component each include an N-well resistor.

[0023] In one or more embodiments, the N-well resistors of the first photosensitive component and the second photosensitive component are formed in a P substrate, wherein the P substrate is grounded.

[0024] In one or more embodiments, one or both of an area and a resistance value of the second photosensitive component are proportional to one or both of an area and a resistance value of the first photosensitive component.

[0025] In one or more embodiments, the first circuit is implemented in an unpackaged integrated circuit of a radio frequency identification tag. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals indicate similar elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0027] Figure 1 A biasing circuit according to the prior art is shown.

[0028] Figure 2 A bias circuit with a compensation circuit according to an embodiment is shown.

[0029] Figure 3 Shows Figure 2 A top view of an example layout of both the bias circuit and the compensation circuit for a photosensitive N-well resistor.

[0030] Figure 4 A cross-sectional view of an N-well resistor is shown in accordance with an embodiment.

[0031] Figure 5 Shows Figure 1 and Figure 2 A graph of the bias current versus light intensity of the bias circuit.

[0032] Figure 6 An RFID tag according to an embodiment is shown. DETAILED DESCRIPTION

[0033] In general, an IC having a bias circuit is provided, the bias circuit including a light-sensitive circuit component, the light-sensitive device adding an undesirable current component to an output when the IC is exposed to light. A compensation circuit is inserted between the bias circuit and the output. The compensation circuit has another light-sensitive circuit component and a current mirror, the current mirror being used to remove the undesirable current component to ensure proper operation of the bias circuit when exposed to light. The bias circuit generates bias currents for different circuits of the chip minus the light-induced current component, thus ensuring that accurate bias currents are provided throughout the integrated circuit and reducing currents that can cause increased power consumption.

[0034] According to an embodiment, a circuit implemented on an integrated circuit is provided, the circuit comprising: a first circuit having a first light-sensitive circuit component and an output for providing a first current, wherein at least a portion of the first current varies with the first light-sensitive circuit component; and a compensation circuit having a current mirror and a second light-sensitive circuit component, the current mirror having an input and an output, the input coupled to receive a second current mirrored from the first current, the output coupled to provide a third current in response to the second current, the second light-sensitive circuit component being configured to match the first light-sensitive circuit component and compensate for the light-induced current provided by the first light-sensitive circuit component, thereby providing the third current without a light-induced current component caused by the first light-sensitive circuit component. The first light-sensitive component and the second light-sensitive component may each include an N-well resistor. The N-well resistor may be formed in a P substrate, and wherein the P substrate may be grounded. One or both of an area and a resistance value of the second light-sensitive component may be proportional to one or both of an area and a resistance value of the first light-sensitive component. The current mirror of the compensation circuit may include: a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground. The second photosensitive circuit component may have a first terminal and a second terminal, and wherein both the first terminal and the second terminal may be coupled to both the control electrodes of the first transistor and the second transistor. The circuit may further include: a third transistor having a first current electrode coupled to a power supply voltage, a control electrode coupled to receive a first bias voltage from the first circuit, and a second current electrode coupled to the first current electrode of the first transistor; and a fourth transistor having a first current electrode coupled to the power supply voltage, and a control electrode and a current electrode both coupled to the first current electrode of the second transistor. The circuit may further include one or more additional circuits, the one or more additional circuits coupled to the first current electrode and the control electrode of the fourth transistor to receive the bias voltage generated by the first circuit. The first circuit may include: a first transistor having a first current electrode, a second current electrode and a control electrode, the second current electrode being coupled to the first end of the first photosensitive component; a second transistor having a first current electrode, a second current electrode coupled to ground, a control electrode and a second current electrode both coupled to the control electrode of the first transistor; and a third transistor having a first current electrode coupled to receive a power supply voltage, a control electrode and a second current electrode both coupled to the first current electrode of the first transistor for providing the first current, the first current being mirrored to form the second current.The first circuit may be implemented in an unpackaged integrated circuit for a radio frequency identification tag.

[0035] In another embodiment, a circuit for compensating for light-induced current in an unpackaged integrated circuit is provided, the circuit comprising: a first circuit having a first photosensitive N-well resistor and an output for providing a first current, wherein at least a portion of the first current varies with the first photosensitive N-well resistor; and a compensation circuit having a current mirror and a second photosensitive N-well resistor, the current mirror having an input and an output, the input coupled to receive a second current mirrored from the first current, the output coupled to provide a third current in response to the second current, the second photosensitive N-well resistor being configured to match the first photosensitive N-well resistor and compensate for the light-induced current component provided by the first photosensitive N-well resistor, wherein the third current is provided without a photogenerated current component. One or both of the area and resistance value of the photosensitive N-well resistor may be proportional to one or both of the area and resistance value of the first photosensitive N-well resistor. The current mirror of the compensation circuit may include: a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground. A second photosensitive N-well resistor may have a first end and a second end, and wherein both the first end and the second end may be coupled to both control electrodes of the first transistor and the second transistor. The circuit may be implemented in an unpackaged integrated circuit that is exposed to light during use.

[0036] In yet another embodiment, a bias circuit for compensating for light-induced current in an unpackaged integrated circuit is provided, the bias circuit comprising: a first circuit comprising: a first transistor having a first current electrode coupled to a power supply voltage, and a second current electrode and a control electrode coupled together; a second transistor having a first current electrode coupled to the power supply voltage, a second current electrode, and a control electrode coupled to both the control electrode and the second current electrode of the first transistor, and a second current electrode; and a third transistor having a first current electrode, a control electrode, and a second current electrode, the first current electrode being coupled to the second current electrode of the first transistor; a fourth transistor having a first current electrode and a control electrode coupled to both the second current electrode of the second transistor and the control electrode of the third transistor, and a second current electrode coupled to a ground terminal; a photosensitive component having a first current electrode coupled to the third transistor; a first end of the second end of the first transistor, and a second end coupled to ground; a compensation circuit, comprising: a fifth transistor having a first current electrode coupled to the power supply terminal, a control electrode coupled to the current electrode of the first transistor, and a second current electrode; a sixth transistor having a first current electrode coupled to the power supply terminal, and a second current electrode and a control electrode coupled together; a seventh transistor having a first current electrode and a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to ground; and an eighth transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the ground terminal; and a second photosensitive component having a first end and a second end, both of which are coupled to the second current electrode of the fifth transistor. The first photosensitive component and the second photosensitive component may each include an N-well resistor. The N-well resistors of the first photosensitive component and the second photosensitive component may be formed in a P substrate, and wherein the P substrate is grounded. One or both of the area and the resistance value of the second photosensitive component may be proportional to one or both of the area and the resistance value of the first photosensitive component. The first circuit may be implemented in an unpackaged integrated circuit of the radio frequency identification tag.

[0037] Figure 2A bias circuit 200 and a compensation circuit 208 according to an embodiment are shown. The bias circuit 200 includes two PMOS transistors 202 and 203, two NMOS transistors 204 and 205, and an N-well resistor 206. In the bias circuit 200, the PMOS transistor 202 has a source connected to a power supply terminal, and a gate and a drain connected together, and the power supply terminal is marked as SUPPLY. The PMOS transistor 203 has a source connected to the power supply terminal SUPPLY, a gate connected to the gate and drain of the transistor 202, and a drain. The NMOS transistor 204 has a drain, a gate, and a source, and the drain is connected to the drain of the PMOS transistor 202. The NMOS transistor 205 has a gate and a drain connected to the drain of the PMOS transistor 203, and a source connected to the ground terminal. The photosensitive N-well resistor 206 has a first end connected to the source of the NMOS transistor 204, and a second end connected to the ground terminal. N-well resistors are suitable for some circuit implementations requiring large resistance values ​​and / or desired temperature bias coefficients.

[0038] The compensation circuit 208 includes PMOS transistors 209 and 210, NMOS transistors 211 and 212, and a photosensitive N-well resistor 213. In the compensation circuit 208, the PMOS transistor 209 has a source connected to the power supply terminal SUPPLY, a gate connected to the gate and drain of the PMOS transistor 202, and a drain at a node 214. The PMOS transistor 210 has a source connected to the power supply terminal SUPPLY, and a gate and a drain connected together. The NMOS transistor 211 has a gate and a drain connected to the drain of the PMOS transistor 209 at a node 214, and a drain connected to a ground terminal. The NMOS transistor 212 has a drain connected to the gate and drain of the PMOS transistor 210, a gate connected to the gate and drain of the NMOS transistor 211 at a node 214, and a source connected to a ground terminal. The photosensitive N-well resistor 213 has a first end and a second end, both of which are connected to the gate and drain of the NMOS transistor 211. The output circuit 201 includes a plurality of output transistors 207 to deliver a plurality of bias currents to different circuits of the chip. Each PMOS transistor 207 has a source connected to the power supply terminal SUPPLY, a gate connected to the gate and drain of the PMOS transistor 210, and a gate connected to the IC. R The bias current is the drain of the circuit.

[0039] The photosensitive N-well resistors are formed on the IC and are very closely matched to each other. In one embodiment, the N-well resistor 206 can be formed using multiple N-well resistors connected in series and / or in parallel, so that the area, surface size, and resistance value of the N-well resistor 206 are proportionally larger than the area and resistance value of the N-well resistor 213. This provides the benefit of reduced area for implementing the N-well resistor 213. As mentioned above, the N-well resistor is suitable for circuit implementations that require large resistance values ​​and / or require a desired bias temperature coefficient.

[0040] The bias current present in bias circuit 200 is generated by the gate-source voltage difference between transistors 204 and 205, which is applied to N-well resistor 206. Because N-well resistor 206 is formed by N-well material in a P-substrate, a parasitic pn junction device created by the N-well and P-substrate materials exists in resistor 206. This means that when N-well resistor 206 is exposed to light, a parallel current may appear at N-well resistor 206 due to the reverse current of the pn junction. This parallel current at N-well resistor 206 is the photocurrent, labeled I L , and once generated by the light source, will be added to the current I R , thereby generating a value of I at the PMOS transistor 207 R Plus I L The output current at Figure 2 Marked as I R +I L The function of bias circuit 200 is similar to Figure 1 The bias circuit 100 in FIG. 1 is shown in FIG. 1 , except that a compensation circuit 208 is added to the bias circuit 200 to remove the photocurrent component I L and prevent the photocurrent component I L The bias current I in the bias circuit 200 is in addition to the output current of the transistor 207. R is generated by the gate-source voltage difference between transistors 204 and 205, which is applied to the photosensitive N-well resistor 206. The bias current I generated in the bias circuit 200 R The current is mirrored to the compensation circuit 208 through the current mirror formed by the PMOS transistors 202 and 209. The bias current I flowing in the PMOS transistor 209 R The bias current I at the PMOS transistor 210 is mirrored to the PMOS transistor 210 through the NMOS mirror formed by the NMOS transistors 211 and 212. R is mirrored to the output PMOS transistor 207 to convert the bias current I R Provides different circuits to the chip.

[0041] once Figure 2 The circuit is exposed to light, due to the reverse current of the pn junction and as Figure 2 As shown, the total current of the bias circuit 200 increases with the photocurrent I L This results in the bias current flowing through PMOS transistor 209 being increased by the term I R +I L Indicates that I R is the resistor current, and I L is the photocurrent from N-well resistor 206 when the chip is exposed to light. This means that the current I R +I L Flows from PMOS transistor 209 into node 214. N-well resistor 213 has a first terminal and a second terminal both connected to node 214, and is similar to N-well resistor 206. In other words, N-well resistor 213 also has a parasitic pn junction that generates a reverse current between node 214 and the grounded P substrate when the chip is exposed to light. Since N-well resistors 206 and 213 have the same form, the light-induced current component I from transistor 209 at node 214 is L will flow through N-well resistor 213, while the bias current component I from transistor 209 at node 214 R will flow through NMOS transistor 211. Therefore, the bias current mirrored from transistor 211 to transistor 212 is bias current I R , that is, there is no photocurrent component I L This means that the bias current I delivered by the output transistor 207 is R Only the bias current I R , and the light-induced current I should not be detected at the output transistor 207 L .

[0042] When the bias circuit 200 with the compensation circuit 208 is operated without light exposure (dark environment), the compensation circuit 208 is transparent, that is, the compensation circuit 208 does not interfere with the I of the output device 207. R This happens because the photosensitive N-well resistor 213 is short-circuited with both ends connected to the node 214, and the pn junction does not generate light-induced current.

[0043] To compensate for the light-induced current of the N-well resistor 206 as discussed above, a closely matched light-sensitive N-well resistor 213 should be provided. To provide a current to cancel the light-induced current of the N-well resistor 206, the N-well resistor 213 should be exposed to exactly the same lighting conditions and provide the same behavior (same temperature gradient, same environment). For proper operation of the compensation circuit 208, the physical implementation and surrounding environment of the N-well resistor 206 and the N-well resistor 213 should be identical. Figure 2 As presented, both N-well resistors 206 and 213 consume significant area of ​​the chip.

[0044] Figure 3 Shows the available Figure 2 A top view of a simple layout of the N-well resistors 206 and 213 of the photosensitive N-well resistors. Figure 3 In the embodiment, there are eight N-well resistors 300 surrounding a compensation N-well resistor 305 in a P substrate 301 of an IC including bias circuit 200 and compensation circuit 208. Each of the N-well resistors 300 and 305 includes a resistor for use with the compensation circuit 208. Figure 2 The circuit elements shown are connected to the contacts 303. Each of the eight N-well resistors 300 is matched as closely as possible to the N-well resistor 305. In one embodiment, the eight N-well resistors 300 are connected in series and / or in parallel ( Figure 3 206 to the photosensitive N-well resistor 213 is eight (8). With this physical implementation, each N-well 300 and 305 has the same surroundings and should produce relatively closely matched photocurrents when the light source is placed on the top or bottom of the chip. In addition, if the light source is placed on the edge of the chip, the N-well ring 302 is used to collect photons. Figure 3 The physical implementation shown also brings another advantage, because the area overhead of the compensation N-well resistor 301 is minimized. However, in this case, the Figure 2 The ratio of the current mirror formed by PMOS transistors 202 and 209 in 201 should be selected to appropriately fit the selected ratio of N-well resistors 206 and 213 .

[0045] Figure 4 It shows that according to the embodiment Figure 3 A simplified cross-sectional view of one of the N-well resistors 300 and 305. Figure 4 In the embodiment, the N well 300 is formed in the P substrate 301. In one embodiment, the P substrate 301 has a P - Conductive type. P formed in P substrate 301 + The N well is used to provide a ground connection for the P substrate 301. Figure 2 The resistive material of the photosensitive N-well resistors 206 and 213 in the compensation circuit 208 is formed. Contacts 303 are formed on the surface of the N-well 300 for circuit connection with other components of the bias circuit 200 and the compensation circuit 208. Contacts 303 can be formed of metal or other types of conductive materials. The junction between the N-well 300 and the P-substrate 301 forms a parasitic pn junction, which can generate a reverse current to the ground when the chip is exposed to light. The N-well 305 for the compensation circuit 208 is formed to closely match the size and other physical and electrical characteristics of the N-well 300.

[0046] Figure 5 Shows Figure 1 and Figure 2 A graph of the bias current versus light intensity of the bias circuit. Figure 5 The effectiveness of the bias circuit 200 with compensation circuit 208 is shown compared to the bias circuit 100 without light induced current compensation. To plot the graph, the chip with the circuit was exposed to a halogen light source and the power intensity of the light source was increased from 0 watts per square meter (W / m 2 ) Scan to 1350W / m 2 For both bias circuits 100 and 200, the expected value of the bias current in the absence of light influence (darkness) is 300 nanoamperes (nA). Figure 5 , the results for bias circuit 100 without optical compensation are represented by curve 400, while the results for bias circuit 200 with optical compensation circuit 208 are represented by curve 401. At maximum scanned light intensity, bias circuit 100 without optical compensation exhibits a bias current with an absolute value equal to about 550 nA, representing an 83.3% change from the original value of 300 nA. Under the same maximum light intensity conditions, bias circuit 200 with optical compensation circuit 208 exhibits a bias current with an absolute value equal to 360 nA, representing a 20% change from the original value of 300 nA. In other words, bias circuit 200 with optical compensation circuit 208 exhibits a smaller change of 4.16 from the original value at maximum scanned light intensity than the circuit without compensation. It should be noted that the results may be different for different circuit implementations.

[0047] Figure 6A radio frequency identification (RFID) tag 500 according to an embodiment is shown. The RFID tag 500 includes an IC 501 (chip) and an antenna 502 connected to the antenna connection of the IC 501. The IC 501 includes the RFID tag 500 and may include a transponder for wireless communication with a reader. Depending on the application, various frequency ranges can be used. The RFID tag 500 may be passive and receive power from a reader device (not shown) via the antenna 502 to operate wirelessly, or may be active and have its own power supply. There are also various ways in which the RFID tag 500 can be implemented. In one embodiment, the RFID tag 500 is implemented on a flexible tape with an adhesive on one side to allow the RFID tag 500 to be attached to an object to be identified. In a low-cost embodiment, the IC 501 may be unpackaged, with the result that the IC 501 may be exposed to various different light types, such as sunlight, halogen light, LED light, etc. The use of the bias circuit 200 with the optical compensation circuit 208 ensures that a constant controlled bias current is provided regardless of whether the chip in the RFID tag 500 is exposed to light.

[0048] Various embodiments or portions of embodiments may be implemented in hardware or as instructions on a non-transitory machine-readable storage medium, which includes any mechanism for storing information in a form readable by a machine, such as a personal computer, laptop, file server, smart phone, or other computing device. Non-transitory machine-readable storage media may include volatile memory and non-volatile memory, such as read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory, etc. Non-transitory machine-readable storage media do not include transitory signals.

[0049] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the appended claims. Therefore, the illustrations and drawings should be regarded as illustrative rather than restrictive, and all such modifications are expected to be included within the scope of the present invention. It is not intended that any advantage, advantage, or solution to a problem described herein with respect to a specific embodiment be interpreted as a key, essential, or indispensable feature or element of any or all claims.

[0050] In addition, as used herein, the terms "a" or "an" are defined as one or more than one. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an". The same applies to the use of definite articles.

[0051] Unless otherwise indicated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other priority of such elements. As used herein, the term "coupled" is not intended to be limited to direct coupling or mechanical coupling.

Claims

1. A circuit implemented on an integrated circuit, characterized in that The circuit comprises: a first circuit having a first light-sensitive circuit component and an output for providing a first current, wherein at least a portion of the first current is a function of the first light-sensitive circuit component; and A compensation circuit having a current mirror and a second light-sensitive circuit component, the current mirror having an input terminal and an output terminal, the input terminal being coupled to receive a second current mirrored from the first current, the output terminal being coupled to provide a third current in response to the second current, the second light-sensitive circuit component being configured to match the first light-sensitive circuit component and compensate for the light-induced current provided by the first light-sensitive circuit component, thereby providing the third current without a light-induced current component caused by the first light-sensitive circuit component.

2. The circuit according to claim 1, characterized in that The first photosensitive component and the second photosensitive component each include an N-well resistor.

3. The circuit according to claim 2, characterized in that The N-well resistor is formed in a P substrate, and wherein the P substrate is grounded.

4. The circuit according to claim 2 or 3, characterized in that One or both of an area and a resistance value of the second photosensitive component are proportional to one or both of an area and a resistance value of the first photosensitive component.

5. A circuit according to any preceding claim, characterised in that The current mirror of the compensation circuit comprises: a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and A second transistor has a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground.

6. The circuit according to claim 5, characterized in that The second light-sensitive circuit component has a first end and a second end, and wherein both the first end and the second end are coupled to both the control electrodes of the first transistor and the second transistor.

7. The circuit according to claim 6, characterized in that Further including: a third transistor having a first current electrode coupled to a supply voltage, a control electrode coupled to receive a first bias voltage from the first circuit, and a second current electrode coupled to the first current electrode of the first transistor; as well as A fourth transistor has a first current electrode coupled to the supply voltage, and a control electrode and a second current electrode both coupled to the first current electrode of the second transistor.

8. The circuit according to claim 7, characterized in that One or more additional circuits are further included, the one or more additional circuits being coupled to the first current electrode and the control electrode of the fourth transistor to receive the bias voltage generated by the first circuit.

9. A circuit for compensating light-induced current in an unpackaged integrated circuit, characterized in that: The circuit comprises: a first circuit having a first photosensitive N-well resistor and an output for providing a first current, wherein at least a portion of the first current is a function of the first photosensitive N-well resistor; and A compensation circuit having a current mirror and a second photosensitive N-well resistor, the current mirror having an input terminal and an output terminal, the input terminal being coupled to receive a second current mirrored from the first current, the output terminal being coupled to provide a third current in response to the second current, the second photosensitive N-well resistor being configured to match the first photosensitive N-well resistor and compensate for a light-induced current component provided by the first photosensitive N-well resistor, wherein the third current is provided without a photogenerated current component.

10. A bias circuit for compensating light-induced current in an unpackaged integrated circuit, characterized in that: The bias circuit comprises: A first circuit comprising: a first transistor having a first current electrode coupled to a supply voltage, and a second current electrode and a control electrode coupled together; a second transistor having a first current electrode coupled to a supply voltage, a second current electrode, and a control electrode coupled to both the control electrode of the first transistor and the second current electrode; and a third transistor having a first current electrode, a control electrode, and a second current electrode, the first current electrode being coupled to the second current electrode of the first transistor; a fourth transistor having a first current electrode and a control electrode coupled to both the second current electrode of the second transistor and the control electrode of the third transistor, and a second current electrode coupled to ground; a photosensitive component having a first terminal coupled to the second terminal of the third transistor and a second terminal coupled to ground; A compensation circuit comprising: a fifth transistor having a first current electrode coupled to the power supply terminal, a control electrode coupled to the current electrode of the first transistor, and a second current electrode; a sixth transistor having a first current electrode coupled to the power supply terminal, and a second current electrode and a control electrode coupled together; a seventh transistor having a first current electrode and a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to ground; and an eighth transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the ground terminal; and A second photosensitive component has a first terminal and a second terminal, both of which are coupled to the second current electrode of the fifth transistor.

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