Semiconductor device and electronic apparatus

Abstract

Provided is a semiconductor device capable of performing a product sum operation with low power consumption. One embodiment of the present invention is a semiconductor device including first and second circuits, the first circuit including a first holding node, and the second circuit including a second holding node. The first circuit is electrically connected to the first and second input wirings and the first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and each of the first and second circuits has a function of holding first and second potentials corresponding to first data at first and second holding nodes. By inputting a potential corresponding to second data to the first and second input wirings, the first circuit outputs a current to one of the first and second wirings, and the second circuit outputs a current to the other of the first and second wirings. The current output to the first wiring or the second wiring by the first and second circuits is determined according to the first and second potentials held by the first and second holding nodes.

Description

[0001] This application is a divisional application of the application filed on October 7, 2019, with international application number PCT / IB2019 / 058507, which entered the Chinese national phase on April 19, 2021, with national application number 201980068769.8, and the invention name is "Semiconductor Devices and Electronic Equipment". Technical Field

[0002] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0003] One embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods or their inspection methods can be cited. Background Art

[0004] The development of integrated circuits modeled after the human brain is gaining momentum. These integrated circuits incorporate electronic circuits modeled after the brain's structure, including circuits equivalent to the brain's "neurons" and "synapses." For this reason, these integrated circuits are sometimes referred to as "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-Neumann architecture, promising parallel processing with significantly lower power consumption compared to Neumann architectures, where power consumption increases with processing speed.

[0005] A data processing model that mimics a neural network and includes neurons and synapses is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose computing devices that use SRAM (Static Random Access Memory) to construct an artificial neural network.

[0006] [Prior technical literature]

[0007] [Patent Document]

[0008] [Non-Patent Literature 1] M. Kang et al., “IEEE Journal of Solid-State Circuits,” 2018, Volume 53, No. 2, pp. 642-655.

[0009] [Non-Patent Document 2] J. Zhang et al., “IEEE Journal of Solid-State Circuits,” 2017, Volume 52, No. 4, pp. 915-924. Summary of the Invention

[0010] Technical problem to be solved by the invention

[0011] In artificial neural networks, calculations are performed by multiplying the binding strength (sometimes called a weight coefficient) of the synapse connecting two neurons by the signal transmitted between the two neurons. In particular, in layered artificial neural networks, the binding strength of the synapse between each of the multiple first neurons in the first layer and one of the second neurons in the second layer must be multiplied by the signal input from each of the multiple first neurons in the first layer to one of the second neurons in the second layer, and these are added together. The number of binding strengths and the number of parameters representing the signal are determined, for example, by the scale of the artificial neural network. In other words, in an artificial neural network, the greater the number of layers and neurons, the greater the number of circuits corresponding to each "neuron" and "synapse," and thus the amount of computation can become enormous.

[0012] The more circuits a chip contains, the higher its power consumption and the greater the heat generated when the device is driven. In particular, the greater the heat generated, the greater the impact on the characteristics of the chip's circuit elements. Therefore, the circuits that make up a chip preferably include circuit elements that are less susceptible to temperature.

[0013] One object of one embodiment of the present invention is to provide a semiconductor device or the like that configures a hierarchical artificial neural network. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that has low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to the effects of ambient temperature. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0014] Note that the purpose of one embodiment of the present invention is not limited to the purpose listed above. The purposes listed above do not preclude the existence of other purposes. In addition, other purposes are purposes not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purposes and other purposes. In addition, one embodiment of the present invention does not necessarily achieve all of the above-mentioned purposes and other purposes.

[0015] Means of solving technical problems (1)

[0017] One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, wherein the first circuit includes a first holding node, the second circuit includes a second holding node, the first circuit is electrically connected to a first input wiring, a second input wiring, a first wiring, and a second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring, the first circuit has a function of holding a first potential corresponding to first data at the first holding node, the second circuit has a function of holding a second potential corresponding to the first data at the second holding node, and the first circuit has a function of: outputting a current corresponding to the first potential to the first wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; and outputting a current corresponding to the first potential to the first wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. The second circuit has: a function of outputting a current corresponding to the first potential to the second wiring when a high-level potential is input to the input wiring; and a function of not outputting a current corresponding to the first potential to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. The second circuit has: a function of outputting a current corresponding to the second potential to the second wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; a function of outputting a current corresponding to the second potential to the first wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring; and a function of not outputting a current corresponding to the second potential to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. (2)

[0019] In addition, one embodiment of the present invention is a semiconductor device, wherein in the structure of the above (1), the first circuit includes first to fourth transistors and a first capacitor, the second circuit includes fifth to eighth transistors and a second capacitor, the first holding node is electrically connected to the first terminal of the first transistor, the gate of the second transistor and the first terminal of the first capacitor, the first terminal of the second transistor is electrically connected to the second terminal of the first capacitor, the second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor, the gate of the third transistor is electrically connected to the first input wiring, the gate of the fourth transistor is electrically connected to the second input wiring, the second terminal of the third transistor is electrically connected to the first wiring, and the second terminal of the fourth transistor is electrically connected to the second wiring, the second holding node is electrically connected to the first terminal of the fifth transistor, the gate of the sixth transistor and the first terminal of the second capacitor, the first terminal of the sixth transistor is electrically connected to the second terminal of the second capacitor, the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, the gate of the seventh transistor is electrically connected to the first input wiring, the gate of the eighth transistor is electrically connected to the second input wiring, the second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. (3)

[0021] In addition, one embodiment of the present invention is a semiconductor device, wherein in the above (1), the first circuit includes first to fourth transistors, a ninth transistor, and a first capacitor, the second circuit includes fifth to eighth transistors, a tenth transistor, and a second capacitor, the first holding node is electrically connected to the first terminal of the first transistor, the gate of the second transistor, the gate of the ninth transistor, and the first terminal of the first capacitor, the second terminal of the first capacitor is electrically connected to the first terminal of the second transistor and the first terminal of the ninth transistor, the second terminal of the second transistor is electrically connected to the first terminal of the third transistor, the second terminal of the ninth transistor is electrically connected to the first terminal of the fourth transistor, the gate of the third transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is electrically connected to the second input wiring. The second terminal of the third transistor is electrically connected to the first wiring, the second terminal of the fourth transistor is electrically connected to the second wiring, the second holding node is electrically connected to the first terminal of the fifth transistor, the gate of the sixth transistor, the gate of the tenth transistor and the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the first terminal of the sixth transistor and the first terminal of the tenth transistor, the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor, the second terminal of the tenth transistor is electrically connected to the first terminal of the eighth transistor, the gate of the seventh transistor is electrically connected to the first input wiring, the gate of the eighth transistor is electrically connected to the second input wiring, the second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. (4)

[0023] In addition, one embodiment of the present invention is a semiconductor device, wherein in the structure of the above (1), the first circuit includes first to fourth transistors, a first logic circuit, and a second logic circuit, the second circuit includes fifth to eighth transistors, a third logic circuit, and a fourth logic circuit, each of the first to fourth logic circuits has a function of outputting an inverted signal of a signal input to an input terminal from an output terminal, the first holding node is electrically connected to the input terminal of the first logic circuit, the output terminal of the second logic circuit, the first terminal of the first transistor, and the gate of the second transistor, the output terminal of the first logic circuit is electrically connected to the input terminal of the second logic circuit, the second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor, and the gate of the third transistor is electrically connected to The first input wiring is electrically connected, the gate of the fourth transistor is electrically connected to the second input wiring, the second terminal of the third transistor is electrically connected to the first wiring, the second terminal of the fourth transistor is electrically connected to the second wiring, the second holding node is electrically connected to the input terminal of the third logic circuit, the output terminal of the fourth logic circuit, the first terminal of the fifth transistor, and the gate of the sixth transistor, the output terminal of the third logic circuit is electrically connected to the input terminal of the fourth logic circuit, the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, the gate of the seventh transistor is electrically connected to the first input wiring, the gate of the eighth transistor is electrically connected to the second input wiring, the second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. (5)

[0025] In addition, one embodiment of the present invention is a semiconductor device, wherein in the structure of the above (1), the first circuit includes first to fourth transistors, a first logic circuit, and a second logic circuit, the second circuit includes sixth to eighth transistors, each of the first logic circuit and the second logic circuit has a function of outputting an inverted signal of a signal input to an input terminal from an output terminal, the first holding node is electrically connected to the input terminal of the first logic circuit, the output terminal of the second logic circuit, the first terminal of the first transistor, and the gate of the second transistor, the output terminal of the first logic circuit is electrically connected to the input terminal of the second logic circuit, the second terminal of the second transistor is electrically connected to the first terminal of the third transistor, and the first terminal of the fourth transistor The gate of the third transistor is electrically connected to the first input wiring, the gate of the fourth transistor is electrically connected to the second input wiring, the second terminal of the third transistor is electrically connected to the first wiring, the second terminal of the fourth transistor is electrically connected to the second wiring, the second holding node is electrically connected to the input terminal of the second logic circuit, the output terminal of the first logic circuit and the gate of the sixth transistor, the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, the gate of the seventh transistor is electrically connected to the first input wiring, the gate of the eighth transistor is electrically connected to the second input wiring, the second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. (6)

[0027] In addition, one embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, wherein the first circuit includes a first load circuit, and the second circuit includes a second load circuit, each of the first load circuit and the second load circuit includes a first terminal and a second terminal, and each of the first load circuit and the second load circuit has a function of changing a resistance value between the first terminal and the second terminal according to first data, the first circuit is electrically connected to a first input wiring, a second input wiring, the first wiring, and the second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring, and the first circuit has a function of outputting a current corresponding to the resistance value of the first load circuit to the first wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, and a function of outputting a current corresponding to the resistance value of the first load circuit to the first wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. The second circuit has a function of outputting a current corresponding to the resistance value of the first load circuit to the second wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; and a function of not outputting a current corresponding to the resistance value of the first load circuit to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. The second circuit has a function of outputting a current corresponding to the resistance value of the second load circuit to the second wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; a function of outputting a current corresponding to the resistance value of the second load circuit to the first wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring; and a function of not outputting a current corresponding to the resistance value of the second load circuit to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. (7)

[0029] In addition, one embodiment of the present invention is a semiconductor device, wherein in the structure of the above (6), the first circuit includes a third transistor and a fourth transistor, the second circuit includes a seventh transistor and an eighth transistor, the first terminal of the first load circuit is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor, the gate of the third transistor is electrically connected to the first input wiring, the gate of the fourth transistor is electrically connected to the second input wiring, the second terminal of the third transistor is electrically connected to the first wiring, the second terminal of the fourth transistor is electrically connected to the second wiring, the first terminal of the second load circuit is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, the gate of the seventh transistor is electrically connected to the first input wiring, the gate of the eighth transistor is electrically connected to the second input wiring, the second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. (8)

[0031] In addition, one embodiment of the present invention is a semiconductor device, wherein in the structure of the above (7), the first circuit includes a first transistor, the second circuit includes a second transistor, the first terminal of the first transistor is electrically connected to the first terminal of the first load circuit, and the first terminal of the second transistor is electrically connected to the first terminal of the second load circuit. (9)

[0033] In addition, one embodiment of the present invention is a semiconductor device, wherein in any one of the structures (6) to (8) above, the first load circuit includes any one of a variable resistor, an MTJ element, and a phase change memory, and the second load circuit includes any one of a variable resistor, an MTJ element, and a phase change memory. (10)

[0035] In addition, one embodiment of the present invention is a semiconductor device, wherein in any one of the structures (1) to (9) above, the semiconductor device includes a third circuit and a fourth circuit, the third circuit having a function of inputting a potential corresponding to second data to each of the first input wiring and the second input wiring, and the fourth circuit having a function of comparing a current flowing through the first wiring with a current flowing through the second wiring and outputting a potential corresponding to the product of the first data and the second data from an output terminal of the fourth circuit. (11)

[0037] In addition, one embodiment of the present invention is an electronic device including any one of the semiconductor devices (1) to (10) described above, wherein the semiconductor device performs neural network calculations.

[0038] Note that in this specification and other documents, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit that includes a semiconductor element (transistor, diode, photodiode, etc.), and a device that includes such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that contain chips in packages. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, or sometimes include semiconductor devices.

[0039] In this specification, the phrase "X and Y are connected" indicates that the following are disclosed: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the drawings or text; other connection relationships are also disclosed within the scope of the drawings or text. X and Y are both objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0040] As an example of electrically connecting X and Y, one or more elements capable of electrically connecting X and Y (e.g., switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) may be connected between X and Y. Furthermore, a switch has the function of controlling whether to turn on or off. In other words, whether current flows is controlled by placing the switch in a conductive state (on) or a non-conductive state (off).

[0041] As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y may be connected between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifting circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generating circuits, storage circuits, control circuits, etc.). Note that even if other circuits are interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0042] Furthermore, when it is explicitly stated that "X is electrically connected to Y," this includes the following: X and Y are electrically connected (in other words, they are connected with another element or other circuit interposed therebetween); X and Y are functionally connected (in other words, they are connected with another circuit interposed therebetween); and X and Y are directly connected (in other words, they are connected without any other element or other circuit interposed therebetween). In other words, when "electrically connected" is explicitly stated, the same thing applies as when "connected" is simply explicitly stated.

[0043] For example, it can be expressed as “X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in sequence.” Alternatively, it can be expressed as “the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in sequence.” Alternatively, it can be expressed as “X is electrically connected to Y through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are arranged in sequence.” By specifying the connection order in the circuit structure using the same display method as this example, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished and the technical scope can be determined. Note that this display method is an example and is not limited to the above display method. Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0044] Furthermore, even when independent components are electrically connected on a circuit diagram, a single component may sometimes perform the functions of multiple components. For example, when a portion of a wiring serves as an electrode, a single conductive film may perform the functions of both the wiring and the electrode. Therefore, the term "electrically connected" in this specification also encompasses situations where a single conductive film performs the functions of multiple components.

[0045] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other is used as the drain. Therefore, in this specification, etc., the source and drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, a back gate may be included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and back gate of the transistor is sometimes referred to as the second gate. Moreover, in the same transistor, "gate" and "back gate" may sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0046] In this specification, a node may also be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region, depending on the circuit structure or device structure. Terminals, wiring, etc. may also be referred to as nodes.

[0047] In this specification and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is ground potential (earth potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc., may vary depending on the reference potential.

[0048] "Electric current" refers to the phenomenon of charge movement (conduction). For example, the description of "conduction occurs in a positively charged body" can be replaced by the description of "conduction occurs in a negatively charged body in the opposite direction". Therefore, in this specification, etc., unless otherwise specified, "electrical current" refers to the phenomenon of charge movement (conduction) when carriers move. Here, as carriers, electrons, holes, anions, cations, complex ions, etc. can be cited. The carriers vary depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is recorded as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is recorded as a negative current amount. Therefore, in this specification, etc., unless otherwise specified, with respect to the positive and negative of current (or the direction of current), the description of "current flows from element A to element B" can be replaced by the description of "current flows from element B to element A". In addition, the description of "current is input to element A" can be replaced by the description of "current is output from element A".

[0049] In addition, in this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion between constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. In addition, these ordinal numbers do not limit the order of the constituent elements. In addition, for example, a constituent element referred to as "first" in one embodiment of this specification, etc. may be referred to as "second" in another embodiment or claim. In addition, for example, in this specification, etc., a constituent element referred to as "first" in one embodiment may be omitted in the scope of another embodiment or claim.

[0050] In this specification, for convenience, words and phrases such as "upper" and "lower" that represent configurations are sometimes used to describe the positional relationship of components with reference to the accompanying drawings. In addition, the positional relationship of the components is appropriately changed depending on the direction in which each component is described. Therefore, the wording is not limited to the words and phrases described in the specification, etc., and words and phrases can be appropriately replaced according to the situation. For example, in the expression "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can also be referred to as "an insulator located below the conductor".

[0051] Furthermore, the terms "above" and "below" are not limited to situations where components are positioned "directly above" or "directly below" and in direct contact. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with the insulating layer; other components may be between insulating layer A and electrode B.

[0052] In this specification, etc., the terms "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be interchanged with "conductive film." Furthermore, "insulating film" may be interchanged with "insulating layer." Furthermore, depending on the situation or state, other terms may be used in place of "film" and "layer." For example, "conductive layer" or "conductive film" may be interchanged with "conductive body." Furthermore, for example, "insulating layer" or "insulating film" may be interchanged with "insulator."

[0053] Note that in this specification and other contexts, the terms "electrode" and "wiring" do not functionally limit the components they represent. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the term "electrode" or "wiring" also encompasses the integration of multiple electrodes or wirings.

[0054] In this specification, etc., the terms "wiring," "signal line," and "power line" can be interchanged depending on the situation or status. For example, "wiring" can sometimes be replaced with "signal line." Also, for example, "wiring" can sometimes be replaced with "power line." Vice versa, "signal line" or "power line" can sometimes be replaced with "wiring." Sometimes "power line" can be replaced with "signal line." Vice versa, "signal line" can sometimes be replaced with "power line." Furthermore, depending on the situation or status, the "potential" applied to the wiring can be replaced with "signal." Vice versa, "signal" can sometimes be replaced with "potential."

[0055] In this specification, etc., impurities of a semiconductor refer to substances other than the main components that constitute the semiconductor film. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0056] In this specification, etc., a switch refers to an element that controls whether or not current flows by switching between a conductive state (on) and a non-conductive state (off). Alternatively, a switch refers to an element that selects and switches the path of current. Examples of switches include electrical switches and mechanical switches. In other words, a switch is not limited to a specific element as long as it can control current.

[0057] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors), or logic circuits combining these elements. When a transistor is used as a switch, the "on state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When a transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0058] An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology, which has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0059] Effects of the Invention

[0060] One embodiment of the present invention can provide a semiconductor device or the like that configures a hierarchical artificial neural network. Another embodiment of the present invention can provide a semiconductor device or the like that has low power consumption. Another embodiment of the present invention can provide a semiconductor device or the like that is less susceptible to the effects of ambient temperature. Another embodiment of the present invention can provide a novel semiconductor device or the like.

[0061] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. In addition, other effects are effects that are not mentioned above but will be described in the following description. Note that one embodiment of the present invention has at least one of the effects listed above and / or other effects. In addition, one embodiment of the present invention achieves at least one of the effects listed above and other effects. Therefore, depending on the circumstances, one embodiment of the present invention may not have the effects listed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1A 、 Figure 1B is a diagram illustrating a layered neural network.

[0063] Figure 2 is a circuit diagram showing a structural example of a semiconductor device.

[0064] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0065] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0066] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0067] Figure 6 is a circuit diagram showing a structural example of a semiconductor device.

[0068] Figure 7 is a circuit diagram showing a structural example of a semiconductor device.

[0069] Figure 8 is a circuit diagram showing a structural example of a semiconductor device.

[0070] Figure 9A 、 Figure 9B 、 Figure 9C is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0071] Figure 10A 、 Figure 10B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0072] Figure 11A 、 Figure 11B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0073] Figure 12A 、 Figure 12B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0074] Figure 13A 、 Figure 13B 、 Figure 13C It is a timing chart showing an operation example of a circuit included in the semiconductor device.

[0075] Figure 14A 、 Figure 14B 、 Figure 14C It is a timing chart showing an operation example of a circuit included in the semiconductor device.

[0076] Figure 15A 、 Figure 15B 、 Figure 15C It is a timing chart showing an operation example of a circuit included in the semiconductor device.

[0077] Figure 16A 、 Figure 16B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0078] Figure 17 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0079] Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0080] Figure 19 is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0081] Figure 20A 、 Figure 20B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0082] Figure 21A 、 Figure 21B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0083] Figure 22A 、 Figure 22B 、 Figure 22C is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0084] Figure 23A 、 Figure 23B 、 Figure 23C is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0085] Figure 24A 、 Figure 24B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0086] Figure 25A 、 Figure 25B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0087] Figure 26A 、 Figure 26B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0088] Figure 27A 、 Figure 27B is a circuit diagram showing a structural example of a circuit included in a semiconductor device.

[0089] Figure 28 is a cross-sectional view showing a structural example of a semiconductor device.

[0090] Figure 29 is a cross-sectional view showing a structural example of a semiconductor device.

[0091] Figure 30A 、 Figure 30B 、 Figure 30C 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor.

[0092] Figure 31A 、 Figure 31B 、 Figure 31C 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor.

[0093] Figure 32A 、 Figure 32B 、 Figure 32C 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor.

[0094] Figure 33A 、 Figure 33B 、 Figure 33C 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor.

[0095] Figure 34A 、 Figure 34B 、 Figure 34C 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor.

[0096] Figure 35A 、 Figure 35B 、 Figure 35C 1 and 2 are a plan view and a cross-sectional view showing a structural example of a transistor.

[0097] Figure 36A 、 Figure 36B 1 and 2 are a plan view and a perspective view showing a structural example of a transistor.

[0098] Figure 37A 、 Figure 37B is a cross-sectional view showing a structural example of a transistor.

[0099] Figure 38A 、 Figure 38B 、 Figure 38C 1 and 2 are a plan view and a perspective view showing a structural example of a capacitor.

[0100] Figure 39A 、 Figure 39B 、 Figure 39C 1 and 2 are a plan view and a perspective view showing a structural example of a capacitor.

[0101] Figure 40A 、 Figure 40B 、 Figure 40C 、 Figure 40D It is a perspective view showing an example of a semiconductor wafer and electronic components.

[0102] Figure 41 It is a perspective view showing an example of an electronic device.

[0103] Figure 42A is a front view showing an example of an electronic device, Figure 42B 、 Figure 42C It is a perspective view showing an example of an electronic device. DETAILED DESCRIPTION

[0104] In artificial neural networks (hereinafter referred to as neural networks), the strength of synaptic connections can be altered by feeding the neural network with existing information. This process of determining the strength of synapses by feeding the neural network with existing information is sometimes referred to as "learning."

[0105] Furthermore, by providing information to a neural network that has already "learned" (determined its binding strength), new information can be output based on that binding strength. This process of outputting new information based on the provided information and binding strength in a neural network is sometimes called "inference" or "cognition."

[0106] Examples of neural network models include Hopfield neural networks and hierarchical neural networks. In particular, neural networks with a multilayer structure are sometimes referred to as "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes referred to as "deep learning."

[0107] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying effect, a rectifying effect and a switching effect, the metal oxide is referred to as a metal oxide semiconductor. In addition, an OS FET or an OS transistor may also be referred to as a transistor comprising a metal oxide or an oxide semiconductor.

[0108] In this specification and other documents, metal oxides containing nitrogen may also be referred to as metal oxides (metal oxides). In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides (metal oxynitrides).

[0109] In this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0110] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in that embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0111] Note that the contents described in the embodiments refer to the contents described in the various drawings in each embodiment or the contents described in the text described in the specification.

[0112] In addition, more figures can be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment, and at least one figure (or part thereof) shown in one or more other embodiments.

[0113] The embodiments described in this specification are described with reference to the accompanying drawings. Note that a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiment, the same figure mark is sometimes used in different drawings to represent the same part or the part with the same function, and repeated description is omitted. In the drawings such as stereograms, the illustration of some constituent elements is sometimes omitted for the sake of clarity.

[0114] In this specification, when the same symbol is used for multiple elements and it is necessary to distinguish them, a symbol for identification such as "_1", "[n]", or "[m,n]" may be added to the symbol.

[0115] In the drawings, sizes, layer thicknesses, and regions are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate idealized examples, and therefore the present invention is not limited to the shapes or numerical values ​​shown. For example, variations in signals, voltages, or currents due to noise or timing variations may be included.

[0116] (Implementation Method 1)

[0117] In this embodiment, a semiconductor device as one embodiment of the present invention, that is, a calculation circuit that performs calculations of a neural network, is described.

[0118] <Hierarchical Neural Network>

[0119] First, a layered neural network is described. A layered neural network includes, for example, one input layer, one or more intermediate (hidden) layers, and one output layer, and is composed of three or more layers in total. Figure 1A The layered neural network 100 shown is an example thereof. The neural network 100 includes the first layer to the R-th layer (where R can be an integer greater than 4). In particular, the first layer corresponds to the input layer, the R-th layer corresponds to the output layer, and the other layers correspond to the intermediate layers. Note that in Figure 1A In FIG. 1 , the (k−1)th layer and the kth layer (here, k is an integer of 3 or more and R−1 or less) are shown as intermediate layers, and other intermediate layers are omitted.

[0120] Each layer of the neural network 100 includes one or more neurons. Figure 1A In the first layer, there are neurons N1 (1) To neuron N p (1)(Here, p is an integer greater than or equal to 1.) The (k-1)th layer includes neurons N1 (k-1) To neuron N m (k-1) (Here, m is an integer greater than 1.) The kth layer includes neurons N1 (k) To neuron N n (k) (Here, n is an integer greater than 1.) The Rth layer includes neurons N1 (R) To neuron N q (R) (Here, q is an integer greater than or equal to 1.)

[0121] in addition, Figure 1A In addition to neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the neuron N in the (k-1) layer is also shown. i (k-1) (Here, i is an integer greater than or equal to 1 and less than or equal to m.) The neurons N in the k-th layer j (k) (Here, j is an integer greater than or equal to 1 and less than or equal to n.) Other neurons are omitted.

[0122] Next, the transmission of signals from the neurons of the previous layer to the neurons of the next layer and the signals input to or output from each neuron are described. Note that in this specification, the focus is on the neurons N in the kth layer. j (k) .

[0123] Figure 1B Shows the neurons N in the kth layer j (k) , input to neuron N j (k) The signal from neuron N j (k) Output signal.

[0124] Specifically, the neuron N1 in the (k-1)th layer (k-1) To neuron N m (k-1) The output signal of each of the z1 (k-1) to z m(k-1) To neuron N j (k) Output. Then, neuron N j (k) According to z1 (k-1) to z m (k-1) Generate z j (k) And z j (k) The output signal is output to each neuron in the (k+1)th layer (not shown).

[0125] The transmission strength of the signal input from the neurons of the previous layer to the neurons of the next layer is determined by the binding strength of the synapses connecting them (hereinafter referred to as weight coefficients). In the neural network 100, the signal output from the neurons of the previous layer is multiplied by the corresponding weight coefficients and input to the neurons of the next layer. When i is set to an integer greater than 1 and less than m and the neurons N of the (k-1) layer are i (k-1) With the neurons N in the kth layer j (k) The weight coefficient of the synapse between When the input is to the neuron N in the kth layer j (k) The signal can be expressed by formula (1.1).

[0126] [Formula 1]

[0127]

[0128] In other words, from the neuron N1 in the (k-1)th layer (k-1) To neuron N m (k-1) Each neuron N in the kth layer j (k) When transmitting a signal, z1 is used as the signal (k-1) to z m (k-1) is multiplied by the weight coefficient corresponding to each signal ( to ). Then, for the neurons N in the kth layer j (k) enter to At this time, for the neurons N in the kth layer j (k) The sum of the input signals u j (k) This becomes equation (1.2).

[0129] [Formula 2]

[0130]

[0131] Neuron N j (k) According to u j (k) Generate output signal z j (k) Here, the following formula is used to define the j (k) The output signal z j (k) .

[0132] [Formula 3]

[0133]

[0134] Function f(u j ( k )) is the activation function in a layered neural network. A step function, linear ramp function, sigmoid function, and so on can be used. You can use the same activation function in all neurons, or you can use different activation functions in all neurons. Furthermore, the activation function can be the same or different in each layer.

[0135] The signals output by the neurons in each layer can be either analog or digital. For example, the digital values ​​can be either binary or ternary. When the signals are analog, a linear ramp function, a sigmoid function, or the like can be used as the activation function. When the signals are binary digital, a step function that outputs -1 or 1, or 0 or 1, can be used, for example. Furthermore, the signals output by the neurons in each layer can also be ternary or more. In this case, a ternary activation function can be used, such as a step function that outputs -1, 0, or 1, or a step function that outputs 0, 1, or 2.

[0136] Neural network 100 receives an input signal from the first layer (input layer). Each layer from the first layer (input layer) to the last layer (output layer) sequentially generates an output signal using equations (1.1) to (1.3) based on the signal input from the previous layer, and then outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of the calculation performed by neural network 100.

[0137] <Configuration Example of Arithmetic Circuit>

[0138] Here, an example of an arithmetic circuit capable of performing the calculations of equations (1.2) and (1.3) in the above-mentioned neural network 100 is described. Note that in this arithmetic circuit, as an example, the weight coefficients of the synaptic circuits of the neural network 100 are set to binary values ​​(a combination of "-1" and "+1" or a combination of "0" and "+1", etc.) or ternary values ​​(a combination of "-1", "0", and "1", etc.), and the activation function of the neuron is a function that outputs a binary value (a combination of "-1" and "+1" or a combination of "0" and "+1", etc.) or a ternary value (a combination of "-1", "0", and "1"). In addition, in this specification, etc., one of the weight coefficients and the value of the signal input from the neurons of the previous layer to the neurons of the next layer (sometimes referred to as the calculation value) is referred to as the first data, and the other is referred to as the second data.

[0139] For example, Figure 2 The arithmetic circuit 110 shown is a semiconductor device including an array unit ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 110 is a semiconductor device that receives an input signal. Figure 1A and Figure 1B Neuron N1 in the kth layer (k) To neuron N n (k) Signal z1 (k-1) to z m (k-1) Processing is performed to generate the (k) To neuron N n (k) Each output signal z1 (k) to z n (k) circuit.

[0140] Furthermore, all or part of arithmetic circuit 110 can be used for purposes other than neural networks and AI. For example, when performing sum-of-product operations or matrix operations in image processing or scientific computing, all or part of arithmetic circuit 110 can be used to perform these operations. In other words, all or part of arithmetic circuit 110 can be used for general calculations in addition to AI calculations.

[0141] Circuit ILD is electrically connected to, for example, wiring IL[1] to wiring IL[n] and wiring ILB[1] to wiring ILB[n]. Circuit WLD is electrically connected to, for example, wiring WLS[1] to wiring WLS[m]. Circuit XLD is electrically connected to, for example, wiring XLS[1] to wiring XLS[m]. Circuit AFP is electrically connected to, for example, wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n].

[0142] Array Department ALP

[0143] The array unit ALP includes, for example, m×n circuits MP. The circuits MP are arranged in a matrix of, for example, m rows and n columns within the array unit ALP. Figure 2 In , the circuit MP located in row i and column j (where i is an integer from 1 to m, and j is an integer from 1 to n) is represented as circuit MP[i, j]. Figure 2 In FIG. 1 , only the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n], and the circuit MP[m,n] are shown, and the other circuits MPC are omitted.

[0144] The circuit MP[i,j] is electrically connected to, for example, the wiring IL[j], the wiring ILB[j], the wiring WLS[i], the wiring XLS[i], the wiring OL[j], and the wiring OLB[j].

[0145] The circuit MP[i,j] has, for example, a holding neuron N i (k-1) and neuron N j (k) Specifically, the circuit MP[i, j] holds data (e.g., potential, resistance, current, etc.) corresponding to the first data (weight coefficient) input from the wiring IL[j] and the wiring ILB[j]. In addition, the circuit MP[i, j] has the function of receiving the weight coefficient from the neuron N i (k-1) Output signal z i (k-1) Specifically, the circuit MP[i, j] inputs the second data z from the wiring XLS[i], and outputs the product of the first data (sometimes referred to as the other of the first data and the second data. Here, it is referred to as the second data). i (k-1) , data (e.g., current, voltage, etc.) corresponding to the product of the first data and the second data, or data (e.g., current, voltage, etc.) related to the product of the first data and the second data, is output to the wiring OL[j] and the wiring OLB[j]. Note that an example is shown in which the wiring IL[j] and the wiring ILB[j] are not provided, but one embodiment of the present invention is not limited to this, and only one of the wiring IL[j] and the wiring ILB[j] may be provided. Also, an example is shown in which the wiring OL[j] and the wiring OLB[j] are provided, but one embodiment of the present invention is not limited to this, and only one of the wiring OL[j] and the wiring OLB[j] may be provided.

[0146] Circuit ILD

[0147] For example, the circuit ILD has a first data element corresponding to each input of the circuit MP[1,1] to the circuit MP[m,n] through the wiring IL[1] to the wiring IL[n] and the wiring ILB[1] to the wiring ILB[n]. to Specifically, the circuit ILD supplies the first data corresponding to the weight coefficient to the circuit MP[i, j] through the wiring IL[j] and the wiring ILB[j]. data (e.g., potential, resistance, or current).

[0148] Circuit WLD

[0149] Circuit WLD, for example, has a function of selecting a circuit MP into which data corresponding to first data (e.g., potential, resistance, current, etc.) input from circuit ILD is written. For example, when writing data (e.g., potential, resistance, current, etc.) to circuits MP[i,1] to MP[i,n] located in the i-th row of array portion ALP, circuit WLD, for example, supplies a signal to wiring WLS[i] for turning on or off the write switching elements included in circuits MP[i,1] to MP[i,n], and supplies wiring WLS with a potential for turning off the write switching elements included in circuits MP other than the i-th row. Note that while an example of wiring WLS[i] is shown, one embodiment of the present invention is not limited to this. For example, multiple wirings WLS[i] may also be provided.

[0150] <<Circuit XLD>>

[0151] For example, the circuit XLD supplies the circuit MP[1,1] to the circuit MP[m,n] through the wiring XLS[1] to the wiring XLS[m] with the equivalent of the signal from the neuron N1. (k-1) To neuron N m (k) The second data z1 of the output operation value (k-1) to z m (k-1) Specifically, the circuit XLD supplies the circuit MP[i,1] to the circuit MP[i,n] by the wiring XLS[i] from the neuron N i (k-1) The output corresponds to the second data z i (k-1) Note that although an example of configuring wiring XLS[i] is shown, one embodiment of the present invention is not limited to this. For example, multiple wirings XLS[i] may be configured.

[0152] Circuit AFP

[0153] Circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. Circuit ACTF[j] is electrically connected to wiring OL[j] and wiring OLB[j]. Circuit ACTF[j] generates, for example, a signal corresponding to each data (e.g., potential, current value, etc.) input from wiring OL[j] and wiring OLB[j]. For example, it compares each data (e.g., potential, current value, etc.) input from wiring OL[j] and wiring OLB[j] to generate a signal corresponding to the comparison result. This signal is equivalent to the signal from neuron N. j (k) Output signal z j (k) . In other words, the circuit ACTF[1] to the circuit ACTF[n] are used, for example, as a circuit for performing operations on the activation function of the above-mentioned neural network. Note that one embodiment of the present invention is not limited to this. For example, the circuit ACTF[1] to the circuit ACTF[n] may also have a function of converting an analog signal into a digital signal. Or, for example, the circuit ACTF[1] to the circuit ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting the output impedance. Note that an example in which the circuit ACTF is configured is shown, but one embodiment of the present invention is not limited to this, and the circuit ACTF may not be configured.

[0154] Circuits ACTF[1] to ACTF[n] can be implemented, for example, Figure 3A The circuit structure shown. Figure 3A For example, a signal z is generated based on the current input from the wiring OL[j] and the wiring OLB[j]. j (k) Specifically, Figure 3A The output will be a 2-valued signal z j (k) An example of an arithmetic circuit for the output activation function.

[0155] exist Figure 3AIn FIG, circuit ACTF[j] includes a resistor RE, a resistor REB, and a comparator CMP. Resistors RE and REB have the function of converting current into voltage. Therefore, any element or circuit that has the function of converting current into voltage is not limited to resistors. Wiring OL[j] is electrically connected to the first terminal of resistor RE and the first input terminal of comparator CMP, and wiring OLB[j] is electrically connected to the first terminal of resistor REB and the second input terminal of comparator CMP. In addition, the second terminal of resistor RE is electrically connected to wiring VAL, and the second terminal of resistor REB is electrically connected to wiring VAL. Note that the second terminal of resistor RE and the second terminal of resistor REB can also be connected to the same wiring. Alternatively, they can also be connected to other wirings with the same potential.

[0156] The resistance values ​​of the resistors RE and REB are preferably the same. For example, the difference between the resistance values ​​of the resistors RE and REB is preferably within 10%, and more preferably within 5%. Note that one embodiment of the present invention is not limited to this. Depending on circumstances or conditions, the resistance values ​​of the resistors RE and REB may be set to different values.

[0157] Wiring VAL is used, for example, as a wiring for supplying a constant voltage. This constant voltage can be, for example, a high-level potential VDD, a low-level potential VSS, or a ground potential (GND). Furthermore, this constant voltage is preferably appropriately set according to the configuration of circuit MP. Alternatively, for example, a pulse signal may be supplied to wiring VAL instead of a constant voltage.

[0158] The voltage between the first and second terminals of resistor RE is determined by the current flowing through wiring OL[j]. Therefore, the resistance value of resistor RE and the voltage corresponding to this current are input to the first input terminal of comparator CMP. Similarly, the voltage between the first and second terminals of resistor REB is determined by the current flowing through wiring OLB[j]. Therefore, the resistance value of resistor REB and the voltage corresponding to this current are input to the second input terminal of comparator CMP.

[0159] Comparator CMP, for example, has the function of comparing the voltages input to its first and second input terminals and outputting a signal from its output terminal based on the comparison result. For example, comparator CMP can output a high-level potential from its output terminal when the voltage input to its second input terminal is higher than the voltage input to its first input terminal, and a low-level potential from its output terminal when the voltage input to its first input terminal is higher than the voltage input to its second input terminal. In other words, the potentials output from comparator CMP's output terminal are either a high-level potential or a low-level potential. Therefore, the output signal z output by circuit ACTF[j] isj (k) For example, each of the high-level potential and the low-level potential output from the output terminal of the comparator CMP can be used as the output signal z j (k) Corresponding to "+1" and "-1". In addition, depending on the situation, each of the high-level potential and the low-level potential output from the output terminal of the comparator CMP can also be used as the output signal z j (k) Corresponding to "+1", "0".

[0160] In addition, Figure 3A The circuit ACTF[j] uses resistors RE and REB, but any element or circuit that has the function of converting current into voltage is not limited to resistors. Figure 3A The resistors RE and REB of the circuit ACTF[j] can be replaced by other circuit elements. For example, Figure 3B The circuit ACTF[j] shown is Figure 3A The circuit ACTF[j] can be replaced by the resistor RE and the resistor REB with the capacitor CE and the capacitor CEB. Figure 3A The circuit ACTF[j] works in roughly the same manner. In addition, the value of the electrostatic capacitance of each of the capacitors CE and CEB is preferably equal to each other. For example, the difference in the value of the electrostatic capacitance of each of the capacitors CE and CEB is preferably within 10%, more preferably within 5%. Note that one embodiment of the present invention is not limited to this. In addition, a circuit for initializing the charge accumulated in the capacitors CE and CEB may be provided. For example, a switch may be provided in such a manner that the capacitor CE is connected in parallel. In other words, it may be that the second terminal of the switch is connected to the wiring VAL, and the first terminal of the switch is connected to the first terminal of the capacitor CE, the wiring OL[j], and the first input terminal of the comparator CMP. Alternatively, it may be that the second terminal of the switch is connected to a wiring different from the wiring VAL, and the first terminal of the switch is connected to the first terminal of the capacitor CE, the wiring OL[j], and the first input terminal of the comparator CMP. In addition, Figure 3C The circuit ACTF[j] shown is Figure 3A The circuit ACTF[j] can be replaced with a circuit in which the resistors RE and REB are replaced with diodes DE and DEB. Figure 3A The directions of the diode elements DE and DEB (the connection points between the anode and the cathode) are preferably changed appropriately according to the potential of the wiring VAL.

[0161] in addition, Figures 3A to 3CThe comparator CMP in the circuit ACTF[j] can be replaced by an operational amplifier OP, for example. Figure 3D The circuit shown in ACTF[j] shows that Figure 3A The circuit diagram of the circuit ACTF[j] is shown in FIG. 1 , in which the comparator CMP is replaced by the operational amplifier OP.

[0162] In addition, you can also Figure 3B The circuit ACTF[j] is provided with switches S01a and S01b. Thus, the circuit ACTF[j] can maintain a potential corresponding to the current input from the wiring OL[j] and the wiring OLB[j] in each of the capacitors CE and CEB. Figure 3E As shown, as a specific example of the circuit, the following structure can be adopted: the first terminal of the switch S01a is electrically connected to the wiring OL[j], the second terminal of the switch S01a is electrically connected to the first terminal of the capacitor CE and the first input terminal of the comparator CMP, the first terminal of the switch S01b is electrically connected to the wiring OLB[j], and the second terminal of the switch S01b is electrically connected to the first terminal of the capacitor CEB and the second input terminal of the comparator CMP. Figure 3E In circuit ACTF[j], when the potential of wiring OL[j] and wiring OLB[j] is input to the first and second input terminals of comparator CMP, the potential can be input by turning on each of switches S01a and S01b. Furthermore, by subsequently turning off both switches S01a and S01b, the potential input to each of the first and second input terminals of comparator CMP is maintained at capacitors CE and CEB. Switches S01a and S01b can be electrical switches such as analog switches or transistors. Mechanical switches can also be mechanical switches. Note that when transistors are used as switches S01a and S01b, they can be OS transistors or transistors whose channel formation regions include silicon (hereinafter referred to as Si transistors). Alternatively, the voltage values ​​of capacitors CE and CEB can be controlled by controlling the period during which switches S01a and S01b are both turned on. For example, when the current flowing through capacitors CE and CEB is large, the voltage across capacitors CE and CEB can be prevented from becoming excessively high by shortening the period during which switches S01a and S01b are both in the off state.

[0163] in addition, Figures 3A to 3C 、 Figure 3E The comparator CMP in the circuit ACTF[j] can be a chopper comparator, for example. Figure 3FThe illustrated comparator CMP is a chopper comparator and includes switches S02a, S02b, S03, a capacitor CC, and an inverter circuit INV3. Like the switches S01a and S01b described above, switches S02a, S02b, and S03 can be mechanical switches, OS transistors, Si transistors, or other transistors.

[0164] A first terminal of switch S02a is electrically connected to terminal VinT, a first terminal of switch S02b is electrically connected to terminal VrefT, and a second terminal of switch S02a is electrically connected to the second terminal of switch S02b and the first terminal of capacitor CC. The second terminal of capacitor CC is electrically connected to the input terminal of inverter circuit INV3 and the first terminal of switch S03. Terminal VoutT is electrically connected to the output terminal of inverter circuit INV3 and the second terminal of switch S03.

[0165] The terminal VinT is used as a terminal for inputting an input potential to the comparator CMP, the terminal VrefT is used as a terminal for inputting a reference potential to the comparator CMP, and the terminal VoutT is used as a terminal for outputting an output potential from the comparator CMP. The terminal VinT may correspond to Figures 3A to 3C 、 Figure 3E One of the first terminal and the second terminal of the comparator CMP, the terminal VrefT may correspond to Figures 3A to 3C 、 Figure 3E The other of the first terminal and the second terminal of the comparator CMP.

[0166] Figures 3A to 3E The circuit ACTF[j] outputs a binary output signal z j (k) The activation function operation circuit of the circuit ACTF[j] can also be used to convert the output signal z j (k) This is a structure that outputs three or more values ​​or analog values.

[0167] Figures 4A to 4F The signal z is generated based on the current input from the wiring OL[j] and the wiring OLB[j]. j (k) The circuit is shown to output a 3-valued output signal z. j (k) An example of an activation function operation circuit.

[0168] Figure 4AThe circuit ACTF[j] shown includes a resistor RE, a resistor REB, a comparator CMPa, and a comparator CMPb. Wiring OL[j] is electrically connected to the first terminal of resistor RE and the first input terminal of comparator CMPa, while wiring OLB[j] is electrically connected to the first terminal of resistor REB and the first input terminal of comparator CMPb. Furthermore, the second input terminal of comparator CMPa and the second input terminal of comparator CMPb are electrically connected to wiring VrefL. Furthermore, the second terminal of resistor RE is electrically connected to wiring VAL, and the second terminal of resistor REB is electrically connected to wiring VAL.

[0169] The wiring VrefL is used to supply a constant voltage V ref Wiring, V ref For example, it is preferably above GND and below VDD. In addition, depending on the situation, V ref It can also be a potential lower than GND or a potential higher than VDD. ref It is regarded as a reference potential (comparison potential) in the comparator CMPa and the comparator CMPb.

[0170] The voltage between the first and second terminals of resistor RE is determined by the current flowing through wiring OL[j]. Therefore, the resistance value of resistor RE and the voltage corresponding to this current are input to the first input terminal of comparator CMPa. Similarly, the voltage between the first and second terminals of resistor REB is determined by the current flowing through wiring OLB[j]. Therefore, the resistance value of resistor REB and the voltage corresponding to this current are input to the first input terminal of comparator CMPb.

[0171] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal and outputs a signal from the output terminal of the comparator CMPa according to the comparison result. For example, the comparator CMPa may output a signal when the voltage input to the second input terminal (V ref ) is higher than the voltage input to the first input terminal, a high level potential is output from the output terminal of the comparator CMPa, and when the voltage input to the first input terminal is higher than the voltage input to the second input terminal (V ref ) when a low-level potential is output from the output terminal of the comparator CMPa.

[0172] Similar to the comparator CMPa, the comparator CMPb compares the voltages input to the first input terminal and the second input terminal and outputs a signal from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb may output a signal based on the voltage input to the second input terminal (V ref) is higher than the voltage input to the first input terminal, a high level potential is output from the output terminal of the comparator CMPb, and a high level potential is output when the voltage input to the first input terminal is higher than the voltage input to the second input terminal (V ref ), a low-level potential is output from the output terminal of the comparator CMPb.

[0173] At this time, the potential output from each output terminal of the comparator CMPa and the comparator CMPb represents a three-valued output signal z. j (k) For example, when a high-level potential is output from the output terminal of the comparator CMPa and a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) It can be “+1”. When a low-level potential is output from the output terminal of the comparator CMPa and a high-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) It can be “-1”. When a low-level potential is output from the output terminal of the comparator CMPa and a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) Can be "+0".

[0174] In addition, the circuit ACTF[j] is not limited to Figure 4A The circuit structure shown can be changed according to the situation. For example, when Figure 4A When the two output results of the comparator CMPa and the comparator CMPb are to be combined into one signal in the circuit ACTF[j], a conversion circuit TRF may be provided in the circuit ACTF[j]. Figure 4B The circuit ACTF[j] is Figure 4A The circuit ACTF[j] is provided with a conversion circuit TRF, and the output terminals of the comparators CMPa and CMPb are electrically connected to the input terminals of the conversion circuit TRF. As a specific example of the conversion circuit TRF, a digital-to-analog conversion circuit (in this case, the signal z j (k) is the analog value. ) etc.

[0175] In addition, for example, Figure 4A In the embodiment, the wiring VrefL electrically connected to the second input terminal of each of the comparators CMPa and CMPb may be replaced with two wirings, namely, the wirings Vref1L and Vref2L. Figure 4C The circuit ACTF[j] has Figure 4AIn the circuit ACTF[j], the second terminal of comparator CMPa is electrically connected to wiring Vref1L and not to wiring VrefL, while the second terminal of comparator CMPb is electrically connected to wiring Vref2L and not to wiring VrefL. By setting different potentials to the wirings Vref1L and Vref2L, the reference potentials of comparators CMPa and CMPb can be set independently.

[0176] In addition, for example, as Figures 4A to 4C In addition to the circuit ACTF[j], an amplifier circuit or an impedance converter circuit may be used. For example, Figure 4D The circuit shown, ACTF[j], is used to Figure 2 The circuit AFP of the arithmetic circuit 110. Figure 4D The circuit ACTF[j] includes a resistor RE, a resistor REB, an operational amplifier OPa, and an operational amplifier OPb, and is used as an amplification circuit.

[0177] Wiring OL[j] is electrically connected to the first terminal of resistor RE and the non-inverting input terminal of operational amplifier OPa, while wiring OLB[j] is electrically connected to the first terminal of resistor REB and the non-inverting input terminal of operational amplifier OPb. Furthermore, the non-inverting input terminal of operational amplifier OPa is electrically connected to the output terminal of operational amplifier OPa, while the inverting input terminal of operational amplifier OPb is electrically connected to the output terminal of operational amplifier OPb. Furthermore, the second terminal of resistor RE is electrically connected to wiring VAL, while the second terminal of resistor REB is electrically connected to wiring VAL.

[0178] In other words, Figure 4D The operational amplifiers OPa and OPb in the circuit ACTF[j] have a voltage follower connection structure. With this structure, the potential output from the output terminal of the operational amplifier OPa is substantially the same as the potential input to the non-inverting input terminal of the operational amplifier OPa, and the potential output from the output terminal of the operational amplifier OPb is substantially the same as the potential input to the non-inverting input terminal of the operational amplifier OPb. In this case, the output signal z j (k) As two analog values, the circuit ACTF[j] outputs the output. Note that the output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb can also be connected to the input terminal of the comparator CMP. Furthermore, the output from the comparator CMP can also be the output signal z j (k) .

[0179] In addition, for example, as Figures 4A to 4DIn addition to the structure of the circuit ACTF[j], an integration circuit, a current-voltage conversion circuit, etc. can also be used. Furthermore, an integration circuit or a current-voltage conversion circuit can also be formed using an operational amplifier. For example, Figure 4E The circuit shown, ACTF[j], is used to Figure 2 The circuit AFP of the arithmetic circuit 110. Figure 4E The circuit ACTF[j] includes an operational amplifier OPa, an operational amplifier OPb, a load element LEa, and a load element LEb.

[0180] Wiring OL[j] is electrically connected to the first input terminal (e.g., the inverting input terminal) of the operational amplifier OPa and the first terminal of the load element LEa. Wiring OLB[j] is electrically connected to the first input terminal (e.g., the inverting input terminal) of the operational amplifier OPb and the first terminal of the load element LEb. Furthermore, the second input terminal (e.g., the non-inverting input terminal) of the operational amplifier OPa is electrically connected to wiring Vref1L, and the second input terminal (e.g., the non-inverting input terminal) of the operational amplifier OPb is electrically connected to wiring Vref2L. The second terminal of the load element LEa is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is electrically connected to the output terminal of the operational amplifier OPb.

[0181] Here, the wiring Vref1L and the wiring Vref2L are used as wirings for supplying the same voltage or different voltages to each other. Therefore, the wiring Vref1L and the wiring Vref2L may be combined into one wiring.

[0182] exist Figure 4E In the circuit ACTF[j], resistors and capacitors can be used as the load elements LEa and LEb, for example. In particular, by using capacitors as the load elements LEa and LEb, the operational amplifier OPa and the load element LEa, as well as the operational amplifier OPb and the load element LEb, are both used as integrating circuits. In other words, charge accumulates in each capacitor (load elements LEa and LEb) according to the amount of current flowing through the wiring OL[j] or wiring OLB[j]. In other words, the integrated current amount flowing through the wiring OL[j] and wiring OLB[j] is converted into a voltage using the integrating circuit and output as the signal z. j (k) Note that the output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb can also be connected to the input terminal of the comparator CMP. And the output from the comparator CMP is the output signal z j (k)Alternatively, a circuit may be provided to initialize the charge accumulated in the capacitors of load element LEa and load element LEb. For example, a switch may be provided in parallel with load element LEa (capacitor). In other words, the second terminal of the switch may be connected to the output terminal of operational amplifier OPa, and the first terminal of the switch may be connected to wiring OL[j] and the first input terminal (e.g., the inverting input terminal) of operational amplifier OPa.

[0183] In addition, Figure 4E In the circuit ACTF[j], when converting the current flowing through the wiring OL[j] and the wiring OLB[j] into a voltage and outputting it, resistors may be used as the load elements LEa and LEb in addition to capacitors.

[0184] In addition, for example, as Figures 4A to 4E The circuit ACTF[j] can be Figure 4F The circuit shown, ACTF[j], is applied to Figure 2 The circuit AFP of the arithmetic circuit 110. Figure 4F The circuit ACTF[j] includes a resistor RE, a resistor REB, an analog-to-digital conversion circuit ADCa, and an analog-to-digital conversion circuit ADCb.

[0185] Wiring OL[j] is electrically connected to an input terminal of analog-to-digital conversion circuit ADCa and a first terminal of resistor RE. Wiring OLB[j] is electrically connected to an input terminal of analog-to-digital conversion circuit ADCb and a first terminal of resistor REB. The second terminal of resistor RE is electrically connected to wiring VAL, and the second terminal of resistor REB is electrically connected to wiring VAL.

[0186] exist Figure 4F In the circuit ACTF[j], the potential of each first terminal of the resistor RE and the resistor REB is determined by the current flowing through the wiring OL[j] and the wiring OLB[j]. Then, the circuit ACTF[j] converts the analog potential into a digital value of two or more values ​​(for example, 256 values) by the analog-to-digital conversion circuits ADCa and ADCb, and outputs the digital value as a signal z. j (k) Output function.

[0187] and Figure 3B 、 Figure 3C same, Figures 4A to 4F The resistors RE and REB shown in FIG. 4 can be replaced by capacitors CE and CEB or diode elements DE and DEB. Figures 4A to 4F When the resistors RE and REB shown in the figure are replaced by capacitors CE and CEB, Figure 3ESimilarly, switches S01a and S01b are provided to hold the potential input from wiring OL[j] and wiring OLB[j].

[0188] in addition, Figure 2 The operation circuit 110 can change the number of wirings electrically connected to the circuit MP[i, j] according to the circuit structure of the circuit MP[i, j]. Figure 2 In the arithmetic circuit 110, the wiring WLS[i] electrically connected to the circuit MP[i, j] may be one or more wirings. In addition, for example, the wiring XLS[i] electrically connected to the circuit MP[i, j] may be one or more wirings.

[0189] Circuit MP

[0190] Next, a configuration example of the circuit MP[i, j] in the arithmetic circuit 110 will be described.

[0191] Figure 5A The following illustrates an example configuration of circuit MP[i, j] that can be used in arithmetic circuit 110. Circuit MP[i, j] includes, for example, circuit MC and circuit MCr. Circuit MC and circuit MCr calculate the product of weight coefficients and neuron input signals (calculated values) in circuit MP. Circuit MC can have the same configuration as circuit MCr or a different configuration. Therefore, to distinguish it from circuit MC, the symbol "r" is appended to circuit MCr. Furthermore, the symbols of circuit elements in circuit MCr, described later, are also appended with "r."

[0192] For example, the circuit MC includes a holding unit HC, and the circuit MCr includes a holding unit HCr. Each of the holding unit HC and the holding unit HCr has a function of holding data (e.g., potential, resistance value, current value, etc.). In addition, the first data set by the circuit MP[i, j] is The first data is determined by the data (e.g., potential, resistance, current, etc.) held by each of the holding unit HC and the holding unit HCr. The wiring IL[j] and the wiring ILB[j] of each data (for example, potential, resistance value, current value, etc.) are electrically connected.

[0193] Figure 5A The wiring WL[i] shown is equivalent to Figure 2 The wiring WLS[i] in the circuit MP[i, j] is electrically connected to each of the holding portion HC and the holding portion HCr. When the first data is written to each of the holding portion HC and the holding portion HCr in the circuit MP[i, j], When the data (e.g., potential, resistance value, current value, etc.) corresponding to the first data is input, the wiring IL[j] and the holding portion HC are brought into conduction, and the wiring ILB[j] and the holding portion HCr are brought into conduction. The potential etc. can be input to each of the holding part HC and the holding part HCr. Then, a predetermined potential is supplied to the wiring WL[i] to make the wiring IL[j] and the holding part HC non-conductive and the wiring ILB[j] and the holding part HCr non-conductive. As a result, each of the holding part HC and the holding part HCr holds the first data. The various potentials, etc.

[0194] For example, consider the first data In the case of any of the three values ​​of "-1", "0", and "1". When the first data is "1", for example, the holding portion HC holds a high level potential and the holding portion HCr holds a low level potential. When the first data is "-1", for example, the holding portion HC holds a low level potential and the holding portion HCr holds a high level potential. When the first data is "0", for example, the holding portion HC holds a low level potential and the holding portion HCr holds a low level potential. For analog values, specifically, "negative analog value", "0" or "positive analog value". When the value is a "positive analog value", for example, the holding portion HC holds a high analog potential and the holding portion HCr holds a low analog potential. When the first data is a "negative analog value", for example, the holding portion HC holds a low level potential and the holding portion HCr holds a high level analog potential. When the first data is "0", for example, the holding portion HC holds a low level potential and the holding portion HCr holds a low level potential. Note that a multi-bit (multi-value) digital value may also be used as the analog value. In other words, for example, in the first data When the first data is "1", "2", or "3", for example, the holding portion HC holds a high level potential corresponding to the potential of "1", "2", or "3", and the holding portion HCr holds a low level potential. For example, when the absolute values ​​of "-1", "-2", and "-3" are "-1", "-2", and "-3", the holding portion HC holds a low level potential, and the holding portion HCr holds a high level potential of "1", "2", and "3" corresponding to the absolute values ​​of "-1", "-2", and "-3". When it is "0", for example, the holding portion HC holds a low-level potential and the holding portion HCr holds a low-level potential.

[0195] In addition, for example, the circuit MC has a function of outputting a current, a voltage, etc. corresponding to the data held by the holding portion HC (for example, potential, resistance value, current value, etc.) to one of the wiring OL[j] and the wiring OLB[j], and the circuit MCr has a function of outputting a current, a voltage, etc. corresponding to the data held by the holding portion HCr (for example, potential, resistance value, current value, etc.) to the other of the wiring OL[j] and the wiring OLB[j]. For example, when the holding portion HC maintains a high-level potential, the circuit MC outputs a current having a first current value, and when the holding portion HC maintains a low-level potential, the circuit MC outputs a current having a second current value. Similarly, when the holding portion HCr maintains a high-level potential, the circuit MCr outputs a current having a first current value, and when the holding portion HCr maintains a low-level potential, the circuit MCr outputs a current having a second current value. Note that the magnitude of each of the first current value and the second current value varies depending on the structure of the circuit MC, the circuit MCr, the holding portion HC, the holding portion HCr, the first data For example, the first current value may be greater than or less than the second current value. In addition, sometimes one of the first current value and the second current value is zero current, that is, 0. In addition, sometimes the direction in which the current having the first current value flows is different from the direction in which the current having the second current value flows. In particular, for example, in the first data When the first data is any of the three values ​​of "-1", "0", and "1", it is preferable to configure the circuit MC and the circuit MCr so that one of the first current value and the second current value is 0. When the first current value or the second current value is an analog value, for example, a “negative analog value”, “0” or a “positive analog value”, the first current value or the second current value may be an analog value.

[0196] In this specification, etc., the current, voltage, etc. corresponding to the data (e.g., potential, resistance, current, etc.) held in the holding portion HC and the holding portion HCr may be positive, negative, or a mixture of positive and negative currents or voltages. In other words, for example, the description "having a function of outputting a current, voltage, etc. corresponding to the data (e.g., potential, resistance, current, etc.) held in the holding portion HC to one of the wiring OL[j] and the wiring OLB[j], and the circuit MCr having a function of outputting a current, voltage, etc. corresponding to the data (e.g., potential, resistance, current, etc.) held in the holding portion HCr to the other of the wiring OL[j] and the wiring OLB[j]" can be replaced with the description "having a function of discharging a current, voltage, etc. corresponding to the data (e.g., potential, resistance, current, etc.) held in the holding portion HC from one of the wiring OL[j] and the wiring OLB[j], and the circuit MCr having a function of discharging a current corresponding to the potential held in the holding portion HCr from the other of the wiring OL[j] and the wiring OLB[j]."

[0197] Figure 5A The wiring X1L[i] and the wiring X2L[i] shown are equivalent to Figure 2 The second data z input to the circuit MP[i, j] is the wiring XLS[i]. i (k-1) For example, it is determined by the potential, current, etc. of each of the wiring X1L[i] and the wiring X2L[i]. Therefore, the circuit MC and the circuit MCr are inputted with the second data z through the wiring X1L[i] and the wiring X2L[i]. i (k-1) The potentials of .

[0198] Circuit MC is electrically connected to wiring OL[j] and wiring OLB[j], and circuit MCr is electrically connected to wiring OL[j] and wiring OLB[j]. Circuit MC and circuit MCr output signals corresponding to the first data to wiring OL[j] and wiring OLB[j] based on the potential input to wiring X1L[i] and wiring X2L[i]. With the second data z i (k-1)The product of current, potential, etc. Specifically, for example, the wiring to which the current from circuits MC and MCr is output is determined by the potential of wiring X1L[i] and wiring X2L[i]. For example, each of circuits MC and MCr has a circuit structure in which the current output from circuit MC flows through one of wiring OL[j] and wiring OLB[j], and the current output from circuit MCr flows through the other of wiring OL[j] and wiring OLB[j]. In other words, the currents output from circuits MC and MCr do not flow through the same wiring, but rather through different wirings. Note that, for example, current may not flow from circuits MC and MCr to wiring OL[j] and wiring OLB[j].

[0199] For example, consider the second data z i (k-1) When the value is any of the three values ​​of "-1", "0", and "1". i (k-1) When the second data z is "1", the circuit MP makes the circuit MC and the wiring OL[j] conductive and makes the circuit MCr and the wiring OLB[j] conductive. i (k-1) When the value is "-1", the circuit MP makes the circuit MC and the wiring OLB[j] conductive and the circuit MCr and the wiring OL[j] conductive. i (k-1) When it is "0", in order to prevent the current output by each circuit MC and MCr from flowing through the wiring OL[j] and the wiring OLB[j], the circuit MP puts the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] in a non-conductive state and puts the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] in a non-conductive state.

[0200] An example of summarizing the above operations is shown. When the first data When the second data z is "-1", the current is output from the circuit MCr. i (k-1) When the second data z is "1", the circuit MC and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1) When the first data is "-1", the circuit MC and the wiring OLB[j] and the circuit MCr and the wiring OL[j] are in a conductive state. With the second data z i (k-1)When the product is positive, current is output to the wiring OL[j]. With the second data z i (k-1) When the product is negative, current is output to the wiring OLB[j]. With the second data z i (k-1) When the product is zero, no current is output to the above wiring.

[0201] The above example is specifically recorded in the first data is "1" and the second data z i (k-1) When the first data is "1", for example, a current I1[i,j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MCr to the wiring OLB[j]. is "-1" and the second data z i (k-1) When the value is "1", for example, the current I1[i, j] having the second current value flows from the circuit MC to the wiring OL[j], and the current I2[i, j] having the first current value flows from the circuit MCr to the wiring OLB[j]. In this case, the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j]. is "0" and the second data z i (k -1) When the bit is "1," current I1[i,j] having the second current value flows from the circuit MC to the wiring OL[j], and current I2[i,j] having the second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j], and no current flows from the circuit MCr to the wiring OLB[j].

[0202] In the first data is "1" and the second data z i (k-1) When the value is "-1", the current I1[i,j] with the first current value flows from the circuit MC to the wiring OLB[j], and the current I2[i,j] with the second current value flows from the circuit MCr to the wiring OL[j]. In this case, the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MCr to the wiring OL[j]. is "-1" and the second data zi (k-1) When the value is "-1", the current I1[i,j] with the second current value flows from the circuit MC to the wiring OLB[j], and the current I2[i,j] with the first current value flows from the circuit MCr to the wiring OL[j]. In this case, the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OLB[j]. is "0" and the second data z i (k-1) When the value is "-1," current I1[i,j] having the second current value flows from the circuit MC to the wiring OLB[j], and current I2[i,j] having the second current value flows from the circuit MCr to the wiring OL[j]. In this case, the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OLB[j], and no current flows from the circuit MCr to the wiring OL[j].

[0203] In addition, in the second data z i (k-1) When the first data is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. In any case, current is not output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0204] Thus, for example, in the first data With the second data z i (k-1) When the product of the first data When the value is positive, current flows from the circuit MC to the wiring OL[j]. When the value is negative, the current flows from the circuit MCr to the wiring OL[j]. With the second data z i (k-1) When the product of the first data When the value is positive, current flows from the circuit MC to the wiring OLB[j]. When the current is negative, current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or circuit MCr connected to the wiring OL[j] flows through the wiring OL[j]. In other words, a current having a value of a sum of positive values ​​flows through the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or circuit MCr connected to the wiring OLB[j] flows through the wiring OLB[j]. In other words, a current having a value of a sum of negative values ​​flows through the wiring OLB[j]. Due to the above operation, a product-sum operation can be performed by utilizing the sum of the current values ​​flowing through the wiring OL[j], that is, the sum of positive values, and the sum of the current values ​​flowing through the wiring OLB[j], that is, the sum of negative values. For example, when the sum of the current values ​​flowing through the wiring OL[j] is greater than the sum of the current values ​​flowing through the wiring OLB[j], the result of the product-sum operation can be determined to be a positive value. When the sum of the current values ​​flowing through wiring OL[j] is less than the sum of the current values ​​flowing through wiring OLB[j], the result of the product-sum operation can be determined to be a negative value. For example, when the sum of the current values ​​flowing through wiring OL[j] is approximately equal to the sum of the current values ​​flowing through wiring OLB[j], the result of the product-sum operation can be determined to be zero.

[0205] Note that in the second data z i (k-1) The same operation can be performed when the first data w is any binary value among "-1", "0", and "1", for example, the binary value of "-1" and "1" or the binary value of "0" and "1". i (k-1) The same operation can be performed even when the value is any binary value among "-1", "0", and "1", for example, the binary values ​​of "-1" and "1" or the binary values ​​of "0" and "1".

[0206] In addition, the first data It can also be an analog value or a multi-bit (multi-value) digital value. As a specific example, a "negative analog value" can be obtained instead of "-1" and a "positive analog value" can be obtained instead of "1". In this case, the level of the current flowing from the circuit MC or the circuit MCr is also, for example, the level corresponding to the first data. The absolute value of the analog value.

[0207] Next, explain how to Figure 5A Note that the modification examples of the circuit MP[i, j] are mainly explained in relation to Figure 5A The circuit MP[i, j] has different parts, and sometimes omitted with Figure 5A The circuit MP[i, j] is the same as the description of the parts.

[0208] Figure 5BThe circuit MP[i, j] shown is Figure 5A A variation of the circuit MP[i, j]. Figure 5A Similarly, for the circuit MP[i, j], Figure 5B The circuit MP[i, j] includes the circuit MC and the circuit MCr. However, Figure 5B The circuit MP[i, j] does not include a holding portion HCr in the circuit MCr, which is different from Figure 5A The circuits MP[i, j] are different.

[0209] In addition, since the circuit MCr does not include the holding portion HCr, the application Figure 5B The arithmetic circuit of the circuit MP[i,j] may not include the wiring ILB[j] for supplying the potential held in the holding portion HCr. Furthermore, the circuit MCr may not be electrically connected to the wiring WL[i].

[0210] exist Figure 5B In the circuit MP[i, j], the holding portion HC in the circuit MC is electrically connected to the circuit MCr. In other words, Figure 5B The circuit MP[i, j] has a structure in which the circuit MCr and the circuit MC share the holding unit HC. For example, the holding unit HC can supply an inverted signal of the signal held by the holding unit HC to the circuit MCr. This allows the circuit MC and the circuit MCr to perform different operations. In addition, by making the internal circuit structures of the circuit MC and the circuit MCr different, the current output by the circuit MC and the circuit MCr for the same signal held by the holding unit HC can be different. Here, by holding the first data in the holding unit HC, the current output by the circuit MC and the circuit MCr can be different. The potential corresponding to the second data z is supplied to the wiring X1L[i] and the wiring X2L[i]. i (k-1) The circuit MP[i, j] can output the first data to the wiring OL[j] and the wiring OLB[j]. With the second data z i (k-1) The product of the current.

[0211] application Figure 5B The operation circuit 110 of the circuit MP can be changed to Figure 6 The circuit structure of the operation circuit 120 shown in FIG. The operation circuit 120 has Figure 2 The arithmetic circuit 110 does not include the structure of the wiring ILB[1] to the wiring ILB[m].

[0212] Figure 5C The circuit MP[i, j] shown is Figure 5A A variation of the circuit MP[i, j] can be applied to Figure 6 An example of the structure of the circuit MP[i, j] of the arithmetic circuit 120. Figure 5A Similarly, for the circuit MP[i, j], Figure 5C The circuit MP[i, j] includes the circuit MC and the circuit MCr. Figure 5C The structure of the wiring electrically connected to the circuit MP[i, j] is Figure 5A The circuits MP[i, j] are different.

[0213] Figure 5C The wiring W1L[i] and the wiring W2L[i] shown are equivalent to Figure 6 The wiring WLS[i] in FIG. 1 is electrically connected to the holding portion HC, and the wiring W2L[i] is electrically connected to the holding portion HCr.

[0214] In addition, the wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr.

[0215] exist Figure 5C In the circuit MP[i, j], when the holding part HC and the holding part HCr hold different potentials, it is preferable to hold the potentials in the holding part HC and the holding part HCr in sequence rather than simultaneously. For example, consider the case where the first data of the circuit MP[i, j] can be represented by holding the first potential in the holding part HC and holding the second potential in the holding part HCr. First, a specified potential is supplied to the wiring W1L[i] and the wiring W2L[i] respectively, so that the holding part HC and the wiring IL[j] are in a conductive state, and the holding part HCr and the wiring IL[j] are in a non-conductive state. Next, by supplying a first potential to the wiring IL[j], the first potential is supplied to the holding part HC. Then, a specified potential is supplied to the wiring W1L[i] and the wiring W2L[i] respectively, so that the holding part HC and the wiring IL[j] are in a non-conductive state, and the holding part HCr and the wiring IL[j] are in a conductive state. Then, by supplying a second potential to the wiring IL[j], the second potential can be supplied to the holding part HCr. Thus, the circuit MP[i, j] can be set as the first data

[0216] Furthermore, the holding portion HC and the holding portion HCr are kept at substantially the same potential (the first data of the circuit MP[i, j] is set by keeping the holding portion HC and the holding portion HCr at substantially the same potential). ) when the holding portion HC and the wiring IL[j] are in a conductive state and the holding portion HCr and the wiring IL[j] are in a conductive state, respectively, a specified potential is supplied to the wiring W1L[i] and the wiring W2L[i], and then the potential is supplied to the wiring IL[j].

[0217] Figure 5C The circuit MP[i, j] stores the first data corresponding to the first data in the holding part HC and the holding part HCr. The potential corresponding to the second data z is supplied to the wiring X1L[i] and the wiring X2L[i]. i (k-1) The potential, and Figure 5A The circuit MP[i, j] similarly outputs the first data to the wiring OL[j] and the wiring OLB[j]. With the second data z i (k -1) The product of the current.

[0218] Figure 5D The circuit MP[i, j] shown is Figure 5A A variation of the circuit MP[i, j]. Figure 5A Similarly, for the circuit MP[i, j], Figure 5D The circuit MP[i, j] includes the circuit MC and the circuit MCr. Figure 5D The structure of the wiring electrically connected to the circuit MP[i, j] is Figure 5A The circuits MP[i, j] are different.

[0219] Figure 5D The wiring IOL[j] is used as Figure 5A The wiring IL[j] and wiring OL[j] in are combined into one wiring, Figure 5D The wiring IOLB[j] is used as Figure 5A The wiring ILB[j] and the wiring OLB[j] in FIG. 1 are combined into one wiring. Therefore, the wiring IOL[j] is electrically connected to the holding portion HC, the circuit MC, and the circuit MCr, and the wiring IOLB[j] is electrically connected to the holding portion HCr, the circuit MC, and the circuit MCr.

[0220] exist Figure 5D The circuit MP[i, j] holds the first data When the first data is input, a predetermined potential is input to the wiring X1L[i] and the wiring X2L[i], so that the circuit MC and the wiring IOL[j] and the circuit MC and the wiring IOLB[j] are in a non-conductive state, and the circuit MCr and the wiring IOL[j] and the circuit MCr and the wiring IOLB[j] are in a non-conductive state. Then, a predetermined potential is input to the wiring WL[i], so that the holding portion HC and the wiring IOL[j] are in a conductive state, and the holding portion HCr and the wiring IOLB[j] are in a conductive state, and the first data is supplied to each of the wirings IOL[j] and IOLB[j]. Each potential can be input to each of the holding portion HC and the holding portion HCr. Furthermore, by supplying a predetermined potential to the wiring WL[i] so that the holding portion HC and the wiring IOL[j] are in a non-conductive state and the holding portion HCr and the wiring IOLB[j] are in a non-conductive state, both the holding portion HC and the holding portion HCr can hold the first data. The potentials of .

[0221] By holding the first data in each of the holding unit HC and the holding unit HCr Then, the wiring X1L[i] and the wiring X2L[i] are supplied with the potential corresponding to the second data z i (k-1) The potential, and Figure 5A The circuit MP[i, j] similarly outputs the first data to the wiring OL[j] and the wiring OLB[j]. With the second data z i (k-1) The product of the current.

[0222] application Figure 5D The operation circuit 110 of the circuit MP can be changed to Figure 7 The circuit structure of the operation circuit 130 shown in FIG. The operation circuit 130 has a circuit structure of Figure 2 In the arithmetic circuit 110, the wiring IL[1] to the wiring IL[n] and the wiring OL[1] to the wiring OL[n] are combined into the wiring IOL[1] to the wiring IOL[n], and the wiring ILB[1] to the wiring ILB[n] and the wiring OLB[1] to the wiring OLB[n] are combined into the wiring IOLB[1] to the wiring IOLB[n]. In addition, in the arithmetic circuit 130, the wiring IOL[1] to the wiring IOL[n] and the wiring IOLB[1] to the wiring IOLB[n] are electrically connected to the circuit ILD. In other words, the wiring IOL[j] and the wiring IOLB[j] have a function for transmitting the first data to the circuit MP[i, j]. In this case, when transmitting the first data to the circuit MP[i, j], the first data (k)When the circuit ILD is connected to the wiring IOL[j] and the wiring IOLB[j], the circuit ILD is preferably connected to the wiring IOL[j] and the wiring IOLB[j], and the circuit ACTF[j] is preferably connected to the wiring IOL[j] and the wiring IOLB[j]. When the circuit ACTF[j] is connected to the wiring IOL[j] and the wiring IOLB[j], the circuit ILD is preferably connected to the wiring IOL[j] and the wiring IOLB[j], and the circuit ACTF[j] is preferably connected to the wiring IOL[j] and the wiring IOLB[j].

[0223] Figure 5E The circuit MP[i, j] shown is Figure 5A A variation of the circuit MP[i, j] can be applied to Figure 2 An example of the structure of the circuit MP[i, j] of the arithmetic circuit 110. Figure 5A Similarly, for the circuit MP[i, j], Figure 5E The circuit MP[i, j] includes the circuit MC and the circuit MCr. Figure 5E The circuit MP[i, j] and Figure 5A The circuits MP[i, j] are different in that: the circuit MC is not electrically connected to the wiring OLB[j]; and the circuit MCr is not electrically connected to the wiring OL[j].

[0224] Figure 5E The wiring WL[i] shown is equivalent to Figure 2 The wiring WLS[i] in FIG. 1 is electrically connected to the holding portion HC and the holding portion HCr.

[0225] in addition, Figure 5E The wiring XL[i] shown is equivalent to Figure 2 The wiring XLS[i] in FIG. 1 is electrically connected to the circuit MC and the circuit MCr.

[0226] As explained later, Figure 5E In the circuit MP[i, j], the circuit MC is not electrically connected to the wiring OLB[j], and the circuit MCr is not electrically connected to the wiring OL[j]. In other words, Figure 5E The circuit MP[i, j] and 5A to 5D The circuits MP[i, j] are different, that is, the current output from the circuit MC does not flow through the wiring OLB[j], and the current output from the circuit MCr does not flow through the wiring OL[j].

[0227] therefore, Figure 5E The circuit MP[i, j] preferably has the following characteristics: i(k-1) When the value is "0" or "1", it is applied to the operation circuit. i (k-1) When the second data z is "1", the circuit MP makes the circuit MC and the wiring OL[j] conductive and makes the circuit MCr and the wiring OLB[j] conductive. i (k-1) When it is "0", in order to prevent the current of each output of circuit MC and circuit MCr from flowing through wiring OL[j] and OLB[j], circuit MP puts circuit MC and wiring OL[j] in a non-conductive state, and puts circuit MCr and wiring OLB[j] in a non-conductive state.

[0228] Figure 5E The circuit MP[i, j] can be applied to the operation circuit 111, for example, in the first data The second data z is any one of the three values ​​of "-1", "0", and "1". i (k-1) The operation is performed when the value is "0" or "1". Figure 5E The circuit MP[i, j] in the first data It can also work when it is any binary value among "-1", "0", and "1", for example, binary values ​​of "-1", "1" or binary values ​​of "0", "1". Alternatively, it may be an analog value or a multi-bit (multi-value) digital value. As a specific example, a "negative analog value" may be obtained instead of "-1" and a "positive analog value" may be obtained instead of "1". In this case, the level of the current flowing from the circuit MC or the circuit MCr may also correspond to the first data. The absolute value of the analog value.

[0229] and Figure 5A same, Figure 5F The circuit MP[i, j] shown in FIG. 1 is capable of outputting the first data to the wiring OL[j] and the wiring OLB[j]. With the second data z i (k-1) The product of the currents in the circuit. Figure 5F The circuit MP[i, j] can be applied to Figure 2 The operation circuit 110.

[0230] Figure 5F The circuit MP[i,j] includes a transistor MZ in addition to the circuit MC and the circuit MCr.

[0231] The first terminal of transistor MZ is electrically connected to the first terminal of circuit MC and the first terminal of circuit MCr. The second terminal of transistor MZ is electrically connected to wiring VL. The gate of transistor MZ is electrically connected to wiring XL[i].

[0232] Wiring VL is used, for example, as a wiring for supplying a constant voltage. This constant voltage is preferably determined based on the configuration of circuit MP[i,j] or arithmetic circuit 110. Examples of this constant voltage include high-level potential VDD, low-level potential VSS, and ground potential.

[0233] in addition, Figure 5F The wiring WL[i] shown is equivalent to Figure 2 The wiring WLS[i] in the arithmetic circuit 110 is electrically connected to the holding portion HC and the holding portion HCr.

[0234] Furthermore, the wiring OL[j] is electrically connected to the second terminal of the circuit MC. Furthermore, the wiring OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0235] The wiring IL[j] is electrically connected to the holding portion HC, and the wiring ILB[j] is electrically connected to the holding portion HCr.

[0236] About Figure 5F The operation when each of the holding part HC and the holding part HCr in the circuit MP[i, j] holds the potential corresponding to the first data is described with reference to FIG. Figure 5A Description of the operation of the circuit MP[i, j] to hold the potential corresponding to the first data.

[0237] exist Figure 5F In the circuit MP[i, j] of the circuit MC, when the constant voltage supplied by the wiring VL is supplied to the first terminal of the circuit MC, the circuit MC has the function of causing a current corresponding to the potential held by the holding portion HC to flow between the first and second terminals of the circuit MC. In addition, when the constant voltage supplied by the wiring VL is supplied to the first terminal of the circuit MC, the circuit MCr has the function of causing a current corresponding to the potential held by the holding portion HCr to flow between the first and second terminals of the circuit MCr. In other words, by causing each of the holding portions HC and HCr of the circuit MP[i, j] to hold the first data The potential of VL determines the amount of current flowing between the first and second terminals of circuit MC and the amount of current flowing between the first and second terminals of circuit MCr. Note that when the constant voltage supplied by wiring VL is not supplied to the first terminal of circuit MC (circuit MCr), for example, circuit MC (circuit MCr) can be considered to not allow current to flow between the first and second terminals of circuit MC (circuit MCr).

[0238] For example, when each of the holding part HC and the holding part HCr holds the first data corresponding to "1", When the potential is 0, the circuit MC is supplied with a constant voltage supplied by the wiring VL, and the circuit MC causes a specified current to flow between the first terminal and the second terminal of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. Note that at this time, the circuit MCr does not cause a current to flow between the first terminal and the second terminal of the circuit MCr. Therefore, a current does not flow between the circuit MCr and the wiring OLB. In addition, for example, when each of the holding parts HC and HCr holds the first data corresponding to "-1", When the potential is 0, the circuit MCr causes a specified current to flow between the first and second terminals of the circuit MCr by supplying the constant voltage supplied by the wiring VL to the circuit MC. Therefore, current flows between the circuit MCr and the wiring OLB. Note that at this time, the circuit MC does not cause current to flow between the first and second terminals of the circuit MC. Therefore, current does not flow between the circuit MC and the wiring OL. In addition, for example, each of the holding portion HC and the holding portion HCr holds the first data corresponding to "0". When the potential is 0.001, circuit MC does not allow current to flow between the first and second terminals of circuit MC, and circuit MCr does not allow current to flow between the first and second terminals of circuit MCr, regardless of the constant voltage supplied to wiring VL in circuit MC and circuit MCr. In other words, current does not flow between circuit MC and wiring OL, and current does not flow between circuit MCr and wiring OLB.

[0239] about Figure 5F The first data corresponding to the first data held by the holding part HC and the holding part HCr in the circuit MP[i, j] For a specific example of the potential, refer to Figure 5A The circuit MP[i, j] is recorded. In addition, Figure 5A Similarly, in the circuit MP[i, j] Figure 5F In the circuit MP[i, j], the holding part HC and the holding part HCr may have the function of holding data such as current and resistance value instead of the potential, and the circuit MC and the circuit MCr may have the function of passing the current according to the data.

[0240] in addition, Figure 5F The wiring XL[i] shown is equivalent to Figure 2 The second data z input to the circuit MP[i, j] is the wiring XLS[i] in the arithmetic circuit 110. i (k-1) For example, it is determined by the wiring XL[i], the current, etc. Thus, the gate of the transistor MZ is inputted with the second data z via the wiring XL[i]. i (k-1) The potential.

[0241] For example, consider the second data z i (k-1) When the value becomes one of the two values ​​"0" and "1". i (k-1) When the second data z is "1", a high level potential is supplied to the wiring XL[i]. At this time, the transistor MZ is in the on state, so the circuit MP makes the wiring VL and the first terminal of the circuit MC conductive and the wiring VL and the first terminal of the circuit MCr conductive. In other words, in the second data z i (k-1) When the second data z is "1", a constant voltage from the wiring VL is supplied to the circuit MC and the circuit MCr. i (k-1) When the second data z is "0", a low level potential is supplied to the wiring XL[i]. At this time, the circuit MP makes the circuit MC and the wiring OLB[j] non-conductive and the circuit MCr and the wiring OL[j] non-conductive. In other words, in the second data z i (k-1) When it is “0”, the constant voltage from the wiring VL is not supplied to the circuit MC and the circuit MCr.

[0242] Here, for example, in the first data is "1" and the second data z i (k-1) When the first data is "1", the current flows between the circuit MC and the wiring OL and does not flow between the circuit MCr and the wiring BLB. is "-1" and the second data z i (k-1) When the first data is "1", the current does not flow between the circuit MC and the wiring OL, but flows between the circuit MCr and the wiring OLB. is "0" and the second data z i (k-1) When the second data z is "1", the current does not flow between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB. i (k-1) When it is "0", even if the first data Even if the value is any of "-1", "0" and "1", no current flows between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB.

[0243] In other words, with Figure 5E Similarly, for the circuit MP[i, j], Figure 5F The circuit MP[i, j] can be used in the first data The second data z is any one of the three values ​​of "-1", "0", and "1". i (k-1) The operation is performed when the value is "0" or "1". Figure 5E Similarly, for the circuit MP[i, j], Figure 5F The circuit MP[i, j] in the first data It can also work when it is any binary value among "-1", "0", and "1", for example, binary values ​​of "-1" and "1" or binary values ​​of "0" and "1". Alternatively, it may be an analog value or a multi-bit (multi-value) digital value. As a specific example, a "negative analog value" may be obtained instead of "-1" and a "positive analog value" may be obtained instead of "1". In this case, the level of the current flowing from the circuit MC or the circuit MCr may also correspond to the first data. The absolute value of the analog value.

[0244] <Operation Example of Arithmetic Circuit>

[0245] Next, explain Figure 2 Note that in the description of this working example, as an example, Figure 8 The operation circuit 110 is shown.

[0246] Figure 8 The operation circuit 110 is focused on the Figure 2 The circuit of the j-th column of the operation circuit 110 is shown in the figure. In other words, Figure 8 The operation circuit 110 is equivalent to a circuit that performs the following operation, namely Figure 1A The pair of neurons N in the neural network 100 shown j (k) Input comes from neuron N1 (k-1) To neuron N m (k-1) Signal z1 (k-1) to z m (k-1) and weight coefficient w1 (k-1) j (k) to w m (k-1) j (k) and the operation of the activation function using the result of the product-sum operation. Figure 8 The array portion ALP of the arithmetic circuit 110 includes a circuit MP using Figure 5A Circuit MP.

[0247] First, in the operation circuit 110, the circuits MP[1,j] to MP[m,j] set the first data to As the first data The setting method of can be exemplified by the following steps: circuit WLD sequentially inputs a specified potential to wirings WLS[1] to WLS[m], sequentially selects circuits MP[1,j] to MP[m,j], and supplies a potential corresponding to the first data to the holding portion HC of circuit MC and the holding portion HCr of circuit MCr included in the selected circuit MP from circuit ILD via wiring IL[j] and wiring ILB[j]. After supplying the potential, circuit WLD deselects each of circuits MP[1,j] to MP[m,j], thereby allowing the holding portion HC of circuit MC and the holding portion HCr of circuit MCr included in each of circuits MP[1,j] to MP[m,j] to hold the data corresponding to the first data w1. (k-1) j (k) to w m (k-1) j (k) As an example, in the first data w1 (k-1) j (k) to w m (k-1) j (k) When each of the first data w1 is positive, a value corresponding to the positive value is input to the holding unit HC, and a value equivalent to zero is input to the holding unit HCr. (k-1) j (k) to w m (k-1) j (k) When each of is a negative value, a value equivalent to zero is input to the holding unit HC, and a value corresponding to the absolute value of the negative value is input to the holding unit HCr.

[0248] Next, the circuit XLD supplies the second data z1 to each of the wiring X1L[1] to the wiring X1L[m] and the wiring X2L[1] to the wiring X2L[m]. (k-1) to z m (k-1) Specifically, the second data z1 is supplied to the wiring X1L[i] and the wiring X2L[i]. (k-1) . Wiring X1L[i] and wiring X2L[i] are equivalent to Figure 2 The wiring XLS[i] of the operation circuit 110 is shown.

[0249] According to the second data z1 input to each of the circuits MP[1,j] to MP[m,j] (k-1) to z m (k-1) The conduction states of the circuits MC and MCr, and the wiring OL[j] and OLB[j] included in the circuits MP[i,j] to MP[m,j] are determined. Specifically, the circuits MP[i,j] and MP[m,j] are determined based on the second data z. i (k-1) The state becomes any of the following: "circuit MC is conductive to wiring OL[j] and circuit MCr is conductive to wiring OLB[j]"; "circuit MC is conductive to wiring OLB[j] and circuit MCr is conductive to wiring OL[j]"; and "circuit MC and circuit MCr are not conductive to wiring OL[j] and OLB[j] respectively". For example, in the second data z1 (k-1) When the value is positive, the value between the circuit MC and the wiring OL[j] can be in a conductive state and the circuit MCr can be in a conductive state with the wiring OLB[j] is input to the wiring X1L[1]. Furthermore, the value between the circuit MC and the wiring OLB[j] can be in a non-conductive state and the circuit MCr can be in a non-conductive state with the wiring X2L[1]. (k-1) When the value is negative, the value between the circuit MC and the wiring OLB[j] can be in a conductive state and the circuit MCr can be in a conductive state with the wiring OL[j] is input to the wiring X1L[1]. Furthermore, the value between the circuit MC and the wiring OL[j] can be in a non-conductive state and the circuit MCr can be in a non-conductive state with the wiring OLB[j] is input to the wiring X2L[1]. (k-1) When 0 is zero, a value is input to the wiring X1L[1] to allow non-conduction between the circuit MC and the wiring OLB[j], and a value is input to the wiring X2L[1] to allow non-conduction between the circuit MC and the wiring OLB[j], and a value is input to the wiring X2L[1] to allow non-conduction between the circuit MC and the wiring OLB[j], and a value is input to the wiring X2L[1].

[0250] By inputting the second data z into the circuit MP[i, j] i (k-1) The conduction state or non-conduction state between the circuit MC and the circuit MCr included in the circuit MP[i, j] and the wiring OL[j] and the circuit OLB[j] is determined, and current is input and output between the circuit MC and the circuit MCr and the wiring OL[j] and the wiring OLB[j]. The amount of the current is determined based on the first data set in the circuit MP[i, j]. and / or second data z i(k-1) Decide.

[0251] For example, in circuit MP[i, j], the current flowing from wiring OL[j] to circuit MC or circuit MCr is represented as I[i, j], and the current flowing from wiring OLB[j] to circuit MC or circuit MCr is represented as I[i, j]. B [i, j]. Then, the current flowing from the circuit ACTF[j] through the wiring OL[j] is expressed as I out [j] and the current flowing from wiring OLB[j] to circuit ACTF[j] is expressed as I Bout [j], I out [j] and I Bout [j] can be expressed as the following formula.

[0252] [Formula 4]

[0253]

[0254] When in circuit MP[i,j], for example, the first data When the first data is "+1", the circuit MC discharges I(+1) and the circuit MCr discharges I(-1). When the first data is "-1", the circuit MC outputs I(-1), and the circuit MCr outputs I(+1). When it is "0", the circuit MC discharges I(-1), and the circuit MCr discharges I(-1).

[0255] Furthermore, in the second data z i (k-1) When the value is "+1", the circuit MP[i, j] is in the following state: "Conduction between the circuit MC and the wiring OL[j], conduction between the circuit MCr and the wiring OLB[j], non-conduction between the circuit MC and the wiring OLB[j], and non-conduction between the circuit MCr and the wiring OL[j]". i (k-1) When it is "-1", the circuit MP[i, j] becomes the following state: "Conduction between circuit MC and wiring OLB[j], conduction between circuit MCr and wiring OL[j], non-conduction between circuit MC and wiring OL[j], and non-conduction between circuit MCr and wiring OLB[j]". i (k-1) When it is "0", the circuit MP[i, j] becomes the following state: "There is no conduction between the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j], there is no conduction between the circuit MCr and the wiring OL[j] and between the circuit MCr and OLB[j], there is no conduction between the circuit MCr and the wiring OL[j] and between the circuit MCr and OLB[j]".

[0256] At this time, the following table shows the current I[i, j] flowing from the wiring OL[j] to the circuit MC or the circuit MCr in the circuit MP[i, j] and the current I[i, j] flowing from the wiring OLB[j] to the circuit MC or the circuit MCr. B [i, j]. Note that, depending on the situation, the circuit MP[i, j] may be configured so that the current amount of I(-1) is 0. In addition, the current I[i, j] may be the current flowing from the circuit MC or the circuit MCr through the wiring OL[j]. Similarly, the current I B [i, j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0257] [Table 1]

[0258]

[0259] Next, the I flowing from each of the wiring OL[j] and the wiring OLB[j] out [j] and I Bout [j] are input to the circuit ACTF[j], the circuit ACTF[j] performs I out [j] and I Bout [j], etc. Circuit ACTF[j] outputs the neuron N according to the result of the comparison, for example. j (k) The signal z transmitted to the neurons in the (k+1)th layer j (k) .

[0260] Depend on Figure 8 The operation circuit 110 can, for example, perform the operation on the neuron N j (k) Input comes from neuron N1 (k-1) To neuron N m (k-1) Signal z1 (k-1) to z m (k-1) and weight coefficient w1 (k-1) j (k) to w m (k-1) j (k) The product-sum operation and the activation function operation using the result of the product-sum operation. And, by setting the circuit MP of n columns, Figure 8 The array portion ALP of the arithmetic circuit may have Figure 2 The circuit structure of the operation circuit 110 is the same as that of the operation circuit 110. In other words, Figure 2 The operation circuit 110 can simultaneously perform neuron N1 (k) To neuron N n(k) Each product-sum operation and the operation of the activation function using the result of the product-sum operation.

[0261] 《Examples of Modifications of Circuits, Etc. Included in Arithmetic Circuits》

[0262] For example, it is preferable to use OS transistors for part or all of the transistors included in each of the array portion ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, and circuit MP. For example, when the off-state current is preferably reduced, a transistor having a function of retaining charge accumulated in a capacitor is preferably an OS transistor. In particular, when an OS transistor is used as the transistor, it is particularly preferable that the OS transistor have the structure of the transistor described in Embodiment 3. Note that one embodiment of the present invention is not limited to this.

[0263] Furthermore, transistors included in the array portion ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, and circuit MP, for example, may use transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) in addition to OS transistors. Silicon, for example, may be single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon. Transistors other than OS transistors and Si transistors may include transistors using semiconductors such as Ge as active layers, transistors using compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe as active layers, transistors using carbon nanotubes as active layers, and transistors using organic semiconductors as active layers.

[0264] Note that, regarding the metal oxide of the semiconductor layer of the OS transistor, an n-type semiconductor can be manufactured using a metal oxide containing indium (e.g., In oxide) or a metal oxide containing zinc (e.g., Zn oxide). However, manufacturing a p-type semiconductor is sometimes difficult from the perspectives of mobility and reliability. Therefore, the arithmetic circuits 110, 120, and 130 may also have a structure in which OS transistors are used as n-channel transistors and Si transistors are used as p-channel transistors in the array portion ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, and circuit MP, etc.

[0265] Note that this embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0266] (Implementation Method 2)

[0267] In this embodiment, a specific configuration example of the circuit MP described in the above-mentioned first embodiment will be described.

[0268] Note that in embodiment 1, the symbols of the circuit MP are attached with [1, 1], [i, j], [m, n], etc., which indicate the positions within the array unit ALP. However, unless otherwise specified, this embodiment omits attaching [1, 1], [i, j], [m, n], etc. to the symbols of the circuit MP.

[0269] <Structure Example 1>

[0270] First, the description can be applied to Figure 5A An example of the circuit configuration of the circuit MP. Figure 9A The circuit MP shown is Figure 5A An example of the structure of the circuit MP, Figure 9A The circuit MC included in the circuit MP includes, for example, transistors M1 to M4 and a capacitor C1. In addition, for example, the transistor M1 and the capacitor C1 constitute a holding portion HC.

[0271] Figure 9A The transistors M1 to M4 shown, for example, use n-channel transistors with a multi-gate structure including gates above and below the channel, and the transistors M1 to M4 all include a first gate and a second gate. Note that in this specification, etc., for convenience, for example, the first gate is recorded as the gate (sometimes recorded as the front gate), and the second gate is recorded as the back gate to distinguish them, but the first gate and the second gate can be interchanged. Therefore, in this specification, etc., "gate" can be recorded as "back gate". Similarly, "back gate" can be recorded as "gate". Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with a connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0272] In addition, the semiconductor device of one embodiment of the present invention does not depend on the connection structure of the back gate of the transistor. Figure 9A The transistors M1 to M4 shown in the figure all show a back gate without showing the connection relationship of the back gate, but the electrical connection point of the back gate can be determined during the design. For example, in a transistor including a back gate, in order to increase the on-state current of the transistor, the gate and the back gate can be electrically connected. In other words, for example, the gate and the back gate can also be electrically connected in each of the transistors M1 to M4. In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring electrically connected to an external circuit is provided and a potential is supplied to the back gate of the transistor through the external circuit. Figure 9A In addition, the same applies to transistors described in other parts of the specification or transistors shown in other drawings.

[0273] In addition, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the semiconductor device. Figure 9C As shown, Figure 9A The transistors M1 to M4 and the transistors M1r to M4r shown in the figure may also be transistors without back gates, i.e., transistors with single gate structures. In addition, some transistors may include back gates while other transistors may not. Figure 9A The same applies to transistors described in other parts of the specification and transistors shown in other drawings other than the circuit diagram shown.

[0274] In addition, in this specification, etc., transistors of various structures can be used as transistors. Therefore, there is no limitation on the type of transistor used. As an example of a transistor, a transistor having single crystal silicon or a transistor having a non-single crystal semiconductor film represented by amorphous silicon, polycrystalline silicon or microcrystalline (also called nanocrystalline, semi-amorphous) silicon can be used. Alternatively, a thin film transistor (TFT) can be used that makes these semiconductors thin films. The use of TFTs has various advantages. For example, since it can be manufactured at a lower temperature than in the case of manufacturing single crystal silicon, it is possible to reduce manufacturing costs or increase the size of the manufacturing equipment. Since the manufacturing equipment can be enlarged, it can be manufactured on a large substrate. Therefore, since multiple display devices can be manufactured simultaneously, it can be manufactured at a low cost. Alternatively, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a light-transmitting substrate. Alternatively, the light transmittance of a display element can be controlled by using a transistor formed on a light-transmitting substrate. Alternatively, since the film thickness of the transistor is relatively thin, a portion of the film forming the transistor can be light-transmitting. Therefore, the aperture ratio can be increased.

[0275] As an example of a transistor, a transistor including a compound semiconductor (for example, SiGe, GaAs, etc.) or an oxide semiconductor (for example, Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.) can be used. Alternatively, a thin film transistor can be used in which the above-mentioned compound semiconductor or the above-mentioned oxide semiconductor is thin-filmed. As a result, the manufacturing temperature can be lowered, so that, for example, the transistor can be manufactured at room temperature. As a result, a transistor can be formed directly on a substrate with low heat resistance, such as a plastic substrate or a thin film substrate. In addition, these compound semiconductors or oxide semiconductors can be used not only for the channel portion of the transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, pixel electrodes, or light-transmitting electrodes, etc. Since the above-mentioned semiconductor can be deposited or formed simultaneously with the transistor, the cost can be reduced.

[0276] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. Therefore, it can be manufactured at room temperature, manufactured with a low vacuum degree, or manufactured on a large substrate. Therefore, it can be manufactured even without using a mask (reticle), so the layout of the transistor can be easily changed. Alternatively, because it can be manufactured without using an etchant, the material cost can be reduced and the number of steps can be reduced. Alternatively, because a film can be formed only on the required portion, the cost is lower than that of a manufacturing method in which a film is formed on the entire surface and then etched, and no material is wasted.

[0277] As an example of a transistor, a transistor including an organic semiconductor or carbon nanotube can be used. This allows the transistor to be formed on a flexible substrate. Devices using transistors including an organic semiconductor or carbon nanotube are also impact-resistant.

[0278] Transistors of various other structures can also be used as transistors. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as transistors. By using MOS transistors as transistors, the size of the transistor can be reduced. Therefore, multiple transistors can be installed. By using bipolar transistors as transistors, a larger current can flow. Therefore, the circuit can operate at high speed. Note that MOS transistors, bipolar transistors, etc. can also be formed on a single substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc.

[0279] Another example of a transistor is a structure in which gate electrodes are placed above and below the active layer. By using a structure in which gate electrodes are placed above and below the active layer, multiple transistors can be connected in parallel. This increases the channel area, thereby increasing the current. Alternatively, by using a structure in which gate electrodes are placed above and below the active layer, a depletion layer is easily formed, thereby improving the S value.

[0280] In addition, as an example of a transistor, a structure in which a gate electrode is arranged above an active layer, a structure in which a gate electrode is arranged below an active layer, a staggered structure, an inversely staggered structure, a structure in which the active layer is divided into a plurality of regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series may be adopted. Alternatively, as a transistor, transistors having various structures such as a planar type, a FIN type, a TRI-GATE type, a top gate type, a bottom gate type, and a dual gate type (where gates are arranged above and below a channel) may be used.

[0281] In addition, as an example of a transistor, a structure in which the active layer (or a portion thereof) overlaps with the source electrode or the drain electrode can be adopted. By adopting a structure in which the active layer (or a portion thereof) overlaps with the source electrode or the drain electrode, unstable operation caused by charge accumulation in a portion of the active layer can be prevented.

[0282] Furthermore, as an example of a transistor, a structure having an LDD region can be employed. Providing an LDD region can reduce the off-state current or improve the voltage resistance of the transistor (improving reliability). Alternatively, providing an LDD region allows the transistor to operate in a saturation region, so that even if the voltage between the drain and source changes, the leakage current does not change significantly, thereby achieving a voltage-current characteristic with a flat tilt angle.

[0283] In addition, in this specification, etc., various substrates can be used to form transistors. There is no particular limitation on the type of substrate. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate comprising a stainless steel foil, a tungsten substrate, a substrate comprising a tungsten foil, a flexible substrate, a bonding film, a paper comprising a fibrous material or a substrate film, etc. can be cited. As an example of a glass substrate, barium borosilicate glass, aluminoborosilicate glass or soda-lime glass can be cited. As flexible substrates, bonding films, substrate films, etc., the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Alternatively, as an example, synthetic resins such as acrylic resins can be cited. Alternatively, as an example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Alternatively, polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, paper, and the like can be cited as examples. In particular, by using semiconductor substrates, single crystal substrates, or SOI substrates to manufacture transistors, it is possible to manufacture transistors with low variations in characteristics, size, and shape, high current capabilities, and small size. When circuits are constructed using these transistors, low power consumption and high circuit integration can be achieved.

[0284] Alternatively, a flexible substrate can be used as the substrate, and transistors can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate and the transistor. The peeling layer can be used in situations where a portion or all of a semiconductor device is manufactured on the peeling layer, and then separated from the substrate and transferred to another substrate. In this case, the transistor can also be transferred to a substrate with low heat resistance or a flexible substrate. For example, the peeling layer can be a laminated structure of an inorganic film such as a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as a polyimide film is formed on a substrate.

[0285] In addition, a transistor can be formed using one substrate and then transferred to another substrate. As a substrate for transferring a transistor, in addition to the above-mentioned substrates on which transistors can be set, a paper substrate, a cellophane substrate, an aromatic polyamide film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium, rayon, regenerated polyester), etc.), a leather substrate, a rubber substrate, etc. can be used. By using the above-mentioned substrates, transistors with good characteristics, transistors with low power consumption, devices that are not easily damaged, improved heat resistance, lightweight or thinning can be achieved.

[0286] Furthermore, all circuits required to implement a given function can be formed on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate). This can reduce costs by reducing the number of components, or improve reliability by reducing the number of connections between circuit components.

[0287] Note that all circuits required to implement a specified function may not be formed on the same substrate. In other words, a portion of the circuit required to implement a specified function may be formed on a certain substrate, and another portion of the circuit required to implement the specified function may be formed on another substrate. For example, a portion of the circuit required to implement a specified function may be formed on a glass substrate, and another portion of the circuit required to implement the specified function may be formed on a single crystal substrate (or SOI substrate). Furthermore, a single crystal substrate (also called an IC chip) forming another portion of the circuit required to implement a specified function may be connected to a glass substrate via COG (Chip On Glass), thereby configuring the IC chip on the glass substrate. Alternatively, the IC chip and the glass substrate may be connected using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board. In this way, by forming a portion of the circuit and the pixel portion on the same substrate, costs can be reduced by reducing the number of components, or reliability can be improved by reducing the number of connections between circuit components. In particular, in many cases, circuits with high drive voltages or high drive frequencies consume high power. Therefore, these circuits are formed on a separate substrate (e.g., a single crystal substrate) from the pixel portion to form an IC chip. Using this IC chip can prevent an increase in power consumption.

[0288] exist Figure 9A In circuit MP, the first terminal of transistor M1 is electrically connected to wiring IL. The second terminal of transistor M1 is electrically connected to the first terminal of capacitor C1 and the gate of transistor M2. The gate of transistor M1 is electrically connected to wiring WL. The first terminal of transistor M2 is electrically connected to the second terminal of capacitor C1 and wiring VL. The second terminal of transistor M2 is electrically connected to the first terminal of transistor M3 and the first terminal of transistor M4. The second terminal of transistor M3 is electrically connected to wiring OL. The gate of transistor M3 is electrically connected to wiring X1L. The second terminal of transistor M4 is electrically connected to wiring OLB. The gate of transistor M4 is electrically connected to wiring X2L. Note that, as Figure 9BAs shown, the second terminal of the capacitor C1 may be electrically connected to another wiring VLm instead of being electrically connected to the wiring VL. Similarly, the second terminal of the capacitor C1r may be electrically connected to another wiring VLmr instead of being electrically connected to the wiring VLr. Figure 9A In addition, in the circuit diagrams of other drawings, the second terminal of the capacitor C1 is electrically connected to another wiring VLm but not to the wiring VL. Figure 9B For example, the wiring VL and the wiring VLr may be combined into one wiring, and the wiring VLm and the wiring VLmr may be combined into one wiring (not shown).

[0289] Note that in Figure 9A In the holding portion HC shown, a point at which the second terminal of the transistor M1 , the first terminal of the capacitor C1 , and the gate of the transistor M2 are electrically connected is referred to as a node nd1 .

[0290] As described in Embodiment 1, the holding portion HC has a function of holding a potential corresponding to the first data w. By inputting the potential from the wiring IL while the transistor M1 is turned on, writing to the capacitor C1 and then turning the transistor M1 off, including Figure 9A The holding unit HC in the circuit MC holds the potential. Thus, the potential of the node nd1 can be held as a potential corresponding to the first data.

[0291] Furthermore, in order to maintain the potential of node nd1 for a long period of time, transistor M1 preferably uses a transistor with low off-state current. For example, an OS transistor can be used as a transistor with low off-state current. Alternatively, a transistor with a back gate can be used as transistor M1. Applying a low-level potential to the back gate can shift the threshold voltage toward the positive side, thereby reducing the off-state current.

[0292] The circuit MCr has substantially the same circuit configuration as that of the circuit MC. Therefore, to distinguish the circuit elements included in the circuit MC from those included in the circuit MCr, the circuit elements included in the circuit MCr are denoted by "r".

[0293] The connection structure in circuit MCr, which differs from that in circuit MC, will be described. The second terminal of transistor M3r is electrically connected to wiring OLB but not to wiring OL, and the second terminal of transistor M4r is electrically connected to wiring OL but not to wiring OLB. The first terminal of transistor M2 is electrically connected to wiring VLr.

[0294] In order to simply explain the current input to or output from the circuit MP in the working example described later, Figure 9A The two ends of the wiring OL shown are denoted as a node ina and a node outa, and the two ends of the wiring OLB are denoted as a node inb and a node outb.

[0295] Wiring VL is used, for example, as a wiring for supplying a constant voltage. When transistor M2 or transistor M2r is an n-channel transistor, for example, a low-level potential VSS, a ground potential, or a low-level potential other than the above can be used as the constant voltage. In addition, similarly to wiring VL, wiring VLr is used as a wiring for supplying a constant voltage, and a low-level potential VSS, a ground potential, or the like can be used as the constant voltage. In this case, circuits ACTF[1] to ACTF[n] of operation circuits 110, 120, and 130 use Figures 3A to 3E 、 Figures 4A to 4D 、 Figure 4F In the circuit shown, the constant voltage supplied by VAL electrically connected to the circuits ACTF[1] to ACTF[n] is preferably higher than the potential supplied by the wiring VL and the wiring VLr, and is preferably VDD, for example.

[0296] In addition, the constant voltage supplied by the wiring VLr may be different from or the same as the constant voltage supplied by the wiring VL. For example, when the constant voltage supplied by the wiring VLr is substantially the same as the constant voltage supplied by the wiring VLr, Figure 10A As shown in the circuit MP of FIG. 1 , the wiring VLr can be the same wiring as the wiring VL.

[0297] in addition, Figure 9A The structure of the circuit MP can be changed according to the situation. Figure 10B As shown, you can also Figure 9A The transistors M2, M2r, M3, M3r, M4, and M4r of the circuit MP are replaced by p-channel transistors M2p, M2pr, M3p, M3pr, M4p, and M4pr, respectively. In particular, when the transistors M2 and M2r are replaced by p-channel transistors, it is preferable to use a high-level potential VDD as the constant voltage supplied to the wiring VL. In addition, in addition to the above-mentioned cases, when the circuits ACTF[1] to ACTF[n] as the operation circuits 110, 120, and 130 are used, Figures 3A to 3E 、 Figures 4A to 4D 、 Figure 4F When the circuit is connected to ACTF[1] to ACTF[n], the constant voltage supplied by VAL electrically connected to the circuits ACTF[1] to ACTF[n] is preferably the ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of current flow also changes.

[0298] In addition, similarly, the transistor M1 can also be replaced by a p-channel transistor. Figure 10B In Figure 9AThe transistors M2, M2r, M3, M3r, M4 and M4r of the circuit MP are replaced by the transistors M2p, M2pr, M3p, M3pr, M4p and M4pr of p-channel transistors respectively. Figure 9A One or more of the transistors M2, M2r, M3, M3r, M4, and M4r in the circuit MP are replaced with p-channel transistors.

[0299] In addition, for example, Figure 11A As shown, you can also Figure 9A The transistors M3, M3r, M4, and M4r of the circuit MP are replaced by analog switches A3, A4, A3r, and A4r, respectively. Figure 11A Also shown are wiring X1LB and wiring X2LB for operating analog switches A3, A4, A3r, and A4r. Wiring X1LB is electrically connected to analog switches A3 and A3r, and wiring X2LB is electrically connected to analog switches A4 and A4r. An inverted signal of a signal input to wiring X1L is input to wiring X1LB, and an inverted signal of a signal input to wiring X2L is input to wiring X2LB. Furthermore, as shown in FIG. Figure 11B As shown, the wiring X1L and the wiring X2L may be combined into the wiring XL, and the wiring X1LB and the wiring X2LB may be combined into the wiring XLB. Furthermore, for example, the analog switches A3, A4, A3r, and A4r may also employ a CMOS structure using n-channel transistors and p-channel transistors.

[0300] In addition, for example, Figure 12A As shown, Figure 9A The transistor M4 and the transistor M4r of the circuit MP are replaced by the transistor M4p and the transistor M4pr of the p-channel transistor respectively. Figure 12A In the circuit MP, the gate of the transistor M3 is electrically connected to the gate of the transistor M4p and the wiring XL. The wiring XL is equivalent to connecting Figure 9A The two wirings X1L and X2L in the wiring XL are combined into one wiring. Transistor M3 and transistor M4p have different polarities, and the gates of transistors M3 and M4p are both electrically connected to wiring XL. Thus, by supplying a specified potential to wiring XL, one of transistors M3 and M4p can be turned on, while the other can be turned off.

[0301] In addition, for example, Figure 12B As shown, it can also be Figure 9A The circuit MP further includes transistors M2m and M2mr, and the electrical connection points of the first terminals of the transistors M4 and M4r are changed. Figure 12B In the circuit MP, the first terminal of the transistor M2m is electrically connected to the second terminal of the capacitor C1, the first terminal of the transistor M2, and the wiring VL, and the second terminal of the transistor M2m is electrically connected to the first terminal of the transistor M4. Figure 9A In the circuit MP, the second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M4, but Figure 12B In the circuit MP, the second terminal of the transistor M2 is not electrically connected to the first terminal of the transistor M4. Figure 12B In the illustrated circuit MP, the currents flowing through transistors M3 and M4 are determined by the gate potentials of transistors M2 and M2m, respectively. Furthermore, for example, the dimensions of transistors M2 and M2m, such as channel length or channel width, are preferably identical. This circuit structure allows for efficient layout. Furthermore, it is possible to make the currents flowing through transistors M3 and M4 consistent.

[0302] Work Examples >>

[0303] Next, explain Figure 9A An example of the operation of the circuit MP is shown.

[0304] 13A to 13C 、 14A to 14C 、 Figures 15A to 15C 1 and 2 are timing charts illustrating an operation example of the circuit MP, and each chart illustrates changes in the potentials of the wiring IL, the wiring ILB, the wiring WL, the wiring X1L, the wiring X2L, the node nd1 , and the node nd1 r. 13A to 13C 、 14A to 14C 、 Figures 15A to 15C The high in the description indicates a high level potential, and the low indicates a low level potential. The amount of current output from the wiring OL to the node outa (or from the node outa to the wiring OL) is denoted as I OL In addition, the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is denoted as I OLB .exist 13A to 13C 、 14A to 14C 、 Figures 15A to 15C The timing diagram shown also shows the current I OL , I OLB The amount of change.

[0305] Note that in this working example, the constant voltage supplied to the wirings VL and VLr is set to VSS (low-level potential). At this time, current flows from the wiring VAL through the wiring OL to the wiring VL. Similarly, current flows from the wiring VAL through the wiring OLB to the wiring VLr.

[0306] In this specification, the terms "low-level potential" and "high-level potential" do not refer to specific potentials. The specific potentials may differ depending on the wiring. For example, the low-level potential and high-level potential held by nodes nd1 and nd1r may differ from the low-level potential and high-level potential applied to wiring X1L and wiring X2L.

[0307] Before describing the working example, the weight coefficients held by circuit MP are defined as follows. When node nd1 of the holding unit HC maintains a high-level potential and node nd1r of the holding unit HCr maintains a low-level potential, circuit MP maintains a weight coefficient of "+1." When node nd1 of the holding unit HC maintains a low-level potential and node nd1r of the holding unit HCr maintains a high-level potential, circuit MP maintains a weight coefficient of "-1." When node nd1 of the holding unit HC maintains a low-level potential and node nd1r of the holding unit HCr maintains a low-level potential, circuit MP maintains a weight coefficient of "0." For example, the high-level potential held at nodes nd1 and nd1r can be VDD or a potential slightly lower than VDD, while the low-level potential held at nodes nd1 and nd1r can be VSS. Alternatively, analog values ​​can be used as weight coefficients. In this case, for example, when the weight coefficients are positive analog values, node nd1 of the holding unit HC maintains a high-level analog potential and node nd1r of the holding unit HCr maintains a low-level potential. For example, when the weight coefficient is a "negative analog value," node nd1 of the holding unit HC holds a low-level potential, while node nd1r of the holding unit HCr holds a high-level analog potential. When the weight coefficient is "0," for example, node nd1 of the holding unit HC holds a low-level potential, while node nd1r of the holding unit HCr holds a low-level potential.

[0308] Furthermore, the signals (calculated values) input to the neurons of circuit MP are defined as follows, for example. When a high-level potential is applied to wiring X1L and a low-level potential is applied to wiring X2L, "+1" is input to circuit MP as a neuron signal. When a low-level potential is applied to wiring X1L and a high-level potential is applied to wiring X2L, "-1" is input to circuit MP as a neuron signal. When a low-level potential is applied to wiring X1L and a low-level potential is applied to wiring X2L, "0" is input to circuit MP as a neuron signal.

[0309] In addition, in this specification, unless otherwise specified, transistors M2 and M2r sometimes operate in the saturation region when they are turned on. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are sometimes appropriately biased so that the transistor operates in the saturation region. Note that one embodiment of the present invention is not limited to this. In order to reduce the amplitude of the supplied voltage, transistors M2 and M2r can also operate in the linear region. In addition, when the weight coefficient is an analog value, transistors M2 and M2r can also operate in the linear region and in the saturation region, for example, depending on the size of the weight coefficient.

[0310] In this specification, unless otherwise specified, transistors M1, M3, M4, M1r, M3r, and M4r are said to operate in the linear region when turned on. In other words, this includes the case where the gate voltage, source voltage, and drain voltage of each of the above transistors are appropriately biased so that the transistor operates in the linear region.

[0311] Hereinafter, an example of the operation of the circuit MP will be described based on the possible combinations of values ​​that the weight coefficients and the neuron signals can take.

[0312] [Condition 1]

[0313] First, for example, consider a case where the weight coefficient w is “0” and the signal (calculated value) input to the neuron of the circuit MP is “+1”. Figure 13A This is a timing diagram of the circuit MP at this time.

[0314] During the period from time T1 to time T2, an initialization potential V for initializing the potential of the node nd1 of the holding portion HC and the potential of the node nd1r of the holding portion HCr is input to each of the wiring IL and the wiring ILB. ini . Note that in Figure 13A In, V ini Higher than the low level potential and lower than the high level potential, but V ini Alternatively, V ini Alternatively, the same potential as the low-level potential or the same potential as the high-level potential may be set. Alternatively, different initialization potentials V may be applied to the wiring IL and the wiring ILB. ini In addition, the initialization potential V may not be input to the wiring IL and the wiring ILB. ini In other words, the period from time T1 to time T2 may not be provided.

[0315] Furthermore, during the period from time T1 to time T2, a low-level potential is input to the wiring WL, so that both the transistor M1 and the transistor M1r are in an off state.

[0316] In addition, during the period from time T1 to time T2, the potentials of the nodes nd1 and nd1r are not particularly set. Figure 13A In the example, the potentials of the nodes nd1 and nd1r are set higher than the low-level potential and lower than V ini The potential.

[0317] A low-level potential is supplied to each of the wiring X1L and the wiring X2L. Therefore, the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r are all in an off state.

[0318] Furthermore, during the period from time T2 to time T3, a high-level potential is input to the wiring WL. Therefore, both transistors M1 and M1r are turned on, and the wiring IL and the node nd1 are conductive, while the wiring ILB and the node nd1r are conductive. Therefore, the potentials of the nodes nd1 and nd1r both reach V ini Note that the potentials of the nodes nd1 and nd1r may not be the initialization potential V ini In other words, the period from time T2 to time T3 may not be provided.

[0319] Between time T3 and time T4, a low-level potential is applied to wiring IL and wiring ILB, and "0" is input as the weight w. Even after time T3, a high-level potential continues to be applied to wiring WL, and "0" is input as the weight w. This turns transistors M1 and M1r on. Consequently, the potentials of nodes nd1 and nd1r both reach a low level.

[0320] During the period from time T4 to time T5 , a low-level potential is input to the wiring WL, thereby turning off both the transistor M1 and the transistor M1r, and holding the potentials of the nodes nd1 and nd1r by the capacitors C1 and C1r, respectively.

[0321] Through the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "0".

[0322] Through the above operation, the potential of each gate of the transistor M2 and the transistor M2r becomes a low-level potential. Since the potential of each first terminal of the transistor M2 and the transistor M2r is VSS, both the transistor M2 and the transistor M2r are turned off.

[0323] During the period from time T5 to time T6, for example, the initialization potential V is input to the wiring IL and the wiring ILB. iniNote that this operation is not particularly necessary, so the initialization potential V may not be input to the wiring IL and the wiring ILB. ini In other words, the period from time T5 to time T6 may not be provided. In addition, different potentials may be input to the wiring IL and the wiring ILB.

[0324] After time T6, when the neuron signal "+1" is input to circuit MP, a high-level potential is input to wiring X1L, and a low-level potential is input to wiring X2L. Consequently, transistors M3 and M3r are both on, while transistors M4 and M4r are both off. In other words, through this operation, conduction occurs between circuit MC and wiring OL, and between circuit MCr and wiring OLB.

[0325] At this time, in the circuit MC, the transistor M2 is in the off state, so no current flows between the wiring OL and the wiring VL. In other words, the current I output from the node outa of the wiring OL is OL There is no change before and after time T6. Similarly, in circuit MCr, transistor M2r is in the off state, so no current flows between wiring OLB and wiring VLr. In other words, the current I output from node outb of wiring OLB is OLB It also does not change before and after time T6.

[0326] In this condition, the weight coefficient is "0" and the signal input to the neuron of the circuit MP is "+1", so when using equation (1.1), the product of the weight coefficient and the neuron signal becomes "0". The result of the product of the weight coefficient and the neuron signal being "0" corresponds to the current I after time T6 during the operation of the circuit MP. OL and current I OLB The situation does not change.

[0327] Alternatively, multiple sum-of-product operations can be performed by changing only the calculated value without updating the weight w once input. In this case, updating the weight w is unnecessary, reducing power consumption. Furthermore, to reduce the frequency of updating the weight w, it is necessary to maintain the weight w for a long period of time. In this case, for example, when using OS transistors, the low off-state current allows the weight w to be maintained for a long period of time.

[0328] [Condition 2]

[0329] First, for example, consider a case where the weight coefficient w is "+1" and the signal (calculated value) input to the neuron of the circuit MP is "+1". Figure 13B This is a timing diagram of the circuit MP at this time.

[0330] Since the operation during the period from time T1 to time T3 under condition 2 is the same as the operation during the period from time T1 to time T3 under condition 1, reference is made to the description of the operation during the period from time T1 to time T3 under condition 1.

[0331] Between time T3 and time T4, a high-level potential is applied to wiring IL, inputting "1" as weight w. Wiring WL continues to receive a high-level potential after time T3, outputting "1" as weight w. Consequently, transistors M1 and M1r are turned on. Consequently, the potential at node nd1 becomes high, and the potential at node nd1r becomes low.

[0332] During the period from time T4 to time T5, a low-level potential is input to the wiring WL, thereby turning off both the transistor M1 and the transistor M1r, and holding the potentials of the nodes nd1 and nd1r by the capacitors C1 and C1r, respectively.

[0333] Through the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "+1".

[0334] Through the above operation, the gate potential of transistor M2 becomes high, the gate potential of transistor M2r becomes low, and the potential of each first terminal of transistor M2 and transistor M2r becomes VSS. Therefore, transistor M2 becomes on and transistor M2r becomes off.

[0335] Since the operation during the period from time T5 to time T6 under condition 2 is the same as the operation during the period from time T5 to time T6 under condition 1, reference will be made to the description of the operation during the period from time T5 to time T6 under condition 1.

[0336] After time T6, when the neuron signal "+1" is input to circuit MP, a high-level potential is input to wiring X1L, and a low-level potential is input to wiring X2L. Consequently, transistors M3 and M3r are both turned on, while transistors M4 and M4r are both turned off. In other words, through this operation, conduction occurs between circuit MC and wiring OL, and between circuit MCr and wiring OLB.

[0337] At this time, in the circuit MC, the transistor M2 is in the off state, so the current flows between the wiring OL and the wiring VL. In other words, the current I output from the node outa of the wiring OL is OL After time T6, the Figure 13B In the OLThe increase is expressed as ΔI. ). On the other hand, in circuit MCr, transistor M2r is in the off state, so no current flows between wiring OLB and wiring VLr. In other words, the current I output from node outb of wiring OLB is OLB It also does not change before and after time T6.

[0338] In this condition, the weight coefficient w is "+1" and the signal (calculated value) input to the neuron of the circuit MP is "+1". Therefore, when using equation (1.1), the product of the weight coefficient and the neuron signal is "+1". The result of the product of the weight coefficient and the neuron signal being "1" corresponds to the current I OL The current I changes OLB Unchanged situation.

[0339] [Condition 3]

[0340] Next, consider, for example, a case where the weight coefficient w is "-1" and the signal (calculated value) input to the neuron of the circuit MP is "+1". Figure 13C This is a timing diagram of the circuit MP at this time.

[0341] Since the operation during the period from time T1 to time T3 of condition 3 is the same as the operation during the period from time T1 to time T3 of condition 1, reference is made to the description of the operation during the period from time T1 to time T3 of condition 1.

[0342] Between time T3 and time T4, a low-level potential is applied to wiring IL, and a high-level potential is applied to wiring ILB, inputting "-1" as the weight w. Wiring WL continues to receive a high-level potential even after time T3, turning on transistors M1 and M1r. Consequently, "-1" is input as the weight w, causing the potential at node nd1 to become low, while the potential at node nd1r to become high.

[0343] During the period from time T4 to time T5, a low-level potential is input to the wiring WL, thereby turning off both the transistor M1 and the transistor M1r, and holding the potentials of the nodes nd1 and nd1r by the capacitors C1 and C1r, respectively.

[0344] Through the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "-1".

[0345] Through the above operation, the gate potential of transistor M2 becomes low, the gate potential of transistor M2r becomes high, and the potentials of the first terminals of transistors M2 and M2r become VSS. Therefore, transistor M2 becomes off and transistor M2r becomes on.

[0346] Since the operation during the period from time T5 to time T6 of condition 3 is the same as the operation during the period from time T5 to time T6 of condition 1, the description of the operation during the period from time T5 to time T6 of condition 1 is referred to.

[0347] After time T6, when the neuron signal "+1" is input to circuit MP, a high-level potential is input to wiring X1L, and a low-level potential is input to wiring X2L. Consequently, transistors M3 and M3r are both turned on, while transistors M4 and M4r are both turned off. In other words, through this operation, conduction occurs between circuit MC and wiring OL, and between circuit MCr and wiring OLB.

[0348] At this time, in the circuit MC, the transistor M2 is in the off state, so no current flows between the wiring OL and the wiring VL. In other words, the current I output from the node outa of the wiring OL is OL On the other hand, in the circuit MCr, the transistor M2r is in the on state, so the current flows between the wiring OLB and the wiring VLr. In other words, the current I output from the node outb of the wiring OLB is OLB Also increases after time T6 (at Figure 13C In the OLB The increase is recorded as △I.).

[0349] In this condition, the weight coefficient w is "-1" and the signal (calculated value) input to the neuron of the circuit MP is "+1". Therefore, when using equation (1.1), the product of the weight coefficient and the neuron signal is "-1". The result of the product of the weight coefficient and the neuron signal being "-1" corresponds to the current I OL The current I does not change OLB Changing circumstances.

[0350] [Condition 4]

[0351] This condition refers to the operation of the circuit MP when, for example, the weight coefficient w is “0” and the signal (calculated value) of the neuron input to the circuit MP is “−1”. Figure 14A This is a timing diagram of the circuit MP at this time.

[0352] Since the operation during the period from time T1 to time T6 under condition 4 is the same as the operation during the period from time T1 to time T6 under condition 1, the description of the operation during the period from time T1 to time T6 under condition 1 is referred to.

[0353] After time T6, when a neuron signal "-1" is input to circuit MP, a low-level potential is input to wiring X1L, and a high-level potential is input to wiring X2L. Consequently, transistors M3 and M3r are both off, while transistors M4 and M4r are both on. In other words, this operation establishes electrical continuity between circuit MC and wiring OL, and between circuit MCr and wiring OLB.

[0354] At this time, in the circuit MC, the transistor M2 is in the off state, so no current flows between the wiring OLB and the wiring VL. In other words, the current I output from the node outb of the wiring OLB is OLB Also, it does not change before and after time T6. Similarly, in circuit MCr, transistor M2r is in the off state, so no current flows between wiring OL and wiring VLr. In other words, the current I output from node outa of wiring OL is OL There is no change before and after time T6.

[0355] In this condition, the weight coefficient w is "0" and the signal (calculated value) input to the neuron of the circuit MP is "-1", so when using equation (1.1), the product of the weight coefficient and the neuron signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" corresponds to the current I OL and current I OLB The case where both remain unchanged is consistent with the result of the circuit operation in condition 1.

[0356] [Condition 5]

[0357] This condition refers to the operation of the circuit MP when, for example, the weight coefficient w is set to "+1" and the signal (calculated value) of the neuron input to the circuit MP is set to "-1". Figure 14B This is a timing diagram of the circuit MP at this time.

[0358] Since the operation during the period from time T1 to time T6 under condition 5 is the same as the operation during the period from time T1 to time T6 under condition 2, the description of the operation during the period from time T1 to time T6 under condition 2 is referred to.

[0359] After time T6, when a neuron signal "-1" is input to circuit MP, a low-level potential is input to wiring X1L, and a high-level potential is input to wiring X2L. Consequently, transistors M3 and M3r are both off, while transistors M4 and M4r are both on. In other words, through this operation, conduction occurs between circuit MC and wiring OLB, and between circuit MCr and wiring OL.

[0360] At this time, in the circuit MC, the transistor M2 is in the on state, so the current flows between the wiring OLB and the wiring VL. In other words, the current I output from the node outb of the wiring OLB is OLB Also increases after time T6 (at Figure 14B In the OLB The increase is denoted as ΔI. ). On the other hand, in the circuit MCr, the transistor M2r is in the off state, so no current flows between the wiring OL and the wiring VLr. In other words, the current I output from the node outa of the wiring OL is OL There is no change before and after time T6.

[0361] In this condition, the weight coefficient w is "+1" and the signal (calculated value) input to the neuron of the circuit MP is "-1". Therefore, when using equation (1.1), the product of the weight coefficient and the neuron signal is "-1". The result of the product of the weight coefficient and the neuron signal being "-1" corresponds to the current I OL The current I does not change OLB The changes are consistent with the results of the circuit operation in condition 3.

[0362] [Condition 6]

[0363] This condition refers to the operation of the circuit MP when, for example, the weight coefficient w is set to "-1" and the signal (calculated value) of the neuron input to the circuit MP is set to "-1". Figure 14C This is a timing diagram of the circuit MP at this time.

[0364] Since the operation during the period from time T1 to time T6 of condition 6 is the same as the operation during the period from time T1 to time T6 of condition 3, the description of the operation during the period from time T1 to time T6 of condition 3 is referred to.

[0365] After time T6, when a neuron signal "-1" is input to circuit MP, a low-level potential is input to wiring X1L, and a high-level potential is input to wiring X2L. Consequently, transistors M3 and M3r are both off, while transistors M4 and M4r are both on. In other words, this operation establishes electrical continuity between circuit MC and wiring OL, and between circuit MCr and wiring OLB.

[0366] At this time, in the circuit MC, the transistor M2 is in the off state, so no current flows between the wiring OLB and the wiring VL. In other words, the current I output from the node outb of the wiring OLB is OLBOn the other hand, in the circuit MCr, the transistor M2r is in the on state, so the current flows between the wiring OL and the wiring VLr. In other words, the current I output from the node outa of the wiring OL is OL Also increases after time T6 (at Figure 14C In the OL The increase is recorded as △I.).

[0367] In this condition, the weight coefficient w is "-1" and the signal (calculated value) input to the neuron of the circuit MP is "-1", so when using equation (1.1), the product of the weight coefficient and the neuron signal is "+1". The result of the product of the weight coefficient and the neuron signal being "+1" corresponds to the current I after time T6 during the operation of the circuit MP. OL The current I changes OLB The case where there is no change is consistent with the result of the circuit operation in condition 2.

[0368] [Condition 7]

[0369] In this condition, for example, the operation of the circuit MP is considered as condition 7 when the weight coefficient w is “0” and the signal (calculated value) of the neuron input to the circuit MP is “0”. Figure 15A This is a timing diagram of the circuit MP at this time.

[0370] Since the operation during the period from time T1 to time T6 under condition 7 is the same as the operation during the period from time T1 to time T6 under condition 1, the description of the operation during the period from time T1 to time T6 under condition 1 is referred to.

[0371] After time T6, when a neuron signal "0" is input to circuit MP, a low-level potential is input to wiring X1L, and a low-level potential is input to wiring X2L. Consequently, transistors M3, M3r, M4, and M4r are all turned off. In other words, through the above operation, circuits MC and MCr are both non-conductive with wiring OL and wiring OLB.

[0372] Therefore, in the circuit MC, no current flows from the wiring OL to one of the wiring VL and the wiring VLr. In other words, the current I output from the node outb of the wiring OLB is OLB Also, the current I outputted from the node outa of the wiring OL does not change before and after the time T6. Similarly, in the circuit MCr, no current flows between the wiring OLB and the other of the wiring VL and the wiring VLr. In other words, the current I outputted from the node outa of the wiring OL OL There is no change before and after time T6.

[0373] In this condition, the weight coefficient w is "0" and the signal input to the neuron of the circuit MP is "0", so when using equation (1.1), the product of the weight coefficient and the neuron signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" corresponds to the current I after time T6 during the operation of the circuit MP. OL and current I OLB The situation where both conditions do not change is consistent with the results of the circuit operation in conditions 1 and 4.

[0374] [Condition 8]

[0375] In this condition, for example, the operation of the circuit MP is considered as condition 8 when the weight coefficient w is "+1" and the signal (calculated value) of the neuron input to the circuit MP is "0". Figure 15B This is a timing diagram of the circuit MP at this time.

[0376] Since the operation during the period from time T1 to time T6 of condition 8 is the same as the operation during the period from time T1 to time T6 of condition 2, the description of the operation during the period from time T1 to time T6 of condition 2 is referred to.

[0377] After time T6, when a neuron signal "0" is input to circuit MP, a low-level potential is input to wiring X1L, and a low-level potential is input to wiring X2L. In other words, the operation after time T6 in condition 7 is the same as that in condition 7. Therefore, through the above operation, circuit MC becomes non-conductive with both wiring OL and wiring OLB, and circuit MCr becomes non-conductive with both wiring OL and wiring OLB. Therefore, no current flows from wiring OL or wiring OLB to either wiring VL or wiring VLr, and the current I output from node outa of wiring OL is OL and the current I output from the node outb of the wiring OLB OLB They do not change before and after time T6.

[0378] In this condition, the weight coefficient w is "+1" and the signal (calculated value) input to the neuron of the circuit MP is "0", so when using equation (1.1), the product of the weight coefficient and the neuron signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" corresponds to the current I OL and current I OLB The case where nothing changes is consistent with the results of the circuit operation under conditions 1, 4, and 7.

[0379] [Condition 9]

[0380] In this condition, for example, the operation of the circuit MP is considered as condition 9 when the weight coefficient w is "-1" and the signal (calculated value) of the neuron input to the circuit MP is "0". Figure 15C This is a timing diagram of the circuit MP at this time.

[0381] Since the operation during the period from time T1 to time T6 of condition 9 is the same as the operation during the period from time T1 to time T6 of condition 3, the description of the operation during the period from time T1 to time T6 of condition 3 is referred to.

[0382] After time T6, when a neuron signal "0" is input to circuit MP, a low-level potential is input to wiring X1L, and a low-level potential is input to wiring X2L. In other words, the operation after time T6 in condition 7 is the same as that in condition 7. Therefore, through the above operation, circuit MC becomes non-conductive with both wiring OL and wiring OLB, and circuit MCr becomes non-conductive with both wiring OL and wiring OLB. Therefore, no current flows from wiring OL or wiring OLB to either wiring VL or wiring VLr, and the current I output from node outa of wiring OL is OL and the current I output from the node outb of the wiring OLB OLB They do not change before and after time T6.

[0383] In this condition, the weight coefficient w is "-1" and the signal (calculated value) input to the neuron of the circuit MP is "0", so when using equation (1.1), the product of the weight coefficient and the neuron signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" corresponds to the current I OL and current I OLB The case where nothing changes is consistent with the results of the circuit operation under conditions 1, 4, 7, and 8.

[0384] The following table shows the results of the working example under the above conditions 1 to 9. Note that in the following table, a high-level potential is expressed as high, and a low-level potential is expressed as low.

[0385] [Table 2]

[0386]

[0387] Here, an example is shown in which one circuit MC and one circuit MCr are connected to each of the wiring OL and the wiring OLB. Figure 2 、 Figure 6 、 Figure 7 、 Figure 8As shown in FIGURE 2, when multiple circuits MC and multiple circuits MCr are connected to each of wiring OL and wiring OLB, the currents output from each circuit MC and each circuit MCr are combined according to Kirchhoff's current law. The result is a sum operation. In other words, a product operation is performed in each circuit MC and circuit MCr, and the currents from the multiple circuits MC and multiple circuits MCr are combined to perform a sum operation. This results in a product-sum operation.

[0388] Here, in the operation of circuit MP, by performing calculations in which the weight coefficients are set to only two values, "+1" and "-1", and the neuron signals are set to only two values, "+1" and "-1", circuit MP can perform the same operation as an exclusive-NOR circuit (coincidence circuit).

[0389] In addition, in the operation of circuit MP, by setting the weight coefficients to only two values ​​of "+1" and "0" and setting the neuron signals to only two values ​​of "+1" and "0", circuit MP can perform the same operation as the logical multiplication circuit.

[0390] In this working example, the potentials in the holding section HC and the holding section HCr included in the circuits MC and MCr of the circuit MP are set to a high-level potential or a low-level potential. However, the holding section HC and the holding section HCr each hold a potential representing an analog value. For example, when the weight coefficient is a "positive analog value," a high-level analog potential is held at node nd1 of the holding section HC, while a low-level potential is held at node nd1r of the holding section HCr. When the weight coefficient is a "negative analog value," a low-level analog potential is held at node nd1 of the holding section HC, while a high-level analog potential is held at node nd1r of the holding section HCr. Current I OL and current I OLB The current level corresponds to the analog potential level. Figure 9A In the circuit MP, and also in other circuits MP described in this specification, the holding parts HC and HCr may hold potentials representing analog values.

[0391] <Structure Example 2>

[0392] Next, the following description can be applied to Figure 5C and Figure 5D An example of the circuit configuration of the circuit MP is shown.

[0393] Figure 16A The circuit MP shown is Figure 5C An example of the structure of the circuit MP, with Figure 9A The difference between the circuit MP and the wiring IL is that the wiring IL and the wiring ILB are combined into one; Figure 9A The wiring WL uses the wiring W1L and the wiring W2L.

[0394] exist Figure 16A In the circuit MP, the first terminal of the transistor M1 and the first terminal of the transistor M1r are electrically connected to the wiring IL. Furthermore, the gate of the transistor M1 is electrically connected to the wiring W1L, and the gate of the transistor M1r is electrically connected to the wiring W2L. Note that the circuit is omitted. Figure 16A The circuit MP in the Figure 9A The connection structure of the circuit MP is the same as that of the other parts.

[0395] In setting Figure 16A When the weight coefficient of the circuit MP is changed, the potential supplied to the wirings W1L and W2L is first changed to turn on the transistor M1 and turn off the transistor M1r. Then, the potential held in the holding portion HC is supplied from the wiring IL to turn off the transistor M1. Then, the potential supplied to the wirings W1L and W2L is changed to turn off the transistor M1 and turn on the transistor M1r. Then, the potential held in the holding portion HCr is supplied from the wiring IL to turn off the transistor M1r. In this way, Figure 16A The circuit MP can hold a potential corresponding to the weight coefficient in the holding portion HC and the holding portion HCr by supplying a potential to the holding portion HC and the holding portion HCr in sequence from the wiring IL.

[0396] Figure 16B The circuit MP shown is Figure 5D An example of the structure of the circuit MP, with Figure 9A The circuit MP is different in that the wiring IL and the wiring OL are combined into the wiring IOL; and the wiring ILB and the wiring OLB are combined into the wiring IOLB.

[0397] exist Figure 16B In the circuit MP, the first terminal of the transistor M1 is electrically connected to the wiring IOL, and the first terminal of the transistor M1r is electrically connected to the wiring IOLB. Furthermore, the second terminal of the transistor M3 is electrically connected to the wiring IOL, the second terminal of the transistor M4 is electrically connected to the wiring IOLB, the second terminal of the transistor M3r is electrically connected to the wiring IOLB, and the second terminal of the transistor M4r is electrically connected to the wiring IOL. Note that the circuit MP is omitted. Figure 16B The circuit MP in the Figure 9A The connection structure of the circuit MP is the same as that of the other parts.

[0398] exist Figure 16B In the circuit MP, the holding portion HC is electrically connected to the wiring IOL, the holding portion HCr is electrically connected to the wiring IOLB, and the wiring WL is electrically connected to the gates of the transistors M1 and M1r. Figure 9ASimilarly to the circuit MP, a potential corresponding to the weight coefficient can be written to the holding part HC and the holding part HCr at the same time.

[0399] <Structure Example 3>

[0400] and Figure 9A The circuit MP is different, Figure 17 The circuit MP shown includes a holding portion HCs and a holding portion HCsr in addition to the holding portion HC and the holding portion HCr.

[0401] Included in Figure 17 The circuit MC in the circuit MP is Figure 9A In addition to the circuit elements included in the circuit MP, the circuit MP also includes a transistor M1s, a transistor M2s, a transistor M5, a transistor M5s, and a capacitor C1s. Figure 17 Circuit MCr in circuit MP includes the same circuit elements as circuit MC, and thus includes transistor M1sr, transistor M2sr, transistor M5r, transistor M5sr, and capacitor C1sr corresponding to transistor M1s, transistor M2s, transistor M5, transistor M5s, and capacitor C1s of circuit MC, respectively.

[0402] In this specification, unless otherwise specified, transistors M5, M5s, M5r, and M5sr are considered to operate in the linear region when turned on. In other words, this includes the case where the gate voltage, source voltage, and drain voltage of each of the transistors are appropriately biased so that the transistor operates in the linear region.

[0403] Next, explain Figure 17 The structure of the circuit MP. Note that the Figure 17 The circuit MP in the Figure 9A The description of the parts of the circuit MP having the same structure.

[0404] The gate of transistor M1 is electrically connected to wiring W1L. The first terminal of transistor M5 is electrically connected to the second terminal of transistor M2, the second terminal of transistor M5 is electrically connected to the first terminal of transistor M3 and the first terminal of transistor M4, and the gate of transistor M5 is electrically connected to wiring S1L.

[0405] A first terminal of transistor M1s is electrically connected to wiring IL, a second terminal of transistor M1s is electrically connected to the first terminal of capacitor C1s and the gate of transistor M2s, and the gate of transistor M1s is electrically connected to wiring W2L. A first terminal of transistor M2s is electrically connected to the second terminal of capacitor C1s and wiring VLs, and the second terminal of transistor M2s is electrically connected to the first terminal of transistor M5s. A second terminal of transistor M5s is electrically connected to the first terminal of transistor M3 and the first terminal of transistor M4, and the gate of transistor M5s is electrically connected to wiring S2L.

[0406] exist Figure 17 In the circuit MP, the circuit MCr has substantially the same circuit structure as the circuit MC. Therefore, to distinguish the circuit elements included in the circuit MC from those included in the circuit MCr, the symbols of the circuit elements included in the circuit MCr are appended with "r".

[0407] Furthermore, wiring VLs is used as a wiring for supplying a constant voltage. This constant voltage can be a low-level potential such as VSS, a low-level potential other than VSS, or a ground potential. Alternatively, this constant voltage can be set to a high-level potential such as VDD. Furthermore, the constant voltage supplied by wiring VLs can be different from or the same as the constant voltage supplied by wiring VL. For example, if the constant voltage supplied by wiring VL is substantially the same as the constant voltage supplied by wiring VLs, wiring VLs can be the same wiring as wiring VL.

[0408] Furthermore, wiring VLsr is used as a wiring for supplying a constant voltage. This constant voltage can be a low-level potential such as VSS, a low-level potential other than VSS, or a ground potential. Alternatively, this constant voltage can be set to a high-level potential such as VDD. Furthermore, the constant voltage supplied by wiring VLsr can be different from or the same as the constant voltage supplied by wiring VLr. For example, if the constant voltage supplied by wiring VLr is substantially the same as the constant voltage supplied by wiring VLsr, wiring VLsr can be the same wiring as wiring VLr.

[0409] Furthermore, the constant voltage supplied to each of the wirings VL, VLs, VLr, and VLsr may be different voltages or the same voltage. Furthermore, the constant voltage supplied to two or three wirings selected from the wirings VL, VLs, VLr, and VLsr may be the same.

[0410] The wiring S1L is used as a wiring for supplying a potential for turning on or off the transistors M5 and M5r, and the wiring S2L is used as a wiring for supplying a potential for turning on or off the transistors M5s and M5sr.

[0411] By adopting Figure 17 The structure of the circuit MP, Figure 5C 、 Figure 5D The circuit MP shown can maintain two weight coefficients. Specifically, Figure 17 The circuit MP can hold the potential corresponding to the first weight coefficient in the holding portion HC of the circuit MC and the holding portion HCr of the circuit MCr, and hold the potential corresponding to the second weight coefficient in the holding portion HCs of the circuit MC and the holding portion HCsr of the circuit MC. Figure 17 The circuit MP can switch the weight coefficient used for the operation by the potential supplied from the wiring S1L and the wiring S2L. For example, by making each holding part HC and holding part HCr in the circuit MP[1,j] to the circuit MP[m,j] included in the operation circuit 110 hold the weight coefficient w1 (k-1) j (k) to w m (k-1) j (k) The potential of the circuit MP[1,j] to the circuit MP[m,j] included in the operation circuit 110 is maintained by each holding portion HCs, HCsr equivalent to the weight coefficient w1 (k-1) h (k) to w m (k-1) h (k) (Here, h is an integer greater than or equal to 1 and not equal to j.) to control the potential of the wiring XLS[1] to the wiring XLS[m] ( Figure 17 The wiring X1L, X2L in the circuit MP) input corresponds to the signal z1 (k-1) to z m (k-1) At this time, by applying a high-level potential to the wiring S1L to turn on the transistors M5 and M5r and applying a low-level potential to the wiring S2L to turn off the transistors M5s and M5sr, the circuits MP[1, j] to MP[m, j] of the arithmetic circuit 110 can calculate the weight coefficient w1. (k -1) j (k) to w m (k-1) j (k) With signal z1 (k-1) to z m (k-1)In addition, by applying a low-level potential to the wiring S1L to turn off the transistors M5 and M5r and applying a high-level potential to the wiring S2L to turn on the transistors M5s and M5sr, the circuits MP[1, j] to MP[m, j] of the operation circuit 110 can perform weight coefficient w1. (k-1) h (k) to w m (k-1) h (k) With signal z1 (k-1) to z m (k-1) The operation of the product sum and activation function.

[0412] As described above, by using the arithmetic circuit 110 Figure 17 The circuit MP can maintain two weight coefficients and can switch the weight coefficients to perform product sum and activation function operations. For example, when the number of neurons in the kth layer is greater than n, the circuit MP can maintain two weight coefficients and switch the weight coefficients to perform product sum and activation function operations. Figure 17 The calculation circuit 110 of the circuit MP is very effective when performing calculations in an intermediate layer different from the k-th layer. Figure 17 In the circuit MP, each of the circuit MC and the circuit MCr includes two holding portions. However, the circuit MC and the circuit MCr may include three or more holding portions depending on circumstances.

[0413] <Structure Example 4>

[0414] Figure 18A The circuit MP shown is applicable to Figure 5A The circuit MP of the holding part HC and the holding part HCr each includes a load circuit LC, a load circuit LCr instead of the capacitor C1, the capacitor C1r, which is different from Figure 9A The circuit MP is different.

[0415] exist Figure 18A In the circuit MC of the circuit MP, a first terminal of the load circuit LC is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M3, and the first terminal of the transistor M4, and a second terminal of the load circuit LC is electrically connected to the wiring VL.

[0416] exist Figure 18A In the circuit MP, the circuit MCr has substantially the same circuit structure as the circuit MC. Therefore, to distinguish the circuit elements included in the circuit MC from those included in the circuit MCr, the symbols of the circuit elements included in the circuit MCr are appended with "r".

[0417] Here, the wiring VL and the wiring VLr are used as wiring for supplying a constant voltage VCNS. As VCNS, for example, a ground potential (GND) or a low potential within a range in which the load circuits LC and LCr operate normally can be used.

[0418] For example, load circuit LC or load circuit LCr is a circuit capable of varying the resistance value between a first terminal and a second terminal. By varying the resistance value between the first terminal and the second terminal of load circuit LC or load circuit LCr, the amount of current flowing between the first terminal and the second terminal of load circuit LC or load circuit LCr can be varied.

[0419] Here, it is explained Figure 18A A method for changing the resistance value between the first and second terminals of load circuits LC and LCr in circuit MP. First, a low-level potential is input to each of wirings X1L and X2L, turning off transistors M3, M3r, M4, and M4r. Next, a high-level potential is input to wiring WL, turning on transistors M1 and M1r, thereby changing the potential of wiring IL (wiring ILB) and setting the resistance value between the first and second terminals of load circuit LC (load circuit LCr). For example, a method includes inputting a potential to reset the resistance value between the first and second terminals of load circuit LC (load circuit LCr) to wiring IL (wiring ILB), and then inputting a potential to achieve a desired resistance value between the first and second terminals of load circuit LC (load circuit LCr) to wiring IL (wiring ILB). After setting the resistance value between the first and second terminals of load circuit LC (load circuit LCr) to the desired value, a low-level potential is input to wiring WL, turning off transistors M1 and M1r.

[0420] like Figure 18B As shown in FIG. 1 , a variable resistor VR can be used as the load circuit LC or the load circuit LCr. Figure 18C As shown in FIG. 1 , as the load circuit LC and the load circuit LCr, for example, a circuit VC including an MTJ element MR can be used. Figure 18D As shown, as the load circuit LC and the load circuit LCr, for example, a resistor including a phase change material used in a phase change memory (PCM) or the like (in this specification, etc., for convenience, referred to as a phase change memory PCM) can be used.

[0421] In addition, the circuit MP using the load circuit LC and the load circuit LCr is not limited to Figure 18A The structure shown can be changed according to the situation Figure 18A The structure of the circuit MP. Figure 18AExamples of changes to the circuit MP include: Figure 18A The circuit MP does not include the circuit structure including the wiring IL, the wiring ILB, the transistor M1, and the transistor M1r. Figure 19 is a circuit diagram showing the circuit structure, and Figure 5D A structural example of the circuit MP.

[0422] exist Figure 19 In circuit MP, the resistance value between the first and second terminals of load circuit LC is set as follows: a high-level potential is input to wiring X1L and a low-level potential is input to wiring X2L, thereby turning on transistor M3 and turning off transistor M4. A potential is then supplied from wiring 10L through transistor M3 to the first terminal of load circuit LC. Furthermore, in this case, a potential can be supplied from wiring 10LB through transistor M3r to the first terminal of load circuit LCr. Therefore, the resistance value between the first and second terminals of load circuit LC can be set simultaneously with the resistance value between the first and second terminals of load circuit LCr.

[0423] Alternatively, the resistance value between the first and second terminals of load circuit LC can be set by inputting a low-level potential to wiring X1L and a low-level potential to wiring X2L, thereby turning on transistor M3 and turning off transistor M4. A potential is then supplied from wiring 10LB through transistor M4 to the first terminal of load circuit LC. Furthermore, in this case, a potential can be supplied from wiring 10L through transistor M4r to the first terminal of load circuit LCr. Therefore, the resistance value between the first and second terminals of load circuit LC can be set simultaneously with the resistance value between the first and second terminals of load circuit LCr.

[0424] in addition, Figure 18A 、 Figure 19 The resistance value between the first terminal and the second terminal of each of the load circuit LC and the load circuit LCr shown may be two values ​​or three or more values, or may be an analog value.

[0425] <Structure Example 5>

[0426] Figure 20A The circuit MP shown is applicable to Figure 5A The circuit MP of the circuit, each of the holding part HC and the holding part HCr includes a circuit structure of an inverter loop instead of the capacitor C1 and the capacitor C1r, which is different from Figure 9A The circuit MP is different.

[0427] exist Figure 20AIn the circuit MC of the circuit MP, the holding part HC includes an inverter circuit INV1 and an inverter circuit INV2. The input terminal of the inverter circuit INV1 is electrically connected to the output terminal of the inverter circuit INV2, the second terminal of the transistor M1, and the gate of the transistor M2. Figure 9A Similarly to the description above, the electrical connection point between the second terminal of transistor M1, the gate of transistor M2, the input terminal of inverter circuit INV1, and the output terminal of inverter circuit INV2 is referred to as node nd1. Note that node nd1 may be connected to the output terminal of inverter circuit INV1 instead of the input terminal of inverter circuit INV1.

[0428] exist Figure 20A In the circuit MP, the circuit MCr has substantially the same circuit structure as the circuit MC. Therefore, to distinguish the circuit elements included in the circuit MC from those included in the circuit MCr, the symbols of the circuit elements included in the circuit MCr are appended with "r".

[0429] The holding section HC included in the circuit MC forms an inverter loop with the inverter circuit INV1 and the inverter circuit INV2, and the holding section HCr included in the circuit MCr forms an inverter loop with the inverter circuit INV1r and the inverter circuit INV2r. In other words, Figure 20A The circuit MP can hold a potential corresponding to a weight coefficient by each inverter loop of the holding part HC and the holding part HCr.

[0430] Note that in Figure 20A Although circuit MP shows inverter circuits INV1, INV1r, INV2, and INV2r, at least one of inverter circuits INV1, INV1r, INV2, and INV2r can be replaced with a logic circuit that receives an input signal and outputs an inverted signal of the input signal. Examples of such logic circuits include NAND circuits, NOR circuits, XOR circuits, and combinations thereof. Specifically, when replacing the inverter circuit with a NAND circuit, a high-level potential can be input to one of the two input terminals of the NAND circuit as a fixed potential, allowing the NAND circuit to function as an inverter circuit. Furthermore, when replacing the inverter circuit with a NOR circuit, a low-level potential can be input to one of the two input terminals of the NOR circuit as a fixed potential, allowing the NOR circuit to function as an inverter circuit. Furthermore, when the inverter circuit is replaced with an XOR circuit, the XOR circuit can be used as an inverter circuit by inputting a high-level potential to one of the two input terminals of the XOR circuit as a fixed level.

[0431] As described above, the inverter circuit described in this specification and the like can be replaced by a logic circuit such as a NAND circuit, a NOR circuit, an XOR circuit, or a combination of these circuits. Therefore, in this specification and the like, an "inverter circuit" may also be referred to as a "logic circuit."

[0432] in addition, Figure 20A The structure of the circuit MP can be changed according to circumstances. Figure 20B Show changes Figure 20A Example of circuit MP. Figure 20B The circuit MP has Figure 20A The circuit MCr of the circuit MP has a structure in which the holding portion HCr is not provided and the holding portion HC of the circuit MC is electrically connected to the gate of the transistor M2r of the circuit MCr.

[0433] exist Figure 20B In FIG, the electrical connection point between the output terminal of the inverter circuit INV1 and the input terminal of the inverter circuit INV2 is referred to as a node nd2. In other words, the potential of the node nd2 is input to the gate of the transistor M2r.

[0434] Figure 20B In the illustrated circuit MP, the holding section HCr is not provided in the circuit MCr. Instead, the potential supplied to the gate of the transistor M2r is held by the holding section HC of the circuit MC. Furthermore, the holding section HC has an inverter loop structure formed by the inverter circuit INV1 and the inverter circuit INV2. Therefore, one of a high-level potential and a low-level potential is held at the node nd1, and the other of the high-level potential and the low-level potential is held at the node nd2.

[0435] Note that due to the structure of the inverter loop, the holding portion HC cannot maintain the same potential at both the node nd1 and the node nd2. Figure 20B In the circuit MP, the weight coefficient expressed by maintaining the same potential at the node nd1 and the node nd2 cannot be set. Specifically, in the above working example, the gates of the transistors M2 and M2r cannot maintain a low level potential, so Figure 20B The weight coefficient is set to "0" in the circuit MP.

[0436] <Structure Example 6>

[0437] Figure 21A The circuit MP shown is applicable to Figure 5A In the circuit MP, each of the holding portion HC and the holding portion HCr includes two transistors and two capacitors, which is different from the Figure 9A The circuit MP is different.

[0438] exist Figure 21AIn the circuit MC of the circuit MP shown, the holding portion HC includes a transistor M1, a transistor M1s, a capacitor C2, and a capacitor C2s. The first terminal of the transistor M1 is electrically connected to the wiring IL, the second terminal of the transistor M1 is electrically connected to the first terminal of the capacitor C2 and the gate of the transistor M6, and the gate of the transistor M1 is electrically connected to the wiring WL. The first terminal of the transistor M1s is electrically connected to the wiring IL, the second terminal of the transistor M1s is electrically connected to the first terminal of the capacitor C2s and the gate of the transistor M7, and the gate of the transistor M1s is electrically connected to the wiring WL. Figure 9A Similarly, the electrical connection point between the second terminal of transistor M1, the gate of transistor M6 and the first terminal of capacitor C2 is called nd1, and the electrical connection point between the second terminal of transistor M1s, the gate of transistor M7 and the first terminal of capacitor C2s is called nd1s.

[0439] A second terminal of the capacitor C2 is electrically connected to the wiring X1L, and a second terminal of the capacitor C2s is electrically connected to the wiring X2L.

[0440] A first terminal of the transistor M6 is electrically connected to a first terminal of the transistor M7 and the wiring VL, a second terminal of the transistor M6 is electrically connected to the wiring OL, and a second terminal of the transistor M7 is electrically connected to the wiring OLB.

[0441] exist Figure 21A In the circuit MP, the circuit MCr has substantially the same circuit structure as the circuit MC. Therefore, to distinguish the circuit elements included in the circuit MC from those included in the circuit MCr, the symbols of the circuit elements included in the circuit MCr are appended with "r".

[0442] The holding section HC included in circuit MC has the function of maintaining a potential using capacitors C2 and C2s. Specifically, by inputting a high-level potential to wiring WL, turning on transistors M1 and M1s, and then inputting a specified potential to wiring IL, the specified potential is written to the first terminals of capacitors C2 and C2s. Subsequently, by inputting a low-level potential to wiring WL, turning off transistors M1 and M1s, the specified potential can be maintained at both nodes nd1 and nd1s of the holding section HC. Furthermore, when the specified potential is written to and maintained in the holding section HC, the potentials of wirings X1L and X2L are preferably constant, for example, and more preferably, a potential higher than the low-level potential and lower than the high-level potential. For convenience, this constant potential is referred to as a reference potential.

[0443] In addition, Figure 21AIn the circuit MP, the wiring WL is electrically connected to each of the holding part HC and the holding part HCr. Therefore, when a potential equivalent to the weight coefficient is written to the holding part HC and the holding part HCr for holding, a specified potential is written to the holding part HC and the holding part HCr at the same time when the potential of the wiring WL is a high-level potential, and then the potential of the wiring WL is made a low-level potential to make the transistors M1, the transistor M1s, the transistor M1r and the transistor M1sr all in the off state.

[0444] Here, the signal input to the neuron of circuit MP is defined as follows: When a voltage higher than a reference potential (hereinafter referred to as a high-level potential) is applied to wiring X1L and a voltage lower than a reference potential (hereinafter referred to as a low-level potential) is applied to wiring X2L, a "+1" signal is input to circuit MP as a neuron. When a low-level potential is applied to wiring X1L and a high-level potential is applied to wiring X2L, a "-1" signal is input to circuit MP as a neuron. When a low-level potential is applied to both wiring X1L and wiring X2L, a "0" signal is input to circuit MP as a neuron.

[0445] For example, when a potential corresponding to the weight coefficient is held in the holding units HC and HCr, and a "+1" signal is input to circuit MP as a neuron, a high-level potential is input to wiring X1L. Therefore, the potentials at nodes nd1 and nd1r increase due to capacitive coupling between capacitors C2 and C2r. Consequently, the potentials at the gates of transistors M6 and M6r increase, turning on transistors M6 and M6r. Furthermore, a low-level potential is input to wiring X2L, causing the potentials at nodes nd1s and nd1sr to decrease due to capacitive coupling between capacitors C2s and C2sr. Consequently, the potentials at the gates of transistors M7 and M7r decrease, turning off transistors M7 and M7r. In other words, the "+1" signal input to circuit MP as a neuron causes conduction between circuit MC and wiring OL, and conduction between circuit MCr and wiring OLB.

[0446] For example, when a potential corresponding to the weight coefficient is held in the holding units HC and HCr, and a "-1" signal is input to circuit MP as a neuron, a low-level potential is input to wiring X1L. Therefore, the potentials at nodes nd1 and nd1r decrease due to capacitive coupling between capacitors C2 and C2r. Consequently, the potentials at the gates of transistors M6 and M6r decrease, turning off transistors M6 and M6r. Furthermore, a high-level potential is input to wiring X2L, causing the potentials at nodes nd1s and nd1sr to increase due to capacitive coupling between capacitors C2s and C2sr. Consequently, the potentials at the gates of transistors M7 and M7r increase, turning on transistors M7 and M7r. In other words, the "-1" signal input to circuit MP as a neuron causes conduction between circuit MC and wiring OLB, and conduction between circuit MCr and wiring OL.

[0447] For example, when a potential corresponding to the weight coefficient is held in the holding units HC and HCr, and a "0" signal is input to circuit MP as a neuron, a low-level potential is input to wiring X1L. As a result, the potentials at nodes nd1 and nd1r decrease due to capacitive coupling between capacitors C2 and C2r. Consequently, the potentials at the gates of transistors M6 and M6r decrease, turning off transistors M6 and M6r. Furthermore, a low-level potential is input to wiring X2L, and the potentials at nodes nd1s and nd1sr decrease due to capacitive coupling between capacitors C2s and C2sr. Consequently, the potentials at the gates of transistors M7 and M7r decrease, turning off transistors M7 and M7r. In other words, by inputting a "0" signal to circuit MP as a neuron, circuit MC and wirings OL and OLB, as well as circuit MCr and wirings OL and OLB, become non-conductive.

[0448] In addition, the on-states of transistors M6, M6r, M7, and M7r are preferably operated in the saturation region, for example. Therefore, it is preferable to appropriately bias the gates, sources, and drains of transistors M6, M6r, M7, and M7r so that the transistors operate in the saturation region when on. By operating the on-states of transistors M6, M6r, M7, and M7r in the saturation region, the current flowing between the source and drain of the transistors increases when the potential between the gate and source increases. In other words, when wiring X1L (wiring X2L) is at a high level, the current flowing between the source and drain of transistors M6 and M6r (transistor M7 and transistor M7r) is determined by the potential of nodes nd1 and nd1r (nodes nd1s and nodes nd1sr). Note that one embodiment of the present invention is not limited to this.

[0449] in addition, Figure 21A The structure of the circuit MP can be changed according to circumstances. Figure 21B Show changes Figure 21A Example of circuit MP. Figure 21B The circuit MP has Figure 21A The transistors M6, M6r, M7, and M7r of the circuit MP do not have back gates. Therefore, the transistors M6, M6r, M7, and M7r included in the circuit MP do not depend on the transistor structure and can be determined during design.

[0450] For example, as Figure 21B The transistors M6, M6r, M7, and M7r can be Si transistors whose active layers include single-crystal silicon or non-single-crystal silicon. Figure 21B The transistors M6, M6r, M7, and M7r can be OS transistors whose active layers include an oxide semiconductor. Alternatively, transistors including an organic semiconductor, a compound semiconductor, or the like can be used as the transistors M6, M6r, M7, and M7r.

[0451] As described above, by using the arithmetic circuit 110 Figure 21A 、 Figure 21B The circuit MP can be used with Figure 9A The circuit MP similarly performs product-sum and activation function operations.

[0452] <Structure Example 7>

[0453] In structural examples 1 to 6, a circuit MP is described that can calculate the product of the three values ​​of the weight coefficients "+1", "-1", and "0" maintained by the circuit MP and the three values ​​of the signals "+1", "-1", and "0" of the neurons corresponding to the potentials input from the wiring X1L and the wiring X2L. In the present structural example, a circuit MP is described that can, for example, calculate the product of the three values ​​of the weight coefficients "+1", "-1", and "0" and the two values ​​of the signals (calculated values) "+1" and "0" of the neurons.

[0454] Figure 22A The circuit MP shown is Figure 9A The circuit MP does not have a structure in which transistors M4 and M4r are provided. In addition, the circuit MP does not have a structure in which transistors M4 and M4r are provided. Figure 22A In the embodiment, there is no wiring X2L for inputting potential to each gate of the transistor M4 and the transistor M4r. Figure 22A In the figure, the wiring corresponding to the wiring X1L is referred to as wiring XL.

[0455] exist Figure 22A The weight coefficient set in the circuit MP is set to "+1" when the node nd1 of the holding part HC maintains a high level potential and the node nd1r of the holding part HCr maintains a low level potential, is set to "-1" when the node nd1 of the holding part HC maintains a low level potential and the node nd1r of the holding part HCr maintains a high level potential, and is set to "0" when the node nd1 of the holding part HC maintains a low level potential and the node nd1r of the holding part HCr maintains a low level potential.

[0456] In addition, Figure 22A The neuron signal input to the circuit MP is set to “+1” when a high-level potential is applied to the wiring XL, and is set to “0” when a low-level potential is applied to the wiring XL.

[0457] Figure 22A The operation of the circuit MP refers to the description of the working example of the structural example 1.

[0458] When Figure 22A When the weight coefficients and the input neuron signals are defined as above in the circuit MP, the weight coefficients are shown in the following table: When the neuron signal is input to the circuit MP, the current I output from the node outa of the wiring OL is OL and the current I output from the node outb of the wiring OLB. OLB Note that in the table below, high-level potential is represented as high and low-level potential is represented as low.

[0459] [Table 3]

[0460]

[0461] As shown in the table above, Figure 22A Circuit MP can calculate the product of the three values ​​of the weight coefficients "+1," "-1," and "0" and the two values ​​of the neuron signals "+1" and "0." Furthermore, the weight coefficients can be binary or ternary, and need not be ternary. For example, they can be binary values ​​of "+1" and "0," or binary values ​​of "+1" and "-1." Alternatively, the weight coefficients can be either analog values ​​or multi-bit (multi-valued) digital values.

[0462] In this working example, the potential in the holding section HC and the holding section HCr included in each of the circuits MC and MCr of the circuit MP is set to a high-level potential or a low-level potential. However, the holding section HC and the holding section HCr may also hold a potential representing an analog value. For example, when the weight coefficient is a "positive analog value," a high-level analog potential is held at node nd1 of the holding section HC, and a low-level potential is held at node nd1r of the holding section HCr. For example, when the weight coefficient is a "negative analog value," a low-level potential is held at node nd1 of the holding section HC, and a high-level analog potential is held at node nd1r of the holding section HCr. Current I OL and current I OLB The level of the current corresponds to the level of the analog potential.

[0463] and Figure 16A Similarly, the circuit MP Figure 22A The circuit MP may have a structure in which the wiring IL and the wiring ILB are combined into one and the wiring WL is divided into the wirings W1L and W2L. Figure 22B The above circuit structure is shown. Figure 22B The circuit MP can be applied, for example, to Figure 6 The operation circuit 120. Note that Figure 22B The working method of the circuit MP refers to Figure 16A Description of the working method of circuit MP.

[0464] in addition, Figure 22A The circuit MP may also adopt a structure in which the wiring XL is divided into the wiring X1L and the wiring X2L. Figure 22C The circuit structure is shown above. When a high-level potential or a low-level potential is supplied to wiring X1L and wiring X2L, respectively, there are four combinations of on and off states for each of transistors M3 and M3r. Furthermore, when a high-level potential or a low-level potential is held at node nd1 of holding unit HC and node nd1r of holding unit HCr, there are four combinations of potentials held at nodes nd1 and nd1r.

[0465] Specifically, when the node nd1 is held at a high level potential and a high level potential is applied to the wiring X1L, the wiring OL and the wiring VL are electrically connected, so the amount of current I flowing through the wiring OL is OL Furthermore, when a high-level potential is applied to the node nd1r and a high-level potential is applied to the wiring X2L, the wiring OLB and the wiring VLr are electrically connected, so the amount of current I flowing through the wiring OLB is OLB The following table shows the changes in Figure 22C In the circuit MP, the current I output from the node outa of the wiring OL is determined by the combination of the potentials held at the nodes nd1 and nd1r and the combination of the potentials supplied from the wirings X1L and X2L. OL The presence or absence of changes in and the current I output from the node outb of the wiring OLB OLB Note that in the table below, high-level potential is represented as high and low-level potential is represented as low.

[0466] [Table 4]

[0467] nd1 nd1r X1L X2L <![CDATA[I OL Changes]]> <![CDATA[I OLB Changes]]> low low high low No No high low high low have No low high high low No No high high high low have No low low low high No No high low low high No No low high low high No have high high low high No have low low low low No No high low low low No No low high low low No No high high low low No No low low high high No No high low high high have No low high high high No have high high high high have have

[0468] Next, the following describes Figures 22A to 22C The MP circuit has different structures.

[0469] and Figure 22A Similarly, the circuit MP Figure 23A The circuit MP shown is a circuit that calculates the product of the three values ​​of weight coefficients "+1", "-1", and "0" and the two values ​​of neuron signals "+1" and "0". The transistors M1s, M1sr, M7, M7r, capacitors C2s, and C2sr are not provided. Figure 21A The structure of the circuit MP. In addition, because Figure 23A Since capacitors C2s and C2sr are not provided, wiring X2L for inputting potential to the second terminals of capacitors C2s and C2sr is not provided. Figure 23A In the figure, the wiring corresponding to the wiring X1L is referred to as wiring XL.

[0470] about Figure 23A For the work, refer to the description of Structural Example 6.

[0471] and Figure 22A Similarly, by defining the circuit MP Figure 23AThe weight coefficients of the circuit MP and the signals of the neurons are shown in the table above. The product of the three values ​​of the weight coefficients "+1", "-1", and "0" and the two values ​​of the neuron signals "+1" and "0" can be calculated. In addition, the weight coefficient can also be 2 or more than 3 values, and can be other than 3 values. For example, it can be 2 values ​​of "+1" and "0" or 2 values ​​of "+1" and "-1". Alternatively, the weight coefficient can be either an analog value or a multi-bit (multi-value) digital value. For example, the potential in the holding part HC and the holding part HCr included in the circuit MC and the circuit MCr of the circuit MP is set to a high-level potential or a low-level potential, but a potential representing the analog value is maintained in the holding part HC and the holding part HCr. For example, when the weight coefficient is a "positive analog value", a high-level analog potential is maintained at the node nd1 of the holding part HC, and a low-level potential is maintained at the node nd1r of the holding part HCr. For example, when the weight coefficient is a "negative analog value", the node nd1 of the holding unit HC holds a low-level potential, and the node nd1r of the holding unit HCr holds a high-level analog potential. OL and current I OLB The level of the current corresponds to the level of the analog potential.

[0472] and Figure 16A Similarly, the circuit MP Figure 23A The circuit MP may have a structure in which the wiring IL and the wiring ILB are combined into one and the wiring WL is divided into the wirings W1L and W2L. Figure 23B The above circuit structure is shown. Figure 23B The circuit MP can be applied, for example, to Figure 6 The operation circuit 120. Note that Figure 23B The working method of the circuit MP refers to Figure 16A Description of the working method of circuit MP.

[0473] In addition, with Figure 22C Similarly, the circuit MP Figure 23A The circuit MP may also adopt a structure in which the wiring XL is divided into the wiring X1L and the wiring X2L. Figure 23CThe above circuit structure is shown. When a high-level potential or a low-level potential is supplied to the wiring X1L and the wiring X2L, respectively, there are four combinations of the on state and the off state of each of the transistors M6 and M6r. In addition, when a high-level potential or a low-level potential is maintained at each node nd1 and the node nd1r of the holding part HC and the holding part HCr, there are four combinations of the potentials maintained at the node nd1 and the node nd1r. In addition, for example, the potential in the holding part HC and the holding part HCr included in the circuit MC and MCr of the circuit MP is set to a high-level potential or a low-level potential, but the potential representing the analog value is maintained in the holding part HC and the holding part HCr. For example, when the weight coefficient is a "positive analog value", a high-level analog potential is maintained at the node nd1 of the holding part HC, and a low-level potential is maintained at the node nd1r of the holding part HCr. For example, when the weight coefficient is a "negative analog value", a low-level potential is maintained at the node nd1 of the holding part HC, and a high-level analog potential is maintained at the node nd1r of the holding part HCr. Current I OL and current I OLB The level of the current corresponds to the level of the analog potential.

[0474] exist Figure 23C In the circuit MP, the change of the current flowing through the wiring OL and the wiring OLB can be regarded as Figure 22C The circuit MP is the same. Therefore, Figure 22C The above table shows that the circuit MP is described in Figure 23C In the circuit MP, the current I output from the node outa of the wiring OL is determined by the combination of the potentials held at the nodes nd1 and nd1r and the combination of the potentials supplied from the wirings X1L and X2L. OL The presence or absence of changes in and the current I output from the node outb of the wiring OLB OLB The presence or absence of changes.

[0475] <Structure Example 8>

[0476] Figure 24A The circuit MP shown is applicable to Figure 5F The circuit of MP is an example of a circuit.

[0477] Figure 24A The circuit MP includes a circuit MC, a circuit MCr, and a transistor MZ.

[0478] exist Figure 24A In the circuit MP, the circuit MCr has substantially the same circuit structure as the circuit MC. Therefore, to distinguish the circuit elements included in the circuit MC from those included in the circuit MCr, the symbols of the circuit elements included in the circuit MCr are appended with "r".

[0479] Furthermore, the circuit MC includes a holding portion HC and a transistor M8 , and the circuit MCr includes a holding portion HCr and a transistor M8 r .

[0480] Included in Figure 24A The holding portion HC in the circuit MC of the circuit MP can be, for example, the same as that included in Figures 9A to 9C 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B The holding portion HC in the circuit MP and the circuit MC has the same structure.

[0481] A first terminal of transistor M8 is electrically connected to a first terminal of transistor MZ. A gate of transistor M8 is electrically connected to a second terminal of transistor M1 and a first terminal of capacitor C1. A second terminal of transistor M8 is electrically connected to wiring OL. A second terminal of capacitor C1 is electrically connected to wiring CVL. A first terminal of transistor M1 is electrically connected to wiring IL.

[0482] A first terminal of transistor M8r is electrically connected to a first terminal of transistor MZ. A gate of transistor M8r is electrically connected to a second terminal of transistor M1r and a first terminal of capacitor C1r. A second terminal of transistor M8r is electrically connected to wiring OLB. A second terminal of capacitor C1r is electrically connected to wiring CVL. A first terminal of transistor M1 is electrically connected to wiring ILB.

[0483] The wiring CVL is used as a wiring for supplying a constant voltage, for example, a high-level potential, a low-level potential, a ground potential, or the like can be used as the constant voltage.

[0484] and keep in Figure 9A The holding part HC and the holding part HCr in the circuit MP shown in FIG. 1 are similarly held. Figure 24A The holding units HC and HCr in the circuit MP can hold potentials corresponding to the weights. Specifically, for example, a predetermined potential is supplied to the wiring WL to turn on transistors M1 and M1r, a potential is supplied from the wiring IL to the first terminal of capacitor C1, and a potential is supplied from the wiring ILB to the first terminal of capacitor C1r. Then, a predetermined potential is supplied to the wiring WL to turn off transistors M1 and M1r.

[0485] Here, for example, Figure 24AThe weight coefficient set in the circuit MP is set to "+1" when the node nd1 of the holding part HC maintains a high level potential and the node nd1r of the holding part HCr maintains a low level potential, is set to "-1" when the node nd1 of the holding part HC maintains a low level potential and the node nd1r of the holding part HCr maintains a high level potential, and is set to "0" when the node nd1 of the holding part HC maintains a low level potential and the node nd1r of the holding part HCr maintains a low level potential.

[0486] The potentials of the gates of transistors M8 and M8r are determined by holding potentials corresponding to the weights in holding units HC and HCr, respectively. For example, the current flowing from circuit MP through wiring IL and / or wiring ILB is determined by supplying a potential corresponding to the value of the neuron's signal to wiring XL. For example, when a high-level potential is supplied to wiring XL as second data "1," a constant voltage supplied by wiring VL is supplied to the first terminal of transistor M8 and the first terminal of transistor M8r. At this time, when the potential of the gate of transistor M8 is high, current flows between the first and second terminals of transistor M8. When the potential of the gate of transistor M8 is low, no current flows between the first and second terminals of transistor M8. Similarly, when the potential of the gate of transistor M8r is high, current flows between the first and second terminals of transistor M8r. When the potential of the gate of transistor M8r is low, no current flows between the first and second terminals of transistor M8r. Furthermore, for example, when a low-level potential is supplied to wiring XL as second data "0", the constant voltage supplied by wiring VL is not supplied to the first terminal of transistor M8 and the first terminal of transistor M8r, so current does not flow between the first and second terminals of each transistor.

[0487] In other words, to summarize the above, when the product of the weight coefficient and the value of the neuron signal is "+1," the designated current flows from circuit MC through wiring OL and does not flow from circuit MCr through wiring OLB. Furthermore, when the product of the weight coefficient and the value of the neuron signal is "-1," the designated current flows from circuit MCr through wiring OLB and does not flow from circuit MC through wiring OL. Furthermore, when the product of the weight coefficient and the value of the neuron signal is "0," the designated current flows from circuit MC through wiring OL and does not flow from circuit MCr through wiring OLB.

[0488] The above table is the same as the circuit MP described in the structural example 7. Figure 24A The circuit MP can calculate the product of the three values ​​of the weight coefficients "+1", "-1", and "0" and the two values ​​of the neuron signals "+1" and "0". In addition, similarly to the circuit MP described in the structural example 7, Figure 24AThe circuit MP may be configured such that the weight coefficients are set as analog values, multi-bit (multi-value) digital values, or the like.

[0489] Furthermore, the arithmetic circuit of the semiconductor device which can be applied to one embodiment of the present invention Figure 24A The circuit MP can be appropriately changed according to the situation.

[0490] For example, in Figure 7 The operation circuit 130 uses Figure 24A When the circuit MP is Figure 24A The structure of the circuit MP is changed to Figure 24B The structure of the circuit MP shown in the figure is sufficient. Figure 24B The circuit MP has the Figure 24A In the circuit MP, the wiring OL and the wiring IL are combined into one wiring IOL, and the wiring OLB and the wiring ILB are combined into one wiring IOLB. Figure 24B The wiring XL shown is equivalent to Figure 7 Any one of the wiring XLS[1] to the wiring XLS[m] shown, Figure 24B The wiring WL shown is equivalent to Figure 7 Any one of the wiring WLS[1] to the wiring WLS[m] shown.

[0491] In addition, it can be applied to Figure 5A The circuit of MP is not limited to Figure 24A Circuit MP.

[0492] For example, the structure described in Example 4 can be Figure 18A The circuit MP is changed to be applicable to Figure 5A The circuit of MP. Figure 25A The circuit MP shown is applicable to Figure 5A The circuit of MP circuit, with Figure 18A Similarly, it includes a holding portion HC having a load circuit LC and a holding portion HCr having a load circuit LCr. Note that Figure 25A Work reference Figure 24A Circuit MP, Figure 18A Description of the circuit MP et al. working example.

[0493] In addition, for example, in Figure 7 The operation circuit 130 uses Figure 25A When the circuit MP is Figure 25A The structure of the circuit MP is changed to Figure 25B The structure of the circuit MP shown in the figure is sufficient. Figure 25B The circuit MP has the following structure: Figure 25AIn the circuit MP, the wiring OL and the wiring IL are combined into one wiring IOL, the wiring OLB and the wiring ILB are combined into one wiring IOLB, and the transistor M1 and the transistor M1r are not provided. Figure 25B The wiring XL shown is equivalent to Figure 7 Any one of the wiring XLS[1] to the wiring XLS[m] shown, Figure 25B The wiring WL shown is equivalent to Figure 7 Any one of the wiring WLS[1] to the wiring WLS[m] shown.

[0494] In addition, for example, the structure described in Structural Example 5 may be Figure 20A The circuit MP is changed to be applicable to Figure 5A The circuit of MP. Figure 26A The circuit MP shown is applicable to Figure 5A The circuit of MP circuit, with Figure 20A Similarly, it includes a holding unit HC including an inverter circuit INV1 and an inverter circuit INV2, and a holding unit HCr including an inverter circuit INV1r and an inverter circuit INV2r. Figure 26A The circuit MP is not provided with transistors M3, M3r, M4, and M4r. Note that Figure 26A Work reference Figure 24A Circuit MP, Figure 20A Description of the circuit MP et al. working example.

[0495] For example, the structure described in Example 5 can be Figure 20B The circuit MP is changed to be applicable to Figure 5A The circuit of MP. Figure 26B The circuit MP shown is applicable to Figure 5A The circuit of MP circuit, with Figure 20B Similarly, the holding unit HC including the inverter circuit INV1 and the inverter circuit INV2 is included. Figure 26B The circuit MP is not provided with transistors M3, M3r, M4, and M4r. Note that Figure 26B Work reference Figure 24A Circuit MP, Figure 20B Description of the circuit MP et al. working example.

[0496] For example, the structure described in Structural Example 7 can be Figure 22A The circuit MP is changed to be applicable to Figure 5A The circuit of MP. Figure 27A The circuit MP shown is applicable to Figure 5A The circuit of MP is the circuit of Figure 22AA modified example of the circuit MP. Note that Figure 22A The circuit MP and Figure 22A The differences of the circuit MP are as follows: the second terminal of the capacitor C1 is electrically connected to the wiring VL; the second terminal of the capacitor C1r is electrically connected to the wiring VL; the first terminal of the transistor M2 and the first terminal of the transistor M2 are electrically connected to the first terminal of the transistor MZ; the transistor M3 and the transistor M3r are not provided; etc. Note that Figure 27A Work reference Figure 24A Circuit MP, Figure 22A Description of the circuit MP et al. working example.

[0497] In addition, for example, in Figure 6 The operation circuit 120 uses Figure 27A When the circuit MP is Figure 27A The structure of the circuit MP is changed to Figure 27B The structure of the circuit MP shown in the figure is sufficient. Figure 27B In the circuit MP, Figure 27A The wiring IL and the wiring ILB in the circuit MP are combined into one wiring IL. Figure 27B The wiring XL shown is equivalent to Figure 6 Any one of the wiring XLS[1] to the wiring XLS[m] shown, Figure 27B The wiring WL shown is equivalent to Figure 6 Any one of the wiring WLS[1] to the wiring WLS[m] shown.

[0498] Note that this embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0499] (Implementation 3)

[0500] In this embodiment, a structural example of the OS transistor described in the above embodiment that can be applied to a semiconductor device is described.

[0501] <Structural Examples of Semiconductor Devices>

[0502] Figure 28 The semiconductor device shown includes a transistor 300 , a transistor 500 , and a capacitor 600 . Figure 30A is a cross-sectional view of the transistor 500 in the channel length direction, Figure 30B is a cross-sectional view of the transistor 500 in the channel width direction. Figure 30C is a cross-sectional view of the transistor 300 in the channel width direction.

[0503] Transistor 500 is a transistor containing a metal oxide in its channel formation region (OS transistor). Because transistor 500 has a low off-state current, using this OS transistor in a semiconductor device, particularly transistors M1, M3, and M4 of circuit MP included in arithmetic circuit 110, allows for long-term retention of written data. In other words, the frequency of refresh operations is low or no refresh operation is required, thereby reducing power consumption of the semiconductor device.

[0504] The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistor 300 and the transistor 500. In addition, the capacitor 600 may be the capacitor C1, the capacitor C1r, etc. in the circuit MP.

[0505] Transistor 300 is provided on substrate 311 and includes: a conductor 316, an insulator 315, a semiconductor region 313 formed by a portion of substrate 311; and low-resistance regions 314a and 314b serving as source and drain regions. Transistor 300 can be applied to the transistors of the above-described embodiments, for example.

[0506] like Figure 30C As shown, in transistor 300, conductor 316 covers the top surface and side surfaces of semiconductor region 313 in the channel width direction via insulator 315. By thus providing transistor 300 with a Fin structure, the effective channel width increases, thereby improving the on-state characteristics of transistor 300. Furthermore, since the influence of the electric field on the gate electrode can be reduced, the off-state characteristics of transistor 300 can be improved.

[0507] In addition, the transistor 300 may be a p-channel transistor or an n-channel transistor.

[0508] The channel formation region of the semiconductor region 313, the region adjacent thereto, the low-resistance region 314a and the low-resistance region 314b used as the source or drain region, and the like preferably comprise a semiconductor such as a silicon-based semiconductor, more preferably single-crystalline silicon. Alternatively, materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide) may be used. Silicon, in which the effective mass is controlled by applying stress to the crystal lattice and changing the interplanar spacing, may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) using GaAs, GaAlAs, or the like.

[0509] The low-resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus, or an element imparting p-type conductivity such as boron.

[0510] As the conductor 316 used as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0511] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the conductor material. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. To achieve both conductivity and embeddability, a laminate of a metal material such as tungsten or aluminum is preferably used as the conductor, with tungsten being particularly preferred for its heat resistance.

[0512] Notice, Figure 28 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method. For example, when a unipolar circuit having only OS transistors is used in a semiconductor device, as shown in FIG. Figure 29 As shown in FIG. 3 , the structure of the transistor 300 may be the same as that of the transistor 500 using an oxide semiconductor. The structure of the transistor 500 will be described later.

[0513] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 300 .

[0514] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0515] Note that in this specification, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon nitride oxide" refers to a material containing more nitrogen than oxygen. Note that in this specification, "aluminum oxynitride" refers to a material containing more oxygen than nitrogen, while "aluminum nitride oxide" refers to a material containing more nitrogen than oxygen.

[0516] The insulator 322 can also be used as a planarization film to planarize steps caused by the transistor 300 disposed thereunder. For example, to improve the flatness of the top surface of the insulator 322, the top surface can be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0517] As the insulator 324 , a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 311 , the transistor 300 , or the like into a region where the transistor 500 is provided is preferably used.

[0518] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferable to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 300. Specifically, the film that inhibits the diffusion of hydrogen refers to a film that has a small amount of hydrogen released.

[0519] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the film surface temperature in TDS analysis is within the range of 50°C to 500°C, and the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324, the amount of hydrogen released from the insulator 324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0520] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0521] Furthermore, conductors 328 and 330, etc., connected to capacitor 600 or transistor 500, are embedded in insulators 320, 322, 324, and 326. Furthermore, conductors 328 and 330 function as plugs or wiring. Note that the same reference numeral may be used to represent multiple conductors that function as plugs or wiring. Furthermore, in this specification and other documents, a wiring and a plug connected to the wiring may be considered a single component. That is, a portion of a conductor may function as wiring, and a portion of a conductor may function as a plug.

[0522] As the material for each plug and wiring (conductor 328 and conductor 330, etc.), a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being particularly preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0523] A wiring layer may be formed on the insulator 326 and the conductor 330. Figure 28In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed between the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. The conductor 356 can be formed using the same material as the conductors 328 and 330.

[0524] In addition, similar to insulator 324, insulator 350 is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 356 preferably includes a conductor having a hydrogen barrier property. In particular, a conductor having a hydrogen barrier property is formed within the opening of insulator 350 having a hydrogen barrier property. This structure allows transistor 300 and transistor 500 to be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0525] Note that tantalum nitride is preferably used as a conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the electrical conductivity as wiring can be maintained while also suppressing the diffusion of hydrogen from the transistor 300. In this case, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

[0526] Alternatively, a wiring layer may be formed on the insulator 354 and the conductor 356. For example, Figure 28 Insulator 360, insulator 362, and insulator 364 are stacked in this order. Furthermore, conductor 366 is formed between insulators 360, 362, and 364. Conductor 366 functions as a plug or wiring. Conductor 366 can be formed using the same material as conductors 328 and 330.

[0527] Insulator 360, similar to insulator 324, is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 366 preferably includes a conductor having a hydrogen barrier property. In particular, a conductor having a hydrogen barrier property is formed within the opening of insulator 360 having a hydrogen barrier property. This structure allows transistor 300 and transistor 500 to be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0528] Alternatively, a wiring layer may be formed on the insulator 364 and the conductor 366. For example, Figure 28Insulator 370, insulator 372, and insulator 374 are stacked in this order. Furthermore, conductor 376 is formed between insulators 370, 372, and 374. Conductor 376 functions as a plug or wiring. Conductor 376 can be formed using the same material as conductors 328 and 330.

[0529] Insulator 370, similar to insulator 324, is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 376 preferably includes a conductor having a hydrogen barrier property. In particular, a conductor having a hydrogen barrier property is formed within the opening of insulator 370 having a hydrogen barrier property. This structure allows transistor 300 and transistor 500 to be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0530] Alternatively, a wiring layer may be formed on the insulator 374 and the conductor 376. Figure 28 Insulator 380, insulator 382, ​​and insulator 384 are stacked in this order. Furthermore, conductor 386 is formed between insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. Conductor 386 can be formed using the same material as conductors 328 and 330.

[0531] Insulator 380, similar to insulator 324, is preferably made of, for example, an insulator having a hydrogen barrier property. Furthermore, conductor 386 preferably includes a conductor having a hydrogen barrier property. In particular, a conductor having a hydrogen barrier property is formed within the opening of insulator 380 having a hydrogen barrier property. This structure allows transistor 300 and transistor 500 to be separated by a barrier layer, thereby suppressing the diffusion of hydrogen from transistor 300 into transistor 500.

[0532] While the above description includes a wiring layer including conductor 356, a wiring layer including conductor 366, a wiring layer including conductor 376, and a wiring layer including conductor 386, the semiconductor device of this embodiment is not limited thereto. The number of wiring layers identical to the wiring layer including conductor 356 may be three or fewer, and the number of wiring layers identical to the wiring layer including conductor 356 may be five or more.

[0533] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As one of the insulators 510, 512, 514, and 516, a substance having a barrier property against oxygen or hydrogen is preferably used.

[0534] For example, the insulator 510 and the insulator 514 are preferably made of a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 311 or the region where the transistor 300 is provided into the region where the transistor 500 is provided. Therefore, the insulator 510 and the insulator 514 can be made of the same material as the insulator 324.

[0535] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferable to provide a film that inhibits the diffusion of hydrogen between transistor 300 and transistor 500. Specifically, the film that inhibits the diffusion of hydrogen refers to a film that has a small amount of hydrogen released.

[0536] For example, as a film having a barrier property against hydrogen, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are preferably used for the insulator 510 and the insulator 514 .

[0537] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen and hydrogen and moisture that can cause changes in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0538] For example, the insulators 512 and 516 can use the same material as the insulator 320. Furthermore, by using a material with a low dielectric constant as the insulator, parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulators 512 and 516.

[0539] Furthermore, a conductor 518 or a conductor constituting the transistor 500 (for example, the conductor 503) is embedded in the insulators 510, 512, 514, and 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using the same material as the conductors 328 and 330.

[0540] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties to oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer having barrier properties to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 300 into the transistor 500.

[0541] The transistor 500 is provided above the insulator 516 .

[0542] like Figure 30A and Figure 30B As shown, transistor 500 includes: a conductor 503 embedded in an insulator 514 and an insulator 516; an insulator 520 arranged on the insulator 516 and the conductor 503; an insulator 522 arranged on the insulator 520; an insulator 524 arranged on the insulator 522; an oxide 530a arranged on the insulator 524; an oxide 530b arranged on the oxide 530a; a conductor 542a and a conductor 542b arranged on the oxide 530b and separated from each other; an insulator 580 arranged on the conductors 542a and 542b and having an opening overlapping with the conductors 542a and 542b; an oxide 530c arranged on the bottom and side surfaces of the opening; an insulator 550 arranged on the formation surface of the oxide 530c; and a conductor 560 arranged on the formation surface of the insulator 550.

[0543] In addition, if Figure 30A and Figure 30B As shown in FIG. 5 , an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Figure 30A and Figure 30B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 550 and a conductor 560b embedded inside the conductor 560a. Figure 30A and Figure 30B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 550 .

[0544] Note that below, the oxide 530 a , the oxide 530 b , and the oxide 530 c may be collectively referred to as an oxide 530 .

[0545] In transistor 500, three layers of oxide 530a, oxide 530b, and oxide 530c are stacked in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. In addition, in transistor 500, conductor 560 has a two-layer structure, but the present invention is not limited to this. For example, conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that, Figure 28 、 Figure 30A The structure of the transistor 500 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method.

[0546] Here, conductor 560 is used as the gate electrode of the transistor, and conductor 542a and conductor 542b are used as the source electrode or drain electrode. As described above, conductor 560 is buried in the opening of insulator 580 and in the area between conductor 542a and conductor 542b. The arrangement of conductor 560, conductor 542a, and conductor 542b relative to the opening of insulator 580 is selected to be self-aligned. In other words, in transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. As a result, conductor 560 can be formed without providing room for alignment, so the area occupied by transistor 500 can be reduced. As a result, miniaturization and high integration of semiconductor devices can be achieved.

[0547] Furthermore, conductor 560 is formed in a self-aligned manner in the region between conductor 542a and conductor 542b. Therefore, conductor 560 does not include any region overlapping conductors 542a and 542b. This reduces parasitic capacitance between conductor 560 and conductors 542a and 542b. Consequently, the switching speed of transistor 500 can be increased, enabling transistor 500 to have high-frequency characteristics.

[0548] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, by independently changing the potential supplied to conductor 503 without interlocking it with the potential supplied to conductor 560, the threshold voltage of transistor 500 can be controlled. In particular, by supplying a negative potential to conductor 503, the threshold voltage of transistor 500 can be made greater than 0V and the off-state current can be reduced. Therefore, when a negative potential is applied to conductor 503, the drain current when the potential supplied to conductor 560 is 0V can be reduced compared to when no negative potential is applied to conductor 503.

[0549] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated by the conductor 560 and the electric field generated by the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification, etc., the structure of a transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0550] Conductor 503 has the same structure as conductor 518. Conductor 503a is formed so as to contact the inner walls of the openings of insulator 514 and insulator 516, and conductor 503b is formed inside the conductor 503a. While conductor 503a and conductor 503b are stacked in transistor 500, the present invention is not limited to this. For example, conductor 503 may have a single-layer structure or a stacked structure of three or more layers.

[0551] Here, as the conductor 503a, a conductive material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (preventing these impurities from penetrating easily) is preferably used. Furthermore, a conductive material that has the function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (preventing this oxygen from penetrating easily) is preferably used. In this specification, "the function of inhibiting the diffusion of impurities or oxygen" refers to the function of inhibiting the diffusion of any one or both of these impurities and oxygen.

[0552] For example, by providing the conductor 503a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0553] In addition, when the conductor 503 also has a wiring function, a highly conductive material mainly composed of tungsten, copper, or aluminum is preferably used as the conductor 503b. In the drawings, the conductor 503b has a single-layer structure, but it may also have a stacked-layer structure. For example, a stacked-layer structure of titanium, titanium nitride, and the above-mentioned conductive materials may be used.

[0554] The insulator 520 , the insulator 522 , the insulator 524 , and the insulator 550 function as a second gate insulating film.

[0555] Here, an insulator 524 that is in contact with the oxide 530 preferably contains oxygen exceeding the stoichiometric composition. In other words, an excess oxygen region is preferably formed in the insulator 524. By providing the insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, thereby improving the reliability of the transistor 500.

[0556] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released, calculated as oxygen atoms in TDS (Thermal Desorption Spectroscopy), is 1.0×10 18 atoms / cm 3 above, preferably 1.0×10 19 atoms / cm 3More than 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0557] In addition, the insulator having the above-mentioned excess oxygen region may be brought into contact with the oxide 530 and subjected to one or more of a heat treatment, a microwave treatment, and an RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction of breaking the bond of VoH occurs, in other words, a reaction of "VoH→Vo+H" occurs, and dehydrogenation can be achieved. A portion of the hydrogen generated here sometimes bonds with oxygen and is removed from the oxide 530 or the insulator near the oxide 530 as H2O. In addition, a portion of the hydrogen sometimes diffuses into the conductor 542 (conductor 542a and conductor 542b) or is captured by the conductor 542 (also called being doped).

[0558] In addition, the above-mentioned microwave treatment preferably uses, for example, an apparatus having a power for generating high-density plasma or an apparatus for applying RF power to one side of the substrate. For example, by using a gas containing oxygen and using high-density plasma, a high-density oxygen radical can be generated, and by applying RF to one side of the substrate, the oxygen radicals generated by the high-density plasma can be effectively introduced into the oxide 530 or the insulator near the oxide 530. In addition, in the above-mentioned microwave treatment, the pressure is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the apparatus for performing the microwave treatment, oxygen and argon are used, for example, and the microwave treatment is performed under the condition that the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0559] In addition, during the manufacturing process of the transistor 500, it is preferable to perform heat treatment in a state where the surface of the oxide 530 is exposed. This heat treatment is preferably performed at a temperature of, for example, 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. Therefore, oxygen can be supplied to the oxide 530, and oxygen defects (Vo) can be reduced. In addition, the heat treatment can also be performed under reduced pressure. For example, the heat treatment is preferably performed in an oxygen atmosphere. Alternatively, the heat treatment can be performed in a nitrogen gas or inert gas atmosphere, and then in order to compensate for the oxygen that has been released, the heat treatment can be performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. Alternatively, after the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher, the heat treatment can be continuously performed in a nitrogen gas or inert gas atmosphere.

[0560] Furthermore, by oxidizing the oxide 530, oxygen vacancies in the oxide 530 can be filled with supplied oxygen. In other words, the "Vo + O → null" reaction can be promoted. Furthermore, hydrogen remaining in the oxide 530 reacts with the supplied oxygen and is removed as H2O (dehydration). This prevents the hydrogen remaining in the oxide 530 from re-bonding to oxygen vacancies to form VoH.

[0561] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0562] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen or impurities because oxygen contained in the oxide 530 does not diffuse toward the insulator 520. In addition, the conductor 503 can be suppressed from reacting with oxygen contained in the insulator 524 or the oxide 530.

[0563] As the insulator 522, for example, a single layer or stack of insulators made of so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) is preferably used. As transistors are miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material as the insulator used as the gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0564] In particular, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used as an insulating material that has the function of suppressing the diffusion of impurities and oxygen (making oxygen less likely to permeate). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When such a material is used to form the insulator 522, the insulator 522 serves as a layer that suppresses the release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the surrounding area of ​​the transistor 500.

[0565] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0566] The insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferred because of their thermal stability. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, a stacked structure of the insulator 520 can be formed that is thermally stable and has a high relative dielectric constant.

[0567] exist Figure 30A and Figure 30B In the transistor 500, the insulator 520, the insulator 522, and the insulator 524 are used as the second gate insulating film having a three-layer stacked structure. However, the second gate insulating film may have a stacked structure of a single layer, two layers, or four or more layers. In this case, the stacked structure is not limited to being made of the same material, and a stacked structure formed of different materials may also be used.

[0568] In the transistor 500, a metal oxide used as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably CAAC-OS or CAC-OS described in Embodiment 4. In addition, as the oxide 530, In-Ga oxide or In-Zn oxide can also be used.

[0569] Furthermore, a metal oxide with low carrier density is preferably used for the transistor 500. To reduce the carrier density of the metal oxide, the impurity concentration in the metal oxide can be reduced to reduce the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic." Examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0570] In particular, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to produce water, sometimes forming oxygen vacancies in the metal oxide. Furthermore, when hydrogen enters oxygen vacancies in oxide 530, the oxygen vacancies sometimes bond with hydrogen to form VoH. VoH sometimes acts as a donor and generates electrons, which serve as carriers. Furthermore, sometimes electrons, which serve as carriers, are generated by the bonding of some of the hydrogen to oxygen bonded to metal atoms. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to have normally-on characteristics. Furthermore, hydrogen in metal oxides is easily mobilized by heat, electric fields, and other factors, so when the metal oxide contains a large amount of hydrogen, transistor reliability may be reduced. In one embodiment of the present invention, it is preferable to minimize VoH in oxide 530 to achieve high-purity intrinsic or substantially high-purity intrinsic. To obtain a metal oxide with such a significantly reduced VoH, it is important to: remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment); and to supply oxygen to the metal oxide to fill the oxygen vacancies (sometimes referred to as oxidation treatment). By using a metal oxide with significantly reduced impurities such as VoH in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0571] Defects in which hydrogen enters oxygen defects serve as donors for metal oxides. However, it is difficult to quantitatively evaluate this defect. Therefore, in metal oxides, the carrier concentration is sometimes used instead of the donor concentration for evaluation. Therefore, in this specification, etc., as a parameter of the metal oxide, the carrier concentration in a state assuming no electric field is applied is sometimes used instead of the donor concentration. In other words, the "carrier concentration" described in this specification, etc. may also sometimes be referred to as the "donor concentration."

[0572] Therefore, when a metal oxide is used as the oxide 530, it is preferable to reduce the amount of hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide measured by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0573] When a metal oxide is used as the oxide 530, the carrier concentration of the metal oxide in the channel formation region is preferably 1×10 18 cm -3 less than 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and further preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 12 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration of the metal oxide in the channel formation region, and it can be set to 1×10 -9 cm -3 .

[0574] Furthermore, when a metal oxide is used as the oxide 530, when the conductor 542 (conductor 542a and conductor 542b) contacts the oxide 530, oxygen in the oxide 530 may diffuse into the conductor 542, causing the conductor 542 to be oxidized. When the conductor 542 is oxidized, the conductivity of the conductor 542 is likely to decrease. Alternatively, "oxygen in the oxide 530 diffuses into the conductor 542" may be referred to as "conductor 542 absorbs oxygen in the oxide 530."

[0575] In addition, when oxygen in the oxide 530 diffuses into the conductor 542 (conductor 542a and conductor 542b), an insulating region is sometimes formed at the interface between the conductor 542a and the oxide 530b and near the interface, and at the interface between the conductor 542b and the oxide 530b and near the interface. This region contains more oxygen than the conductor 542, so it can be considered that the resistivity of this region is higher than that of the conductor 542a and the conductor 542b. In this case, the three-layer structure of the conductor 542, this region, and the oxide 530b can be considered to be a three-layer structure composed of metal, insulator, and semiconductor, sometimes referred to as an MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure with the MIS structure as the main structure.

[0576] Note that the above-mentioned insulating region is not limited to being formed between the conductor 542 and the oxide 530b. For example, sometimes an insulating region is formed between the conductor 542 and the oxide 530c, between the conductor 542 and the oxide 530b, or between the conductor 542 and the oxide 530c.

[0577] The metal oxide used as the channel formation region in the oxide 530 preferably has a band gap of 2 eV or greater, preferably 2.5 eV or greater. Using a metal oxide with a wide band gap can reduce the off-state current of the transistor.

[0578] In oxide 530, when oxide 530a is provided below oxide 530b, impurities can be prevented from diffusing from structures below oxide 530a to oxide 530b. When oxide 530c is provided above oxide 530b, impurities can be prevented from diffusing from structures above oxide 530c to oxide 530b.

[0579] Furthermore, the oxide 530 preferably has a stacked structure of oxides having different atomic number ratios of metal atoms. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used in the oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used in the oxide 530b. Furthermore, the atomic number ratio of the element M relative to In in the metal oxide used in the oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used in the oxide 530b. Furthermore, the atomic number ratio of In relative to the element M in the metal oxide used in the oxide 530b is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used in the oxide 530a. The metal oxide used in either the oxide 530a or the oxide 530b can be used as the oxide 530c.

[0580] The conduction band bottom energies of oxides 530a and 530c are preferably higher than the conduction band bottom energy of oxide 530b. In other words, the electron affinity of oxides 530a and 530c is preferably lower than that of oxide 530b.

[0581] Here, the energy level of the conduction band bottom changes smoothly at the junction of oxide 530a, oxide 530b, and oxide 530c. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of oxide 530a, oxide 530b, and oxide 530c changing continuously or being continuously connected. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c.

[0582] Specifically, by making oxide 530a and oxide 530b, and oxide 530b and oxide 530c contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. are preferably used as oxide 530a and oxide 530c.

[0583] In this case, the main path for carriers is through oxide 530b. By making oxide 530a and oxide 530c have the above structure, the defect state density at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c, can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0584] Conductors 542a and 542b, serving as source and drain electrodes, are provided on oxide 530b. Conductors 542a and 542b are preferably metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing these metal elements, or alloys combining these metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are also preferred because they have barrier properties against hydrogen and oxygen.

[0585] Although FIG30 shows single-layer conductors 542a and 542b, a stacked structure of two or more layers may be employed. For example, a stacked tantalum nitride film and a tungsten film is preferred. Alternatively, a stacked titanium film and an aluminum film may be employed. Furthermore, a two-layer structure comprising an aluminum film stacked on a tungsten film, a two-layer structure comprising a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure comprising a copper film stacked on a titanium film, or a two-layer structure comprising a copper film stacked on a tungsten film may also be employed.

[0586] Alternatively, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film, and a titanium film or a titanium nitride film is formed thereon; a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereon; or a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0587] In addition, if Figure 30A As shown, regions 543a and 543b may be formed as low-resistance regions at and near the interface between oxide 530 and conductor 542a (conductor 542b). In this case, region 543a serves as one of the source and drain regions, while region 543b serves as the other. Furthermore, a channel formation region is formed in the region sandwiched between regions 543a and 543b.

[0588] By forming the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer composed of the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in the region 543a (region 543b). In this case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0589] The insulator 544 is provided to cover the conductors 542 a and 542 b to suppress oxidation of the conductors 542 a and 542 b . In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and to be in contact with the insulator 524 .

[0590] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, and magnesium. Alternatively, the insulator 544 can be made of silicon nitride oxide or silicon nitride.

[0591] In particular, as the insulator 544, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium oxides, is preferably used. Hafnium aluminate is particularly heat-resistant compared to hafnium oxide films. Therefore, it is less likely to crystallize during the subsequent heat treatment process, making it preferred. Furthermore, if the conductors 542a and 542b are made of oxidation-resistant materials or their conductivity does not significantly decrease even after oxygen absorption, the insulator 544 is not necessarily required. Appropriate design can be used depending on the desired transistor characteristics.

[0592] The inclusion of the insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b through the oxide 530c and the insulator 550. In addition, oxidation of the conductor 560 by excess oxygen contained in the insulator 580 can be prevented.

[0593] Insulator 550 is used as a first gate insulating film. Insulator 550 is preferably disposed in contact with the inner side (top and side surfaces) of oxide 530c. Like insulator 524, insulator 550 is preferably formed using an insulator containing excess oxygen that releases oxygen upon heating.

[0594] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0595] By providing an insulator that releases oxygen when heated as the insulator 550 in contact with the top surface of the oxide 530c, oxygen can be efficiently supplied from the insulator 550 through the oxide 530c to the channel formation region of the oxide 530b. Furthermore, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 550. The thickness of the insulator 550 is preferably not less than 1 nm and not more than 20 nm.

[0596] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 550 to the conductor 560. Providing a metal oxide that suppresses oxygen diffusion suppresses the diffusion of excess oxygen from the insulator 550 to the conductor 560. In other words, the reduction in excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As this metal oxide, a material that can be used for the insulator 544 can be used.

[0597] In addition, similar to the second gate insulating film, the insulator 550 may also have a stacked structure. As transistors become increasingly miniaturized and highly integrated, the thinner the gate insulating film becomes, the more problems such as leakage current may arise. Therefore, by using a stacked structure of a high-k material and a thermally stable material as the insulator used as the gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Furthermore, a stacked structure with thermal stability and a high relative dielectric constant can be achieved.

[0598] exist Figure 30A and Figure 30B In the embodiment, the conductor 560 used as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0599] As the conductor 560a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b due to the oxygen contained in the insulator 550 and the decrease in conductivity. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide is preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be applied to the oxide 530 can be used. At this time, by forming the conductor 560a using a sputtering method, the resistance value of the conductor 560b can be reduced to make it a conductor. The conductor can be referred to as an OC (Oxide Conductor) electrode.

[0600] Conductor 560b is preferably a conductive material primarily composed of tungsten, copper, or aluminum. Since conductor 560b also functions as wiring, it is preferable to use a highly conductive material. For example, a conductive material primarily composed of tungsten, copper, or aluminum can be used. Conductor 560b may also have a laminated structure; for example, a laminated structure of titanium, titanium nitride, and the aforementioned conductive materials can be used.

[0601] Insulator 580 is preferably provided on conductors 542a and 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, insulator 580 preferably comprises silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, silicon oxide with pores, or resin. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide and silicon oxide with pores are particularly preferred because they easily form excess oxygen regions in subsequent steps.

[0602] The insulator 580 preferably has an excess oxygen region. By placing the insulator 580, which releases oxygen upon heating, in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Furthermore, the concentration of impurities such as water and hydrogen in the insulator 580 is preferably reduced.

[0603] The opening of the insulator 580 is formed so as to overlap with the region between the conductors 542a and 542b. Thus, the conductor 560 is embedded in the opening of the insulator 580 and in the region between the conductors 542a and 542b.

[0604] As semiconductor devices are miniaturized, gate lengths need to be shortened, but a decrease in the conducti...

Claims

1. A semiconductor device comprising a first circuit and a second circuit, in, The first circuit includes a first holding node, The second circuit includes a second holding node, The first circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The first circuit has a function of holding a first potential corresponding to first data at the first holding node. The second circuit has a function of holding a second potential corresponding to the first data at the second holding node. The first circuit has: A function of outputting a current corresponding to the first potential to the first wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; A function of outputting a current corresponding to the first potential to the second wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring; as well as A function of not outputting a current corresponding to the first potential to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, Furthermore, the second circuit has: A function of outputting a current corresponding to the second potential to the second wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; A function of outputting a current corresponding to the second potential to the first wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring; as well as A function of not outputting a current corresponding to the second potential to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring.

2. The semiconductor device according to claim 1, The first circuit includes first to fourth transistors and a first capacitor, The second circuit includes fifth to eighth transistors and a second capacitor, The first holding node is electrically connected to a first terminal of the first transistor, a gate of the second transistor, and a first terminal of the first capacitor. a first terminal of the second transistor is electrically connected to a second terminal of the first capacitor, The second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor, The gate of the third transistor is electrically connected to the first input wiring, The gate of the fourth transistor is electrically connected to the second input wiring, A second terminal of the third transistor is electrically connected to the first wiring, A second terminal of the fourth transistor is electrically connected to the second wiring, The second holding node is electrically connected to the first terminal of the fifth transistor, the gate of the sixth transistor, and the first terminal of the second capacitor. A first terminal of the sixth transistor is electrically connected to a second terminal of the second capacitor, The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, The gate of the seventh transistor is electrically connected to the first input wiring, The gate of the eighth transistor is electrically connected to the second input wiring, A second terminal of the seventh transistor is electrically connected to the second wiring, And a second terminal of the eighth transistor is electrically connected to the first wiring.

3. The semiconductor device according to claim 1, The first circuit includes first to fourth transistors, a ninth transistor and a first capacitor, The second circuit includes fifth to eighth transistors, a tenth transistor and a second capacitor, The first holding node is electrically connected to a first terminal of the first transistor, a gate of the second transistor, a gate of the ninth transistor, and a first terminal of the first capacitor. The second terminal of the first capacitor is electrically connected to the first terminal of the second transistor and the first terminal of the ninth transistor, The second terminal of the second transistor is electrically connected to the first terminal of the third transistor, The second terminal of the ninth transistor is electrically connected to the first terminal of the fourth transistor, The gate of the third transistor is electrically connected to the first input wiring, The gate of the fourth transistor is electrically connected to the second input wiring, A second terminal of the third transistor is electrically connected to the first wiring, A second terminal of the fourth transistor is electrically connected to the second wiring, The second holding node is electrically connected to a first terminal of the fifth transistor, a gate of the sixth transistor, a gate of the tenth transistor, and a first terminal of the second capacitor. The second terminal of the second capacitor is electrically connected to the first terminal of the sixth transistor and the first terminal of the tenth transistor, The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor, The second terminal of the tenth transistor is electrically connected to the first terminal of the eighth transistor, The gate of the seventh transistor is electrically connected to the first input wiring, The gate of the eighth transistor is electrically connected to the second input wiring, A second terminal of the seventh transistor is electrically connected to the second wiring, And a second terminal of the eighth transistor is electrically connected to the first wiring.

4. The semiconductor device according to claim 1, The first circuit includes first to fourth transistors, a first logic circuit and a second logic circuit. The second circuit includes fifth to eighth transistors, a third logic circuit, and a fourth logic circuit. Each of the first to fourth logic circuits has a function of outputting an inverted signal of a signal input to an input terminal from an output terminal, The first holding node is electrically connected to an input terminal of the first logic circuit, an output terminal of the second logic circuit, a first terminal of the first transistor, and a gate of the second transistor. The output terminal of the first logic circuit is electrically connected to the input terminal of the second logic circuit, The second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor, The gate of the third transistor is electrically connected to the first input wiring, The gate of the fourth transistor is electrically connected to the second input wiring, A second terminal of the third transistor is electrically connected to the first wiring, A second terminal of the fourth transistor is electrically connected to the second wiring, The second holding node is electrically connected to an input terminal of the third logic circuit, an output terminal of the fourth logic circuit, a first terminal of the fifth transistor, and a gate of the sixth transistor. The output terminal of the third logic circuit is electrically connected to the input terminal of the fourth logic circuit, The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, The gate of the seventh transistor is electrically connected to the first input wiring, The gate of the eighth transistor is electrically connected to the second input wiring, A second terminal of the seventh transistor is electrically connected to the second wiring, And a second terminal of the eighth transistor is electrically connected to the first wiring.

5. The semiconductor device according to claim 1, The first circuit includes first to fourth transistors, a first logic circuit and a second logic circuit. The second circuit includes sixth to eighth transistors, Each of the first logic circuit and the second logic circuit has a function of outputting an inverted signal of a signal input to an input terminal from an output terminal, The first holding node is electrically connected to an input terminal of the first logic circuit, an output terminal of the second logic circuit, a first terminal of the first transistor, and a gate of the second transistor. The output terminal of the first logic circuit is electrically connected to the input terminal of the second logic circuit, The second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor, The gate of the third transistor is electrically connected to the first input wiring, The gate of the fourth transistor is electrically connected to the second input wiring, A second terminal of the third transistor is electrically connected to the first wiring, A second terminal of the fourth transistor is electrically connected to the second wiring, The second holding node is electrically connected to an input terminal of the second logic circuit, an output terminal of the first logic circuit, and a gate of the sixth transistor. The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor, The gate of the seventh transistor is electrically connected to the first input wiring, The gate of the eighth transistor is electrically connected to the second input wiring, A second terminal of the seventh transistor is electrically connected to the second wiring, And a second terminal of the eighth transistor is electrically connected to the first wiring.

6. A semiconductor device comprising a first circuit and a second circuit, in, The first circuit includes a first load circuit, The second circuit includes a second load circuit, Each of the first load circuit and the second load circuit includes a first terminal and a second terminal, Each of the first load circuit and the second load circuit has a function of changing a resistance value between a first terminal and a second terminal according to first data. The first circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The first circuit has: A function of outputting a current corresponding to the resistance value of the first load circuit to the first wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring; A function of outputting a current corresponding to the resistance value of the first load circuit to the second wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring; as well as a function of not outputting a current corresponding to the resistance value of the first load circuit to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, Furthermore, the second circuit has: when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, outputting a current corresponding to the resistance value of the second load circuit to the second wiring; A function of outputting a current corresponding to the resistance value of the second load circuit to the first wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring; as well as A function of not outputting a current corresponding to the resistance value of the second load circuit to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring.

7. The semiconductor device according to claim 6, The first circuit includes a third transistor and a fourth transistor, The second circuit includes a seventh transistor and an eighth transistor, The first terminal of the first load circuit is electrically connected to the first terminal of the third transistor and the first terminal of the fourth transistor. The gate of the third transistor is electrically connected to the first input wiring, The gate of the fourth transistor is electrically connected to the second input wiring, A second terminal of the third transistor is electrically connected to the first wiring, A second terminal of the fourth transistor is electrically connected to the second wiring, The first terminal of the second load circuit is electrically connected to the first terminal of the seventh transistor and the first terminal of the eighth transistor. The gate of the seventh transistor is electrically connected to the first input wiring, The gate of the eighth transistor is electrically connected to the second input wiring, A second terminal of the seventh transistor is electrically connected to the second wiring, And a second terminal of the eighth transistor is electrically connected to the first wiring.

8. The semiconductor device according to claim 7, wherein the first circuit comprises a first transistor, The second circuit includes a second transistor, A first terminal of the first transistor is electrically connected to a first terminal of the first load circuit, And the first terminal of the second transistor is electrically connected to the first terminal of the second load circuit.

9. The semiconductor device according to any one of claims 6 to 8, wherein the first load circuit includes any one of a variable resistor, an MTJ element, and a phase change memory, And the second load circuit includes any one of a variable resistor, an MTJ element, and a phase change memory.

10. The semiconductor device according to any one of claims 1 to 9, comprising a third circuit and a fourth circuit, wherein the third circuit has a function of inputting a potential corresponding to second data to the first input wiring and the second input wiring, respectively; The fourth circuit has a function of comparing a current flowing through the first wiring and a current flowing through the second wiring and outputting a potential corresponding to a product of the first data and the second data from an output terminal of the fourth circuit.

11. An electronic device, comprising: The semiconductor device according to any one of claims 1 to 10, The semiconductor device performs neural network calculations.

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