Driving method and driving circuit of display panel and display panel

Abstract

The invention relates to a driving method and a driving circuit of a display panel, and the display panel. The method comprises the following steps: acquiring a data voltage of a current frame; determining whether the data voltage is a first data voltage or a second data voltage according to the polarity and the gray-scale value of the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; under the condition that the data voltage is the first data voltage, writing the first data voltage into the pixel unit by using a first time sequence signal; and under the condition that the data voltage is the second data voltage, writing the second data voltage into the pixel unit by using a second time sequence signal, wherein the first time sequence signal is delayed by a preset time relative to the second time sequence signal. Through the method and the device, the technical problem that a local ghosting phenomenon still occurs during non-specific gray scale change due to the fact that a correction scheme in the prior art cannot well cover a full gray scale range is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel driving method, a driving circuit and a display panel. Background Art

[0002] The pixel unit of the LCD display panel is controlled by a thin film transistor (TFT). When the gate voltage (Vgh / Vgl) of the TFT is switched, its parasitic capacitance (Cgs), liquid crystal capacitance (Clc) and storage capacitance (Cst) form a coupling loop to generate a feed-through voltage (Vkb). The amplitude of the feed-through voltage is directly related to the capacitance values ​​of the parasitic capacitance, liquid crystal capacitance and storage capacitance. At the same time, the capacitance value of the liquid crystal capacitor is regulated by the grayscale, and the change of the grayscale will cause the capacitance value of the liquid crystal capacitor to change.

[0003] Therefore, when switching between different grayscales, the difference in feed-through voltage makes it impossible to completely reset the effective voltage between the pixel electrode and the common electrode (Vcom), forming a DC voltage bias across frames. This bias continues to act on the liquid crystal molecules, changing their arrangement state, causing the residual image to be "burned" on the screen, that is, the afterimage phenomenon occurs.

[0004] In the prior art, the grayscale reference voltage (Gamma voltage) of a specific grayscale (such as grayscale 0) is usually corrected to suppress the afterimage phenomenon. However, such a correction scheme is only for a specific grayscale and cannot cover the entire grayscale range well, resulting in the local afterimage phenomenon still occurring when non-specific grayscale changes. Summary of the invention

[0005] The present application provides a display panel driving method, a driving circuit and a display panel to solve the technical problem that the correction scheme of the prior art cannot cover the full grayscale range well, resulting in local afterimage phenomenon when non-specific grayscale changes occur.

[0006] In a first aspect, the present application provides a method for driving a display panel, the method comprising: Get the data voltage of the current frame; Determining the data voltage as a first data voltage or a second data voltage according to the polarity and grayscale value of the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; When the data voltage is the first data voltage, the first data voltage is written into the pixel unit using a first timing signal; and when the data voltage is the second data voltage, the second data voltage is written into the pixel unit using a second timing signal; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

[0007] In a feasible embodiment of the present application, determining the data voltage as the first data voltage or the second data voltage according to the polarity and the grayscale value of the data voltage includes: Determine the polarity of the data voltage, and determine the grayscale interval to which the grayscale value of the data voltage belongs; wherein the polarity of the data voltage is positive or negative, the grayscale interval is a first grayscale interval or a second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; In the case where the polarity and the grayscale value of the data voltage meet a first judgment condition, determining that the data voltage is the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

[0008] In a feasible embodiment of the present application, determining the polarity of the data voltage includes: Get the common voltage; comparing the data voltage with the common voltage; In a case where the data voltage is greater than the common voltage, determining that the polarity of the data voltage is positive; In a case where the data voltage is lower than the common voltage, the polarity of the data voltage is determined to be a negative polarity.

[0009] In a feasible embodiment of the present application, determining the grayscale interval to which the grayscale value of the data voltage belongs includes: Obtain a grayscale mapping table; wherein the grayscale mapping table includes N grayscale values ​​that increase in sequence, and N is an integer greater than 0; Determine a first boundary grayscale value and a second boundary grayscale value according to the grayscale mapping table; wherein the first boundary grayscale value is smaller than the second boundary grayscale value; When the grayscale value of the data voltage is less than the first boundary grayscale value and greater than 0, determining that the grayscale value of the data voltage belongs to the first grayscale interval; When the grayscale value of the data voltage is smaller than the maximum grayscale value in the grayscale mapping table and larger than the second boundary grayscale value, it is determined that the grayscale value of the data voltage belongs to the second grayscale interval.

[0010] In a feasible embodiment of the present application, determining the first boundary grayscale value and the second boundary grayscale value according to the grayscale mapping table includes: Determine that the nth grayscale value in the grayscale mapping table is the first boundary grayscale value; wherein n=F(N / 4), and F() is a floor rounding function; Determine that the mth grayscale value in the grayscale mapping table is the second boundary grayscale value; wherein, m=H(3N / 4), and H() is a rounding-up function.

[0011] In a second aspect, the present application provides a driving circuit of a display panel, the circuit comprising a source driving module, a comparison module and a timing control module, one end of the source driving module is connected to one end of the comparison module, and the other end of the comparison module is connected to one end of the timing control module, wherein: The source driving module is used to output the data voltage of the current frame to the comparison module; The comparison module is used to determine whether the data voltage is the first data voltage or the second data voltage according to the polarity and grayscale value of the data voltage, and output a timing control signal to the timing control module according to the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; The timing control module is used to generate the first timing signal or the second timing signal, and use the first timing signal to write the first data voltage into the pixel unit according to the timing control signal, and use the second timing signal to write the second data voltage into the pixel unit; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

[0012] In a feasible embodiment of the present application, the comparison module is used to: In the case where the polarity and the grayscale value of the data voltage meet a first judgment condition, determining that the data voltage is the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to the second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

[0013] In a feasible embodiment of the present application, the comparison module includes a comparison circuit, and the comparison circuit includes a first switch unit, a second switch unit, a first comparator, a second comparator, a third comparator and an XOR gate, wherein: The positive input terminal of the first comparator is connected to the data voltage output terminal of the source driving module, the negative input terminal of the first comparator is connected to the common electrode, and the output terminal of the first comparator is respectively connected to the first input terminal of the XOR gate, the control terminal of the first switch unit and the control terminal of the second switch unit; wherein the data voltage output terminal of the source driving module is used to output the data voltage, and the common electrode is used to output the common voltage; The inverting input terminal of the second comparator is connected to the first terminal of the first switch unit, the non-inverting input terminal of the second comparator is connected to the gamma voltage output terminal of the source driving module, the output terminal of the second comparator is connected to the second input terminal of the XOR gate, and the second terminal of the first switch unit is connected to the data voltage output terminal of the source driving module; wherein the gamma voltage output terminal of the source driving module is used to output a standard gamma voltage; The inverting input terminal of the third comparator is connected to the first terminal of the second switch unit, the non-inverting input terminal of the third comparator is connected to the gamma voltage output terminal of the source driving module, the output terminal of the third comparator is connected to the second input terminal of the XOR gate, and the second terminal of the second switch unit is connected to the data voltage output terminal of the source driving module; The output end of the XOR gate is connected to the timing control module.

[0014] In a feasible embodiment of the present application, the first switch unit includes an NMOS tube, the gate of the NMOS tube is connected to the output end of the first comparator as the control end of the first switch unit, the drain of the NMOS tube is connected to the inverting input end of the second comparator as the first end of the first switch unit, and the source of the NMOS tube is connected to the data voltage output end of the source driving module as the second end of the first switch unit; The second switch unit includes a PMOS tube, the gate of the PMOS tube serves as the control end of the second switch unit and is connected to the output end of the first comparator, the drain of the PMOS tube serves as the first end of the second switch unit and is connected to the inverting input end of the third comparator, and the source of the PMOS tube serves as the second end of the second switch unit and is connected to the data voltage output end of the source driving module.

[0015] In a third aspect, the present application provides a display panel, comprising a driving circuit for the display panel as described in any one of the embodiments of the second aspect above.

[0016] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: It is understandable that the effective voltage of the pixel unit is actually composed of two parts: the charging voltage (the voltage actually acting on the pixel unit) and the feed-through voltage. The difference in feed-through voltage under different grayscales leads to differences in the effective voltage. When the effective voltage is not consistent with the target grayscale voltage, the afterimage phenomenon occurs.

[0017] In the technical solution provided by the present application, the data voltage of the current frame is distinguished, and the data voltage is determined to be the first data voltage or the second data voltage according to the polarity and grayscale value of the data voltage, so as to judge whether the data voltage will generate an excessive feed-through voltage when written into the pixel unit. When the data voltage is the first data voltage, it is written through the first timing signal to reduce the charging time of the first data voltage to the pixel unit, thereby reducing the charging voltage and compensating for the excessive feed-through voltage; when the data voltage is the second data voltage, it is written through the second timing signal, so that the charging time of the second data voltage is relatively standard and the charging voltage will not be reduced.

[0018] It can be seen that through the technical solution provided by the present application, the charging time is changed to change the charging voltage, so that the charging voltage and the feed-through voltage form complementary cancellation at different gray scales, and finally the effective voltage at each gray scale is made as consistent as possible, thereby solving the technical problem that the correction solution of the prior art cannot cover the entire gray scale range well, resulting in the local afterimage phenomenon still occurring when non-specific gray scales change. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0022] Figure 1 A schematic diagram of a flow chart of a method for driving a display panel provided in an embodiment of the present application; Figure 2A schematic diagram of the corresponding relationship between a timing signal and a data voltage in a display panel driving method provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a driving circuit of a display panel provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a comparison circuit in a driving circuit of a display panel provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0023] Description of reference numerals: 1. Source drive module; 2. Comparison module; 3. Timing control module; 4. Comparison circuit; 41. First switch unit; 42. Second switch unit; U1. First comparator; U2. Second comparator; U3. Third comparator; U4. XOR gate; Q1. NMOS tube; Q2. PMOS tube. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0025] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0026] In order to solve the technical problem that the correction scheme of the prior art cannot cover the full grayscale range well, resulting in local afterimage phenomenon still occurring when non-specific grayscale changes occur, the present application provides a display panel driving method, driving circuit and display panel, which can eliminate the afterimage phenomenon under full grayscale.

[0027] In order to more clearly illustrate the technical solution provided by the present application, the generation principle of the afterimage phenomenon is first explained in detail.

[0028] Figure 1 A schematic diagram of a driving method of a display panel provided in an embodiment of the present application is shown in FIG. Figure 1A display panel driving method provided in an embodiment of the present application includes the following steps: S1: Get the data voltage of the current frame; Specifically, the data voltage is generated by a driver chip (Driver IC) of the display panel. The driver chip generates a corresponding data voltage according to a digital signal transmitted by a timing controller (TCON), thereby controlling the pixel unit to display.

[0029] When the display panel needs to display a frame of picture, it obtains the data voltage corresponding to the current frame from the driving chip.

[0030] S2: determining the data voltage to be a first data voltage or a second data voltage according to the polarity and grayscale value of the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; Specifically, after obtaining the data voltage of the current frame, the data voltage is classified according to the polarity and grayscale value of the data voltage, and the data voltage is identified as the first data voltage or the second data voltage. The feed-through voltage generated by the first data voltage when writing into the pixel unit is greater than the feed-through voltage generated by the second data voltage when writing into the pixel unit.

[0031] In a feasible embodiment of the present application, determining the data voltage as the first data voltage or the second data voltage according to the polarity and the grayscale value of the data voltage includes: Determine the polarity of the data voltage, and determine the grayscale interval to which the grayscale value of the data voltage belongs; wherein the polarity of the data voltage is positive polarity or negative polarity, the grayscale interval is a first grayscale interval or a second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; When the polarity and grayscale value of the data voltage meet the first judgment condition, the data voltage is determined to be the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

[0032] Specifically, since the grayscale value of the data voltage will specifically affect the value of the feed-through voltage generated when the data voltage acts on the pixel unit, and the grayscale value of the data voltage has different effects on data voltages of different polarities, the data voltage is determined as the first data voltage or the second data voltage according to the polarity and grayscale value of the data voltage, thereby determining whether the data voltage will generate a larger feed-through voltage on the pixel unit.

[0033] The polarity of the data voltage is positive or negative, the grayscale value of the data voltage belongs to the first grayscale interval or the second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval.

[0034] When the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to the second grayscale interval, it is determined that a larger feed-through voltage will be generated when the data voltage acts on the pixel unit. At this time, the data voltage is determined to be the first data voltage.

[0035] When the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval, it is determined that the data voltage will not generate a large feed-through voltage when acting on the pixel unit, and the data voltage is determined to be the second data voltage.

[0036] In a feasible embodiment of the present application, the polarity of the data voltage is determined based on the numerical relationship between the data voltage and the common voltage.

[0037] In this embodiment, a common voltage is obtained from a common electrode, and the common voltage is compared with a data voltage. When the data voltage is greater than the common voltage, the polarity of the data voltage is determined to be positive, and when the data voltage is less than the common voltage, the polarity of the data voltage is determined to be negative.

[0038] As a specific example, when the driving chip generates the data voltage, the driving chip synchronously obtains the common voltage, and compares the common voltage with the data voltage through a comparator provided in the driving chip, thereby determining the polarity of the data voltage.

[0039] In a feasible embodiment of the present application, the grayscale interval to which the grayscale value of the data voltage belongs is determined based on the relationship between the data voltage and the first boundary grayscale value and the second boundary grayscale value.

[0040] In this embodiment, a grayscale mapping table is obtained; wherein the grayscale mapping table includes N grayscale values ​​that increase in sequence, and N is an integer greater than 0; a first boundary grayscale value and a second boundary grayscale value are determined according to the grayscale mapping table; wherein the first boundary grayscale value is less than the second boundary grayscale value; when the grayscale value of the data voltage is less than the first boundary grayscale value and greater than 0, it is determined that the grayscale value of the data voltage belongs to the first grayscale interval; when the grayscale value of the data voltage is less than the maximum grayscale value in the grayscale mapping table and greater than the second boundary grayscale value, it is determined that the grayscale value of the data voltage belongs to the second grayscale interval.

[0041] Specifically, the grayscale mapping table includes N grayscale values ​​that increase in sequence, and each grayscale value corresponds to a specific gamma voltage. The first boundary grayscale value and the second boundary grayscale value are determined based on the grayscale mapping table, and the grayscale interval of the grayscale value of the data voltage is determined based on the relationship between the grayscale value of the data voltage and the first boundary grayscale value and the second boundary grayscale value.

[0042] It can be understood that, assuming that the first boundary grayscale value is gamma a, the second boundary grayscale value is gamma b, and the maximum grayscale value in the grayscale mapping table is gamma c, the first grayscale interval is actually (0, gamma a), and the second grayscale interval is actually (gamma b, gamma c).

[0043] As a specific example, a digital signal is obtained from a timing controller, and the grayscale value of the data voltage is directly identified from the digital signal. The grayscale interval of the grayscale value of the data voltage is determined through the numerical relationship between the grayscale value of the data voltage and the first boundary grayscale value and the second boundary grayscale value.

[0044] As a specific example, the amplitude of the first gamma voltage and the amplitude of the second gamma voltage are determined based on the grayscale mapping table, the first gamma voltage is the gamma voltage corresponding to the first boundary grayscale value, and the second gamma voltage is the gamma voltage corresponding to the second boundary grayscale value, and the grayscale interval in which the grayscale value of the data voltage is located is determined by comparing the amplitude of the data voltage with the amplitude of the first gamma voltage and the amplitude of the second gamma voltage.

[0045] In a feasible embodiment of the present application, it is necessary to more accurately determine the first boundary grayscale value and the second boundary grayscale value, so as to select the data voltage with a larger feed-through voltage when acting on the pixel unit as the first data voltage. In this embodiment, determining the first boundary grayscale value and the second boundary grayscale value according to the grayscale mapping table includes: Determine that the nth grayscale value in the grayscale mapping table is the first boundary grayscale value; wherein n=F(N / 4), and F() is a rounding down function; Determine the mth grayscale value in the grayscale mapping table as the second boundary grayscale value; wherein, m=H(3N / 4), and H() is a rounding-up function.

[0046] Specifically, among the N grayscale values ​​in the grayscale mapping table, usually the gamma voltages corresponding to the first N / 2 grayscale values ​​are positive polarities, and the gamma voltages corresponding to the last N / 2 grayscale values ​​are negative polarities.

[0047] The nth grayscale value is selected as the first boundary grayscale value, n=F(N / 4), F() is a rounding-down function, that is, for the data voltage of the positive polarity, the data voltage with the lower grayscale value is determined to be the first data voltage; the mth grayscale value is selected as the second boundary grayscale value, m=H(3N / 4), H() is a rounding-up function, that is, for the data voltage of the negative polarity, the data voltage with the higher grayscale value is determined to be the first data voltage.

[0048] In some actual examples, the grayscale mapping table includes 14 grayscale values ​​(gm1-gm14), then the first boundary grayscale value n=F(14 / 4)=3, gm3 is selected as the first boundary grayscale value, the second boundary grayscale value m=F(3×14 / 4)=11, and gm11 is selected as the second boundary grayscale value.

[0049] It can be understood that, generally speaking, the gamma voltage corresponding to the front grayscale value (i.e., gm0-gmN / 2) in the grayscale mapping table is a positive polarity voltage, and the gamma voltage corresponding to the rear grayscale value (i.e., gmN / 2-gmN) in the grayscale mapping table is a positive polarity voltage. Through the above embodiment, the boundary is adaptively divided according to the total length of the grayscale mapping table, and the design of panels with different resolutions is compatible, which avoids the adaptability problem caused by artificially preset parameters and improves the versatility of the solution.

[0050] Based on the above embodiments, it can be understood that the first data voltage is actually a positive polarity low grayscale data voltage and a negative polarity high grayscale data voltage, and the second data voltage is actually a positive polarity high grayscale data voltage and a negative polarity low grayscale data voltage.

[0051] S3: when the data voltage is the first data voltage, using the first timing signal to write the first data voltage into the pixel unit; and when the data voltage is the second data voltage, using the second timing signal to write the second data voltage into the pixel unit; wherein the first timing signal is delayed by a preset time relative to the second timing signal; Specifically, after determining the category of the data voltage, the data voltage is written into the pixel unit through different timing signals. When the data voltage is the first data voltage, the first timing signal is used to write the first data voltage into the pixel unit. When the data voltage is the second data voltage, the second timing signal is used to write the second data voltage into the pixel unit. The first timing signal is delayed by a preset time relative to the second timing signal.

[0052] As a specific example, the first timing signal is delayed by 0.5-2 μs relative to the second timing signal.

[0053] Figure 2 A schematic diagram of the corresponding relationship between the timing signal and the data voltage in a display panel driving method provided in an embodiment of the present application, with reference to Figure 2 When the data voltage is the first data voltage, that is, the data voltage is a data voltage of a positive polarity low gray scale (V0+) or a negative polarity high gray scale (V255-), under the control of the first timing signal, the charging time of the pixel unit by the first data voltage is obviously insufficient, which makes the charging voltage of the pixel unit smaller.

[0054] When the data voltage is the second data voltage, that is, the data voltage is a data voltage of a positive polarity high gray scale (V255+) or a negative polarity low gray scale (V0-), or the data voltage is a positive polarity middle gray scale (V64+) or a negative polarity middle gray scale (V64-), under the control of the second timing signal, the second data voltage has sufficient charging time for the pixel unit, which makes the charging voltage of the pixel unit normal.

[0055] Since the effective voltage of the pixel unit depends on the charging voltage and the feed-through voltage, when the data voltage is the first data voltage and the feed-through voltage is large, the large feed-through voltage can be compensated by reducing the charging voltage. When the data voltage is the second data voltage and the feed-through voltage is small, no compensation is required.

[0056] In this way, the effective voltages of the first data voltage and the second data voltage tend to be consistent when they are written into the pixel unit. No matter what grayscale the data voltage of the current frame is, the feed-through voltage changed by the grayscale will be compensated by the synchronously changed charging voltage, so that the effective voltages of the pixel units at each grayscale are basically consistent, thereby avoiding the generation of the afterimage phenomenon.

[0057] Through the technical solution provided in the present application, the charging time is changed to change the charging voltage, so that the charging voltage and the feed-through voltage form complementary cancellation at different gray scales, and finally the effective voltage at each gray scale is made as consistent as possible, thereby solving the technical problem that the correction solution of the prior art cannot cover the entire gray scale range well, resulting in the local afterimage phenomenon still occurring when non-specific gray scales change.

[0058] Figure 3 FIG. 1 is a schematic diagram of a structure of a driving circuit of a display panel provided in an embodiment of the present application. The embodiment of the present application also provides a driving circuit of a display panel. Figure 3 The device includes a source driving module 1, a comparison module 2 and a timing control module 3, one end of the source driving module 1 is connected to one end of the comparison module 2, and the other end of the comparison module 2 is connected to one end of the timing control module 3, wherein: The source driving module 1 is used to output the data voltage of the current frame to the comparison module 2; The comparison module 2 is used to determine whether the data voltage is the first data voltage or the second data voltage according to the polarity and grayscale value of the data voltage, and output a timing control signal to the timing control module 3 according to the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; The timing control module 3 is used to generate a first timing signal or a second timing signal, and uses the first timing signal to write the first data voltage into the pixel unit according to the timing control signal, and uses the second timing signal to write the second data voltage into the pixel unit; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

[0059] Specifically, the source driving module 1 generates a data voltage based on a digital signal, and outputs the data voltage to the comparison module 2. As a specific example, the source driving module 1 may be a drive IC in a display panel.

[0060] The comparison module 2 classifies the data voltage, determines whether the data voltage is the first data voltage or the second data voltage, and outputs a corresponding timing control signal to the timing control module 3 according to the category of the data voltage. In a feasible embodiment of the present application, when the comparison module 2 determines that the data voltage is the first data voltage, the first timing control signal is output to the timing control module 3, and when the comparison module 2 determines that the data voltage is the second data voltage, the second timing control signal is output to the timing control module 3.

[0061] Two timing signals are generated in the timing control module 3, which are the first timing signal or the second timing signal, and the first timing signal is delayed by a preset time relative to the second timing signal. The timing control module 3 selects the first timing signal or the second timing signal based on the received timing control signal, so that the first data voltage is written into the pixel unit using the first timing signal, and the second data voltage is written into the pixel unit using the second timing signal. As a specific example, the timing control module 3 can be a timing controller (TCON) in the display panel.

[0062] In a feasible embodiment of the present application, the timing control module 3 determines whether to select the first timing signal or the second timing signal through the timing control signal. When the timing control module 3 receives the first timing control signal, the data voltage is written into the pixel unit through the first timing signal, and when the timing control module 3 receives the second timing control signal, the data voltage is written into the pixel unit through the second timing signal.

[0063] Based on the above embodiments, the driving circuit provided in the embodiment of the present application is significantly different from the prior art. The driving circuit provided in the embodiment of the present application is additionally provided with a comparison module to accurately classify the data voltage and determine the data voltage as the first data voltage and the second data voltage.

[0064] At the same time, the driving circuit provided in the embodiment of the present application additionally sets a timing signal in the timing control module, and realizes the writing control of the data voltage through the first timing signal and the second timing signal, thereby completing the compensation of the effective voltage under different gray scales. Figure 4 This is a schematic diagram of the structure of a comparison circuit 4 in a display panel driving circuit provided in an embodiment of the present application, referring to Figure 4 In a feasible embodiment of the present application, the comparison module 2 includes a comparison circuit 4, and the comparison circuit 4 includes a first switch unit 41, a second switch unit 42, a first comparator U1, a second comparator U2, a third comparator U3 and an XOR gate U4, wherein: The positive input terminal of the first comparator U1 is connected to the data voltage output terminal of the source driving module 1, the negative input terminal of the first comparator U1 is connected to the common electrode, and the output terminal of the first comparator U1 is respectively connected to the first input terminal of the XOR gate U4, the control terminal of the first switch unit 41 and the control terminal of the second switch unit 42; wherein the data voltage output terminal of the source driving module 1 is used to output the data voltage, and the common electrode is used to output the common voltage; The inverting input terminal of the second comparator U2 is connected to the first terminal of the first switch unit 41, the non-inverting input terminal of the second comparator U2 is connected to the gamma voltage output terminal of the source driver module 1, the output terminal of the second comparator U2 is connected to the second input terminal of the XOR gate U4, and the second terminal of the first switch unit 41 is connected to the data voltage output terminal of the source driver module 1; wherein the gamma voltage output terminal of the source driver module 1 is used to output a standard gamma voltage; The inverting input terminal of the third comparator U3 is connected to the first terminal of the second switch unit 42, the non-inverting input terminal of the third comparator U3 is connected to the gamma voltage output terminal of the source driver module 1, the output terminal of the third comparator U3 is connected to the second input terminal of the XOR gate U4, and the second terminal of the second switch unit 42 is connected to the data voltage output terminal of the source driver module 1; The output end of the XOR gate U4 is connected to the timing control module 3 .

[0065] Specifically, the positive input terminal of the first comparator U1 is connected to the data voltage output terminal of the source driving module 1, and the negative input terminal of the first comparator U1 is connected to the common electrode. The first comparator U1 receives the data voltage through the positive input terminal and the common voltage through the negative input terminal, and outputs different output signals according to the numerical relationship between the data voltage and the common voltage.

[0066] It can be seen that the first comparator U1 realizes the judgment of the polarity of the data voltage. The common voltage is used as a reference point, and the polarity is determined in real time by the first comparator U1, simplifying the polarity recognition logic. Compared with the solution relying on digital signal analysis, this embodiment has a faster response speed and avoids misjudgment caused by signal transmission delay, ensuring the real-time and accuracy of polarity classification.

[0067] At the same time, the output end of the first comparator U1 is respectively connected to the control end of the first switch unit 41 and the control end of the second switch unit 42. The first comparator U1 changes the conduction status of the first switch unit 41 and the second switch unit 42 by outputting signals to the control end of the first switch unit 41 and the control end of the second switch unit 42, thereby controlling the working conditions of the second comparator U2 and the third comparator U3.

[0068] In a feasible embodiment of the present application, the control end of the first switch unit 41 is turned on when a high-level signal is received, and is turned off when a low-level signal is received.

[0069] As a specific example, the first switch unit 41 includes an NMOS tube Q1, the gate of the NMOS tube Q1 is connected to the output end of the first comparator U1 as the control end of the first switch unit 41, the drain of the NMOS tube Q1 is connected to the inverting input end of the second comparator U2 as the first end of the first switch unit 41, and the source of the NMOS tube Q1 is connected to the data voltage output end of the source driving module 1 as the second end of the first switch unit 41.

[0070] In other examples, the first switch unit 41 may also be a transistor, an electric control switch or the like, as long as it can be turned on when receiving a high-level signal and turned off when receiving a low-level signal.

[0071] In a feasible embodiment of the present application, the control end of the second switch unit 42 is turned on when receiving a low-level signal, and is turned off when receiving a high-level signal.

[0072] As a specific example, the second switch unit 42 includes a PMOS tube Q2, the gate of the PMOS tube Q2 is connected to the output end of the first comparator U1 as the control end of the second switch unit 42, the drain of the PMOS tube Q2 is connected to the inverting input end of the third comparator U3 as the first end of the second switch unit 42, and the source of the PMOS tube Q2 is connected to the data voltage output end of the source driver module 1 as the second end of the second switch unit 42.

[0073] In other examples, the second switch unit 42 may also be a transistor, an electric control switch or the like, as long as it can be turned on when receiving a low-level signal and turned off when receiving a high-level signal.

[0074] The inverting input terminal of the second comparator U2 is connected to the first terminal of the first switch unit 41, and the non-inverting input terminal of the second comparator U2 is connected to the gamma voltage output terminal of the source driving module 1. When the first switch unit 41 is turned on, the second comparator U2 compares the data voltage input from the inverting input terminal with the standard gamma voltage input from the non-inverting input terminal, and outputs different output signals according to the numerical relationship between the data voltage and the standard gamma voltage.

[0075] The inverting input terminal of the third comparator U3 is connected to the first terminal of the second switch unit 42, and the non-inverting input terminal of the third comparator U3 is connected to the gamma voltage output terminal of the source driving module 1. When the second switch unit 42 is turned on, the third comparator U3 compares the data voltage input from the inverting input terminal with the standard gamma voltage input from the non-inverting input terminal, and outputs different output signals according to the numerical relationship between the data voltage and the standard gamma voltage.

[0076] It can be seen that the second comparator U2 and the third comparator U3 realize the determination of the gray scale interval to which the gray scale value of the data voltage belongs.

[0077] XOR gate U4 outputs different timing control signals to the timing controller according to the output signals of the first comparator U1, the second comparator U2 and the third comparator U3. When the types of data voltages are different, different timing control signals can be output to the timing controller through XOR gate U4.

[0078] In the above embodiment, the positive polarity path is controlled by the first switch unit 41, the negative polarity path is controlled by the second switch unit 42, and the timing control signal is output by the XOR gate U4, so the hardware complexity is low and the power consumption is low. Multiple comparators work together to realize the double verification of grayscale interval and polarity, ensuring that the compensation action is triggered only under the necessary polarity and grayscale, reducing the power consumption waste caused by invalid timing adjustment.

[0079] Reference Figure 4, the data voltage is marked as Data, the common voltage is marked as Vcom, the standard gamma voltage includes a first standard gamma voltage and a second standard gamma voltage, the first standard gamma voltage is marked as gmA, the second standard gamma voltage is marked as gmB, the output signal of the first comparator U1 is marked as Sel1, the output signal of the second comparator U2 is marked as Sel2, the output signal of the third comparator U3 is marked as Sel3, and the output signal of the XOR gate U4 is marked as Sel4.

[0080] When the data voltage is a positive polarity low grayscale data voltage (i.e., the first data voltage), Data is greater than Vcom, and Data is less than gmA. At this time, Sel1 is a high level signal, so that the first switch unit 41 is turned on, the second switch unit 42 is turned off, and Sel2 is a low level signal. The XOR gate U4 outputs a high level signal to the timing controller according to Sel1 and Sel2.

[0081] When the data voltage is a positive polarity high grayscale data voltage (i.e., the second data voltage), Data is greater than Vcom, and Data is greater than gmA. At this time, Sel1 is a high level signal, so that the first switch unit 41 is turned on, the second switch unit 42 is turned off, and Sel2 is a high level signal. The XOR gate U4 outputs a low level signal to the timing controller according to Sel1 and Sel2.

[0082] When the data voltage is a negative polarity high grayscale data voltage (i.e., the first data voltage), Data is less than Vcom, and Data is greater than gmB. At this time, Sel1 is a low level signal, so that the second switch unit 42 is turned on, the first switch unit 41 is turned off, and Sel3 is a high level signal. The XOR gate U4 outputs a high level signal to the timing controller according to Sel1 and Sel2.

[0083] When the data voltage is a negative polarity low grayscale data voltage (i.e., the second data voltage), Data is less than Vcom, and Data is less than gmB. At this time, Sel1 is a low level signal, so that the second switch unit 42 is turned on, the first switch unit 41 is turned off, and Sel3 is a low level signal. The XOR gate U4 outputs a low level signal to the timing controller according to Sel1 and Sel2.

[0084] It can be seen that, through the above-mentioned comparison circuit 4, when the data voltage is the first data voltage, a high level signal is output to the timing controller, and when the data voltage is the second data voltage, a low level signal is output to the timing controller. The output signal of the comparison circuit 4 is the timing control signal, and the timing control signal is divided into the first timing control signal and the second timing control signal based on the level.

[0085] Based on the above circuit embodiment, the data voltage is identified by the comparison module 2 set between the source driving module 1 and the timing control module 3, and the data voltage is determined to be the first data voltage or the second data voltage based on a simple hardware circuit, so that the effective voltage is compensated based on the different categories of data voltage, and the afterimage phenomenon is eliminated in a more convenient way.

[0086] Figure 5 A schematic diagram of a display panel provided in an embodiment of the present application. The embodiment of the present application also provides a display panel, referring to Figure 5 A display panel provided in an embodiment of the present application includes a display area and a non-display area, the non-display area is arranged around the display area, and the driving circuit is arranged in the non-display area.

[0087] In another embodiment, a control board and a chip-on-film are also included, the control board is connected to the non-display area of ​​the display panel through the chip-on-film, the drive circuit of the display panel is arranged on the control board and the chip-on-film, and the display panel includes a drive circuit as described in any of the above circuit embodiments. It should be understood that the terms used in the text are only for the purpose of describing specific example embodiments and are not intended to be limited. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "said" as used in the text may also be expressed as including plural forms. The terms "include", "include", "contain" and "have" are inclusive and therefore indicate the existence of the stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described in the text are not interpreted as requiring them to be performed in the specific order described or illustrated unless the execution order is clearly indicated. It should also be understood that additional or alternative steps can be used.

[0088] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A method for driving a display panel, characterized in that: The method comprises: Get the data voltage of the current frame; Determining the data voltage as a first data voltage or a second data voltage according to the polarity and grayscale value of the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; When the data voltage is the first data voltage, the first data voltage is written into the pixel unit using a first timing signal; and when the data voltage is the second data voltage, the second data voltage is written into the pixel unit using a second timing signal; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

2. The method according to claim 1, characterized in that Determining the data voltage as a first data voltage or a second data voltage according to the polarity and the grayscale value of the data voltage includes: Determine the polarity of the data voltage, and determine the grayscale interval to which the grayscale value of the data voltage belongs; wherein the polarity of the data voltage is positive or negative, the grayscale interval is a first grayscale interval or a second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; In the case where the polarity and the grayscale value of the data voltage meet a first judgment condition, determining that the data voltage is the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

3. The method according to claim 2, characterized in that Determining the polarity of the data voltage includes: Get the common voltage; comparing the data voltage with the common voltage; In a case where the data voltage is greater than the common voltage, determining that the polarity of the data voltage is positive; In a case where the data voltage is lower than the common voltage, the polarity of the data voltage is determined to be a negative polarity.

4. The method according to claim 2, characterized in that: Determining the grayscale interval to which the grayscale value of the data voltage belongs includes: Obtain a grayscale mapping table; wherein the grayscale mapping table includes N grayscale values ​​that increase in sequence, and N is an integer greater than 0; Determine a first boundary grayscale value and a second boundary grayscale value according to the grayscale mapping table; wherein the first boundary grayscale value is smaller than the second boundary grayscale value; When the grayscale value of the data voltage is less than the first boundary grayscale value and greater than 0, determining that the grayscale value of the data voltage belongs to the first grayscale interval; When the grayscale value of the data voltage is smaller than the maximum grayscale value in the grayscale mapping table and larger than the second boundary grayscale value, it is determined that the grayscale value of the data voltage belongs to the second grayscale interval.

5. The method according to claim 4, characterized in that Determining a first boundary grayscale value and a second boundary grayscale value according to the grayscale mapping table includes: Determine that the nth grayscale value in the grayscale mapping table is the first boundary grayscale value; wherein n=F(N / 4), and F() is a floor rounding function; Determine that the mth grayscale value in the grayscale mapping table is the second boundary grayscale value; wherein, m=H(3N / 4), and H() is a rounding-up function.

6. A driving circuit for a display panel, characterized in that: The circuit includes a source driving module, a comparison module and a timing control module, one end of the source driving module is connected to one end of the comparison module, and the other end of the comparison module is connected to one end of the timing control module, wherein: The source driving module is used to output the data voltage of the current frame to the comparison module; The comparison module is used to determine whether the data voltage is the first data voltage or the second data voltage according to the polarity and grayscale value of the data voltage, and output a timing control signal to the timing control module according to the data voltage; wherein the feed-through voltage generated when the first data voltage is written into the pixel unit is greater than the feed-through voltage generated when the second data voltage is written into the pixel unit; The timing control module is used to generate the first timing signal or the second timing signal, and use the first timing signal to write the first data voltage into the pixel unit according to the timing control signal, and use the second timing signal to write the second data voltage into the pixel unit; wherein the first timing signal is delayed by a preset time relative to the second timing signal.

7. The circuit according to claim 6, characterized in that The comparison module is used for: In the case where the polarity and the grayscale value of the data voltage meet a first judgment condition, determining that the data voltage is the first data voltage; wherein the first judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage belongs to a first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage belongs to a second grayscale interval, and the grayscale values ​​in the first grayscale interval are all smaller than the grayscale values ​​in the second grayscale interval; When the polarity and grayscale value of the data voltage meet the second judgment condition, the data voltage is determined to be the second data voltage; wherein the second judgment condition is that the polarity of the data voltage is positive and the grayscale value of the data voltage does not belong to the first grayscale interval, or the polarity of the data voltage is negative and the grayscale value of the data voltage does not belong to the second grayscale interval.

8. The circuit according to claim 6, characterized in that The comparison module includes a comparison circuit, and the comparison circuit includes a first switch unit, a second switch unit, a first comparator, a second comparator, a third comparator and an XOR gate, wherein: The positive input terminal of the first comparator is connected to the data voltage output terminal of the source driving module, the negative input terminal of the first comparator is connected to the common electrode, and the output terminal of the first comparator is respectively connected to the first input terminal of the XOR gate, the control terminal of the first switch unit and the control terminal of the second switch unit; wherein the data voltage output terminal of the source driving module is used to output the data voltage, and the common electrode is used to output the common voltage; The inverting input terminal of the second comparator is connected to the first terminal of the first switch unit, the non-inverting input terminal of the second comparator is connected to the gamma voltage output terminal of the source driving module, the output terminal of the second comparator is connected to the second input terminal of the XOR gate, and the second terminal of the first switch unit is connected to the data voltage output terminal of the source driving module; wherein the gamma voltage output terminal of the source driving module is used to output a standard gamma voltage; The inverting input terminal of the third comparator is connected to the first terminal of the second switch unit, the non-inverting input terminal of the third comparator is connected to the gamma voltage output terminal of the source driving module, the output terminal of the third comparator is connected to the second input terminal of the XOR gate, and the second terminal of the second switch unit is connected to the data voltage output terminal of the source driving module; The output end of the XOR gate is connected to the timing control module.

9. The circuit according to claim 8, characterized in that: The first switch unit includes an NMOS tube, the gate of the NMOS tube is connected to the output end of the first comparator as the control end of the first switch unit, the drain of the NMOS tube is connected to the inverting input end of the second comparator as the first end of the first switch unit, and the source of the NMOS tube is connected to the data voltage output end of the source driving module as the second end of the first switch unit; The second switch unit includes a PMOS tube, the gate of the PMOS tube serves as the control end of the second switch unit and is connected to the output end of the first comparator, the drain of the PMOS tube serves as the first end of the second switch unit and is connected to the inverting input end of the third comparator, and the source of the PMOS tube serves as the second end of the second switch unit and is connected to the data voltage output end of the source driving module.

10. A display panel, comprising a display area and a non-display area, wherein the non-display area is arranged around the display area, and a driving circuit of the display panel is arranged on the non-display area of ​​the display panel, characterized in that: The driving circuit of the display panel includes the driving circuit as described in any one of claims 6 to 9.

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