Method for improving wafer warping, semiconductor structure and preparation method thereof

Abstract

The invention provides a method for improving wafer warping, a semiconductor structure and a preparation method of the semiconductor structure. The method comprises the following steps: providing a wafer, wherein the wafer comprises a front surface and a back surface opposite to the front surface; an oxide layer is formed on the back face of the wafer, a nitride layer is formed on the surface, away from the wafer, of the oxide layer, and the oxide layer and the nitride layer jointly form a protection layer; forming a stress adjusting layer on the surface, away from the wafer, of the protective layer, wherein the thermal expansion coefficient of the stress adjusting layer is smaller than that of the wafer; and growing an epitaxial layer on the front surface of the wafer. According to the method, the upward warping phenomenon of the edge of the wafer can be improved, the structure of the wafer can be stabilized, and the interference of residual stress on a subsequent semiconductor process is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for improving wafer warpage, a semiconductor structure and a preparation method thereof. Background Art

[0002] As the number of semiconductor processes increases, more and more substrates or different front-layer steps are involved. Especially in the epitaxial growth (EPI) stage, during some fast-heating semiconductor processes (such as rapid thermal annealing processes), the thermal stress of some structures is not evenly released, which can easily cause the edge of the wafer to warp upward.

[0003] Wafer warpage can have a series of adverse effects on semiconductor manufacturing processes. For example, in the rapid thermal processing (RTP) process, a high-speed rotating wafer may fall out of the process pocket due to severe warpage, causing the wafer to break or the equipment to sound an alarm, affecting the normal progress of the semiconductor process.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0005] Based on this, the embodiments of the present application provide a method for improving wafer warping, a semiconductor structure and a preparation method thereof, which can improve the upward warping phenomenon of the wafer edge, help stabilize the structure of the wafer, and avoid residual stress from interfering with subsequent semiconductor processes.

[0006] According to some embodiments, the present application provides a method for improving wafer warpage, comprising:

[0007] Providing a wafer, the wafer comprising a front side and a back side opposite to the front side;

[0008] forming an oxide layer on the back side of the wafer, and forming a nitride layer on the surface of the oxide layer away from the wafer, wherein the oxide layer and the nitride layer together constitute a protective layer;

[0009] forming a stress adjustment layer on a surface of the protective layer away from the wafer, wherein the thermal expansion coefficient of the stress adjustment layer is smaller than the thermal expansion coefficient of the wafer;

[0010] An epitaxial layer is grown on the front side of the wafer.

[0011] In some embodiments, forming a stress adjustment layer on a surface of the protective layer away from the wafer includes:

[0012] forming a stress regulating material layer on the front side of the wafer and on the surface of the protective layer away from the wafer;

[0013] The stress adjustment material layer located on the front side of the wafer is removed, and the stress adjustment material layer located on the protective layer away from the wafer surface is retained as a stress adjustment layer.

[0014] In some embodiments, the thickness of the oxide layer ranges from

[0015] In some embodiments, the oxide layer is formed on the back side of the wafer using a low pressure chemical vapor deposition process.

[0016] In some embodiments, the thickness of the nitride layer ranges from

[0017] In some embodiments, the stress regulation layer includes a polysilicon layer.

[0018] In some embodiments, the thickness of the polysilicon layer ranges from

[0019] In some embodiments, the epitaxial layer has a thickness ranging from 14 μm to 16 μm.

[0020] According to some embodiments, the present application also provides a method for preparing a semiconductor structure, comprising the steps of the method for improving wafer warpage provided in any of the aforementioned embodiments.

[0021] According to some embodiments, the present application further provides a semiconductor structure, which is prepared using the semiconductor structure preparation method provided by the aforementioned embodiment.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

[0023] The embodiments of the present application may or at least have the following advantages:

[0024] The embodiment of the present application forms a protective layer on the back side of the wafer and adds a multilayer structure of a stress adjustment layer on the surface of the protective layer. Since the thermal expansion coefficient of the stress adjustment layer is smaller than the thermal expansion coefficient of the wafer, the thermal expansion coefficient distribution of the wafer is improved, especially in the high temperature environment of the epitaxial layer growth. It can significantly alleviate the uneven thermal expansion caused by the epitaxial layer growth and improve the upward warping phenomenon of the wafer edge, which is beneficial to stabilize the structure of the wafer and avoid residual stress from interfering with subsequent semiconductor processes.

[0025] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0027] Figure 1 A schematic flow chart of a method for improving wafer warpage provided in some embodiments of the present application;

[0028] Figure 2 A schematic diagram of a process for forming a stress adjustment layer in a method for improving wafer warpage provided in some embodiments of the present application;

[0029] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained after forming a protective layer in a method for improving wafer warpage provided in some embodiments of the present application;

[0030] Figure 4 A schematic diagram of a cross-sectional structure of a structure obtained after forming a stress adjustment material layer in a method for improving wafer warpage provided in some embodiments of the present application;

[0031] Figure 5 A schematic diagram of a cross-sectional structure of a structure obtained after a stress adjustment layer is formed in a method for improving wafer warpage provided in some embodiments of the present application;

[0032] Figure 6 A schematic diagram of the cross-sectional structure of a structure obtained after growing an epitaxial layer in a method for improving wafer warpage provided in some embodiments of the present application.

[0033] Description of reference numerals:

[0034] 110 , wafer; 120 , protective layer; 121 , oxide layer; 122 , nitride layer; 130 , stress adjustment layer; 130 ′, stress adjustment material layer; 140 , epitaxial layer. DETAILED DESCRIPTION

[0035] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show the structures related to the present application and are not drawn according to the number, shape and size of the structures in actual implementation, the type, quantity and proportion of each structure in actual implementation may be changed arbitrarily, and its structural layout may also be more complicated.

[0039] As more and more semiconductor processes are involved, more and more substrates or different front-layer steps are involved. Especially in the epitaxial growth (EPI) stage, in some semiconductor processes with rapid temperature rise (such as rapid thermal annealing process), the thermal stress of some structures is released unevenly, which can easily cause the edge of the wafer to warp upward. Wafer warping will have a series of adverse effects on the semiconductor process. For example, in the rapid thermal processing (RTP) process, the high-speed rotating wafer may fall out of the process tank (Pocke t) due to severe warping, causing the wafer to break or the equipment to sound an alarm, affecting the normal progress of the semiconductor process.

[0040] Based on this, the present application hopes to provide a solution that can solve the above technical problems, improve the upward warping phenomenon of the wafer edge, help stabilize the structure of the wafer, and avoid residual stress from interfering with subsequent semiconductor processes. The details will be described in the subsequent embodiments.

[0041] See also Figure 1 The present application provides a method for improving wafer warpage, comprising the following steps S100 to S400:

[0042] S100: providing a wafer, wherein the wafer comprises a front side and a back side opposite to the front side.

[0043] S200: forming an oxide layer on the back side of the wafer, and forming a nitride layer on the surface of the oxide layer away from the wafer, the oxide layer and the nitride layer together forming a protective layer.

[0044] S300: forming a stress adjustment layer on a surface of the protection layer away from the wafer, wherein the thermal expansion coefficient of the stress adjustment layer is smaller than the thermal expansion coefficient of the wafer.

[0045] S400: growing an epitaxial layer on the front side of the wafer.

[0046] The embodiment of the present application forms a protective layer on the back side of the wafer and adds a multilayer structure of a stress adjustment layer on the surface of the protective layer. Since the thermal expansion coefficient of the stress adjustment layer is smaller than the thermal expansion coefficient of the wafer, the thermal expansion coefficient distribution of the wafer is improved, especially in the high temperature environment of the epitaxial layer growth. It can significantly alleviate the uneven thermal expansion caused by the epitaxial layer growth and improve the upward warping phenomenon of the wafer edge, which is beneficial to stabilize the structure of the wafer and avoid residual stress from interfering with subsequent semiconductor processes.

[0047] In the present application, the protective layer and the stress adjustment layer are sequentially stacked on the back of the wafer, and the two can together constitute a wafer back seal structure. The present application suppresses the upward warping of the wafer edge during the growth of the epitaxial layer by reasonably configuring the wafer back seal structure, thereby greatly improving the situation in which the wafer edge warps upward due to rapid heating in the subsequent process.

[0048] In step S300, a stress adjustment layer is formed on the surface of the protective layer away from the wafer, which can be specifically performed as follows: Figure 2 Steps S310 to S320 shown:

[0049] S310: forming a stress adjustment material layer on the front side of the wafer and on the surface of the protection layer away from the wafer.

[0050] S320: removing the stress adjustment material layer located on the front side of the wafer, and retaining the stress adjustment material layer located on the protective layer away from the wafer surface as the stress adjustment layer.

[0051] The following combination Figures 3 to 6 The method for improving wafer warpage provided in an embodiment of the present application is described in detail.

[0052] In step S100, refer to Figure 3 , a wafer 110 is provided, and the wafer 110 includes a front side and a back side opposite to the front side.

[0053] In step S200, please continue to refer to Figure 3 An oxide layer 121 is formed on the back side of the wafer 110 , and a nitride layer 122 is formed on the surface of the oxide layer 121 away from the wafer 110 . The oxide layer 121 and the nitride layer 122 together constitute a protective layer 120 .

[0054] The oxide layer 121 is a back sealing material layer that is relatively easy to grow and is used to provide good protection for the back side of the wafer 110 . The preparation process is simple and easy to implement.

[0055] At the same time, considering that the oxide layer 121 alone is not sufficient to resist the acidic substances that may be used in the subsequent cleaning process, the embodiment of the present application forms a nitride layer 122 on the surface of the oxide layer 121 away from the wafer 110 to provide additional protection to prevent the oxide layer 121 from being excessively corroded by the acidic substances during the subsequent cleaning process, resulting in thinning or damage. As a result, the nitride layer 122 can serve as a barrier for self-diffusion, inhibiting the diffusion of doped ions in the wafer 110 to the epitaxial layer 140, and helping to maintain the resistivity of the epitaxial layer stable.

[0056] For example, when the wafer 110 is used in the process of transient voltage suppression (TVS) devices, the substrate in the wafer 110 usually has a high doping concentration, such as a highly doped substrate with a resistivity of 0.001Ω·m to 0.005Ω·m. The highly doped substrate is prone to self-diffusion during high-temperature epitaxial growth, which has an adverse effect on the purity and structural stability of the epitaxial layer 140. With the above embodiment, the oxide layer 121 and the nitride layer 122 together constitute the protective layer 120, which can inhibit the self-diffusion of the highly doped substrate, thereby maintaining the purity and structural stability of the epitaxial layer 140, which is conducive to ensuring the good electrical performance (such as low resistivity) of the TVS device in a high voltage environment.

[0057] As an example, the thickness range of the oxide layer 121 may include For example, the thickness of the oxide layer 121 may be or And so on, but not limited to these.

[0058] The embodiment of the present application does not specifically limit the method for forming the oxide layer 121 on the back side of the wafer 110. For example, the oxide layer 121 can be formed on the back side of the wafer 110 using a low pressure chemical vapor deposition (LPCVD) process. The use of the LPCVD process can provide an oxide layer 121 with better film uniformity and higher quality, which is conducive to improving production yield.

[0059] The oxide layer 121 may include but is not limited to a silicon oxide layer. As an example, tetraethoxysilane (TEOS) may be used as a silicon source to react with oxygen under low pressure conditions to form the aforementioned silicon oxide layer. This process has good step selectivity and excellent oxide film quality.

[0060] As an example, the thickness range of the nitride layer 122 may include For example, the thickness of the nitride layer 122 may be or And so on, but not limited to these.

[0061] It is worth noting that the above The thickness range is based on comprehensive consideration of material properties and device performance. A too thin nitride layer 122 may not provide sufficient barrier, causing doping ions in the wafer 110 to diffuse into the epitaxial layer 140; while a too thick nitride layer 122 may introduce additional interface defects, affecting the electrical performance of the semiconductor device.

[0062] In the actual semiconductor manufacturing process, the thickness of the nitride layer 122 also needs to be compatible with other process steps. The thickness range of the nitride layer 122 can be well matched with other related deposition processes (such as chemical vapor deposition processes), and there is no need to make large-scale modifications to the original process flow and equipment for the nitride layer 122.

[0063] In addition, the thickness of the oxide layer 121 is controlled within The thickness of the nitride layer 122 is controlled between Compared with the conventional back seal structure, the thickness of the protective layer 120 in the above embodiment is relatively small. Thus, when a stress adjustment layer is subsequently formed on the surface of the protective layer away from the wafer, the overall thickness of the wafer back seal structure will not increase.

[0064] In step S300, refer to Figures 4 to 5 A stress adjustment layer 130 is formed on a surface of the protection layer 120 away from the wafer 110 , and the thermal expansion coefficient of the stress adjustment layer 130 is smaller than the thermal expansion coefficient of the wafer 110 .

[0065] In some embodiments, the stress adjustment layer 130 may specifically include a polysilicon (Poly) layer, but is not limited thereto. The polysilicon layer is used as the stress adjustment layer 130, and its thermal expansion coefficient is lower than that of most wafer materials (such as silicon). It plays a regulating role, and can effectively suppress the influence of the expansion of the protective layer 120 on the wafer 110 during the subsequent epitaxial growth process, thereby further reducing the warping tendency of the wafer 110. Polysilicon has good resistance to thermal expansion and is particularly suitable for warping control under high temperature conditions.

[0066] As an example, the thickness range of the stress adjustment layer 130 may include For example, the thickness of the stress adjustment layer 130 may be or By controlling the thickness of the stress adjustment layer 130 to to In this way, the stress adjustment effect can be ensured while increasing the process difficulty caused by excessive material thickness, thereby ensuring the controllability of the process flow and the flatness of the surface of the wafer 110.

[0067] In some embodiments, the thickness of the oxide layer 121 can be controlled to be The thickness of the nitride layer 122 is controlled between At the same time, the thickness of the stress adjustment layer 130 is controlled between By coordinating the thickness of the oxide layer 121 and the nitride layer 122 with the thickness of the stress adjustment layer 130, a reasonable layer thickness ratio is provided to form a comprehensive stress adjustment mechanism. While ensuring that the oxide layer 121 and the nitride layer 122 can achieve a good protection effect, the stress adjustment layer 130 can provide an appropriate stress adjustment effect. In this way, not only can the overall stress state of the wafer 110 be effectively improved, but also the production yield and use reliability of semiconductor devices can be ensured.

[0068] In some embodiments, step S300 forms a stress adjustment layer 130 on a surface of the protection layer 120 away from the wafer 110 , which may be specifically performed as follows: steps S310 - S320 :

[0069] In step S310, Figure 4 As shown, a stress adjustment material layer 130 ′ is formed on the front surface of the wafer 110 and the surface of the protection layer 120 away from the wafer 110 .

[0070] In step S320, Figure 5 As shown, the stress adjustment material layer 130 ′ located on the front side of the wafer 110 is removed, and the stress adjustment material layer 130 ′ located on the protective layer 120 away from the surface of the wafer 110 is retained as the stress adjustment layer 130 .

[0071] The stress adjustment layer 130 is formed by adopting the above steps S310 to S320. Only one deposition process is required to complete the initial formation of the stress adjustment layer 130 (ie, to form the stress adjustment material layer 130'). This method can effectively simplify the process flow, reduce equipment and time costs, and improve process efficiency.

[0072] In the above embodiment, the stress adjustment material layer 130' covers both the front and back sides of the wafer 110 during deposition, thereby reducing the problem of uneven local stress that may be caused by depositing the stress layer on only one side. After the stress adjustment material layer 130' is deposited on both the front and back sides of the wafer 110 and then the front side portion is removed, it can be ensured that the stress adjustment layer 130 retained on the back side of the wafer 110 has uniform thickness and material properties, thereby being able to better adjust the stress distribution of the wafer back seal structure, reduce the possibility of deformation of the wafer 110, and achieve a more ideal anti-warping effect.

[0073] In step S400, refer to Figure 6 , an epitaxial layer 140 is grown on the front side of the wafer 110 .

[0074] As an example, the thickness of the epitaxial layer 140 can be controlled between 14 μm and 16 μm. For example, the thickness of the epitaxial layer 140 can be 14 μm, 15 μm or 16 μm, etc., so as to reduce the impact of the epitaxial layer 140 on the overall stress of the wafer 110, and further reduce the warping tendency of the wafer 110, thereby ensuring the stability and adaptability of the wafer 110 in subsequent processes.

[0075] According to some embodiments, the present application also provides a method for preparing a semiconductor structure, including the steps of the method for improving wafer warpage provided in any of the above embodiments. It can be understood that the technical effects that can be achieved by the above method for improving wafer warpage can also be achieved by the method for preparing the semiconductor structure, and will not be described in detail here.

[0076] According to some embodiments, the present application further provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure provided in the above embodiments. It can be understood that the technical effects that can be achieved by the method for preparing the above semiconductor structure can also be achieved by the semiconductor structure, which will not be described in detail here.

[0077] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for improving wafer warpage, characterized in that: include: Providing a wafer, the wafer comprising a front side and a back side opposite to the front side; forming an oxide layer on the back side of the wafer, and forming a nitride layer on the surface of the oxide layer away from the wafer, wherein the oxide layer and the nitride layer together constitute a protective layer; forming a stress adjustment layer on a surface of the protective layer away from the wafer, wherein the thermal expansion coefficient of the stress adjustment layer is smaller than the thermal expansion coefficient of the wafer; An epitaxial layer is grown on the front side of the wafer.

2. The method for improving wafer warpage according to claim 1, characterized in that: The step of forming a stress adjustment layer on a surface of the protective layer away from the wafer comprises: forming a stress regulating material layer on the front side of the wafer and on the surface of the protective layer away from the wafer; The stress adjustment material layer located on the front side of the wafer is removed, and the stress adjustment material layer located on the protective layer away from the wafer surface is retained as a stress adjustment layer.

3. The method for improving wafer warpage according to claim 1, characterized in that: The thickness range of the oxide layer includes 4. The method for improving wafer warpage according to claim 3, characterized in that: The oxide layer is formed on the back side of the wafer by using a low pressure chemical vapor deposition process.

5. The method for improving wafer warpage according to claim 1, characterized in that: The thickness range of the nitride layer includes 6. The method for improving wafer warpage according to claim 1, characterized in that: The stress adjustment layer includes a polysilicon layer.

7. The method for improving wafer warpage according to claim 6, characterized in that: The thickness range of the polysilicon layer includes 8. The method for improving wafer warpage according to claim 1, characterized in that: The thickness of the epitaxial layer ranges from 14 μm to 16 μm.

9. A method for preparing a semiconductor structure, characterized in that: The method comprises the steps of the method for improving wafer warpage according to any one of claims 1 to 8.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to claim 9.

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