Method for improving thickness uniformity of ion implantation protection layer

Abstract

The invention provides a method for improving the thickness uniformity of an ion implantation protection layer, which comprises the following steps of: providing a substrate, forming a deep groove on a cellular region on the substrate, forming a first gate dielectric layer and a source polycrystalline silicon layer at the bottom of the deep groove, forming an isolation dielectric layer on the first gate dielectric layer and the source polycrystalline silicon layer, and forming a second gate dielectric layer on the isolation dielectric layer, a second gate dielectric layer and a third gate dielectric layer with different thicknesses are formed on the trenches with different depths and the mesa structures on the two sides of the trenches; forming a gate polycrystalline silicon layer for filling the residual deep trench; forming a fourth dielectric layer covering the gate polycrystalline silicon layer, the second gate dielectric layer and the third gate dielectric layer, and performing back etching on the fourth dielectric layer to enable the total thickness of the dielectric layers at all positions on the mesa structure to be a target value; a body region and a source region are formed through ion implantation, and the dielectric layer on the mesa structure serves as an ion implantation protection layer. According to the invention, the thickness of the ion implantation protection layer before ion implantation is uniform, the subsequent implantation depth uniformity is prevented from being greatly influenced, and the convergence of various performance parameters of the product is better.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving the thickness uniformity of an ion implantation protection layer. Background Art

[0002] As one of the main power semiconductor devices, power MOSFET is widely used in communications, computers, automobiles and consumer electronics, and is an important component of discrete devices and intelligent power integrated circuits.

[0003] A power MOS trench gate product forms two gate dielectric layers of different thickness in the cell region. The thinner gate dielectric layer region can discharge charges quickly to achieve a higher frequency application environment.

[0004] The prior art process after forming two gate dielectric layers of different thicknesses includes:

[0005] Step 1, providing a substrate 101, forming a deep trench on the cell region on the substrate 101, forming a first gate dielectric layer 102 and a source polysilicon layer 103 at the bottom of the deep trench, forming an isolation dielectric layer on the first gate dielectric layer 102 and the source polysilicon layer 103, forming a second and third gate dielectric layers (105, 104) of different thicknesses on different deep trenches and mesa structures on both sides thereof, the thinner gate dielectric layer region can quickly discharge charge to achieve a higher frequency application environment, forming a Figure 1 The structure shown;

[0006] Step 2: forming a gate polysilicon layer 106 filling the remaining deep trenches, forming Figure 2 The structure shown;

[0007] Step 3: Please refer to Figure 3 The body region and the source region are formed by ion implantation. Since the thickness of the second and third gate dielectric layers on the mesa structure are inconsistent, the subsequent implantation depth uniformity is greatly affected.

[0008] In order to solve the above problems, it is necessary to propose a new method for improving the thickness uniformity of the ion implantation protection layer. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for improving the uniformity of the thickness of the ion implantation protection layer, so as to solve the problem in the prior art that the thickness of the gate dielectric layer on the mesa structure is inconsistent, which has a great impact on the uniformity of the subsequent implantation depth.

[0010] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving the thickness uniformity of an ion implantation protection layer, comprising:

[0011] Step 1, providing a substrate, forming a deep trench on a cell region on the substrate, forming a first gate dielectric layer and a source polysilicon layer at the bottom of the deep trench, forming an isolation dielectric layer on the first gate dielectric layer and the source polysilicon layer, and forming a second and a third gate dielectric layer with different thicknesses on different deep trenches and mesa structures on both sides thereof;

[0012] Step 2: forming a gate polysilicon layer filling the remaining deep trench;

[0013] Step 3, forming a fourth dielectric layer covering the gate polysilicon layer, the second and third gate dielectric layers, and etching back the fourth dielectric layer so that the total thickness of the dielectric layer at each location on the mesa structure is the target value;

[0014] Step 4: forming a body region and a source region by ion implantation, and the dielectric layer on the mesa structure serves as an ion implantation protection layer.

[0015] Preferably, in step one, the deep trench is formed by photolithography and etching.

[0016] Preferably, the material of the first gate dielectric layer in step 1 is oxide or silicon nitride.

[0017] Preferably, the material of the second and third gate dielectric layers and the isolation dielectric layer in step 1 is oxide.

[0018] Preferably, the method for forming the gate polysilicon layer in step 2 includes: depositing the gate polysilicon layer; grinding the gate polysilicon layer to a first preset height, wherein the height of the second gate dielectric layer is lower than the height of the third gate dielectric layer, and the first preset height is not lower than the height of the third gate dielectric layer; etching the gate polysilicon layer to a third preset height, and the second preset height is not higher than the height of the second gate dielectric layer.

[0019] Preferably, the grinding method in step 2 is chemical mechanical planarization grinding.

[0020] Preferably, the material of the fourth dielectric layer in step three is oxide.

[0021] Preferably, in step three, the fourth dielectric layer is formed by thermal oxidation.

[0022] Preferably, the thickness of the fourth dielectric layer in step three is greater than 800 angstroms.

[0023] As described above, the method of improving the thickness uniformity of the ion implantation protection layer of the present invention has the following beneficial effects:

[0024] The present invention realizes the uniformity of the thickness of the ion implantation protection layer before ion implantation, avoids a significant impact on the uniformity of the subsequent implantation depth, and makes the convergence of various performance parameters of the product better. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram showing the formation of the second and third gate dielectric layers with different thicknesses in the prior art;

[0026] Figure 2 A schematic diagram of forming a gate polysilicon layer in the prior art is shown;

[0027] Figure 3 Shown is a schematic diagram of ion implantation in the prior art;

[0028] Figure 4 Shown is a schematic diagram of the process flow of the present invention;

[0029] Figure 5 It is a schematic diagram showing the formation of the second and third gate dielectric layers with different thicknesses according to the present invention;

[0030] Figure 6 It is a schematic diagram of forming a gate polysilicon layer according to the present invention;

[0031] Figure 7 It is a schematic diagram showing the formation of a fourth dielectric layer according to the present invention;

[0032] Figure 8 It is a schematic diagram of etching back the fourth dielectric layer of the present invention;

[0033] Fig. 9 Shown is a schematic diagram of ion implantation according to the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figure 4 The present invention provides a method for improving the thickness uniformity of an ion implantation protection layer, comprising:

[0036] Step 1: Provide a substrate 201, form a deep trench on the cell region on the substrate 201, form a first gate dielectric layer 202 and a source polysilicon layer 203 at the bottom of the deep trench, form an isolation dielectric layer on the first gate dielectric layer 202 and the source polysilicon layer 203, and form a second and third gate dielectric layers of different thicknesses on different deep trenches and the mesa structures on both sides thereof. The thinner gate dielectric layer region can quickly discharge charges to achieve a higher frequency application environment, forming a Figure 5 The structure shown;

[0037] In some embodiments, in step 1, the deep trench is formed by photolithography and etching, and the etching method is dry etching.

[0038] In some embodiments, the materials of the second and third gate dielectric layers and the isolation dielectric layer in step 1 are oxides.

[0039] In some embodiments, the material of the first gate dielectric layer in step 1 is silicon nitride or silicon dioxide.

[0040] Step 2: forming a gate polysilicon layer 206 filling the remaining deep trenches, forming Figure 6 The structure shown;

[0041] In some embodiments, the method for forming the gate polysilicon layer 206 in step two includes: depositing the gate polysilicon layer 206; grinding the gate polysilicon layer 206 to a first preset height, the height of the second gate dielectric layer 205 is lower than the height of the third gate dielectric layer 204, and the first preset height is not lower than the height of the third gate dielectric layer 204; etching the gate polysilicon layer 206 to a second preset height, the etching method is dry etching or wet etching, and the second preset height is not higher than the height of the second gate dielectric layer 205.

[0042] In some embodiments, the polishing method in step 2 is chemical mechanical planarization polishing.

[0043] Step 3: forming a fourth dielectric layer 207 covering the gate polysilicon layer 206, the second and third gate dielectric layers, Figure 7 The structure shown in FIG. 1 is formed by etching back the fourth dielectric layer 207. The etching back method is dry etching or wet etching, so that the total thickness of the dielectric layer at each location on the mesa structure is the target value, forming a structure as shown in FIG. Figure 8 The structure shown;

[0044] In some embodiments, the material of the fourth dielectric layer 207 in step three is oxide.

[0045] In some embodiments, in step three, the fourth dielectric layer 207 is formed by thermal oxidation, so that the second and third gate dielectric layers, which originally have two thicknesses, have uniform thicknesses after thermal oxidation.

[0046] In some embodiments, the thickness of the fourth dielectric layer 207 in step three is greater than 800 angstroms.

[0047] Step 4: Please refer to Fig. 9 Ion implantation is used to form the body region and source region, and the dielectric layer on the table structure is used as an ion implantation protection layer, which achieves the uniformity of the ion implantation protection layer thickness before implantation, avoids a significant impact on the subsequent implantation depth uniformity, and makes the product's performance parameters more convergent.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] In summary, the present invention achieves uniform thickness of the ion implantation protection layer before ion implantation, avoids a significant impact on the uniformity of subsequent implantation depth, and makes the product's performance parameters more convergent. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the thickness uniformity of an ion implantation protective layer, characterized in that: At least: Step 1, providing a substrate, forming a deep trench on a cell region on the substrate, forming a first gate dielectric layer and a source polysilicon layer at the bottom of the deep trench, forming an isolation dielectric layer on the first gate dielectric layer and the source polysilicon layer, and forming a second and a third gate dielectric layer with different thicknesses on different deep trenches and mesa structures on both sides thereof; Step 2: forming a gate polysilicon layer filling the remaining deep trench; Step 3, forming a fourth dielectric layer covering the gate polysilicon layer, the second and third gate dielectric layers, and etching back the fourth dielectric layer so that the total thickness of the dielectric layer at each location on the mesa structure is the target value; Step 4: forming a body region and a source region by ion implantation, and the dielectric layer on the mesa structure serves as an ion implantation protection layer.

2. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: In step one, the deep trench is formed by photolithography and etching.

3. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: The material of the first gate dielectric layer in step 1 is silicon nitride or silicon dioxide.

4. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: The materials of the second and third gate dielectric layers and the isolation dielectric layer in step 1 are oxides.

5. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: The material of the isolation dielectric layer in step 1 is silicon nitride or silicon dioxide.

6. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: The method for forming the gate polysilicon layer in step 2 includes: depositing the gate polysilicon layer; grinding the gate polysilicon layer to a first preset height, wherein the height of the second gate dielectric layer is lower than the height of the third gate dielectric layer, and the first preset height is not lower than the height of the third gate dielectric layer; etching the gate polysilicon layer to a third preset height, and the second preset height is not higher than the height of the second gate dielectric layer.

7. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 6, characterized in that: The grinding method in step 2 is chemical mechanical planarization grinding.

8. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: The material of the fourth dielectric layer in step three is oxide.

9. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 8, characterized in that: In step three, the fourth dielectric layer is formed by thermal oxidation.

10. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 8, characterized in that: The thickness of the fourth dielectric layer in step three is greater than 800 angstroms.

11. The method for improving the thickness uniformity of the ion implantation protection layer according to claim 1, characterized in that: The method is used for manufacturing a power MOS.

Images