Semiconductor device and manufacturing method thereof
By forming grooves on the outer peripheral edge of the passivation layer opposite to the preformed pad area, and forming a pad metal layer in the opening of the photoresist layer, so that its boundary is located in the groove, the problem of peeling abnormality in the metal pattern boundary during semiconductor device manufacturing is solved, and the quality of the device is improved.
Patent Information
- Application Number
- CN202510103347.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-01-08
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-06
AI Technical Summary
During the manufacturing process of semiconductor devices, the morphology of the photoresist mask changes lead to peeling abnormalities in the boundaries of metal patterns, affecting the quality of the device.
By forming at least one first groove at the outer peripheral edge of the passivation layer opposite to the pre-formed pads, and forming a pad metal layer in the opening of the photoresist layer, the boundary of the pad metal layer is located in the first groove, forming a pattern with step difference.
The boundary roughness of the pad metal layer is increased, the bonding force between it and the passivation layer is enhanced, and the ability to resist peeling abnormalities is improved, and peeling abnormalities occur when the photoresist layer is removed from the boundary of the pad metal layer.
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Figure CN119943676A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art
[0002] Lift-off is a process in which a photoresist with a certain pattern is formed as a mask after coating, exposing and developing the substrate, and then the required metal is evaporated using an evaporation process. After that, the metal on the photoresist mask is stripped off while removing the photoresist mask, leaving a metal pattern on the substrate.
[0003] In the related art, the morphology of the photoresist mask changes due to the influence of temperature, and the bottom of the photoresist mask is easily cross-linked with the metal on the substrate, so that when the photoresist mask and the metal thereon are removed, peeling anomalies occur at the boundaries of the metal deposited on the substrate.
[0004] In view of the above technical problems, the present application provides a new semiconductor device and a method for manufacturing the same. Summary of the invention
[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.
[0006] In view of the existing problems, the present application provides a method for manufacturing a semiconductor device, comprising:
[0007] providing a substrate;
[0008] A dielectric layer, a top metal layer and a passivation layer are sequentially formed on the substrate, and at least one first groove is formed along the peripheral edge of a region of the passivation layer facing the pre-formed pad;
[0009] Forming a patterned photoresist layer on the passivation layer, wherein the photoresist layer has an opening, wherein the opening exposes an area of the preformed pad and a partial area of each of the first grooves close to the preformed pad;
[0010] Depositing a metal material on the photoresist layer and in the opening;
[0011] The photoresist layer and the metal material on the photoresist layer are removed to form a pad metal layer.
[0012] Exemplarily, a dielectric layer, a top metal layer and a passivation layer are sequentially formed on the substrate, and at least one first groove is formed along the peripheral edge of the area of the passivation layer facing the pre-formed pad, including:
[0013] forming a dielectric layer on the substrate;
[0014] Forming at least one first through hole in the dielectric layer at an outer peripheral edge of a region directly facing the pre-formed pad;
[0015] forming a top metal layer on the dielectric layer, wherein a second groove corresponding to the first through hole is conformally formed on the top metal layer;
[0016] A passivation layer is formed on the top metal layer, and a first groove corresponding to the second groove is conformally formed on the passivation layer.
[0017] Exemplarily, a dielectric layer, a top metal layer and a passivation layer are sequentially formed on the substrate, and at least one first groove is formed along the peripheral edge of the area of the passivation layer facing the pre-formed pad, including:
[0018] forming a dielectric layer, a top metal layer and a passivation layer on the substrate in sequence;
[0019] The passivation layer is patterned to form at least one first groove at an outer peripheral edge of a region of the passivation layer facing the pre-formed pad.
[0020] Exemplarily, before forming a patterned photoresist layer on the passivation layer, the method further includes:
[0021] The passivation layer is patterned to form at least one second through hole in a region of the passivation layer facing the pre-formed pad and exposing a portion of the surface of the top metal layer.
[0022] Exemplarily, the at least one first groove is a plurality of grooves arranged at intervals and extending along the peripheral edge of the region of the passivation layer facing the pre-formed pad.
[0023] Alternatively, the at least one first groove is an annular groove arranged along the outer peripheral edge of a region of the passivation layer facing the pre-formed pad.
[0024] Exemplarily, at least one third groove is further formed in a region of the passivation layer outside the second through hole and facing the pre-formed pad, and the third groove is located between the first groove and a region of the second through hole.
[0025] In another aspect, the present application provides a semiconductor device, the semiconductor device comprising:
[0026] substrate;
[0027] A dielectric layer, a top metal layer and a passivation layer are sequentially stacked on the substrate, and the outer peripheral edge of the passivation layer facing the pre-formed pad has at least one first groove;
[0028] The pad metal layer is located in the area of the pre-formed pad and covers a portion of the first groove, and the outer peripheral edge of the pad metal layer is located in the first groove.
[0029] Exemplarily, the outer peripheral edge of the area of the dielectric layer facing the pre-formed pad has at least one first through hole; and the top metal layer has a second groove corresponding to the first through hole.
[0030] Exemplarily, the passivation layer has at least one second through hole in a region facing the pre-formed pad, and the pad metal layer also fills up the second through hole and is electrically connected to the top metal layer.
[0031] Exemplarily, the at least one first groove is a plurality of spaced grooves extending along the peripheral edge of an area of the passivation layer facing the pre-formed pad, or the at least one first groove is an annular groove arranged along the peripheral edge of an area of the passivation layer facing the pre-formed pad.
[0032] Exemplarily, at least one third groove is further provided in a region of the passivation layer outside the second through hole and facing the pre-formed pad, and the third groove is located between the first groove and the second through hole.
[0033] The manufacturing method of the semiconductor device of the present application forms at least one first groove on the peripheral edge of the area of the passivation layer facing the pre-formed pad, and the opening of the photoresist layer exposes the area of the pre-formed pad and a partial area of each first groove close to the pre-formed pad. After the pad metal layer is formed in the opening, the boundary of the pad metal layer is located in the first groove, so that the boundary of the pad metal layer forms a pattern with a step difference, which can increase the roughness of the boundary of the pad metal layer, increase the bonding force between the pad metal layer and the passivation layer, and improve the ability of the pad metal layer to resist peeling anomalies at the boundary, so that when the photoresist layer and the metal material thereon are removed, peeling anomalies at the boundary of the pad metal layer left in the opening can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.
[0035] In the attached figure:
[0036] Figure 1 A cross-sectional schematic diagram of a semiconductor device obtained by a lift-off process in the related art is shown;
[0037] Figure 2 A top view of a semiconductor device obtained by a lift-off process in the related art is shown;
[0038] Figure 3 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;
[0039] FIG. 4A to FIG. 4G A schematic cross-sectional view of a device substrate obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;
[0040] Figure 5 Shows Figure 4G Top view of the . DETAILED DESCRIPTION
[0041] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.
[0042] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.
[0043] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.
[0044] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0046] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.
[0047] In the related art, a substrate 110 is first provided, and then a dielectric layer 120 is formed on the substrate 110, and then a first opening is formed in the dielectric layer 120, and then a top metal layer 130 is formed on the dielectric layer 120 and in the first opening, and then a groove corresponding to the first opening is formed on the top metal layer 130, and then a passivation layer 140 is formed on the top metal layer 130, and then a second opening is formed in the passivation layer 140 to expose a portion of the top metal layer 130, and then a photoresist with a certain pattern is formed on the passivation layer 140 after being coated, exposed, and developed, and a photoresist with a certain pattern is formed as a photoresist mask, and a third opening is provided in the photoresist mask to expose the second opening and the passivation layer 140 around the second opening, and then a metal material is deposited, and the metal material fills the third opening and is electrically connected to the top metal layer 130, and finally the photoresist mask and the metal material thereon are removed, leaving the pad metal layer 150 located in the opening, such as Figure 1 and Figure 2 shown.
[0048] In the above process, since the morphology of the photoresist mask changes due to temperature, the bottom of the photoresist mask is easily cross-linked with the pad metal layer 150, so that when the photoresist mask and the pad metal layer 150 thereon are removed, peeling anomalies occur at the boundary of the pad metal layer 150 located in the opening.
[0049] Therefore, in view of the existence of the above technical problems, the present application proposes a method for manufacturing a semiconductor device, such as Figure 3 As shown, including:
[0050] Step S1, providing a substrate;
[0051] Step S2, forming a dielectric layer, a top metal layer and a passivation layer on the substrate in sequence, and forming at least one first groove along the peripheral edge of a region of the passivation layer facing the pre-formed pad;
[0052] Step S3, forming a patterned photoresist layer on the passivation layer, wherein the photoresist layer has an opening, and the opening exposes the area of the preformed pad and a partial area of each of the first grooves near the preformed pad;
[0053] Step S4, depositing a metal material on the photoresist layer and in the opening;
[0054] Step S5, removing the photoresist layer and the metal material on the photoresist layer to form a pad metal layer.
[0055] The manufacturing method of the semiconductor device of the present application forms at least one first groove on the peripheral edge of the area of the passivation layer facing the pre-formed pad, and the opening of the photoresist layer exposes the area of the pre-formed pad and a partial area of each first groove close to the pre-formed pad. After the pad metal layer is formed in the opening, the boundary of the pad metal layer is located in the first groove, so that the boundary of the pad metal layer forms a pattern with a step difference in the first groove, which can increase the roughness of the boundary of the pad metal layer, increase the bonding force between the pad metal layer and the passivation layer, and improve the ability of the pad metal layer to resist peeling anomalies at the boundary, so that when the photoresist layer and the metal material thereon are removed, peeling anomalies at the boundary of the pad metal layer left in the opening can be avoided.
[0056] Embodiment 1
[0057] Below, reference FIG. 4A to FIG. 4G , Figure 5 The method for manufacturing the semiconductor device of the present application is described in detail, wherein: FIG. 4A to FIG. 4G A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a manufacturing method according to a specific embodiment of the present application is shown, Figure 5 Shows Figure 4G Top view of the .
[0058] Exemplarily, the method for manufacturing a semiconductor device of the present application includes the following steps:
[0059] First, perform step 1, such as Figure 4A As shown, a substrate 210 is provided.
[0060] The substrate 210 may be any suitable semiconductor substrate, such as a bulk silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-sided polished silicon wafers (DSP), or may be ceramic substrates such as alumina, quartz or glass substrates, etc.
[0061] Next, step 2 is performed to sequentially form a dielectric layer 220 , a top metal layer 230 and a passivation layer 240 on the substrate 210 , and at least one first groove 241 is formed along the outer peripheral edge of the region 251 of the passivation layer 240 facing the pre-formed pad.
[0062] In some embodiments, Figure 4B to Figure 4E As shown, a dielectric layer 220, a top metal layer 230 and a passivation layer 240 are sequentially formed on a substrate 210, and at least one first groove 241 is formed along the outer peripheral edge of a region 251 of the passivation layer 240 facing the pre-formed pad. The steps S21 to S24 may be as follows:
[0063] Step S21, as Figure 4B As shown, a dielectric layer 220 is formed on a substrate 210 .
[0064] Exemplarily, the dielectric layer 220 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the dielectric layer 220 may be insulating materials such as silicon dioxide, fluorocarbons, carbon-doped silicon oxide, silicon carbonitride, etc., without limitation. Exemplarily, after forming the dielectric layer 220, the method further includes: performing a planarization process on the dielectric layer 220. Exemplarily, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.
[0065] Step S22, as Figure 4C As shown, at least one first through hole 221 is formed in the dielectric layer 220 at the outer peripheral edge of the region 251 facing the pre-formed pad.
[0066] Exemplarily, the first through hole 221 in the dielectric layer 220 can be formed synchronously with the through hole in the cell region on the substrate 210, that is, when a through hole is formed in the cell region on the substrate 210, the first through hole 221 in the dielectric layer 220 can be formed synchronously.
[0067] Step S23, as Figure 4D As shown, a top metal layer 230 is formed on the dielectric layer 220 , and a second groove 231 corresponding to the first through hole 221 is conformally formed on the top metal layer 230 .
[0068] Exemplarily, the metal may be deposited and annealed to react with the silicon of the substrate 210 to form a top metal layer 230 on the dielectric layer 220, and the thickness of the formed top metal layer 230 is greater than the thickness of the dielectric layer 220, that is, the thickness of the top metal layer 230 is greater than the depth of the first through hole 221. In particular, since at least one first through hole 221 is formed in the dielectric layer 220 in step S22, and the thickness of the top metal layer 230 is greater than the thickness of the dielectric layer 220 (by making the thickness of the top metal layer 230 greater than the thickness of the dielectric layer 220, a groove is subsequently formed in the top metal layer 230 instead of a through hole), after the top metal layer 230 is formed on the dielectric layer 220, a second groove 231 corresponding to the first through hole 221 is conformally formed in the formed top metal layer 230.
[0069] The top metal layer 230 may be aluminum silicide or any other suitable metal material, which is not limited.
[0070] Step S24, as Figure 4E As shown, a passivation layer 240 is formed on the top metal layer 230 , and a first groove 241 corresponding to the second groove 231 is conformally formed on the passivation layer 240 .
[0071] For example, the passivation layer 240 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, the material of the passivation layer 240 may be any suitable passivation layer material, which is not limited.
[0072] The thickness of the formed passivation layer 240 is greater than the depth of the second groove 231 in the top metal layer 230. Since the second groove 231 is formed in the top metal layer 230 in step S213, and the thickness of the passivation layer 240 is greater than the depth of the second groove 231 (by making the thickness of the passivation layer 240 greater than the depth of the second groove 231, a groove is subsequently conformally formed in the passivation layer 240 instead of a through hole), after the passivation layer 240 is formed on the top metal layer 230, a first groove 241 corresponding to the second groove 231 is conformally formed in the formed passivation layer 240.
[0073] In some other embodiments, sequentially forming a dielectric layer 220, a top metal layer 230 and a passivation layer 240 on a substrate 210, and forming at least one first groove along an outer peripheral edge of a region 251 of the passivation layer 240 facing the pre-formed pad may include the following steps S25-S26:
[0074] Step S25 , forming a dielectric layer 220 , a top metal layer 230 and a passivation layer 240 in sequence on the substrate 210 .
[0075] Exemplarily, the dielectric layer 220 may be formed on the substrate by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the dielectric layer may be insulating materials such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, silicon carbonitride, etc., without limitation. Exemplarily, after forming the dielectric layer 220, the method further includes: performing a planarization process on the dielectric layer 220. Exemplarily, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.
[0076] For example, the top metal layer 230 may be formed on the dielectric layer 220 by metal deposition and annealing to make the metal react with the substrate silicon.
[0077] The top metal layer 230 may be aluminum silicide or any other suitable metal material, which is not limited.
[0078] For example, the passivation layer 240 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, the material of the passivation layer 240 may be any suitable passivation layer material, which is not limited.
[0079] In step S26 , the passivation layer 240 is patterned to form at least one first groove 241 at the outer peripheral edge of the region 251 of the passivation layer 240 facing the pre-formed pad.
[0080] Exemplarily, a photoresist mask layer can be formed on the passivation layer 240, and the photoresist mask layer can be patterned through processes such as exposure and development to form a patterned mask layer for defining at least one first groove 241 to be formed; then, the passivation layer 240 is etched with the patterned mask layer to form at least one first groove 241 at the outer peripheral edge of the area 251 of the passivation layer facing the pre-formed pad.
[0081] It should be noted that in the above two processes for forming the first grooves 241, at least one first groove 241 is a plurality of spaced grooves extending along the outer peripheral edge of the region 251 of the passivation layer 240 facing the pre-formed pad, or at least one first groove 241 is an annular groove provided along the outer peripheral edge of the region 251 of the passivation layer 240 facing the pre-formed pad. For example, Figure 5 As shown in the dotted box marked with 221, the first groove 241 is a plurality of long strip grooves (not excluding grooves of other shapes) arranged at intervals and extending along the outer peripheral edge of the area 251 where the pad is preformed, of the passivation layer 240. Accordingly, the second groove 231 formed in the previous process of forming the first groove 241 may also include a long strip groove extending along the outer peripheral edge of the area 251 where the pad is preformed.
[0082] In addition, the shapes of the longitudinal sections of the first groove 241, the first through hole 221 and the second groove 231 can be set according to actual conditions. For example, Figure 4E As shown, the longitudinal sections of the first groove 241 , the first through hole 221 , and the second groove 231 may all be inverted trapezoidal shapes.
[0083] In some embodiments, Figure 4C As shown, before forming the top metal layer 230, it also includes:
[0084] A second opening 222 is formed in the middle of the dielectric layer 220 facing the pre-formed pad region 251 to expose the substrate 410 .
[0085] like Figure 4D As shown, the top metal layer 230 formed on the dielectric layer 220 fills up the second opening 222 , and a fifth groove 232 corresponding to the second opening 222 is conformally formed on the top metal layer 230 .
[0086] like Figure 4E As shown, a sixth groove 244 corresponding to the fifth groove 232 is formed on the passivation layer 240 .
[0087] Illustratively, a photoresist mask layer can be formed on the dielectric layer 220, and the photoresist mask layer can be patterned through processes such as exposure and development to form a patterned mask layer for defining the second opening 222 to be formed; then, the dielectric layer 220 is etched with the patterned mask layer to form a second opening 222 in the middle of the area 251 of the dielectric layer 220 that is opposite to the pre-formed pad.
[0088] It can be understood that when the first through hole 221 needs to be formed in the dielectric layer 220 , the second opening 222 on the dielectric layer 220 can be formed simultaneously with the first through hole 221 .
[0089] Furthermore, the second through hole 242 subsequently formed in the passivation layer 240 is located at the bottom of the passivation layer 240 directly facing the sixth groove 244 .
[0090] In some embodiments, at least one third groove 243 is further formed in a region 251 of the passivation layer 240 facing the pre-formed pad outside the second through hole 242 , and the third groove 243 is located between the first groove 241 and the second through hole 242 .
[0091] Among them, Figure 4C to Figure 4E As shown, at least one first through hole 221 can be formed in the dielectric layer 220, and at least one third through hole 223 can be formed in the region 241 of the dielectric layer 220 outside the second opening 222 and facing the pre-formed pad, and the third through hole 223 is located between the first through hole 221 and the second opening 222. Afterwards, when the top metal layer 230 is formed on the dielectric layer 220, a fourth groove 233 corresponding to the third through hole 223 is formed on the top metal layer 230, and when the passivation layer 240 is formed on the top metal layer 230, a third groove 243 corresponding to the fourth groove 233 is formed on the passivation layer 240.
[0092] Alternatively, while patterning the passivation layer 240 to form at least one first groove 241 at the peripheral edge of the area of the passivation layer 240 facing the pre-formed pad, at least one third groove 243 can be formed in the area 251 of the passivation layer 240 facing the pre-formed pad outside the second through hole 242, and the third groove 243 is located between the first groove 241 and the second through hole 242.
[0093] By forming at least one third groove 243 in the area 251 of the passivation layer 240 facing the pre-formed pad outside the second through hole 242, the bonding force between the subsequently formed pad metal layer 250 and the passivation layer 240 can be further increased, thereby further avoiding peeling anomalies at the boundaries of the pad metal layer 250.
[0094] Similar to the first groove 241, in some embodiments, at least one third groove 243 is a plurality of grooves spaced apart and arranged circumferentially near the outer peripheral edge of the region 251 of the passivation layer 240 facing the pre-formed pad. In other implementations, at least one third groove 243 is at least one annular groove arranged near the outer peripheral edge of the region 251 of the passivation layer facing the pre-formed pad, and there is a certain interval between the third groove 243 and the first groove 241.
[0095] Next, step three is performed to form a patterned photoresist layer on the passivation layer 240 , wherein the photoresist layer has a first opening, and the first opening exposes the pre-formed pad region 251 and a portion of each first groove 241 close to the pre-formed pad region 251 .
[0096] Taking the photoresist layer formed on the passivation layer 240 as an example, a patterned photoresist layer is formed on the passivation layer 240, wherein the photoresist layer has a first opening, and the first opening exposes the region 251 of the preformed pad and a partial region of each first groove 241 close to the region 251 of the preformed pad, and the steps may include:
[0097] A positive photoresist is coated on the passivation layer 240, and then a first mask is used, on which a corresponding pattern is defined, and the positive photoresist is exposed based on the first mask, and then developed using a positive photoresist developer, and the positive photoresist in the exposed area is dissolved in the positive photoresist developer, leaving the positive photoresist in the non-exposed area, that is, the photoresist layer. The formed photoresist layer has a first opening, and the first opening exposes the area 251 of the pre-formed pad and a portion of each first groove 241 near the area 251 of the pre-formed pad.
[0098] Taking the case where the photoresist layer formed on the passivation layer 240 includes a negative positive photoresist, forming a patterned photoresist layer on the passivation layer 240, wherein the photoresist layer has a first opening, and the first opening exposes the region 251 of the preformed pad and a partial region of each first groove 241 close to the region 251 of the preformed pad, may include the following steps:
[0099] A negative photoresist is coated on the passivation layer 240, and then a second mask is used, on which a corresponding pattern is defined, and the negative photoresist is exposed based on the second mask, and then developed using a negative photoresist developer, and the negative photoresist in the non-exposed area is dissolved in the negative photoresist developer, leaving the negative photoresist in the exposed area, that is, the photoresist layer. The formed photoresist layer has a first opening, and the first opening exposes the area 251 of the pre-formed pad and a portion of each first groove 241 near the area 251 of the pre-formed pad.
[0100] It should be noted that since the inner boundary of the photoresist layer is located within a portion of the first groove 241, when the photoresist is subsequently removed, the adhesion between the photoresist and the pad metal layer 250 located within another portion of the first groove 241 can be weakened, thereby avoiding peeling abnormalities in the pad metal layer 250 located within the first groove 241.
[0101] In one example, when at least one first groove 241 is a plurality of spaced grooves extending along the peripheral edge of an area 251 of the passivation layer opposite to the preformed pad, the first opening may expose only the area 251 of the preformed pad and a portion of the area 251 of each first groove 241 near the preformed pad. Alternatively, in addition to exposing the area 251 of the preformed pad and a portion of the area 251 of each first groove 241 near the preformed pad, the first opening may also expose a portion of the area 251 near the preformed pad between adjacent first grooves 241.
[0102] In one example, at least one first groove 241 is an annular groove arranged along the outer peripheral edge of the area 251 of the passivation layer facing the pre-formed pad, and the first opening can only expose the area 251 of the pre-formed pad and a partial area of the annular groove close to the area 251 of the pre-formed pad.
[0103] Next, step four is performed to deposit a metal material on the photoresist layer and in the first opening.
[0104] For example, various deposition methods commonly used in the art can be used to deposit the metal material on the photoresist layer and in the first opening, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). For example, the deposited metal material can be a metal material such as TiNiAg, which is not limited.
[0105] In one example, if Figure 4F and Figure 4G As shown, before forming a patterned photoresist layer on the passivation layer 240 , the process further includes: patterning the passivation layer 240 to form at least one second through hole 242 exposing a portion of the surface of the top metal layer 230 in a region 251 of the passivation layer 240 facing the pre-formed pad.
[0106] Exemplarily, the contact hole process may be used to etch the second through hole 242 on the passivation layer 240. Specifically, a photoresist mask layer may be formed on the passivation layer 240, and the photoresist mask layer may be patterned through processes such as exposure and development to form a patterned mask layer for defining at least one second through hole 242 to be formed; then, the passivation layer 240 is etched with the patterned mask layer to form at least one second through hole 242 exposing a portion of the surface of the top metal layer 230.
[0107] The shape of the second through hole 242 can also be set according to actual conditions, and is not limited thereto. For example, the cross section of the second through hole 242 is a regular hexagon, a regular octagon, or any other suitable shape. Figure 5 As shown in the dotted frame marked 242 , the cross section of the second through hole 242 is preferably a regular hexagon.
[0108] By forming a plurality of second through holes 242 in the area 251 of the passivation layer 240 facing the pre-formed pad, the subsequently formed pad metal layer 250 fills the second through holes 242 and is electrically connected to the top metal layer 230, thereby increasing the roughness of the bottom surface of the pad metal layer 250 located in the area 251 of the pre-formed pad, improving the bonding strength between this part of the pad metal layer 250 and the passivation layer 240, and further enhancing the ability of this part of the pad metal layer 250 to resist peeling anomalies at the boundary during the stripping process.
[0109] Moreover, the pad metal layer 250 formed in the pad pre-formed region 251 fills the second through hole 242 and is electrically connected to the top metal layer 230 , and can also reduce stress between the pad metal layer 250 and the top metal layer 230 .
[0110] Next, execute step 5, such as Figure 4G As shown, the photoresist layer and the metal material on the photoresist layer are removed to form a pad metal layer 250 .
[0111] For example, a conventional lift-off process may be used to remove the photoresist layer, and at the same time, the metal material on the photoresist layer is removed together, leaving only the metal material in the first opening as the pad metal layer 250 .
[0112] Since the boundary of the pad metal layer 250 in the first opening is located in the first groove 241, the boundary of the pad metal layer 250 forms a pattern with a step difference in the first groove 241, thereby increasing the roughness of the boundary of the pad metal layer 250 and improving the ability of the pad metal layer 250 to resist peeling anomalies at the boundary. Therefore, when removing the photoresist layer and the metal material thereon, peeling anomalies can be avoided at the boundary of the pad metal layer 250 left in the first opening. Moreover, the newly added pattern will not affect the electrical parameters and performance of the product, and can make the boundary of the pad metal layer 250 left in the first opening smoother and reduce burrs.
[0113] It is worth mentioning that the order of the above steps is only an example. Under the premise of no conflict, the order of the above steps can also be swapped or performed alternately.
[0114] This completes the introduction to the key manufacturing method of the semiconductor device of the present application. The production of a complete device requires other preceding steps, intermediate steps or subsequent steps, which will not be described in detail here.
[0115] In summary, the manufacturing method of the semiconductor device of the present application forms at least one first groove 241 on the outer peripheral edge of the area 251 of the passivation layer 240 facing the pre-formed pad, and the opening of the photoresist layer exposes the area 251 of the pre-formed pad and a partial area of each first groove 241 close to the pre-formed pad. After the pad metal layer 250 is formed in the opening, the boundary of the pad metal layer 250 is located in the first groove 241, so that the boundary of the pad metal layer 250 forms a pattern with a step difference in the first groove 241, which can increase the roughness of the boundary of the pad metal layer 250, increase the bonding force between the pad metal layer 250 and the passivation layer 240, and improve the ability of the pad metal layer 250 to resist peeling anomalies at the boundary, so that when the photoresist layer and the metal material thereon are removed, peeling anomalies at the boundary of the pad metal layer 250 left in the opening can be avoided.
[0116] Embodiment 2
[0117] The present application also provides a semiconductor device. Figure 4G The semiconductor device of the present application is introduced and explained in detail.
[0118] Specifically, Figure 4GAs shown, the semiconductor device of the present application includes a substrate 210; a dielectric layer 220, a top metal layer 230 and a passivation layer 240 are sequentially stacked on the substrate 210, and the outer peripheral edge of the passivation layer 240 facing the area 251 of the pre-formed pad has at least one first groove 241; a pad metal layer 250 is located in the area 251 of the pre-formed pad and covers a portion of the first groove 241, and the outer peripheral edge of the pad metal layer 250 is located in the first groove 241.
[0119] For example, Figure 4C and Figure 4D As shown, the outer peripheral edge of the area 251 of the dielectric layer 220 facing the pre-formed pad has at least one first through hole 221 ; and the top metal layer 230 has a second groove 231 corresponding to the first through hole 221 .
[0120] For example, Figure 4F As shown, the passivation layer 240 has at least one second through hole 242 in a region 251 facing the pre-formed pad, and the pad metal layer 250 also fills the second through hole 242 to be electrically connected to the top metal layer 230 .
[0121] For example, Figure 5 As shown, the cross section of the second through hole 242 includes a regular hexagon or a regular octagon.
[0122] For example, Figure 5 As shown, at least one first groove is a plurality of spaced grooves extending along the peripheral edge of the area 251 of the passivation layer 240 facing the pre-formed pad, or at least one first groove is an annular groove arranged along the peripheral edge of the area 251 of the passivation layer 240 facing the pre-formed pad.
[0123] Exemplarily, the pad metal layer 250 includes TiNiAg.
[0124] Exemplarily, at least one third groove 243 is further provided in a region 251 of the passivation layer 240 facing the pre-formed pad outside the second through hole 242 , and the third groove 243 is located between the first groove 241 and the second through hole 242 .
[0125] Exemplarily, the middle portion of the dielectric layer 220 opposite to the pre-formed pad region 251 has a second opening 222 exposing the substrate 210, and the top metal layer 230 fills the second opening 222; the top metal layer 230 has a fifth groove 232 corresponding to the second opening 222; and the passivation layer 240 has a sixth groove 244 corresponding to the fifth groove 232.
[0126] It can be understood that the semiconductor device in this embodiment can be manufactured by the method in the aforementioned embodiment one. In order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.
[0127] According to the semiconductor device of the present application, at least one first groove 241 is formed on the outer peripheral edge of the area 251 of the passivation layer 240 facing the pre-formed pad, and the boundary of the pad metal layer 250 is located in the first groove 241, so that the boundary of the pad metal layer 250 forms a pattern with a step difference in the first groove 241, which can increase the roughness of the boundary of the pad metal layer 250, increase the bonding force between the pad metal layer 250 and the passivation layer 240, and improve the ability of the pad metal layer 250 to resist peeling anomalies at the boundary.
[0128] Embodiment 3
[0129] Another embodiment of the present application provides an electronic device, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.
[0130] The electronic device of the present embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the present embodiment has better performance because the above-mentioned semiconductor device is used.
[0131] The present application has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present application is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present application, and these variations and modifications all fall within the scope of protection claimed by the present application. The scope of protection of the present application is defined by the attached claims and their equivalents.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; A dielectric layer, a top metal layer and a passivation layer are sequentially formed on the substrate, and at least one first groove is formed along the peripheral edge of a region of the passivation layer facing the pre-formed pad; Forming a patterned photoresist layer on the passivation layer, wherein the photoresist layer has an opening, wherein the opening exposes an area of the preformed pad and a partial area of each of the first grooves close to the preformed pad; Depositing a metal material on the photoresist layer and in the opening; The photoresist layer and the metal material on the photoresist layer are removed to form a pad metal layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: A dielectric layer, a top metal layer and a passivation layer are sequentially formed on the substrate, and at least one first groove is formed along the peripheral edge of the passivation layer in a region facing the pre-formed pad, comprising: forming a dielectric layer on the substrate; forming at least one first through hole in the dielectric layer at an outer peripheral edge of a region directly facing the preformed pad; forming a top metal layer on the dielectric layer, wherein a second groove corresponding to the first through hole is conformally formed on the top metal layer; A passivation layer is formed on the top metal layer, and a first groove corresponding to the second groove is conformally formed on the passivation layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: A dielectric layer, a top metal layer and a passivation layer are sequentially formed on the substrate, and at least one first groove is formed along the peripheral edge of the passivation layer in a region facing the pre-formed pad, comprising: forming a dielectric layer, a top metal layer and a passivation layer on the substrate in sequence; The passivation layer is patterned to form at least one first groove at an outer peripheral edge of a region of the passivation layer facing the pre-formed pad.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a patterned photoresist layer on the passivation layer, the method further comprises: The passivation layer is patterned to form at least one second through hole in a region of the passivation layer facing the pre-formed pad and exposing a portion of the surface of the top metal layer.
5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: The at least one first groove is a plurality of grooves arranged at intervals and extending along the outer peripheral edge of the region of the passivation layer facing the pre-formed pad. Alternatively, the at least one first groove is an annular groove arranged along the outer peripheral edge of a region of the passivation layer facing the pre-formed pad.
6. The method for manufacturing a semiconductor device according to claim 4, wherein: At least one third groove is further formed in a region of the passivation layer outside the second through hole and facing the pre-formed pad, and the third groove is located between the first groove and the second through hole.
7. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; A dielectric layer, a top metal layer and a passivation layer are sequentially stacked on the substrate, and the outer peripheral edge of the passivation layer facing the pre-formed pad has at least one first groove; The pad metal layer is located in the area of the pre-formed pad and covers a portion of the first groove, and the outer peripheral edge of the pad metal layer is located in the first groove.
8. The semiconductor device according to claim 7, wherein: The outer peripheral edge of the area of the dielectric layer facing the pre-formed pad is provided with at least one first through hole; The top metal layer has a second groove corresponding to the first through hole.
9. The semiconductor device according to claim 7, wherein: The passivation layer has at least one second through hole in a region facing the pre-formed pad, and the pad metal layer fills up the second through hole and is electrically connected to the top metal layer.
10. The semiconductor device according to any one of claims 7 to 9, wherein: The at least one first groove is a plurality of grooves arranged at intervals and extending along the outer peripheral edge of the region of the passivation layer facing the pre-formed pad. Alternatively, the at least one first groove is an annular groove arranged along the outer peripheral edge of a region of the passivation layer facing the pre-formed pad.
11. The semiconductor device according to claim 8, wherein At least one third groove is further provided in a region of the passivation layer outside the second through hole and facing the pre-formed pad, and the third groove is located between the first groove and the second through hole.