Evaluation method for wafer back thinning processing damaged layer

Abstract

The invention relates to the technical field of semiconductors, in particular to a method for evaluating a wafer back thinning processing damaged layer. Comprising the following steps: S1, forming a plurality of PN junctions in array distribution on the surface of each chip of a wafer; the PN junction comprises an N-type well and a P-type well, the N-type well and the P-type well are respectively arranged on the chip substrate, and the P-type well is located in the N-type well; a first power connector terminal is arranged on the chip substrate, a second power connector terminal is arranged on the N-type well, and a third power connector terminal is arranged on the P-type well. S2, the chip is thinned; s3, reverse voltage is connected between the first power connector terminal and the second power connector terminal, and a change curve of leakage current is measured; and S4, analyzing the condition of the wafer damage layer through the leakage current curve. Compared with the prior art, the wafer with a simple PN junction structure is designed. When grinding damage affects a depletion layer of a PN junction in a wafer, leakage current occurs, and the condition of a damage layer in the whole wafer is evaluated by testing the leakage current.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to an evaluation method for a damaged layer in wafer backside thinning processing. Background Art

[0002] In order to improve the performance of semiconductor devices, reduce their power consumption, size and cost, the demand for extremely thin chips is becoming increasingly high. Especially this year, the wafer backside thinning technology is being improved to reduce the final thickness of the Si substrate to more than ten microns or even a few microns. Figure 1 As shown, wafer backside thinning is generally achieved by mechanical grinding technology, but mechanical grinding will produce a damaged layer on the back of the wafer. When the damaged layer approaches the doped layer or functional layer near the surface of the semiconductor device wafer, it will affect the performance of the semiconductor device.

[0003] Currently, the main method for evaluating the damage layer is to observe the crack depth after wafer thinning through an electron microscope (SEM). However, this technology has two limitations: 1) It can only evaluate the visible part (incompleteness). Figure 2 As shown, the damage layer that affects the performance of semiconductor devices is not only the depth of the visible cracks, but also includes lattice dislocations and stress fields deeper than the cracks. The latter two are difficult to characterize using SEM. 2) Only a small part of the wafer can be evaluated (regional limitation). SEM is evaluated by observing the morphology of the cross section of the Si substrate. The observable range is generally from a few microns to several hundred microns, so it is difficult to evaluate the distribution of the damage layer on the entire wafer. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a method for evaluating a damaged layer during wafer backside thinning processing, which can effectively evaluate the impact range of the damaged layer and the distribution of the damaged layer on the entire wafer.

[0005] To achieve the above purpose, a method for evaluating the damaged layer of wafer backside thinning processing is designed, comprising the following steps:

[0006] S1, forming a number of PN junctions distributed in an array on the surface of each chip of the wafer;

[0007] The PN junction includes an N-type well and a P-type well. The chip substrate is provided with an N-type well and a P-type well, respectively, and the P-type well is located inside the N-type well.

[0008] A power connector terminal 1 is provided on the chip substrate, a power connector terminal 2 is provided on the N-type well, and a power connector terminal 3 is provided on the P-type well;

[0009] S2, thinning the chip;

[0010] S3, connect a reverse voltage between the power connector terminal 1 and the power connector terminal 2, and measure the change curve of the leakage current;

[0011] S4, analyzing the condition of the wafer damage layer through the leakage current curve.

[0012] The chip substrate is a P-type Si substrate.

[0013] The depth of the N-type well is greater than that of the P-type well, and the P-type well is contained in the N-type well.

[0014] An isolation trench is provided between adjacent PN junctions.

[0015] In the step S4, the relationship between the leakage current and the PN junction depletion layer defect is shown in the following formula:

[0016] I leakeage ∝N def =ρ def ×S

[0017] Where Ileakage is the leakage current intensity, ρdef is the surface density of defects, and S is the area.

[0018] In the step S4, the difference in the damaged layers of different wafers is obtained by comparing the difference in the different leakage current curves.

[0019] The method further includes step S5, connecting a reverse voltage between the second power connector terminal and the third power connector terminal, measuring a variation curve of the leakage current, and analyzing the condition of the wafer damage layer through the leakage current curve.

[0020] Compared with the prior art, the present invention designs a wafer with a simple PN junction structure. When the grinding damage affects the depletion layer of the PN junction in the wafer, leakage current will occur, and the condition of the damaged layer in the entire wafer can be evaluated by testing the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of wafer thinning in the prior art.

[0022] Figure 2 It is a schematic diagram of processing the damaged layer in the prior art.

[0023] Figure 3 It is a schematic diagram of the principle of PN junction leakage current of the present invention.

[0024] Figure 4 Schematic diagram of the wafer in step S1 of the present invention.

[0025] Figure 5It is a schematic diagram of the chip and PN junction of the present invention.

[0026] Figure 6 for Figure 5 A partial enlarged view of point A in the middle.

[0027] Figure 7 It is a test schematic diagram in an embodiment of the present invention.

[0028] Figure 8 Graph showing evaluation results in an embodiment of the present invention.

[0029] Fig. 9 It is a schematic diagram of the specific use of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below with reference to the accompanying drawings.

[0031] like Figure 3 As shown in the figure, when a reverse voltage is applied to both ends of the PN junction, that is, a positive voltage is applied to the N-type and a negative voltage is applied to the P-type, the thickness of the depletion layer in the middle of the PN junction will become thicker. Since there are very few carriers in the depletion layer, the leakage current between the PN junctions will be very weak. However, when there are defects in the depletion layer, these defects will act as carriers, resulting in an increase in leakage current.

[0032] Based on this, the evaluation method of the wafer backside thinning process damaged layer in this embodiment includes the following steps:

[0033] like Figures 4 to 5 As shown, S1, a plurality of PN junctions 2 distributed in an array are formed on the surface of each chip 1 of the wafer, and a plurality of test pads 5 are also provided on the chip;

[0034] like Figure 6 As shown, the PN junction 2 includes an N-type well 2-1 and a P-type well 2-2. The chip substrate 1-1 is provided with an N-type well 2-1 and a P-type well 2-2, and the P-type well 2-2 is located in the N-type well 2-1.

[0035] A power connector terminal 1 Pin1 is provided on the chip substrate 1-1, a power connector terminal 2 Pin2 is provided on the N-type well 2-1, and a power connector terminal 3 Pin3 is provided on the P-type well 2-2;

[0036] S2, thinning the chip 1;

[0037] S3, connect a reverse voltage between the power connector terminal 1 Pin 1 and the power connector terminal 2 Pin 2, and measure the change curve of the leakage current;

[0038] S4, analyzing the condition of the wafer damaged layer 3 through the leakage current curve.

[0039] S5, connect a reverse voltage between the power connector terminal 2 Pin2 and the power connector terminal 3 Pin3, measure the variation curve of the leakage current, and analyze the situation of the deeper wafer damage layer 3 through the leakage current curve.

[0040] The chip substrate 1 - 1 is a P-type Si substrate. The depth of the N-type well 2 - 1 is greater than that of the P-type well 2 - 2 , and the P-type well 2 - 2 is contained in the N-type well 2 - 1 .

[0041] An isolation groove 2 - 3 is provided between adjacent PN junctions 2 , and the isolation groove 2 - 3 isolates adjacent PN junctions 2 to ensure that they do not interfere with each other.

[0042] In step S3, when a reverse voltage is applied between the power connector terminal 1 Pin1 and the power connector terminal 2 Pin2, the depletion layer 4 between the N-type well 2-1 and the chip substrate 1-1 becomes thicker, and the leakage current between the N-type well 2-1 and the chip substrate 1-1 will be very small. However, when the thinning process damage layer enters the depletion layer 4 and causes defects, the leakage current will increase. Figure 7 Similarly, when a reverse voltage is connected between Pin2 and Pin3 and the grinding damage layer enters its depletion layer, the leakage current between the N-type well and the P-type well will increase.

[0043] Therefore, after the thinning process, this embodiment evaluates the correlation between the thickness of the chip substrate 1-1 and the leakage current between the power connector terminal 1 Pin1 and the power connector terminal 2 Pin2 of all chips on the wafer, and between the power connector terminal 2 Pin2 and the power connector terminal 3 Pin3, so as to obtain the depth, density and distribution of the damage layer on the wafer.

[0044] In step S4, the relationship between the leakage current and the defect of the PN junction depletion layer 4 is shown in the following equation:

[0045] I leakage ∝N def =ρ def ×S

[0046] Where Ileakage is the leakage current intensity, ρdef is the surface density of defects, and S is the area.

[0047] In step S4, the difference between the damaged layers 3 of different wafers can also be obtained by comparing the difference between different leakage current curves.

[0048] like Fig. 9 As shown, in this embodiment, before the thinning process is performed, a pre-test is first performed by a probe to measure the initial leakage current and the thickness of the chip substrate 1-1, and then the thinning process is performed through a temporary bonding process, and then the thinned chip is tested from step S1 to step S5. The test schematic diagram is shown in FIG. Figure 7 The evaluation results are shown in Figure 8 As shown, at the beginning, as the chip substrate 1-1 becomes thinner (the initial thickness of the chip substrate 1-1 in this embodiment is >10um), the leakage current does not change much. However, when the chip substrate 1-1 is thinned to a certain thickness (<3um in this embodiment), the leakage current rises sharply, and a leakage current curve can be obtained. The characteristics of the damaged layer can be evaluated by measuring three data points on the leakage current curve, such as Figure 8 As shown in the figure, ① is the starting point of the leakage current rise, which is related to the maximum depth of the damage layer. ② is the slope of the leakage current rise, which is related to the depth distribution of the damage layer. ③ is the saturation value of the leakage current rise, which is related to the density of the damage layer.

[0049] In specific use, different leakage current curves can be obtained when different grinding processes are used. By comparing the differences in the leakage current curves, the differences in the damaged layers can be obtained.

Claims

1. A method for evaluating a damaged layer of a wafer backside thinning process, characterized in that: The steps include: S1, forming a plurality of PN junctions (2) distributed in an array on the surface of each chip (1) of a wafer; The PN junction (2) includes an N-type well (2-1) and a P-type well (2-2), and the N-type well (2-1) and the P-type well (2-2) are respectively arranged on the chip substrate (1-1), and the P-type well (2-2) is located in the N-type well (2-1); A power connector terminal 1 (Pin1) is provided on the chip substrate (1-1), a power connector terminal 2 (Pin2) is provided on the N-type well (2-1), and a power connector terminal 3 (Pin3) is provided on the P-type well (2-2); S2, thinning the chip (1); S3, connect a reverse voltage between the power connector terminal 1 (Pin1) and the power connector terminal 2 (Pin2), and measure the change curve of the leakage current; S4, analyzing the condition of the wafer damage layer (3) through the leakage current curve.

2. The method for evaluating the damaged layer of wafer backside thinning processing according to claim 1, characterized in that: The chip substrate (1-1) is a P-type Si substrate.

3. The method for evaluating the damaged layer of wafer backside thinning processing according to claim 1, characterized in that: The depth of the N-type well (2-1) is greater than that of the P-type well (2-2), and the P-type well (2-2) is contained in the N-type well (2-1).

4. The method for evaluating a damaged layer caused by wafer backside thinning according to claim 1, characterized in that: Isolation grooves (2-3) are provided between adjacent PN junctions (2).

5. The method for evaluating a damaged layer caused by wafer backside thinning according to claim 1, characterized in that: In the step S4, the relationship between the leakage current and the defect of the PN junction depletion layer (4) is as follows: I leakage ∝N def =ρ def ×S Among them I leakage is the leakage current intensity, ρ def is the surface density of defects, and S is the area.

6. The method for evaluating a damaged layer caused by wafer backside thinning according to claim 1, characterized in that: In the step S4, the difference between different leakage current curves is compared to obtain the difference between different wafer damaged layers (3).

7. The method for evaluating a damaged layer caused by wafer backside thinning according to claim 1, characterized in that: The method further comprises step S5, wherein a reverse voltage is connected between power connector terminal 2 (Pin2) and power connector terminal 3 (Pin3), a leakage current variation curve is measured, and the condition of the wafer damage layer (3) is analyzed through the leakage current curve.

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