Chip bonding estimation method

Abstract

The invention discloses a chip bonding estimation method. The chip bonding estimation method comprises the steps that a chip is provided, the chip is provided with a plurality of contacts, and the sum of the areas when the end faces of the plurality of contacts are orthographically projected on a plane is defined as a preset area; performing three-dimensional imaging on the plurality of end surfaces of the chip by an optical module, and transmitting a signal to a processing module to obtain a three-dimensional structure surface corresponding to the plurality of end surfaces in shape; the processing module obtains a cross section at a pre-estimated depth according to the three-dimensional structure surface, and the area of the cross section is defined as a pre-estimated welding area; and dividing the pre-estimated welding area by the preset area through the processing module to obtain a joint pre-estimated value. Therefore, the bonding estimation value obtained by the chip bonding estimation method is not restricted by the coplanarity specification of the solid-state technology association, and the welding effects of all chip types can be effectively evaluated.

Description

Technical Field

[0001] The present invention relates to a chip measurement method, and in particular to a chip bonding estimation method. Background Art

[0002] The existing chip coplanarity measurement method adopts the specifications of the Joint Electric Devices Association (JEDEC) (such as JEDEC22-B108B), which is mainly built on the measurement of Ball Grid Array (BGA) packaged or Pin Grid Array (PGA) packaged chips to evaluate the chip welding effect. However, with the evolution of chip technology, the existing chip coplanarity measurement method has gradually become difficult to accurately evaluate the welding effect of all chip types, such as Land Grid Array (LGA) packaged chips.

[0003] Therefore, the inventors believe that the above defects can be improved, and have devoted themselves to research and applied scientific principles, and finally proposed the present invention which has a reasonable design and effectively improves the above defects. Summary of the invention

[0004] The purpose of the embodiment of the present invention is to provide a chip bonding prediction method, which can effectively improve the defects that may be caused by the existing chip coplanarity measurement method.

[0005] The embodiment of the present invention discloses a chip joint estimation method, which includes: a pre-step: providing a chip having a plurality of contacts; wherein, when the end faces of the plurality of contacts are projected onto a plane, the sum of their areas is defined as a preset area; wherein, the plurality of contacts of the chip can be used to be respectively arranged on a plurality of solders located on a circuit board, so that the plurality of end faces have a welding area in contact with the plurality of solders; wherein, the chip joint estimation method defines a joint value, which is a ratio of the welding area divided by the preset area; an imaging step: using an optical module to perform stereoscopic imaging of the end faces of the plurality of contacts of the chip, and transmitting signals to a processing module, so as to obtain a three-dimensional facet with a shape corresponding to the plurality of end faces; an estimation step: using the processing module to obtain a cross section of the chip at an estimated depth according to the three-dimensional facet, and the area of ​​the cross section is defined as an estimated welding area; and a judgment step: using the processing module to obtain a joint estimation value by dividing the estimated welding area by the preset area.

[0006] Preferably, the processing module presents the three-dimensional surface in the form of point cloud data.

[0007] Preferably, the optical module includes: a light projector, which emits a structured light based on interference fringes toward multiple contacts of the chip during the imaging step; and multiple light receivers, which receive the structured light reflected by the chip during the imaging step to obtain a signal.

[0008] Preferably, the packaging structure of the chip is further limited to a planar grid array package; wherein, the implementation of the estimation step is further carried out by the processing module obtaining the depression with the largest depth in each contact according to the three-dimensional surface; the implementation of the judgment step is further carried out by the processing module defining the distance between the depression with the largest depth in multiple contacts and the cross section located at the estimated depth as a coplanarity estimation value.

[0009] Preferably, the chip has a package body covering the plurality of contacts, and the end surfaces of the plurality of contacts are exposed from the package body but do not protrude from the bottom edge of the package body.

[0010] Preferably, the chip bonding estimation method further includes in the pre-step: providing a chip measurement device, which includes an optical module, a processing module and at least one carrier module; wherein, at least one carrier module includes: a carrier platform; and an optical glass, which is installed on the carrier platform, and the optical glass has a carrier plane and a light incident surface located on opposite sides; wherein, the carrier plane can be used to set multiple contacts of the chip so that the end face of each contact faces the carrier plane; wherein, the optical module is set corresponding to the light incident surface of the optical glass.

[0011] Preferably, at least one of the carrier modules includes a chip fixture detachably mounted on the carrier platform, which includes two movable pieces; wherein the relative positions of the two movable pieces can be changed relative to the carrier platform to form a retaining groove for accommodating the chip.

[0012] Preferably, the optical glass defines a length direction, and the carrying plane can accommodate multiple chips along the length direction.

[0013] An embodiment of the present invention also discloses a chip bonding estimation method, which includes: a pre-step: providing a chip, which has multiple contacts, wherein when the end faces of the multiple contacts are projected onto a plane, the sum of their areas is defined as a preset area; an imaging step: using an optical module to perform stereoscopic imaging of the end faces of the multiple contacts of the chip, and transmitting signals to a processing module to obtain a three-dimensional surface whose shape corresponds to the multiple end faces; an estimation step: using the processing module to obtain a cross-section of the chip at an estimated depth based on the three-dimensional surface, and its area is defined as an estimated welding area; and a judgment step: using the processing module to divide the estimated welding area by the preset area to obtain a bonding estimation value.

[0014] Preferably, the processing module presents a three-dimensional surface in the form of point cloud data; wherein the optical module includes: a light projector, which emits a structured light based on interference fringes toward multiple contacts of the chip during the imaging step; and multiple light receivers, which receive the structured light reflected by the chip during the imaging step to obtain a signal.

[0015] To sum up, the chip bonding prediction method disclosed in the embodiment of the present invention can estimate the bonding prediction value of the chip in advance by obtaining the three-dimensional configuration surface corresponding to the multiple end faces before the chip is welded, and then evaluate whether the chip should continue the subsequent welding operation, so as to improve the product yield after the welding operation is implemented.

[0016] Furthermore, the chip bonding estimation method disclosed in the embodiment of the present invention obtains the bonding estimation value of the chip, which is not constrained by the coplanarity standard of the Solid State Technology Association and can effectively evaluate the welding effect of all chip types.

[0017] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and are not intended to limit the protection scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 1 is a schematic diagram of a chip bonding estimation method according to an embodiment of the present invention.

[0019] Figure 2 for Figure 1 A three-dimensional schematic diagram of the preceding steps in .

[0020] Figure 3 for Figure 2 Schematic diagram of local decomposition in .

[0021] Figure 4 FIG. 1 is a schematic diagram for explaining the bonding value according to an embodiment of the present invention. FIG.

[0022] Figure 5 FIG. 2 is a schematic diagram for explaining the bonding value according to an embodiment of the present invention. FIG.

[0023] Figure 6 for Figure 1 Schematic diagram of the imaging steps in .

[0024] Figure 7 for Figure 6 Schematic enlargement of region VII.

[0025] Figure 8 for Figure 1 Schematic diagram of the estimation steps in .

[0026] Fig. 9 for Figure 8 A partial schematic diagram of . DETAILED DESCRIPTION

[0027] The following is an explanation of the implementation of the "chip bonding estimation method" disclosed in the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0028] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0029] See also Figures 1 to 9 As shown, it is an embodiment of the present invention. This embodiment discloses a chip bonding estimation method S100, which sequentially includes a pre-step S110, an imaging step S120, an estimation step S130 and a judgment step S140, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, any one of the above-mentioned multiple steps S110 to S140 can be adjusted and changed according to actual needs. The following then sequentially describes each of the steps of the chip bonding estimation method S100.

[0030] The preceding step S110: Figures 1 to 5 As shown, a chip 200 and a chip measuring device 100 for measuring the chip 200 are provided. In this embodiment, the number of the chip 200 is one to introduce the connection relationship between it and the chip measuring device 100, and the chip bonding estimation method S100 is to implement the remaining steps (such as: the imaging step S120, the estimation step S130 and the judgment step S140) by the chip measuring device 100, so as to estimate the bonding value of the chip 200 before the chip 200 is soldered to a circuit board 300, but the present invention is not limited thereto.

[0031] For example, in other embodiments not shown in the present invention, the chip bonding estimation method S100 (or the chip measuring device 100) can be used to simultaneously estimate the bonding values ​​of multiple chips 200; or, the chip bonding estimation method S100 can be implemented by a device different from the chip measuring device 100; or, the chip measuring device 100 can also be used alone (e.g., sold).

[0032] It should be noted that the coplanarity specification (e.g., JEDEC22-B108B) of the Solid State Technology Association (JEDEC) is actually irrelevant to the bonding condition between the chip and the solder. Therefore, the definition of the bonding value used in this embodiment is different from the coplanarity specification of the Solid State Technology Association, so as to more accurately present the welding condition of the chip 200, as described below:

[0033] The chip 200 has a plurality of contacts 201, and when the end faces 2011 of the plurality of contacts 201 are projected onto a plane, the sum of their areas is defined as a preset area. The plurality of contacts 201 of the chip 200 can be used to be respectively disposed on a plurality of solders 400 located on the circuit board 300, so that the plurality of end faces 2011 have a soldering area contacting the plurality of solders 400. Furthermore, the chip joint estimation method S100 defines the joint value, which is a ratio of the soldering area divided by the preset area.

[0034] It should be additionally explained that the package structure of the chip 200 can be further limited to a land grid array (LGA) package, and each of the contacts 201 is a solder pad. In more detail, the chip 200 has a package body 202 covering a plurality of the contacts 201, and the end faces 2011 of the plurality of the contacts 201 are exposed from the package body 202 but do not protrude from the bottom edge of the package body 202, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the chip 200 can also adopt other types of package structures, such as: a ball grid array (BGA) package structure, in which the contact 201 is a solder ball; or a pin grid array (PGA) package structure, in which the contact 201 is a pin.

[0035] To facilitate understanding of the present embodiment, the chip measurement device 100 is described below, which includes a support frame 1, two carrying modules 2 respectively installed at two ends of the support frame 1, a lateral transfer mechanism 3 located inside the support frame 1, an optical module 4 installed on the lateral transfer mechanism 3 and located inside the support frame 1, and a processing module 5 (such as a processor or a computer) electrically coupled to the optical module 4.

[0036] It should be noted that, although the chip measuring device 100 is described in this embodiment as including the above-mentioned components, the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the number of the carrier module 2 included in the chip measuring device 100 can be at least one, and the support frame 1 is correspondingly adjusted to be L-shaped; or, the chip measuring device 100 can omit the lateral transfer mechanism 3 so that the optical module 4 does not move; or, the chip measuring device 100 can also omit the support frame 1 and the lateral transfer mechanism 3, and at least one of the carrier module 2 and the optical module 4 is installed on other components.

[0037] In addition, since the two carrier modules 2 in this embodiment adopt substantially the same structure, and the two carrier modules 2 are also installed substantially symmetrically (e.g., the two carrier modules 2 are arranged facing each other), for the convenience of describing this embodiment, the structure of a single carrier module 2 will be described below, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the chip measurement device 100 may also include a plurality of carrier modules 2 with slightly different structures.

[0038] The carrier module 2 in this embodiment includes a plate-shaped carrier platform 21 (which can also be regarded as an additional circuit board), a longitudinal transfer mechanism 22 connected to the carrier platform 21 and mounted on the support frame 1, an optical glass 23 mounted on the carrier platform 21, and a chip fixture 24 detachably mounted on the carrier platform 21, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the longitudinal transfer mechanism 22 and / or the chip fixture 24 of the carrier module 2 can be omitted or replaced by other components; or, the carrier module 2 can also use a non-plate-shaped carrier platform 21.

[0039] In this embodiment, the carrier 21 includes a first surface 211 and a second surface 212 located on opposite sides, and the carrier 21 is formed with a through hole 213 extending from the first surface 211 to the second surface 212. The through hole 213 of the carrier 21 is elongated in this embodiment and defines a length direction D, and the through hole 213 is preferably formed by recessing an end of the carrier 21 away from the longitudinal transfer mechanism 22. More specifically, the carrier 21 is formed by recessing the first surface 211 to form a ring-shaped receiving groove 214 surrounding the through hole 213.

[0040] Furthermore, the carrier 21 is mounted on the longitudinal transfer mechanism 22, and the longitudinal transfer mechanism 22 can move the carrier 21 along a translation direction H perpendicular to the longitudinal direction D (and the plumb direction V). The carrier 21 is mounted on the longitudinal transfer mechanism 22 at a portion where the through hole 213 is not formed, so that the portion of the carrier 21 where the through hole 213 is formed is suspended.

[0041] It should be additionally explained that, since the carrier 21 is non-translucent in this embodiment, the carrier 21 is formed with the through hole 213 to facilitate the combination with other components to achieve the measurement of the chip 200, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the carrier 21 may also be translucent and not have the through hole 213.

[0042] The optical glass 23 in this embodiment is a transparent flat plate structure, and the optical glass 23 has a supporting plane 231 and a light incident surface 232 located on opposite sides. The light incident surface 232 in this embodiment is also planar, and the shape of the light incident surface 232 is equal to the shape of the supporting plane 231, but the present invention is not limited to this.

[0043] The position of the optical glass 23 corresponds to the through hole 213 (eg, the optical glass 23 is disposed in the receiving groove 214 of the support platform 21), and the optical glass 23 preferably completely covers one side of the through hole 213 (eg, Figure 3 For example, in other embodiments not shown in the present invention, the optical glass 23 may also cover only a portion of the through hole 213.

[0044] Furthermore, the carrying plane 231 can be used to arrange multiple contacts 201 of at least one chip 200, so that the end surface 2011 of each contact 201 faces the carrying plane 231. In this embodiment, the carrying plane 231 of the optical glass 23 is perpendicular to the plumb direction V, and the optical glass 23 is a long strip structure parallel to (or defines) the length direction D, so that the carrying plane 231 can accommodate multiple chips 200 along the length direction D.

[0045] It should be additionally explained that, although the optical glass 23 is described as a flat glass in this embodiment, in other embodiments not shown in the present invention, the supporting plane 231 may only occupy a partial surface of the optical glass 23, and the area of ​​the optical glass 23 outside the supporting plane 231 may be non-planar.

[0046] The chip fixture 24 is installed on the first surface 211 of the carrier 21, so that the optical glass 23 is clamped between the carrier 21 and the chip fixture 24. The chip fixture 24 includes two movable pieces 241, and the relative positions of the two movable pieces 241 can be changed relative to the carrier 21 to form at least one holding groove 242 for accommodating at least one chip 200.

[0047] In this embodiment, the relative movement direction of the two movable pieces 241 is perpendicular to the length direction D and the plumb direction V, and the number of the holding grooves 242 formed by the two movable pieces 241 being assembled together is multiple, and the positions thereof correspond to the carrying plane 231. In other words, the multiple chips 200 disposed on the carrying plane 231 along the length direction D can be clamped by the two movable pieces 241 and positioned in the multiple holding grooves 242 respectively.

[0048] The above is a structural description of a single carrier module 2, and the following will introduce other structures of the chip measurement device 100 and the connection relationship between the two carrier modules 2. The optical module 4 is installed on the lateral transfer mechanism 3 and is arranged corresponding to the light incident surface 232 of the optical glass 23, and the lateral transfer mechanism 3 can make the optical module 4 face the light incident surface 232 of the optical glass 23 and move along the length direction D.

[0049] That is, the optical module 4 can selectively move to the bottom of any chip 200 carried by any of the carrying modules 2 through the lateral transfer mechanism 3. Accordingly, the optical module 4 can measure the multiple contacts 201 of at least one of the chips 200 disposed on the carrying plane 231 through the through holes 213.

[0050] In this embodiment, the optical module 4 includes a positioning bracket 41 installed on the lateral transfer mechanism 3, and a light projector 42 and a plurality of light receivers 43 installed and fixed on the positioning bracket 41. The light projector 42 and the plurality of light receivers 43 are arranged in a row along the length direction D. That is, the arrangement direction of the plurality of light receivers 43 is parallel to the length direction D of the optical glass 23, and the relative movement direction of the two movable sheets 241 is perpendicular to the arrangement direction of the plurality of light receivers 43.

[0051] The above is the description of the pre-step S110. The following will introduce other steps of the chip bonding estimation method S100. The image capturing step S120: Figure 1 , Figure 6 and Figure 7 As shown (please also refer to Figure 2 and Figure 3 ), use the optical module 4 to take a three-dimensional image of the end faces 2011 of the multiple contacts 201 of the chip 200, and transmit the signal to the processing module 5 to obtain the three-dimensional surface S whose shape corresponds to the multiple end faces 2011.

[0052] Specifically, the light projector 42 (in the imaging step S120) emits a structured light L based on interference fringes toward the plurality of contacts 201 of at least one chip 200, and the plurality of light receivers 43 (in the imaging step S120) receive the structured light L reflected by at least one chip 200 to obtain the signal; the processing module 5 presents the three-dimensional surface S in the form of point cloud data (e.g., Figure 8 ), which can be displayed on a screen (not shown), but the present invention is not limited to the above. That is to say, in other embodiments not shown in the present invention, the imaging step S120 can obtain the three-dimensional surface S through various imaging methods according to actual needs.

[0053] The estimation step S130: Figure 1 , Figure 8 and Fig. 9 As shown (please also refer to Figure 2 and Figure 3 ), the processing module 5 obtains a cross section S1 at an estimated depth according to the three-dimensional plane S, and its area is defined as an estimated welding area. In this embodiment, the estimated depth refers to: the contact 201 of the chip 200 may be connected to the corresponding solder 400 (such as: Figure 5 ) depth.

[0054] In addition, the definition of the preset area can also be adjusted according to design requirements; for example, the default area can be the total surface area corresponding to the plurality of end faces 2011 obtained by the processing module 5 through the three-dimensional surface S.

[0055] The judgment step S140: Figures 1 to 5 As shown, the processing module 5 divides the estimated welding area by the preset area to obtain an estimated bonding value, which is used to preliminarily evaluate whether the chip 200 is qualified. In this embodiment, the estimated bonding value refers to: estimating the proportion of the plurality of contacts 201 of the chip 200 connected to the plurality of solders 400 after the chip 200 is soldered to the circuit board 300.

[0056] Furthermore, the qualification standard of the estimated joining value can be adjusted according to actual needs; for example, for automotive products, the qualification standard of the estimated joining value is preferably not less than 90%, while for general products, the qualification standard of the estimated joining value can be not less than 70%.

[0057] Accordingly, the chip bonding estimation method S100 in this embodiment can estimate the bonding estimation value of the chip 200 in advance by obtaining the three-dimensional configuration surface S corresponding to the multiple end surfaces 2011 before the chip 200 is soldered to the multiple solders 400 of the circuit board 300, and then evaluate whether the chip 200 is to continue the subsequent welding operation, so as to improve the product yield after the welding operation is implemented.

[0058] Furthermore, the bonding estimation value of the chip 200 obtained by the chip bonding estimation method S100 in this embodiment is not restricted by the coplanarity standard of the Solid State Technology Association and can effectively evaluate the welding effects of all chip types.

[0059] In addition, the chip measurement device 100 in this embodiment can facilitate obtaining the three-dimensional surface S corresponding to the multiple end faces 2011 through the mutual matching of multiple components (such as: the corresponding configuration between the light projector 42, the multiple light receivers 43 and the optical glass 23), so that the chip measurement device 100 is suitable for various types of chip measurements. Among them, the chip measurement device 100 in this embodiment can also be further provided with the chip fixture 24 so that the chip 200 can be measured in a stable state, so as to effectively improve the accuracy of the three-dimensional surface S.

[0060] It should be additionally explained that the chip bonding estimation method S100 of this embodiment can be further implemented in the estimation step S130 as follows: the processing module 5 obtains the depression P with the largest depth in each of the contacts 201 according to the three-dimensional surface S (e.g.: Fig. 9 ). Furthermore, the determination step S140 is further implemented as follows: the processing module 5 defines a distance between the depression P having the maximum depth among the plurality of contacts 201 and the cross section S1 located at the estimated depth as a coplanarity estimation value.

[0061] In addition, the bonding estimate value in this embodiment can be obtained by first obtaining the coplanarity estimate value and then calculating and inferring, but the present invention is not limited thereto. For example, the bonding estimate value can also be obtained without the coplanarity estimate value; or, the method of obtaining the bonding estimate value can be adjusted according to design requirements.

[0062] Accordingly, the chip bonding estimation method S100 can also provide the coplanarity estimation value that is more familiar to those who are accustomed to using the coplanarity specification of the Solid State Technology Association. Furthermore, the chip bonding estimation method S100 can also reflect the defects that may occur in the production process of each contact 201 of the chip 200 based on the obtained recess P of each contact 201, thereby facilitating the improvement of the production yield of the chip 200.

[0063] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the patent scope of the present invention.

Claims

1. A chip bonding estimation method, characterized in that: The chip bonding estimation method comprises: A pre-step: providing a chip having a plurality of contacts; wherein when the end faces of the plurality of contacts are projected onto a plane, the sum of their areas is defined as a preset area; wherein the plurality of contacts of the chip can be used to be respectively disposed on a plurality of solders located on a circuit board, so that the plurality of end faces have a soldering area contacting the plurality of solders; wherein the chip bonding estimation method defines a bonding value, which is a ratio of the soldering area divided by the preset area; An imaging step: using an optical module to perform stereoscopic imaging of the end faces of the plurality of contacts of the chip, and transmitting a signal to a processing module to obtain a three-dimensional surface having a shape corresponding to the plurality of end faces; An estimation step: using the processing module to obtain a cross section of the three-dimensional surface at an estimated depth, and the area of ​​the cross section is defined as an estimated welding area; and A determination step: by the processing module, dividing the estimated welding area by the preset area to obtain a joint estimation value.

2. The chip bonding estimation method according to claim 1, characterized in that: The processing module presents the three-dimensional surface in the form of point cloud data.

3. The chip bonding estimation method according to claim 2, characterized in that: The optical module comprises: a light projector, which emits a structured light based on interference fringes toward the plurality of contacts of the chip during the imaging step; and A plurality of light receivers receive the structured light reflected by the chip during the imaging step to obtain the signal.

4. The chip bonding estimation method according to claim 1, characterized in that: The packaging structure of the chip is further defined as a planar grid array package; wherein, the implementation of the estimation step is further carried out by the processing module obtaining the depression with the largest depth in each of the contacts according to the three-dimensional surface; the implementation of the judgment step is further carried out by the processing module defining the distance between the depression with the largest depth among the multiple contacts and the cross section located at the estimated depth as a coplanarity estimation value.

5. The chip bonding estimation method according to claim 4, characterized in that: The chip has a package body covering the plurality of contacts, and the end surfaces of the plurality of contacts are exposed from the package body but do not protrude from the bottom edge of the package body.

6. The chip bonding estimation method according to claim 1, characterized in that: The chip bonding estimation method further comprises in the preceding step: providing a chip measurement device, which comprises the optical module, the processing module and at least one carrier module; wherein at least one of the carrier modules comprises: a loading platform; and An optical glass is mounted on the carrier platform, and the optical glass has a carrier plane and a light incident surface located on opposite sides; wherein the carrier plane can be used for arranging the plurality of contacts of the chip so that the end surface of each contact faces the carrier plane; Wherein, the optical module is arranged corresponding to the light incident surface of the optical glass.

7. The chip bonding estimation method according to claim 6, characterized in that: At least one of the carrier modules includes a chip fixture detachably mounted on the carrier platform, which includes two movable pieces; wherein the relative positions of the two movable pieces can be changed relative to the carrier platform to form a retaining groove for accommodating the chip.

8. The chip bonding estimation method according to claim 6, characterized in that: The optical glass is defined with a length direction, and the carrying plane can accommodate a plurality of the chips to be arranged along the length direction.

9. A chip bonding estimation method, characterized in that: The chip bonding estimation method comprises: A pre-step: providing a chip having a plurality of contacts, wherein when the end surfaces of the plurality of contacts are projected onto a plane, the sum of their areas is defined as a preset area; An imaging step: using an optical module to perform stereoscopic imaging of the end faces of the plurality of contacts of the chip, and transmitting a signal to a processing module to obtain a three-dimensional surface having a shape corresponding to the plurality of end faces; An estimation step: using the processing module to obtain a cross section of the three-dimensional surface at an estimated depth, and the area of ​​the cross section is defined as an estimated welding area; and A determination step: by the processing module, dividing the estimated welding area by the preset area to obtain a joint estimation value.

10. The chip bonding estimation method according to claim 9, characterized in that: The processing module presents the three-dimensional surface in the form of point cloud data; wherein the optical module includes: a light projector, which emits a structured light based on interference fringes toward the plurality of contacts of the chip during the imaging step; and A plurality of light receivers receive the structured light reflected by the chip during the imaging step to obtain the signal.

Images