Semiconductor process method and semiconductor device

Abstract

The invention provides a semiconductor process method and a semiconductor device, and the method comprises the steps: providing an SOI substrate which comprises bottom silicon, a buried oxide layer and top silicon which are stacked; forming a plurality of regions with different ion implantation states on the surface of the top silicon; an oxide layer is grown on the surface of the top silicon by consuming the top silicon, and the depths of the top silicon consumed in regions with different ion implantation states are different, so that the thicknesses of the oxide layers correspondingly grown in the different regions are different; and removing the oxide layer, and forming regions with different thicknesses on the top silicon. According to the invention, impurity doping and thermal oxidation are combined, and different top silicon thicknesses are realized on the SOI substrate. Ion implantation is firstly carried out in different device areas, the local silicon thermal oxidation rate is adjusted, and finally top layer silicon with different thicknesses is obtained. According to the invention, a conventional SOI process is used, so that an SOI substrate region of local top silicon with different thicknesses is effectively formed, and a mixed SOI process integrated structure is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor process method and a semiconductor device. Background Art

[0002] SOI (Silicon on Insulator) includes stacked bottom silicon, buried oxide layer and top silicon. Currently, traditional SOI wafers are manufactured for devices with top silicon thickness; and devices of different process modules require different top silicon thicknesses due to differences in operating voltage, etc. From the perspective of process integration, it is necessary to be able to manufacture devices with different top silicon thicknesses and operating voltages on the same wafer. On the other hand, for RF devices, different top silicon thicknesses have a greater impact on the off capacitance Coff of the RF switch. As the thickness of the top silicon increases, the off capacitance Coff increases significantly, which can be used to optimize the performance of the RF switch. Therefore, a suitable method is needed to produce top silicon with different thicknesses on a wafer. Summary of the invention

[0003] The purpose of the present invention is to provide a semiconductor process method and a semiconductor device. The present invention combines impurity doping and thermal oxidation to achieve different top silicon thicknesses on an SOI substrate. By first performing ion implantation in different device regions and adjusting the local silicon thermal oxidation rate, top silicon with different thicknesses is finally obtained. The present invention uses conventional SOI technology to effectively form SOI substrate regions with locally different top silicon thicknesses, thereby realizing a hybrid SOI process integrated structure.

[0004] The present invention provides a semiconductor process method, comprising:

[0005] Providing an SOI substrate, wherein the SOI substrate comprises a stacked bottom silicon layer, a buried oxide layer and a top silicon layer;

[0006] forming a plurality of regions with different ion implantation states on the top silicon surface;

[0007] Growing an oxide layer on the surface of the top silicon by consuming the top silicon, wherein the depths of consuming the top silicon are different in regions with different ion implantation states, so that the thicknesses of the oxide layers grown in different regions are different;

[0008] The oxide layer is removed and the top silicon layer forms regions of different thicknesses.

[0009] Furthermore, the plurality of regions include: a first region, a second region and a third region.

[0010] Furthermore, the first region is not doped, phosphorus ions are implanted into the second region and the third region, and the doping concentration of the second region is less than the doping concentration of the third region.

[0011] Furthermore, the dose of phosphorus ion implantation in the second region is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of phosphorus ion implantation in the third region is 3e15 / cm 2 to 8e15 / cm 2 The energy is between 20KeV and 100Kev.

[0012] Furthermore, the first region is not doped, the second region and the third region are both implanted with boron ions, and the doping concentration of the second region is less than the doping concentration of the third region;

[0013] The dosage of boron ion implantation in the second region is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of boron ion implantation in the third region is 3e15 / cm 2 to 8e15 / cm 2 The energy is between 20KeV and 100Kev.

[0014] Furthermore, the first region is not doped, phosphorus ions are implanted into the second region, boron ions are implanted into the third region, and the doping concentration of the second region is less than the doping concentration of the third region.

[0015] Furthermore, the first region, the second region and the third region are all doped and the doping concentration gradually increases.

[0016] Furthermore, the semiconductor process method specifically includes:

[0017] forming a first photoresist layer on the surface of the top silicon layer, wherein the first photoresist layer exposes the second region; performing a first ion implantation in the second region; and removing the first photoresist layer;

[0018] forming a second photoresist layer on the surface of the top silicon layer, wherein the second photoresist layer exposes the third region; performing a second ion implantation on the third region; and removing the second photoresist layer;

[0019] Growing the oxide layers of different thicknesses in the first region, the second region, and the third region;

[0020] The oxide layer is removed, and the top silicon layer is formed to have different thicknesses in the first region, the second region, and the third region.

[0021] Furthermore, the top silicon layer forms at least two regions with different thicknesses.

[0022] The present invention also provides a semiconductor device, which is formed by the above method, comprising:

[0023] An SOI substrate, wherein the SOI substrate comprises a stacked bottom silicon layer, a buried oxide layer and a top silicon layer;

[0024] The top silicon layer is formed with regions of varying thicknesses.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention provides a semiconductor process method and a semiconductor device, comprising: providing an SOI substrate, the SOI substrate comprising a stacked bottom silicon, a buried oxide layer and a top silicon; forming a plurality of regions with different ion implantation states on the surface of the top silicon; growing an oxide layer on the surface of the top silicon by consuming the top silicon, the regions with different ion implantation states consuming the top silicon at different depths, so that the thickness of the oxide layer grown in each region is different; removing the oxide layer, and forming regions with different thicknesses of the top silicon. The present invention combines impurity doping and thermal oxidation to achieve different top silicon thicknesses on the SOI substrate. By first performing ion implantation in different device regions and adjusting the local silicon thermal oxidation rate, top silicon with different thicknesses is finally obtained. The present invention uses conventional SOI technology to effectively form SOI substrate regions with locally different top silicon thicknesses, thereby realizing a hybrid SOI process integrated structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The present invention is a schematic diagram of a semiconductor process method according to an embodiment of the present invention.

[0028] Figure 2 Schematic diagram of an SOI substrate in a semiconductor process method according to an embodiment of the present invention.

[0029] Figure 3 It is a schematic diagram of performing a first ion implantation in the second region b in the semiconductor process method according to an embodiment of the present invention.

[0030] Figure 4 It is a schematic diagram of removing the first photoresist layer in the semiconductor process method according to an embodiment of the present invention.

[0031] Figure 5 It is a schematic diagram of performing a second ion implantation in the third region c in the semiconductor process method according to an embodiment of the present invention.

[0032] Figure 6 It is a schematic diagram of forming three regions with different ion implantation states in a first region a, a second region b and a third region c in a semiconductor process method according to an embodiment of the present invention.

[0033] Figure 7 It is a schematic diagram of growing an oxide layer on the top silicon surface in the semiconductor process method according to an embodiment of the present invention.

[0034] Figure 8 Schematic diagram of the oxide layer growth model.

[0035] Fig. 9 Schematic diagram after removing the oxide layer.

[0036] The reference numerals are as follows:

[0037] 11-bottom silicon; 12-buried oxide layer; 13-top silicon; a-first region; b-second region; c-third region; 14-first photoresist layer; 15-second photoresist layer; 16-oxide layer. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0039] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0040] The embodiment of the present invention provides a semiconductor process method, such as Figure 1 As shown, including:

[0041] Step S1, providing an SOI substrate, wherein the SOI substrate comprises a stacked bottom silicon layer, a buried oxide layer and a top silicon layer;

[0042] Step S2, forming a plurality of regions with different ion implantation states on the top silicon surface;

[0043] Step S3, growing an oxide layer on the surface of the top silicon by consuming the top silicon, wherein the depths of the top silicon consumed in regions with different ion implantation states are different, so that the thicknesses of the oxide layers grown in different regions are different;

[0044] Step S4, removing the oxide layer, and forming regions of different thicknesses on the top silicon layer.

[0045] The steps of the semiconductor process method according to the embodiment of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Step S1: Figure 2 As shown, a SOI (silicon on insulator) substrate is provided, and the SOI substrate includes a stacked bottom silicon 11, a buried oxide layer 12, and a top silicon 13. The material of the bottom silicon 11 includes silicon, silicon carbide, silicon germanium, or other suitable semiconductor materials. The material of the buried oxide layer 12 includes silicon dioxide or other suitable dielectric materials. The material of the top silicon 13 includes silicon, silicon carbide, silicon germanium, or other suitable semiconductor materials.

[0047] Step S2: forming several regions with different ion implantation states on the surface of the top silicon 13. Figure 3 As shown, the plurality of regions include, for example, a first region a, a second region b, and a third region c. A first photoresist layer 14 is formed on the surface of the top silicon 13, and the first photoresist layer 14 exposes the second region b; and a first ion implantation is performed in the second region b. Figure 4 As shown, the first photoresist layer 14 is removed. Figure 5 As shown, a second photoresist layer 15 is formed on the silicon surface of the top layer 13, and the second photoresist layer 15 exposes the third region c. Figure 6 As shown, a second ion implantation is performed in the third region c to remove the second photoresist layer 15. In this way, three regions with different ion implantation states are formed in the first region a, the second region b and the third region c. This example is described by taking three regions with different ion implantation states as an example, and the number of regions with different ion implantation states is not limited and can be set according to actual needs.

[0048] Step S3: Figure 7 As shown, an oxide layer 16 is grown on the surface of the top silicon 13 by consuming the top silicon 13 , and regions with different ion implantation states consume the top silicon 13 to different depths, so that the thickness of the oxide layer 16 grown in different regions is different.

[0049] like Figure 8 As shown, an oxide layer grows on the silicon surface. For the thermal oxidation process, the thickening of the oxide layer can be explained by the linear (linear growth zone)-parabola (diffusion-limited zone) model. The oxidation rate depends on the diffusion rate of the oxidant in SiO2 and the reaction rate with Si. Therefore, the reaction kinetics are different when the oxide layer is thinner and thicker. Different impurities are redistributed at the Si / SiO2 interface, which affects the characteristics of the oxide film: the segregation coefficient K of boron B B When it is less than 1, the strength of SiO2 network structure becomes weak. It is beneficial for the diffusion of oxidants in the SIO2 layer and increases the oxidation rate. Boron B does not significantly enhance oxidation at low temperatures, but significantly at high temperatures. The segregation coefficient K of phosphorus PP When the value is greater than 1, most of the oxidation is concentrated at the interface and in Si near the interface, which increases the linear oxidation rate in the early stage of oxidation and has little effect on the parabolic rate in the middle and late stages of oxidation. Phosphorus P significantly enhances oxidation at lower temperatures.

[0050] In the first example, when the oxidation thickness is small (for example, the oxide layer thickness range is 0nm-10nm), low temperature 800℃~900℃ dry oxygen thermal oxidation can be used. By doping phosphorus P, the surface linear oxidation rate is controlled: the first area a is not doped, the second area b and the third area c are both injected with phosphorus P ions, and the doping concentration of the second area b (lightly doped) is less than the doping concentration of the third area c (heavily doped); the dose of phosphorus P ion implantation in the second area is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of phosphorus P ion implantation in the third region is 3e15 / cm 2 to 8e15 / cm 2 The energy is between 20KeV and 100KeV. The specific energy and dose are combined according to actual needs, and are only used as examples for reference.

[0051] In the second example, when the oxidation thickness is required to be larger (for example, the oxide layer thickness is greater than 10nm), low temperature 800℃~900℃ dry oxygen thermal oxidation can be used. By doping boron B, the parabolic oxidation rate is controlled: the first region a is not doped, the second region b and the third region c are both implanted with boron ions, and the doping concentration of the second region b is less than the doping concentration of the third region c. The dose of boron B ion implantation in the second region b is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of B ion implantation in the third region c is 3e15 / cm 2 to 8e15 / cm 2 The energy is between 20KeV and 100KeV. The specific energy and dose are combined according to actual needs, and are only used as examples for reference.

[0052] In the third example, the doping combination of N-type ions and P-type ions is used. The first region a is not doped, the second region b is implanted with N-type ions, such as phosphorus P, and the third region c is implanted with P-type ions, such as boron B; the doping concentration of the second region b (lightly doped) is less than the doping concentration of the third region c (heavily doped); the dose of P ions implanted in the second region is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of ion implantation in the third region B is 3e15 / cm 2 to 8e15 / cm 2The energy is between 20KeV and 100KeV. The specific energy and dose are combined according to actual needs, and are only used as examples for reference.

[0053] In a fourth example, the first region a, the second region b and the third region c are all doped and the doping concentration gradually increases.

[0054] Step S4: Fig. 9 As shown, the oxide layer is removed, and the top silicon 13 forms areas of different thicknesses. For SOI wafers, devices of different process modules or devices of the same type need to be classified according to different performances, which require different top silicon thicknesses. The present invention proposes a process integration scheme for realizing different top silicon thicknesses on an SOI substrate, which is embodied in the idea of ​​supporting impurity doping with thermal oxidation, and the doping concentration will increase the oxidation rate. By first performing ion implantation in different device areas and adjusting the local silicon thermal oxidation rate, top silicon of different thicknesses is finally obtained. The present invention uses conventional SOI processes to effectively form SOI substrate areas with top silicon of different local thicknesses, thereby realizing a hybrid SOI process integrated structure.

[0055] The present invention also provides a semiconductor device, which is formed by the above method, such as Fig. 9 As shown, it includes: an SOI substrate, the SOI substrate includes a stacked bottom silicon layer 11, a buried oxide layer 12 and a top silicon layer 13; the top silicon layer 13 is formed with regions of different thicknesses.

[0056] In summary, the present invention provides a semiconductor process method and a semiconductor device, including: providing an SOI substrate, the SOI substrate including a stacked bottom silicon, a buried oxide layer and a top silicon; forming a plurality of regions with different ion implantation states on the surface of the top silicon; growing an oxide layer on the surface of the top silicon by consuming the top silicon, the regions with different ion implantation states consume the top silicon at different depths, so that the thickness of the oxide layer grown in different regions is different; removing the oxide layer, and the top silicon forms regions with different thicknesses. The present invention combines impurity doping and thermal oxidation to achieve different top silicon thicknesses on the SOI substrate. By first performing ion implantation in different device regions and adjusting the local silicon thermal oxidation rate, top silicon with different thicknesses is finally obtained. The present invention uses conventional SOI processes to effectively form SOI substrate regions with locally different top silicon thicknesses, thereby realizing a hybrid SOI process integrated structure.

[0057] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0058] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A semiconductor process method, characterized in that: include: Providing an SOI substrate, wherein the SOI substrate comprises a stacked bottom silicon layer, a buried oxide layer and a top silicon layer; forming a plurality of regions with different ion implantation states on the top silicon surface; Growing an oxide layer on the surface of the top silicon by consuming the top silicon, wherein the depths of consuming the top silicon are different in regions with different ion implantation states, so that the thicknesses of the oxide layers grown in different regions are different; The oxide layer is removed and the top silicon layer forms regions of different thicknesses.

2. The semiconductor process method according to claim 1, wherein: The plurality of regions include: a first region, a second region and a third region.

3. The semiconductor process method according to claim 2, wherein: The first region is not doped, and phosphorus ions are implanted into the second region and the third region. The doping concentration of the second region is lower than the doping concentration of the third region.

4. The semiconductor process method according to claim 3, wherein: The dose of phosphorus ion implantation in the second region is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of phosphorus ion implantation in the third region is 3e15 / cm 2 to 8e15 / cm 2 The energy is between 20KeV and 100Kev.

5. The semiconductor process method according to claim 2, wherein: The first region is not doped, the second region and the third region are both implanted with boron ions, and the doping concentration of the second region is less than the doping concentration of the third region; The dosage of boron ion implantation in the second region is 1e15 / cm 2 To 5e15 / cm 2 The energy is between 20KeV and 100Kev; the dose of boron ion implantation in the third region is 3e15 / cm 2 to 8e15 / cm 2 The energy is between 20KeV and 100Kev.

6. The semiconductor process method according to claim 2, wherein: The first region is not doped, phosphorus ions are implanted in the second region, boron ions are implanted in the third region, and the doping concentration of the second region is less than the doping concentration of the third region.

7. The semiconductor process method according to claim 2, wherein: The first region, the second region and the third region are all doped and the doping concentration increases gradually.

8. The semiconductor process method according to claim 2, wherein: The semiconductor process method specifically comprises: forming a first photoresist layer on the surface of the top silicon layer, wherein the first photoresist layer exposes the second region; performing a first ion implantation in the second region; and removing the first photoresist layer; forming a second photoresist layer on the surface of the top silicon layer, wherein the second photoresist layer exposes the third region; performing a second ion implantation on the third region; and removing the second photoresist layer; Growing the oxide layers of different thicknesses in the first region, the second region, and the third region; The oxide layer is removed, and the top silicon layer is formed to have different thicknesses in the first region, the second region, and the third region.

9. The semiconductor process method according to claim 2, wherein: The top silicon layer forms at least two regions with different thicknesses.

10. A semiconductor device, characterized in that: Formed by the method of any one of claims 1 to 9, comprising: An SOI substrate, wherein the SOI substrate comprises a stacked bottom silicon layer, a buried oxide layer and a top silicon layer; The top layer of silicon is formed with regions of varying thicknesses.

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