High-efficiency active heat dissipation structure of power semiconductor device and preparation method of high-efficiency active heat dissipation structure

Abstract

The invention relates to an efficient active heat dissipation structure of a power semiconductor device and a preparation method of the efficient active heat dissipation structure of the power semiconductor device, and the efficient active heat dissipation structure comprises a hot end substrate 10 containing a liquid flowing channel and a cold end substrate 16 which are parallel to each other. P-type semiconductors 17 and N-type semiconductors 18 are alternately arranged between the hot-end substrate 10 and the cold-end substrate 16 which are provided with the liquid flowing channels, and a third circuit layer 19 is arranged on the outer surface of the cold-end substrate 16 and used for being connected with a power semiconductor chip 22. The heat dissipation structure provided by the invention can greatly reduce the temperature of the substrate at the hot end of the semiconductor cooler, improve the refrigeration efficiency, avoid the problem of large contact thermal resistance caused by a thermal interface material, and realize efficient active heat dissipation of the power semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device packaging applications, and in particular to a high-efficiency active heat dissipation structure of a power semiconductor device and a preparation method thereof. Background Art

[0002] As a power switch device, power semiconductor chip is the most important component in power supply and motor control circuit. As the packaging structure of power devices develops towards high density and miniaturization, the heat flux density of power devices will increase from 100W / cm 2 Increase to 500W / cm 2 , the heat flux of the power module can reach several kW / cm 2 Excessive chip junction temperature will cause serious reliability problems in the module, including solder-ceramic delamination, cracks in the solder layer, and bond wire shedding. Therefore, it is urgent to develop suitable chip efficient heat dissipation technology.

[0003] At present, in order to control the temperature of power semiconductor chips to maximize their performance, the main heat dissipation method for power semiconductor devices is air cooling technology connected to an external radiator, which removes the heat generated by the chip through large heat dissipation fins and cooling fans. However, the capacity of air cooling is very limited and it is difficult to meet the cooling needs of high-density power devices. More and more research is gradually turning to liquid water cooling technology. This method can transfer heat from the chip to a thermal medium with high specific heat capacity, which can effectively control the junction temperature of the chip. It has the advantages of high efficiency, energy saving and environmental protection, but it still cannot avoid the problems of large size and insufficient heat dissipation efficiency. Semiconductor refrigeration technology is based on the Peltier effect of semiconductors, which can realize direct conversion from electricity to temperature difference and has great potential in the field of thermal management of power devices. Compared with traditional heat dissipation forms, the structure of semiconductor coolers is more reliable, stable and has a longer service life. However, the bottom of the hot end substrate of the existing semiconductor refrigerator still needs to be connected to a cooling fan or water cooling device to achieve heat conduction, which is large in size and requires a large space and volume in the system, reducing the integration level. In addition, the semiconductor refrigerator and the external radiator need to be connected through a thermal interface material to achieve heat conduction, which will increase the contact thermal resistance, affect the heat dissipation of the hot end substrate, reduce the cooling capacity of the semiconductor refrigerator, and thus affect the heat dissipation efficiency of the power chip. Summary of the invention

[0004] The purpose of the present invention is to provide a high-efficiency active heat dissipation structure for a power semiconductor device and a preparation method thereof. The proposed heat dissipation structure can greatly reduce the temperature of the hot end substrate of the semiconductor refrigerator, improve the cooling efficiency, avoid the problem of large contact thermal resistance caused by the thermal interface material, and realize high-efficiency active heat dissipation of the power semiconductor device.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A high-efficiency active heat dissipation structure for a power semiconductor device comprises: a hot-end substrate and a cold-end substrate containing a liquid flow channel, wherein the hot-end substrate containing the liquid flow channel is parallel to the cold-end substrate, and P-type semiconductors and N-type semiconductors are alternately arranged between the hot-end substrate and the cold-end substrate containing the liquid flow channel, and a third circuit layer is arranged on the outer surface of the cold-end substrate for connecting to a power semiconductor chip.

[0007] Optionally, the inner surface of the hot end substrate is closely attached to a first circuit layer, the inner surface of the cold end substrate is closely attached to a second circuit layer, the second circuit layer is connected to one end surface of the P-type semiconductor and the N-type semiconductor through a second solder layer, and the first circuit layer is connected to the other end surface of the P-type semiconductor and the N-type semiconductor through a first solder layer.

[0008] Optionally, the third circuit layer is connected to the power semiconductor chip through a third solder layer and a bonding wire, and is connected to the power terminal through the third solder layer.

[0009] Optionally, the liquid flow channel is circular with a diameter of 0.2-3.0 mm, and a coolant is provided in the liquid flow channel, and the coolant is one of water, mineral oil, and electronic fluorinated liquid.

[0010] Optionally, the hot end substrate and the cold end substrate are both made of ceramic material, the ceramic material is one of aluminum oxide, aluminum nitride, and silicon nitride, the hot end substrate has a thickness of 1.0 to 5.0 mm, and the cold end substrate has a thickness of 0.5 to 1.0 mm.

[0011] Optionally, the directions of the internal currents of the P-type semiconductor and the N-type semiconductor are opposite to each other, forming an upper and lower temperature difference, and the heights of the P-type semiconductor and the N-type semiconductor are both 0.8 to 2.5 mm.

[0012] Optionally, the solders of the first solder layer, the second solder layer and the third solder layer are one or more of nano-silver, nano-copper, gold-tin, tin-lead, tin-silver-copper and tin-bismuth.

[0013] The present invention also provides a method for preparing a high-efficiency active heat dissipation structure of a power semiconductor device, comprising:

[0014] Connecting a surface of the P-type semiconductor and the N-type semiconductor to a surface of a hot end substrate containing a liquid flow channel through a first solder layer through a first circuit layer;

[0015] Connecting the other surface of the P-type semiconductor and the N-type semiconductor to the second circuit layer on one surface of the cold end substrate through a second solder layer;

[0016] Connecting the power semiconductor chip and the power terminal surface to the third circuit layer on the other surface of the cold end substrate through the third solder layer;

[0017] The surface of the power semiconductor chip is electrically connected to the third circuit layer on the other surface of the cold end substrate through bonding wires to obtain a high-efficiency active heat dissipation structure for the power semiconductor device.

[0018] The beneficial effects of the present invention are as follows: In view of the problems of increased volume and increased contact thermal resistance caused by the need to connect a cooling device to the bottom of the hot-end substrate of the existing semiconductor refrigerator, the present invention proposes a technical solution of integrating a liquid flow channel inside the hot-end substrate to dissipate heat in situ. This method can greatly improve the heat dissipation efficiency of the hot-end substrate of the semiconductor refrigerator, reduce the size of the radiator and avoid the contact thermal resistance caused by the thermal interface material, thereby achieving efficient active heat dissipation at the device level. In addition, by providing a circuit layer on the top of the cold-end substrate, the present invention can directly connect the power semiconductor chip to the cold-end substrate through solder, saving the material and cost of the substrate under the power chip, and avoiding the contact thermal resistance caused by introducing too many interfaces, thereby forming an integrated solution for the power chip and the radiator. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A cross-sectional view of an active heat dissipation structure of a power semiconductor device provided by an embodiment of the present invention;

[0021] Among them, 10 is a hot end substrate containing a liquid flow channel, 11 is a liquid flow channel, 12 is a first circuit layer, 13 is a first solder layer, 14 is a second solder layer, 15 is a second circuit layer, 16 is a cold end substrate, 17 is a P-type semiconductor, 18 is an N-type semiconductor, 19 is a third circuit layer, 20 is a bonding wire, 21 is a third solder layer, 22 is a power semiconductor chip, and 23 is a power terminal. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Under normal circumstances, the heat of the hot end substrate needs to be dissipated through an external radiator, and the lower surface of the hot end substrate will be connected to the external radiator through a thermal interface material. Connecting an external radiator to achieve heat conduction is large in size, requires a large space and volume in the system, and reduces the integration; in addition, the semiconductor refrigerator and the external radiator need to be connected through a thermal interface material to achieve heat conduction, which will increase the contact thermal resistance, affect the heat dissipation of the hot end substrate, reduce the cooling capacity of the semiconductor refrigerator, and affect the heat dissipation efficiency of the power chip. Therefore, the present invention integrates a liquid cooling channel in the hot end substrate, and the liquid can directly dissipate the heat of the hot end substrate through the above-mentioned channel.

[0025] Embodiment 1:

[0026] The present embodiment provides a high-efficiency active heat dissipation structure for a power semiconductor device, comprising: a hot-end substrate 10 with a liquid flow channel and a cold-end substrate 16, wherein the hot-end substrate 10 with the liquid flow channel is parallel to the cold-end substrate 16, and there are alternatingly arranged P-type semiconductors 17 and N-type semiconductors 18 between the hot-end substrate 10 with the liquid flow channel and the cold-end substrate 16, and a third circuit layer 19 is provided on the outer surface of the cold-end substrate 16 for connecting to a power semiconductor chip 22.

[0027] Furthermore, the inner surface of the hot end substrate 10 is closely attached to the first circuit layer 12, and the inner surface of the cold end substrate 16 is closely attached to the second circuit layer 15. The second circuit layer 15 is connected to one end surface of the P-type semiconductor 17 and the N-type semiconductor 18 through the second solder layer 14, and the first circuit layer 12 is connected to the other end surface of the P-type semiconductor 17 and the N-type semiconductor 18 through the first solder layer 13.

[0028] Furthermore, the third circuit layer 19 is connected to the power semiconductor chip 22 through the third solder layer 21 and the bonding wire 20, and is connected to the power terminal 23 through the third solder layer 21. The third circuit layer 19 is composed of N unconnected sub-circuit layers. The power terminal 23 is used to connect the internal circuit layer of the power device and the external power supply device, carrying current and voltage to ensure reliable connection of the power supply system. The bonding wire 20 is used to realize the internal electrical connection of the power device to ensure that the current can be smoothly transmitted inside the power device.

[0029] Furthermore, the liquid flow channel 11 is circular with a diameter of 0.2-3.0 mm. A coolant is provided in the liquid flow channel 11, and the coolant is one of water, mineral oil, and electronic fluorinated liquid.

[0030] Furthermore, the hot end substrate 10 and the cold end substrate 16 are both made of ceramic material, and the ceramic material is one of aluminum oxide, aluminum nitride, and silicon nitride. The hot end substrate 10 has a thickness of 1.0 to 5.0 mm, and the cold end substrate 16 has a thickness of 0.5 to 1.0 mm.

[0031] Furthermore, the directions of the currents inside the P-type semiconductor 17 and the N-type semiconductor 18 are opposite, forming a temperature difference between the upper and lower parts. The heights of the P-type semiconductor 17 and the N-type semiconductor 18 are both 0.8 to 2.5 mm.

[0032] Furthermore, the solders of the first solder layer 13, the second solder layer 14, and the third solder layer 21 are one or more of nano silver, nano copper, gold tin, tin lead, tin silver copper, and tin bismuth. When the solder layer material is nano silver or nano copper, the materials of different solder layers are the same; in other cases, the materials are different because the preparation process requires three solderings, and the melting points of the solder layer materials must meet the following requirements: first solder layer> second solder layer> third solder layer.

[0033] Furthermore, the power semiconductor chip 22 is one of silicon carbide, gallium nitride, and silicon chips, and its upper surface is electrically connected to the third circuit layer on the upper surface of the cold end substrate 16 through a bonding wire 20, and the bonding wire 20 is one of aluminum wire, aluminum strip, copper wire, and copper clip.

[0034] The present invention can form an in-situ, efficient heat dissipation path by integrating liquid cooling channels. The method can greatly improve the heat dissipation efficiency of the hot end substrate of the semiconductor refrigerator, reduce the size of the heat sink and avoid the contact thermal resistance caused by the thermal interface material, thereby realizing the integrated integration of power devices and heat sinks and efficient active heat dissipation.

[0035] Embodiment 2:

[0036] like Figure 1 As shown, this embodiment provides a high-efficiency active heat dissipation structure for power devices, which includes: a hot-end substrate 10 with a liquid flow channel, a cold-end substrate 16, a P-type semiconductor 17, an N-type semiconductor 18, a power semiconductor chip 22, a power terminal 23, and a bonding wire 20. P-type semiconductors 17 and N-type semiconductors 18 are alternately arranged between the hot-end substrate 10 with a liquid flow channel and the cold-end substrate 16, and the power semiconductor chip 22 and the power terminal 23 are both attached to the upper surface of the cold-end substrate 16. The power semiconductor chip 22 dissipates heat and cools through the temperature difference generated by the P-type semiconductor 17 and the N-type semiconductor 18, and the hot-end substrate 10 dissipates heat through the liquid in the liquid flow channel 11, so as to ensure the heat dissipation efficiency of the semiconductor refrigerator and realize high-efficiency heat dissipation of the power semiconductor device.

[0037] As an implementation mode of this embodiment, the hot end substrate 10 containing the liquid flow channel has a thickness of 5 mm, the liquid flow channel 11 in the substrate is circular in shape with a diameter of 3.0 mm, and a coolant is provided in the liquid flow channel 11 in the substrate, and the coolant is water.

[0038] As an implementation of this embodiment, the cold end substrate 16 is 1.0 mm thick, the P-type semiconductor 17 and the N-type semiconductor 18 are both 1.5 mm high, the P-type semiconductor 17 and the N-type semiconductor 18 are arranged alternately, and the internal current directions are opposite, forming an upper and lower temperature difference.

[0039] As an implementation method of this embodiment, the hot end substrate 10 and the cold end substrate 16 containing the liquid flow channel are both made of ceramic material, and the ceramic material is alumina;

[0040] As an implementation of this embodiment, a first circuit layer 12 is provided on the upper surface of the hot end substrate 10 containing the liquid flow channel, and the first circuit layer 12 is connected to the lower surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 through a first solder layer 13.

[0041] As an implementation method of this embodiment, a second circuit layer 15 is arranged on the lower surface of the cold end substrate 16, and a third circuit layer is arranged on the upper surface. The second circuit layer 15 is connected to the upper surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 through the second solder layer 14, and the third circuit layer is connected to the lower surface of the power semiconductor chip 22 and the power terminal 23 through the third solder layer.

[0042] As an implementation of this embodiment, the first solder layer 13 is nano-silver, the second solder layer 14 is nano-silver, and the solder of the third solder layer is nano-silver.

[0043] As an implementation of this embodiment, the power semiconductor chip 22 is a silicon carbide chip, and its upper surface is electrically connected to the third circuit layer 19 on the upper surface of the cold end substrate 16 through a bonding wire 20, and the bonding wire 20 is an aluminum wire.

[0044] Embodiment three:

[0045] The present embodiment provides a high-efficiency active heat dissipation structure for power devices, including: a hot-end substrate 10 with a liquid flow channel, a cold-end substrate 16, a P-type semiconductor 17, an N-type semiconductor 18, a power semiconductor chip 22, a power terminal 23, and a bonding wire 20. P-type semiconductors 17 and N-type semiconductors 18 are alternately arranged between the hot-end substrate 10 with a liquid flow channel and the cold-end substrate 16, and the power semiconductor chip 22 and the power terminal 23 are both attached to the upper surface of the cold-end substrate 16. The power semiconductor chip 22 dissipates heat and cools through the temperature difference generated by the P-type semiconductor 17 and the N-type semiconductor 18, and the hot-end substrate 10 dissipates heat through the liquid in the liquid flow channel 11, so as to ensure the heat dissipation efficiency of the semiconductor refrigerator and realize high-efficiency heat dissipation of the power semiconductor device.

[0046] As an implementation mode of this embodiment, the hot end substrate 10 containing the liquid flow channel has a thickness of 3 mm, the liquid flow channel 11 in the substrate is circular in shape with a diameter of 1.0 mm, and a coolant is provided in the liquid flow channel 11 in the substrate, and the coolant is an electronic fluoride liquid;

[0047] As an implementation method of this embodiment, the cold end substrate 16 has a thickness of 0.8 mm, the P-type semiconductor 17 and the N-type semiconductor 18 are both 1 mm high, the P-type semiconductor 17 and the N-type semiconductor 18 are arranged alternately, and the internal current directions are opposite, forming an upper and lower temperature difference;

[0048] As an implementation mode of this embodiment, the hot end substrate 10 and the cold end substrate 16 containing the liquid flow channel are both made of ceramic material, and the ceramic material is aluminum nitride;

[0049] As an implementation of this embodiment, a first circuit layer 12 is provided on the upper surface of the hot end substrate 10 containing the liquid flow channel, and the first circuit layer 12 is connected to the lower surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 through a first solder layer 13;

[0050] As an implementation method of this embodiment, a second circuit layer 15 is provided on the lower surface of the cold end substrate 16, and a third circuit layer is provided on the upper surface. The second circuit layer 15 is connected to the upper surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 through a second solder layer 14, and the third circuit layer is connected to the lower surface of the power semiconductor chip 22 and the power terminal 23 through a third solder layer.

[0051] As an implementation of this embodiment, the first solder layer 13 is gold-tin, the second solder layer 14 is tin-silver-copper, and the third solder layer solder is tin-bismuth;

[0052] As an implementation of this embodiment, the power semiconductor chip 22 is a gallium nitride chip, and its upper surface is electrically connected to the third circuit layer on the upper surface of the cold end substrate 16 through a bonding wire 20, and the bonding wire 20 is a copper clip.

[0053] Embodiment 4:

[0054] The present embodiment provides a high-efficiency active heat dissipation structure for power devices, including: a hot-end substrate 10 with a liquid flow channel, a cold-end substrate 16, a P-type semiconductor 17, an N-type semiconductor 18, a power semiconductor chip 22, a power terminal 23, and a bonding wire 20. P-type semiconductors 17 and N-type semiconductors 18 are alternately arranged between the hot-end substrate 10 with a liquid flow channel and the cold-end substrate 16, and the power semiconductor chip 22 and the power terminal 23 are both attached to the upper surface of the cold-end substrate 16. The power semiconductor chip 22 dissipates heat and cools through the temperature difference generated by the P-type semiconductor 17 and the N-type semiconductor 18, and the hot-end substrate 10 dissipates heat through the liquid in the liquid flow channel 11, so as to ensure the heat dissipation efficiency of the semiconductor refrigerator and realize high-efficiency heat dissipation of the power semiconductor device.

[0055] As an implementation of this embodiment, the hot end substrate 10 containing the liquid flow channel has a thickness of 2 mm, the liquid flow channel 11 in the substrate is circular in shape with a diameter of 0.8 mm, and a coolant is provided in the liquid flow channel 11 in the substrate, and the coolant is mineral oil;

[0056] As an implementation method of this embodiment, the cold end substrate 16 has a thickness of 1 mm, the P-type semiconductor 17 and the N-type semiconductor 18 are both 2 mm high, the P-type semiconductor 17 and the N-type semiconductor 18 are arranged alternately, and the internal current directions are opposite, forming an upper and lower temperature difference;

[0057] As an implementation mode of this embodiment, the hot end substrate 10 and the cold end substrate 16 containing the liquid flow channel are both made of ceramic material, and the ceramic material is silicon nitride;

[0058] As an implementation of this embodiment, a first circuit layer 12 is provided on the upper surface of the hot end substrate 10 containing the liquid flow channel, and the first circuit layer 12 is connected to the lower surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 through a first solder layer 13;

[0059] As an implementation method of this embodiment, a second circuit layer 15 is provided on the lower surface of the cold end substrate 16, and a third circuit layer is provided on the upper surface. The second circuit layer 15 is connected to the upper surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 through a second solder layer 14, and the third circuit layer is connected to the lower surface of the power semiconductor chip 22 and the power terminal 23 through a third solder layer.

[0060] As an implementation of this embodiment, the first solder layer 13 is nano silver, the second solder layer 14 is nano silver, and the solder of the third solder layer is tin-silver-copper;

[0061] As an implementation of this embodiment, the power semiconductor chip 22 is a silicon chip, and its upper surface is electrically connected to the third circuit layer on the upper surface of the cold end substrate 16 through a bonding wire 20, and the bonding wire 20 is a copper clip.

[0062] Embodiment five:

[0063] This embodiment provides a method for preparing a high-efficiency active heat dissipation structure of a power semiconductor device, comprising:

[0064] Connecting a surface of a P-type semiconductor 17 and an N-type semiconductor 18 to a surface of a hot-end substrate 10 having a liquid flow channel through a first solder layer 13 through a first circuit layer 12;

[0065] Connect the other surfaces of the P-type semiconductor 17 and the N-type semiconductor 18 to the second circuit layer 15 on one surface of the cold end substrate 16 through the second solder layer 14;

[0066] Connect the power semiconductor chip 22 and the power terminal 23 surface to the third circuit layer on the other surface of the cold end substrate 16 through the third solder layer 21;

[0067] The surface of the power semiconductor chip 22 is electrically connected to the third circuit layer 19 on the other surface of the cold end substrate 16 through the bonding wire 20 to obtain a high-efficiency active heat dissipation structure of the power semiconductor device.

[0068] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A high-efficiency active heat dissipation structure for a power semiconductor device, characterized in that: include: A hot end substrate (10) and a cold end substrate (16) containing a liquid flow channel, wherein the hot end substrate (10) containing the liquid flow channel is parallel to the cold end substrate (16), and alternately arranged P-type semiconductors (17) and N-type semiconductors (18) are provided between the hot end substrate (10) containing the liquid flow channel and the cold end substrate (16), and a third circuit layer (19) is provided on the outer surface of the cold end substrate (16) for connecting to a power semiconductor chip (22).

2. The high-efficiency active heat dissipation structure of power semiconductor devices according to claim 1, characterized in that: The inner surface of the hot end substrate (10) is closely attached to a first circuit layer (12), and the inner surface of the cold end substrate (16) is closely attached to a second circuit layer (15); the second circuit layer (15) is connected to one end surface of the P-type semiconductor (17) and the N-type semiconductor (18) via a second solder layer (14), and the first circuit layer (12) is connected to the other end surface of the P-type semiconductor (17) and the N-type semiconductor (18) via a first solder layer (13).

3. The high-efficiency active heat dissipation structure of power semiconductor devices according to claim 2, characterized in that: The third circuit layer (19) is connected to the power semiconductor chip (22) via a third solder layer (21) and a bonding wire (20), and is connected to a power terminal (23) via the third solder layer (21).

4. The high-efficiency active heat dissipation structure of power semiconductor devices according to claim 1, characterized in that: The liquid flow channel (11) is circular and has a diameter of 0.2-3.0 mm. A coolant is provided in the liquid flow channel (11), and the coolant is one of water, mineral oil, and electronic fluoride liquid.

5. The high-efficiency active heat dissipation structure of power semiconductor devices according to claim 1, characterized in that: The hot end substrate (10) and the cold end substrate (16) are both made of ceramic material, and the ceramic material is one of aluminum oxide, aluminum nitride, and silicon nitride. The hot end substrate (10) has a thickness of 1.0 to 5.0 mm, and the cold end substrate (16) has a thickness of 0.5 to 1.0 mm.

6. The high-efficiency active heat dissipation structure for power semiconductor devices according to claim 1, characterized in that: The directions of the currents inside the P-type semiconductor (17) and the N-type semiconductor (18) are opposite, forming a temperature difference between the upper and lower parts. The heights of the P-type semiconductor (17) and the N-type semiconductor (18) are both 0.8 to 2.5 mm.

7. The high-efficiency active heat dissipation structure for power semiconductor devices according to claim 3, characterized in that: The solders of the first solder layer (13), the second solder layer (14) and the third solder layer (21) are one or more of nano silver, nano copper, gold tin, tin-lead, tin-silver-copper and tin-bismuth.

8. The method for preparing a high-efficiency active heat dissipation structure for a power semiconductor device according to any one of claims 1 to 7, characterized in that: include: Connecting a surface of a P-type semiconductor (17) and an N-type semiconductor (18) to a surface of a hot end substrate (10) containing a liquid flow channel through a first solder layer (13) through a first circuit layer (12); The other surfaces of the P-type semiconductor (17) and the N-type semiconductor (18) are connected to the second circuit layer (15) on one surface of the cold end substrate (16) via a second solder layer (14); Connecting the surfaces of the power semiconductor chip (22) and the power terminal (23) to the third circuit layer on the other surface of the cold end substrate (16) via the third solder layer (21); The surface of the power semiconductor chip (22) is electrically connected to the third circuit layer (19) on the other surface of the cold end substrate (16) via a bonding wire (20), thereby obtaining a high-efficiency active heat dissipation structure for the power semiconductor device.

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