Semiconductor device including crack detection circuit

Abstract

The invention relates to a semiconductor device including a crack detection circuit. A semiconductor device includes a guard ring over a semiconductor substrate, a crack detection circuit, and a conductive sense line. The guard ring is electrically connected to the first impurity doped region of the semiconductor substrate. The conductive sensing line is disposed at a position isolated from the crack detection circuit with the guard ring interposed therebetween, and the conductive sensing line extends along the guard ring and is formed in a shape in which both ends of the conductive sensing line are spaced apart from each other. The semiconductor substrate comprises a second impurity doped region, a third impurity doped region and a fourth impurity doped region, the second impurity doped region is embedded in the first impurity doped region and extends to penetrate through the lower part of the protection ring, and the third impurity doped region penetrates through the first impurity doped region; the third impurity-doped region electrically connects the conductive sensing line to the second impurity-doped region, and the fourth impurity-doped region electrically connects the crack detection circuit to the second impurity-doped region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0151964, filed on November 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to integrated circuit devices, and more particularly to semiconductor devices including crack detection circuits. Background Art

[0004] An integrated circuit (IC) may be integrated in a semiconductor substrate or a semiconductor wafer. A semiconductor substrate may be cut into individual semiconductor devices including an integrated circuit. A semiconductor device may be separated into a chip shape. Due to the process of separating semiconductor devices, cracks may appear in each semiconductor device. The cracks may indicate that some layers constituting the semiconductor device are damaged. The cracks may propagate from the cutting area to the inside of the semiconductor device. Such cracks may become a cause of failure of the integrated circuit integrated in the semiconductor device. Summary of the invention

[0005] In an embodiment of the present disclosure, a semiconductor device may include: a semiconductor substrate including a first impurity-doped region; a guard ring formed on the semiconductor substrate, the guard ring electrically connected to the first impurity-doped region; a crack detection circuit formed on the semiconductor substrate; a conductive sensing line disposed on the semiconductor substrate at a position isolated from the crack detection circuit, the guard ring being interposed between the conductive sensing line and the crack detection circuit, the conductive sensing line being configured to extend along the guard ring and being configured to have two ends spaced apart from each other; a second impurity-doped region buried in the first impurity-doped region and extending below the guard ring; a third impurity-doped region configured to penetrate the first impurity-doped region so that the third impurity-doped region electrically connects one of the two ends of the conductive sensing line to a first portion of the second impurity-doped region; and a fourth impurity-doped region configured to penetrate the first impurity-doped region so that the fourth impurity-doped region electrically connects the crack detection circuit to a second portion of the second impurity-doped region.

[0006] In an embodiment of the present disclosure, a semiconductor device may include: a semiconductor substrate including a first impurity-doped region; a guard ring formed on the semiconductor substrate and electrically connected to the first impurity-doped region; a crack detection circuit formed on the semiconductor substrate; a first conductive sensing line disposed on the semiconductor substrate at a position isolated from the crack detection circuit, the guard ring being interposed between the conductive sensing line and the crack detection circuit, the first conductive sensing line being configured to extend along the guard ring and being configured to have two ends spaced apart from each other; a second conductive sensing line extending along the guard ring between the guard ring and the crack detection circuit on the semiconductor substrate and being configured to have two ends spaced apart from each other; a second impurity-doped region buried in the first impurity-doped region and configured to extend to pass under the guard ring; a third impurity-doped region configured to penetrate the first impurity-doped region to electrically connect one of the two ends of the conductive sensing line to a first portion of the second impurity-doped region; and a fourth impurity-doped region configured to penetrate the first impurity-doped region to electrically connect the crack detection circuit to a second portion of the second impurity-doped region.

[0007] In an embodiment of the present disclosure, a semiconductor device may include: a semiconductor substrate including a first impurity-doped region; a first guard ring and a second guard ring formed on the semiconductor substrate and electrically connected to the first impurity-doped region; a crack detection circuit formed on the semiconductor substrate; a first conductive sensing line isolated from the crack detection circuit on the semiconductor substrate, the first guard ring being interposed between the first conductive sensing line and the crack detection circuit, the first conductive sensing line being disposed between the first guard ring and the second guard ring, being configured to extend along the first guard ring, and being configured to have two ends spaced apart from each other; a second impurity-doped region buried in the first impurity-doped region and being configured to extend to pass under the guard ring; a third impurity-doped region configured to penetrate the first impurity-doped region and electrically connect one of the two ends of the first conductive sensing line to a first portion of the second impurity-doped region; and a fourth impurity-doped region configured to penetrate the first impurity-doped region and electrically connect the crack detection circuit to a second portion of the second impurity-doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 6 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 7 and Figure 8 is a schematic diagram illustrating a semiconductor device according to another embodiment of the present disclosure.

[0010] Figures 9 and 10 is a schematic diagram showing a semiconductor device according to still another embodiment of the present disclosure.

[0011] Fig.11is a schematic diagram illustrating a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The terms used in the description of the present disclosure are selected by considering the functions in the proposed embodiments, and the meanings of these terms may differ depending on the intention of the user, the operator, or the practice in the technical field. If a term has been specifically defined in this specification, the meaning of the term used follows the definition of the term, and if a term has not been specifically defined, the meaning of the term used may be interpreted as the meaning that can be commonly recognized by those skilled in the art.

[0013] In the description of the present disclosure, terms such as “first,” “second,” “third,” “fourth,” “fifth,” “upper,” and “lower” are used to distinguish components from one another but are not intended to limit the components themselves or imply a specific order.

[0014] The embodiments of the present disclosure may be applied to the technical field of realizing integrated circuit devices such as DRAM, NAND flash memory, PcRAM, and ReRAM devices. In addition, the embodiments of the present disclosure may also be applied to the technical field of realizing memory devices for storing data or logic devices for performing logic operations. The embodiments of the present application may be applied to the technical field of realizing a variety of products that require conductive patterns with fine dimensions.

[0015] Throughout the specification, the same reference numerals may denote the same components. Although not mentioned or described in the corresponding drawings, the same reference numerals or similar reference numerals may be described with reference to another drawing. In addition, although no reference numeral is indicated in a part of the corresponding drawings, the part may be described with reference to another drawing.

[0016] Figure 1 is a schematic plan view showing a semiconductor device 100C according to an embodiment of the present disclosure. Figure 1 The planar shape of the XY plane in the XYZ orthogonal coordinate system is shown.

[0017] refer to Figure 1 , the semiconductor device 100C may include a semiconductor substrate 100, a guard ring 200, and a conductive sensing line 300. The semiconductor device 100C may have a semiconductor chip shape that has been cut from a wafer. The semiconductor device 100C or the semiconductor substrate 100 may include an inner region 101 and an outer region 102. The inner region 101 of the semiconductor device 100C or the inner region 101 of the semiconductor substrate 100 may be an active region in which an integrated circuit is integrated. The outer region 102 of the semiconductor device 100C may be a peripheral region surrounding the inner region 101.

[0018] The outer region 102 of the semiconductor device 100C or the outer region 102 of the semiconductor substrate 100 may be an inactive region where no integrated circuit is disposed. The outer region 102 may be a scribe line region. The integrated circuit may include electronic components such as transistors and interconnect wiring structures connecting the electronic components. The integrated circuit may constitute a memory device such as a DRAM or a NAND flash memory.

[0019] The guard ring 200 of the semiconductor device 100C may be formed as a structure to protect an integrated circuit that has been integrated or arranged in the inner region 101. The guard ring 200 may be formed in the outer region 102 of the semiconductor substrate 100 so that the guard ring 200 surrounds a space or region overlapping the inner region 101 of the semiconductor substrate 100. The guard ring 200 may be formed as a structure to surround the inner space by surrounding the inner space overlapping the inner region 101 of the semiconductor substrate 100. The guard ring 200 may be formed as a wall structure that surrounds the inner space by surrounding the inner space overlapping the inner region 101 of the semiconductor substrate 100. The guard ring 200 may include a conductive material or a metal material.

[0020] The semiconductor device 100C may further include a crack detection circuit 190 formed on the semiconductor substrate 100. The crack detection circuit 190 may be configured to detect or monitor the occurrence of a crack by detecting a change in the electrical characteristics of the conductive sensing line 300. The conductive sensing line 300 may be an element that senses a crack occurring in the semiconductor device 100C. The change in electrical characteristics may include a change in the amount of current flowing into the conductive sensing line 300, or a change in the resistance of the conductive sensing line 300. When the conductive sensing line 300 is damaged or broken by a crack, a change in electrical characteristics may occur. The crack detection circuit 190 may be disposed in an inner region 101 of the semiconductor substrate 100 that has been separated by a guard ring 200. The guard ring 200 may surround the region or space including the crack detection circuit 190 by surrounding the region or space. The crack detection circuit 190 may be constructed to include electronic components that have been integrated in the inner region 101 of the semiconductor substrate 100 and circuit lines connecting these electronic components.

[0021] The conductive sensing line 300 may be disposed at a position isolated from the crack detection circuit 190, wherein the guard ring 200 is interposed between the conductive sensing line 300 and the crack detection circuit 190. The conductive sensing line 300 may be disposed in an outer region 102 of the semiconductor substrate 100 outside the guard ring 200. The conductive sensing line 300 may be formed as a wire or a conductive structure extending along the guard ring 200. The conductive sensing line 300 may be formed to include a metal material. The conductive sensing line 300 may extend around the guard ring 200 so that the two ends 300E-1 and 300E-2 of the conductive sensing line 300 are spaced apart from each other in the outer region 102 of the semiconductor substrate 100. The conductive sensing line 300 may extend around the guard ring 200 so that the first end 300E-1 faces the second end 300E-2.

[0022] The semiconductor device 100C may further include a first buried connector 310 and a second buried connector 320. The first buried connector 310 may connect the first end 300E-1 of the conductive sensing line 300 to the crack detection circuit 190. The second buried connector 320 may connect the second end 300E-2 of the conductive sensing line 300 to the crack detection circuit 190. The guard ring 200 may be provided between the conductive sensing line 300 and the crack detection circuit 190. The guard ring 200 may surround the inner region 101 in which the crack detection circuit 190 is arranged. Since the conductive sensing line 300 is electrically isolated from the guard ring 200, the first buried connector 310 and the second buried connector 320 may be formed as a bypass line extending by crossing the guard ring 200 and electrically isolated from the guard ring 200 in structure. The entire portion or a portion of each of the first buried connector 310 and the second buried connector 320 may be formed as a structure that has been buried in a portion of the semiconductor substrate 100 below the guard ring 200. Because a portion of each of the first buried connector 310 and the second buried connector is buried in the portion of the semiconductor substrate 100 below the guard ring 200 , the first buried connector 310 and the second buried connector 320 may each have a feature of extending by crossing over the guard ring 200 and not being electrically connected to the guard ring 200 .

[0023] Figure 2 It is shown in Figure 1 FIG. 1 is a schematic plan view of a crack 150 formed in a semiconductor device 100C.

[0024] Reference Figure 2, the individual semiconductor devices 100C can be separated from the wafer 100W by cutting the wafer 100W. When the wafer 100W is cut in the cutting direction 100D, the crack 150 may appear in the cut area. The crack 150 that has occurred may grow or propagate toward the internal area 101 of the semiconductor chip 100C. As the crack 150 continues, the conductive sensing line 300 may be damaged or broken and disconnected. Therefore, the electrical properties of the conductive sensing line 300, such as the resistance of the conductive sensing line, may be changed. This change in the electrical properties (such as resistance) caused in the conductive sensing line 300 is measured or monitored by the crack detection circuit 190. The guard ring 200 can also act as a barrier to block the propagation of the crack 150.

[0025] Figure 3 It is shown Figure 1 FIG. 1 is a schematic cross-sectional view of a conductive sensing line 300 of a semiconductor device 100C in FIG. Figure 3 Shown along Figure 1 A cross-sectional view taken along line C1-C1'.

[0026] refer to Figure 3 , the stack 330S, the top connection pattern 303, and the bottom connection pattern 304 may constitute a conductive sensing line 300, and conductive patterns 301 and 302 are stacked in each stack 330S. The conductive patterns 301 and 302 may be stacked in a direction substantially perpendicular to the surface of the semiconductor substrate 100, so that the conductive patterns 301 and 302 may constitute a stack 330S. The conductive patterns 301 and 302 may each include a metal layer. The top connection pattern 303 and the bottom connection pattern 304 may each include a metal layer.

[0027] The first conductive pattern 301 may have a pad feature or a line feature extending substantially parallel to the surface of the semiconductor substrate 100. The second conductive pattern 302 may be disposed between the first conductive patterns 301. The first conductive patterns 301 substantially overlap each other in the stacking direction (i.e., vertically or perpendicularly to the semiconductor substrate 100). The second conductive pattern 302 vertically connects the first conductive patterns 301 to each other. A plurality of second conductive patterns 302 may vertically connect the first conductive patterns 301 to each other. The second conductive pattern 302 may have a through-hole feature.

[0028] The top connection pattern 303 may connect two stacks 330S adjacent to each other at the top of the stack. The bottom connection pattern 304 may connect two stacks 330S adjacent to each other at the bottom of the stack. The top connection pattern 303 may connect the first topmost conductive pattern 302T-1 of the conductive patterns 301 and 302 of the first stack 331 and the second topmost conductive pattern 302T-2 of the conductive patterns 301 and 302 of the second stack 332. The bottom connection pattern 304 may connect the first bottommost conductive pattern 302B-1 of the conductive patterns 301 and 302 of the second stack 332 and the second bottommost conductive pattern 302B-2 of the conductive patterns 301 and 302 of the third stack 333. The top connection pattern 303 and the bottom connection pattern 304 may have an alternating order in the direction in which the conductive sensing line 300 extends, and may be provided in plurality. The top connection patterns 303 and the bottom connection patterns 304 may alternately connect the stack 330S of the conductive patterns 301 and 302 , so that the conductive sensing line 300 may be configured to have a continuous chain feature.

[0029] A first insulating layer 400 covering and insulating the stack 330S, the top connection pattern 303, and the bottom connection pattern 304 may be formed on the semiconductor substrate 100. The first insulating layer 400 may include a structure in which a plurality of insulating layers are stacked. The stack 330S, the top connection pattern 303, and the bottom connection pattern 304 in which the conductive patterns 301 and 302 are stacked may be electrically isolated from the semiconductor substrate 100 by the first insulating layer 400. The first insulating layer 400 may include an insulating material, such as silicon oxide or silicon nitride. The first insulating layer 400 may include an organic material, such as a polymer material.

[0030] The semiconductor substrate 100 may include a first impurity-doped region 110. The semiconductor substrate 100 may include a semiconductor material, such as silicon (Si). The first impurity-doped region 110 may be a region in which p-type conductive impurities (i.e., p-dopants) are doped in the semiconductor substrate 100. The first impurity-doped region 110 may be a P-well (PW). The semiconductor substrate 100 may further include a second insulating layer 180 for device isolation. The second insulating layer 180 may electrically isolate the stack 330S in which the conductive patterns 301 and 302 are stacked, the top connection pattern 303, and the bottom connection pattern 304 from the first impurity-doped region 110. The second insulating layer 180 may include an insulating material, such as silicon oxide or silicon nitride.

[0031] Figure 4 It is shown Figure 1 FIG. 1 is a schematic cross-sectional view of a first buried connector 310 of a semiconductor device 100C in FIG. Figure 4 Shown along Figure 1 A cross-sectional view taken along line C2-C2'. Figure 5 It is shown Figure 4 Schematic plan view of the impurity-doped regions 110, 120, 130 and 140.

[0032] Reference Figure 4 and Figure 5 , the first buried connector 310 of the semiconductor device 100C may be configured to be buried in the semiconductor substrate 100. The first buried connector 310 may be configured as an impurity-doped region in which impurities have been formed to have conductivity by being doped into the semiconductor substrate 100. The first buried connector 310 may be configured to include a second impurity-doped region 120, a third impurity-doped region 130, and a fourth impurity-doped region 140. The second impurity-doped region 120 may be an impurity-doped region buried in the first impurity-doped region 110 of the semiconductor substrate 100. The second impurity-doped region 120 may be a region in which impurities of a conductivity type different from that of the first impurity-doped region 110 or impurities of a conductivity type opposite to that of the first impurity-doped region 110 are doped. The second impurity-doped region 120 may be a region in which n-type conductive impurities are doped (i.e., an n-doped region). The second impurity-doped region 120 may be a deep N-well (DNW) formed in the form in which a deep N-well has been buried in a P-well (PW).

[0033] The second impurity-doped region 120 may be surrounded by the first impurity-doped region 110. The connection portion 110P of the first impurity-doped region 110 may overlap with a portion of the second impurity-doped region 120 and may be referred to as the connection portion 110P of the first impurity-doped region 110. Since the connection portion 110P is an extension of the first impurity-doped region 110, the connection portion 110P of the first impurity-doped region 110 may be electrically connected to the first impurity-doped region 110. The guard ring 200 may be electrically connected to the connection portion 110P of the first impurity-doped region 110. Therefore, the bias applied to the first impurity-doped region 110 may be applied to the guard ring 200 through the connection portion 110P of the first impurity-doped region 110. Therefore, the entire portion of the guard ring 200 may overlap with the first impurity-doped region 110 of the semiconductor substrate 100, and the entire portion of the guard ring 200 may be connected to the first impurity-doped region 110. As described above, the bias that has been applied to the first impurity-doped region 110 may also be applied to a connection portion of the first impurity-doped region 110 that overlaps with the second impurity-doped region 120 of the guard ring 200. Therefore, when a bias is applied to the first impurity-doped region 110 of the semiconductor substrate 100, the bias may be applied to the entire portion of the guard ring 200 at substantially the same time. The guard ring 200 and the stack of conductive patterns 201 and 202 constituting the guard ring 200 may be electrically connected to the first impurity-doped region 110, and may be electrically grounded because substantially the entire portion of the guard ring 200 is connected to and overlaps with the first impurity-doped region 110. Therefore, a power delivery network (PDN) of the semiconductor device 100C may be improved.

[0034] The connection portion 110P of the first impurity-doped region 110 may be disposed between the second impurity-doped region 120 and the guard ring 200, and may electrically isolate the second impurity-doped region 120 from the guard ring 200. A pn ​​junction may be formed in the connection portion 110P of the first impurity-doped region 110 and the second impurity-doped region 120. Therefore, when current flows into the second impurity-doped region 120, the connection portion 110P of the first impurity-doped region 110 may function to electrically isolate the second impurity-doped region 120.

[0035] The second impurity-doped region 120 may extend to pass under the guard ring 200. The third impurity-doped region 130 may be formed to be electrically connected to the first portion 120A of the second impurity-doped region 120, that is, a portion of the second impurity-doped region 120 that has extended outside the guard ring 200. The third impurity-doped region 130 may electrically connect the first portion 120A of the second impurity-doped region 120 to the first end 300E-1, that is, both ends of the conductive sensing line ( Figure 1The third impurity-doped region 130 may be formed to penetrate a portion of the first impurity-doped region 110 to contact a first portion 120A of the second impurity-doped region 120. The first portion 120A of the second impurity-doped region 120 may overlap with the third impurity-doped region 130.

[0036] The third impurity-doped region 130 may be formed by doping impurities of a different conductivity type from that of the first impurity-doped region 110 or impurities of a conductivity type opposite to that of the first impurity-doped region 110 into a portion of the semiconductor substrate 100. The third impurity-doped region 130 may be a region in a portion of the semiconductor substrate 100 that has been doped with n-type conductive impurities. The third impurity-doped region 130 may include a first sub-region 131 having a relatively low concentration of doped impurities and a second sub-region 132 having a relatively high concentration of doped impurities. The first sub-region 131 may be formed as an N well. The second sub-region 132 may be formed as an n+ doped region. The third impurity-doped region 130 may be a region in which impurities of the same conductivity type as those of the second impurity-doped region 120 have been doped. The third impurity-doped region 130 may be a region in which impurities having a higher impurity concentration than the second impurity-doped region 120 have been doped.

[0037] The fourth impurity-doped region 140 may be formed in a portion of the semiconductor substrate 100 opposite to the third impurity-doped region 130, wherein a connection portion 110P of the first impurity-doped region 110 electrically connected to the guard ring 200 is interposed between the third impurity-doped region 130 and the portion of the semiconductor substrate 100. The fourth impurity-doped region 140 may be formed to be electrically connected to the second portion 120B, which extends to the outside of the guard ring 200 on a side opposite to the first portion 120A. The fourth impurity-doped region 140 may electrically connect the second portion 120B of the second impurity-doped region 120 to the crack detection circuit 190. The fourth impurity-doped region 140 may be formed to penetrate a portion of the first impurity-doped region 110 to contact the second portion 120B of the second impurity-doped region 120.

[0038] The fourth impurity-doped region 140 may be formed by doping impurities of a conductive type different from that of the first impurity-doped region 110 or impurities of a conductive type opposite to that of the first impurity-doped region 110 in a portion of the semiconductor substrate 100. The fourth impurity-doped region 140 may be a region in which n-type conductive impurities have been doped in a portion of the semiconductor substrate 100. The fourth impurity-doped region 140 may include a third sub-region 141 having a relatively low concentration of doped impurities and a fourth sub-region 142 having a relatively high concentration of doped impurities. The third sub-region 141 may be formed as an N well. The fourth sub-region 142 may be formed as an n+ doped region. The fourth impurity-doped region 140 may be a region in which impurities of the same conductive type as those of the second impurity-doped region 120 have been doped. The fourth impurity-doped region 140 may be a region in which impurities of a higher impurity concentration than those of the second impurity-doped region 120 have been doped.

[0039] A portion of the second insulating layer 180 may be formed on a portion of the surface of the semiconductor substrate 100 so that the second insulating layer 180 electrically isolates a portion of the first impurity-doped region 110 and a portion of the third impurity-doped region 130. The second insulating layer 180 may be an insulating layer for device isolation. Another portion of the second insulating layer 180 may be formed on a portion of the surface of the semiconductor substrate 100 to electrically isolate a portion of the first impurity-doped region 110 and a portion of the fourth impurity-doped region 140.

[0040] The semiconductor device 100C may further include a first vertical connector 391 that electrically connects the first end 300E-1 of the conductive sensing line 300 and the third impurity-doped region 130. The first vertical connector 391 may include a metal material. The first vertical connector 391 may have a through-hole shape. A plurality of first vertical connectors 391 may be disposed between the first end 300E-1 of the conductive sensing line 300 and the third impurity-doped region 130, and may connect the first end 300E-1 of the conductive sensing line 300 and the third impurity-doped region 130. The second sub-region 132 of the third impurity-doped region 130 reduces the contact resistance between the first vertical connector 391 and the third impurity-doped region 130. The semiconductor device 100C may further include a second vertical connector 392 that electrically connects the crack detection circuit 190 and the fourth impurity-doped region 140. The second vertical connector 392 may include a metal material. The second vertical connector 392 may have a through-hole shape. The fourth sub-region 142 of the fourth impurity-doped region 140 reduces the contact resistance between the second vertical connector 392 and the fourth impurity-doped region 140.

[0041] The crack detection circuit 190 may include an electronic component 191 such as a transistor or a diode and a circuit line 192 connecting the electronic component 191. The circuit line 192 may include a conductive pattern or a metal pattern. By connecting the second vertical connector 392 to some portions of the circuit line 192, the crack detection circuit 190 may be electrically connected to the conductive sensing line 300 via the fourth impurity-doped region 140, the second impurity-doped region 120, and the third impurity-doped region 130.

[0042] The guard ring 200 may be formed in a stacked shape in which a plurality of conductive patterns 201 and 202 are stacked. The fourth conductive pattern 202 may be disposed between the third conductive patterns 201 to electrically connect the third conductive patterns 201. Figure 1 Like the guard ring 200 of the semiconductor device 100C, the fourth conductive pattern 202 and the third conductive pattern 201 may extend to surround the inner region 101 of the semiconductor device 100C by surrounding the inner region 101. The fourth conductive pattern 202 and the third conductive pattern 201 may have wall features that surround the inner region 101 of the semiconductor device 100C by surrounding the inner region 101.

[0043] In order to improve the resistance between the guard ring 200 and the connection portion 110P of the first impurity-doped region 110, a fifth impurity-doped region 110J may be formed in the connection portion 110P of the first impurity-doped region 110 by doping impurities into the connection portion 110P. The fifth impurity-doped region 110J may have an impurity concentration higher than that of the first impurity-doped region 110. The fifth impurity-doped region 110J may be a p+ doped region.

[0044] Figure 6 It is shown Figure 1 2 is a schematic cross-sectional view of a second buried connector 320 of a semiconductor device 100C shown in FIG. Figure 6 Shown along Figure 1 A cross-sectional view taken along line C3-C3' shown in FIG.

[0045] refer to Figure 1 and Figure 6 , the second buried connector 320 of the semiconductor device 100C may be configured to be buried in the semiconductor substrate 100. The second buried connector 320 of the semiconductor device 100C may be formed in the semiconductor substrate 100 to be electrically and structurally isolated from the first buried connector 310. The second buried connector 320 may be configured to include substantially the same elements as the first buried connector 310.

[0046] Reference Figure 4 and Figure 6, the second buried connector 320 may be configured as an impurity-doped region such that the impurity-doped region is formed by doping impurities into the semiconductor substrate 100 to have conductivity. The second buried connector 320 may be configured to include a sixth impurity-doped region 120-2, a seventh impurity-doped region 130-2, and an eighth impurity-doped region 140-2. The sixth impurity-doped region 120-2 of the second buried connector 320 may be formed to have substantially the same features (or characteristics) as the second impurity-doped region 120 of the first buried connector 310. The sixth impurity-doped region 120-2 may be an impurity-doped region buried in the first impurity-doped region 110 of the semiconductor substrate 100. The sixth impurity-doped region 120-2 may be a region in which impurities of a conductivity type different from that of the first impurity-doped region 110 or impurities of a conductivity type opposite to that of the first impurity-doped region 110 have been doped. The sixth impurity-doped region 120-2 may be a region in which n-type conductive impurities have been doped (i.e., an n-doped region). The sixth impurity-doped region 120 - 2 may be a deep N-well (DNW) formed in a form in which the sixth impurity-doped region 120 - 2 is buried in a P-well (PW).

[0047] The sixth impurity-doped region 120-2 may be surrounded by the first impurity-doped region 110. The connection portion 110P of the first impurity-doped region 110 may overlap a portion of the sixth impurity-doped region 120-2. Since the connection portion 110P is an extension of the first impurity-doped region 110, the connection portion 110P of the first impurity-doped region 110 may be electrically connected to the first impurity-doped region 110. The guard ring 200 may be electrically connected to the connection portion 110P of the first impurity-doped region 110.

[0048] The connection portion 110P of the first impurity-doped region 110 may be disposed between the sixth impurity-doped region 120-2 and the guard ring 200, and may electrically isolate the sixth impurity-doped region 120-2 from the guard ring 200. The sixth impurity-doped region 120-2 may extend to pass under the guard ring 200. The seventh impurity-doped region 130-2 of the second buried connector 320 may be formed to have substantially the same features (or characteristics) as the third impurity-doped region 130 of the first buried connector 310. The seventh impurity-doped region 130-2 may be formed such that the seventh impurity-doped region 130-2 is electrically connected to a portion of the sixth impurity-doped region 120-2 that has extended to the outside of the guard ring 200.

[0049] The seventh impurity-doped region 130-2 may be formed by doping impurities of a conductive type different from that of the first impurity-doped region 110 or impurities of a conductive type opposite to that of the first impurity-doped region 110 in a portion of the semiconductor substrate 100. The seventh impurity-doped region 130-2 may be a region in which n-type conductive impurities have been doped in a portion of the semiconductor substrate 100. The seventh impurity-doped region 130-2 may include a fifth sub-region 131-2 doped with impurities of a relatively low concentration and a sixth sub-region 132-2 doped with impurities of a relatively high concentration. The seventh impurity-doped region 130-2 may be a region in which impurities of a higher impurity concentration than that of the sixth impurity-doped region 120-2 are doped.

[0050] The eighth impurity-doped region 140-2 may be formed in a portion of the semiconductor substrate 100 opposite to the seventh impurity-doped region 130-2, wherein a connection portion 110P of the first impurity-doped region 110 electrically connected to the guard ring 200 is interposed between the seventh impurity-doped region 130-2 and the eighth impurity-doped region 140-2. The eighth impurity-doped region 140-2 may be formed such that the eighth impurity-doped region 140-2 is electrically connected to a portion of the sixth impurity-doped region 120-2, which portion extends to the outside of the guard ring 200 on a side opposite to the seventh impurity-doped region 130-2. The eighth impurity-doped region 140-2 may electrically connect a portion of the sixth impurity-doped region 120-2 to the crack detection circuit 190. The eighth impurity-doped region 140-2 may be formed to substantially penetrate a portion of the first impurity-doped region 110.

[0051] The eighth impurity-doped region 140-2 may be formed by doping impurities of a conductive type different from that of the first impurity-doped region 110 or impurities of a conductive type opposite to that of the first impurity-doped region 110 in a portion of the semiconductor substrate 100. The eighth impurity-doped region 140-2 may be a region in a portion of the semiconductor substrate 100 that has been doped with n-type conductive impurities. The eighth impurity-doped region 140-2 may include a seventh sub-region 141-2 and an eighth sub-region 142-2, the seventh sub-region 141-2 being doped with impurities of a relatively low concentration, and the eighth sub-region 142-2 being doped with impurities of a relatively high concentration. The seventh sub-region 141-2 may be formed as an N well. The eighth sub-region 142-2 may be formed as an n+ doped region. The eighth impurity-doped region 140-2 may be a region in which impurities with a higher impurity concentration than the sixth impurity-doped region 120-2 are doped.

[0052] A portion of the second insulating layer 180 may be formed in a portion of the surface of the semiconductor substrate 100 so that the second insulating layer 180 electrically isolates a portion of the first impurity-doped region 110 and a portion of the seventh impurity-doped region 130-2. Another portion of the second insulating layer 180 may be formed in a portion of the surface of the semiconductor substrate 100 to electrically isolate a portion of the first impurity-doped region 110 and a portion of the eighth impurity-doped region 140-2.

[0053] The semiconductor device 100C may further include a third vertical connector 391-2 that electrically connects the second end 300E-2 of the conductive sensing line 300 and the seventh impurity-doped region 130-2. The third vertical connector 391-2 may have substantially the same features (or characteristics) as the first vertical connector 391. The semiconductor device 100C may further include a fourth vertical connector 392-2 that electrically connects the crack detection circuit 190 and the eighth impurity-doped region 140-2. The fourth vertical connector 392-2 may have substantially the same features (or characteristics) as the second vertical connector 392.

[0054] The crack detection circuit 190 may include an electronic component 191 and a circuit line 192-2 connecting the electronic component 191. The circuit line 192-2 may include a conductive pattern or a metal pattern. By connecting the fourth vertical connector 392-2 to a portion of the circuit line 192-2, the crack detection circuit 190 may be electrically connected to the conductive sensing line 300 via the eighth impurity-doped region 140-2, the sixth impurity-doped region 120-2, and the seventh impurity-doped region 130-2.

[0055] Figure 7 is a schematic plan view showing a semiconductor device 100C- 1 according to an embodiment of the present disclosure. Figure 8 is shown along Figure 7 A schematic cross-sectional view of a cross-sectional view taken along line C4-C4' in FIG. Figure 7 and Figure 8 In, with Figures 1 to 6 The same reference numerals as those in the drawings represent the same or similar elements.

[0056] refer to Figure 7 and Figure 8, the semiconductor device 100C-1 may include a semiconductor substrate 100, a guard ring 200, a crack detection circuit 190, a first conductive sensing line 300, and a second conductive sensing line 1300. The semiconductor substrate 100 may include a first impurity doped region 110. The first conductive sensing line 300 may be formed on the semiconductor substrate 100 so that the first conductive sensing line 300 is disposed at a position isolated from the crack detection circuit 190, wherein the guard ring 200 is interposed between the first conductive sensing line 300 and the crack detection circuit 190. The first conductive sensing line 300 extends along the guard ring 200 and has two ends spaced apart from each other. The first conductive sensing line 300 may be connected to the crack detection circuit 190 and insulated from the guard ring 200 by a first buried connector 310 and a second buried connector 320. The first conductive sensing line 300 may include a first conductive sensing line 300 having a first conductive sensing line 300 and a second conductive sensing line 300 having a first conductive sensing line 300 and a second conductive sensing line 300 having a second conductive sensing line 300. Figure 1 The connection structure in which the first conductive sensing line 300 and the crack detection circuit 190 are connected through the first buried connector 310 and the second buried connector 320 may have the same structure as described above. Figure 4 and Figure 6 The structure of the description.

[0057] refer to Figure 4 , Figure 7 and Figure 8 , the first buried connector 310 connecting the first end 300E-1 of the first conductive sensing line 300 to the crack detection circuit 190 may be formed to include the second impurity-doped region 120, the third impurity-doped region 130, and the fourth impurity-doped region 140. The second impurity-doped region 120 may be a region buried in the first impurity-doped region 110 and extending to pass under the guard ring 200. The third impurity-doped region 130 may penetrate the first impurity-doped region 110 so that the first end 300E-1 of the first conductive sensing line 300 is electrically connected to a portion of the second impurity-doped region 120. The fourth impurity-doped region 140 may penetrate the first impurity-doped region 110 so that the crack detection circuit 190 is electrically connected to the second portion 120B of the second impurity-doped region 120, that is, another portion of the second impurity-doped region 120. The second portion 120B of the second impurity-doped region 120 may overlap with the fourth impurity-doped region 140. The second impurity-doped region 120 may also include a third portion 120C connecting the first portion 120A and the second portion 120B. The connection portion 110P or the guard ring 200 of the first impurity-doped region 110 may overlap the third portion 120C of the second impurity-doped region 120 .

[0058] refer to Figure 7 and Figure 8, the second conductive sensing line 1300 may be electrically connected to the crack detection circuit 190 through the third connection portion 1310 and the fourth connection portion 1320 respectively connected to both ends of the second conductive sensing line 1300. Since the second conductive sensing line 1300 is disposed in the inner region 101 within the guard ring 200, the third connection portion 1310 and the fourth connection portion 1320 may each be formed to include a conductive pattern or a metal pattern on the semiconductor substrate 100 without intersecting the guard ring 200. The third connection portion 1310 and the fourth connection portion 1320 may include a conductive pattern formed in the first insulating layer 400 formed on the semiconductor substrate 100. Since the third connection portion 1310 and the fourth connection portion 1320 do not intersect the guard ring 200 as described above, the second conductive sensing line 1300 may be formed to be substantially electrically isolated from the semiconductor substrate 100 by the first insulating layer 400. The second conductive sensing line 1300 may be formed to be substantially vertically spaced apart from the first impurity-doped region 110 such that the second conductive sensing line 1300 is spaced substantially vertically apart from the first impurity-doped region 110 and the second impurity-doped region ( Figure 4 The second conductive sensing line 1300 may be arranged not to overlap with the second impurity-doped region 120.

[0059] The second conductive sensing line 1300 may be formed on the semiconductor substrate 100 so that the second conductive sensing line 1300 extends along the guard ring 200 between the guard ring 200 and the crack detection circuit 190 and has two ends spaced apart from each other. The second conductive sensing line 1300 may be formed as an element for detecting or sensing cracks together with the first conductive sensing line 300. The second conductive sensing line 1300 may detect that the crack propagates to the inner region 101 of the semiconductor substrate 100 via the guard ring 200.

[0060] Fig. 9 is a schematic plan view showing a semiconductor device 100C- 2 according to an embodiment of the present disclosure. Fig.10 is shown along Fig. 9 A schematic cross-sectional view of a cross-sectional view taken along line C5-C5' in FIG. Fig. 9 and Fig.10 In, with Figures 1 to 8 The same reference numerals as in the drawings may denote the same elements.

[0061] refer to Fig. 9 and Fig.10, the semiconductor device 100C-2 may include a semiconductor substrate 100, a first guard ring 200, a second guard ring 2200, a crack detection circuit 190, and a first conductive sensing line 300. The semiconductor substrate 100 may include a first impurity doped region 110. The first guard ring 200 and the second guard ring 2200 may be formed on the semiconductor substrate 100 such that the first guard ring 200 and the second guard ring 2200 are electrically connected to the first impurity doped region 110. The first conductive sensing line 300 may be formed on the semiconductor substrate 100 such that the first conductive sensing line 300 is disposed between the first guard ring 200 and the second guard ring 2200. The first conductive sensing line 300 may be formed such that the first conductive sensing line 300 is disposed at a position isolated from the crack detection circuit 190, wherein the first guard ring 200 is interposed between the first conductive sensing line 300 and the crack detection circuit 190, and such that the first conductive sensing line 300 extends along the first guard ring 200 and has two ends spaced apart from each other.

[0062] The first conductive sensing line 300 may be insulated from the first guard ring 200 by the first buried connector 310 and the second buried connector 320, and may be connected to the crack detection circuit 190. The first conductive sensing line 300 may include a first conductive connector 310 and a second conductive connector 320 connected to the reference 300. Figure 1 The connection structure in which the first conductive sensing line 300 and the crack detection circuit 190 are connected through the first buried connector 310 and the second buried connector 320 may have the same structure as described above. Figure 4 and Figure 6 The structure of the description.

[0063] Reference Figure 4 and Fig.10 , the first guard ring 200 may include a reference Figure 4 The first guard ring 200 may be electrically connected to the first impurity-doped region 110. A bias may be applied to the first guard ring 200 through the first impurity-doped region 110. The second guard ring 2200 may have substantially the same features (or characteristics) as the first guard ring 200 or features similar to those of the first guard ring 200. The second guard ring 2200 may be electrically connected to the first impurity-doped region 110. A bias may be applied to the second guard ring 2200 through the first impurity-doped region 110.

[0064] Fig.11 is a schematic plan view showing a semiconductor device 100C-3 according to an embodiment of the present disclosure. Fig.11 In, with Figures 1 to 10 The same reference numerals as in the drawings may denote the same elements.

[0065] refer to Fig.11, the semiconductor device 100C-3 may be constructed to include a semiconductor substrate 100, a first guard ring 200, a second guard ring 2200, a crack detection circuit 190, a first conductive sensing line 300, and a second conductive sensing line 1300. The semiconductor substrate 100 may include a first impurity doped region 110. The first guard ring 200 and the second guard ring 2200 may be formed on the semiconductor substrate 100 such that the first guard ring 200 and the second guard ring 2200 are electrically connected to the first impurity doped region 110. The first conductive sensing line 300 may be formed on the semiconductor substrate 100 such that the first conductive sensing line 300 is disposed between the first guard ring 200 and the second guard ring 2200. The first conductive sensing line 300 may be formed such that the first conductive sensing line 300 is disposed at a position isolated from the crack detection circuit 190, wherein the first guard ring 200 is interposed between the first conductive sensing line 300 and the crack detection circuit 190, and such that the first conductive sensing line 300 extends along the guard ring 200 and has two ends spaced apart from each other. The second conductive sensing line 1300 may be disposed in the inner region 101 within the first guard ring 200. The second conductive sensing line 1300 may be formed as an element for detecting or sensing a crack together with the first conductive sensing line 300.

[0066] Certain specific embodiments of the present disclosure have been described. Persons of ordinary knowledge in the field to which the present invention belongs will appreciate that the present invention can be implemented in a modified form without departing from the inherent characteristics of the present disclosure. Therefore, the disclosed embodiments should be considered from a descriptive point of view rather than from a restrictive point of view. The scope of the present disclosure is described in the claims rather than in the above description, and all differences within their equivalent ranges should be interpreted as being included in the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a semiconductor substrate comprising a first impurity-doped region; a guard ring formed on the semiconductor substrate, the guard ring being electrically connected to the first impurity-doped region; a crack detection circuit formed on the semiconductor substrate; a conductive sensing line disposed on the semiconductor substrate at a position isolated from the crack detection circuit, the guard ring being interposed between the conductive sensing line and the crack detection circuit, the conductive sensing line extending along the guard ring and having two ends spaced apart from each other; a second impurity-doped region buried in the first impurity-doped region and extending below the guard ring; a third impurity-doped region, which: penetrates the first impurity-doped region so that the third impurity-doped region electrically connects one of the two ends of the conductive sensing line to a first portion of the second impurity-doped region; and a fourth impurity-doped region, which: penetrates the first impurity-doped region, so that the fourth impurity-doped region electrically connects the crack detection circuit to the second portion of the second impurity-doped region.

2. The semiconductor device according to claim 1, wherein The first impurity-doped region is doped with impurities having a conductivity type different from that of the second impurity-doped region.

3. The semiconductor device according to claim 1, wherein A portion of the first impurity-doped region is disposed between the second impurity-doped region and the guard ring, and electrically isolates the second impurity-doped region from the guard ring.

4. The semiconductor device according to claim 1, wherein: The first impurity-doped region includes p-type conductive impurities, and The second impurity-doped region includes n-type conductive impurities.

5. The semiconductor device according to claim 1, wherein The third impurity-doped region and the fourth impurity-doped region are each doped with impurities having a conductivity type different from that of the first impurity-doped region.

6. The semiconductor device according to claim 1, wherein The third impurity-doped region and the fourth impurity-doped region each have a higher impurity doping concentration than the second impurity-doped region.

7. The semiconductor device according to claim 1, wherein: The first portion of the second impurity-doped region overlaps with the third impurity-doped region, The second portion of the second impurity-doped region overlaps with the fourth impurity-doped region, and The second impurity-doped region further includes a third portion connecting the first portion and the second portion and overlapping the guard ring.

8. The semiconductor device according to claim 1, further comprising a fifth impurity-doped region disposed within a portion of the first impurity-doped region, the fifth impurity-doped region being disposed between the second impurity-doped region and the guard ring and having a higher impurity doping concentration than the first impurity-doped region. 9 . The semiconductor device according to claim 1 , further comprising an insulating layer formed on a surface of the semiconductor substrate and electrically isolating a portion of the first impurity-doped region and a portion of the third impurity-doped region. 10 . The semiconductor device according to claim 1 , further comprising a first vertical connector electrically connecting the one end of the conductive sensing line and the third impurity-doped region. 11 . The semiconductor device according to claim 1 , further comprising a second vertical connector electrically connecting the crack detection circuit and the fourth impurity doped region.

12. The semiconductor device according to claim 1, wherein The conductive sensing line comprises: a first stack of conductive patterns, a second stack of conductive patterns, and a third stack of conductive patterns, wherein the first stack, the second stack, and the third stack are arranged in sequence; a top connection pattern connecting a first topmost conductive pattern of a first stack of said conductive patterns and a second topmost conductive pattern of a second stack of said conductive patterns; and A bottom connecting pattern connects a first bottommost conductive pattern of the second stack of conductive patterns and a second bottommost conductive pattern of the third stack of conductive patterns.

13. The semiconductor device according to claim 1, wherein The guard ring includes a stack of conductive patterns electrically connected to the first impurity doped region and electrically grounded.

14. The semiconductor device according to claim 1, wherein The guard ring encloses the area including the crack detection circuit by surrounding the area.

15. A semiconductor device comprising: a semiconductor substrate comprising a first impurity-doped region; a guard ring formed on the semiconductor substrate and electrically connected to the first impurity-doped region; a crack detection circuit formed on the semiconductor substrate; a first conductive sensing line disposed on the semiconductor substrate at a position isolated from the crack detection circuit, the guard ring being interposed between the conductive sensing line and the crack detection circuit, the first conductive sensing line extending along the guard ring and having two ends spaced apart from each other; a second conductive sensing line extending along the guard ring between the guard ring and the crack detection circuit over the semiconductor substrate and having two ends spaced apart from each other; a second impurity-doped region buried in the first impurity-doped region and extending to pass under the guard ring; a third impurity-doped region which: penetrates the first impurity-doped region to electrically connect one end of the two ends of the first conductive sensing line to a first portion of the second impurity-doped region; and a fourth impurity-doped region, which: penetrates the first impurity-doped region to electrically connect the crack detection circuit to the second portion of the second impurity-doped region.

16. The semiconductor device according to claim 15, further comprising a conductive pattern formed over the semiconductor substrate, the conductive pattern connecting the second conductive sensing line to the crack detection circuit, in, The second conductive sensing line is electrically isolated from the first impurity-doped region and the second impurity-doped region.

17. The semiconductor device according to claim 15, wherein: The first impurity-doped region is doped with impurities having a conductivity type different from that of the second impurity-doped region.

18. A semiconductor device comprising: a semiconductor substrate comprising a first impurity-doped region; a first guard ring and a second guard ring formed on the semiconductor substrate and electrically connected to the first impurity-doped region; a crack detection circuit formed on the semiconductor substrate; a first conductive sensing line, which is isolated from the crack detection circuit on the semiconductor substrate, the first guard ring being interposed between the first conductive sensing line and the crack detection circuit, the first conductive sensing line being arranged between the first guard ring and the second guard ring, extending along the first guard ring, and having two ends spaced apart from each other; a second impurity-doped region buried in the first impurity-doped region and extending to pass under the guard ring; a third impurity-doped region which: penetrates the first impurity-doped region and electrically connects one end of the two ends of the first conductive sensing line to a first portion of the second impurity-doped region; and a fourth impurity-doped region which penetrates the first impurity-doped region and electrically connects the crack detection circuit to a second portion of the second impurity-doped region. 19 . The semiconductor device according to claim 18 , further comprising a second conductive sensing line extending along the first guard ring between the first guard ring and the crack detection circuit over the semiconductor substrate and having two ends spaced apart from each other.

20. The semiconductor device according to claim 19, further comprising a conductive pattern formed over the semiconductor substrate, such that the conductive pattern connects the second conductive sensing line to the crack detection circuit, in, The second conductive sensing line is electrically isolated from the first impurity-doped region and the second impurity-doped region.

21. The semiconductor device according to claim 18, wherein The second conductive sensing line is disposed not to overlap with the second impurity-doped region.

22. The semiconductor device according to claim 18, wherein The first impurity-doped region is doped with impurities having a conductivity type different from that of the second impurity-doped region.

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