Monostable flip-flop and applicable power supply circuit thereof

Abstract

The invention relates to a power supply circuit, which comprises a jitter elimination circuit, and the jitter elimination circuit comprises a rectification unit which converts a first AC signal and outputs a DC signal; the judging unit is used for receiving the direct-current signal, performing binary coding on the direct-current signal and outputting a first dithering signal; the monostable trigger receives a second dithering signal related to the first dithering signal, the second dithering signal comprises a positive trigger pulse, and the monostable trigger is triggered through the positive trigger pulse, so that an output signal of the monostable trigger is kept stable within a set time; the positive trigger pulse is a first pulse rising edge of the second jitter signal. When the first alternating current signal received by the rectifying unit generates zero-crossing oscillation due to commutation, the monostable trigger is triggered through the positive trigger pulse, so that the output signal of the monostable trigger is kept stable within the set time, the problem of zero-crossing oscillation of the first alternating current signal is solved, and the operation stability of the power supply circuit is improved.

Description

Technical Field

[0001] This case belongs to the field of power supply circuits, and in particular to a monostable trigger used in a debouncing circuit and a power supply circuit applicable thereto. Background Art

[0002] In the power supply circuit, in order to achieve the stability of the entire system, many key parameters are usually collected as control quantities, such as voltage and current. However, due to the influence of some parasitic parameters in the power supply circuit, the collected data will oscillate multiple times at certain moments, and the data fluctuates greatly, which will lead to system instability. In order to further improve the stability of the system, it is crucial to eliminate the influence caused by data oscillation.

[0003] Taking the bridge rectifier circuit in the traditional power supply circuit as an example, the synchronous rectification (SR) is realized by commutating the secondary current flowing through the secondary winding of the transformer, which is a simple and effective control strategy. However, in the engineering application of the traditional power supply circuit, the secondary current is affected by parasitic parameters at the commutation point, resulting in zero-crossing oscillation. The zero-crossing oscillation will further deteriorate the control effect of the synchronous rectification and the stability of the power supply circuit operation.

[0004] Therefore, how to develop a monostable trigger and a power supply circuit applicable thereto to solve the problems faced by the prior art is indeed a topic that needs to be addressed in this field. Summary of the invention

[0005] The purpose of this case is to provide a monostable trigger and a power supply circuit applicable thereto, so as to solve the problems that the AC current or AC voltage of the traditional power supply circuit has zero-crossing oscillation due to the influence of parasitic parameters, resulting in poor control effect of the switch of the power supply circuit and poor stability of the operation of the power supply circuit.

[0006] In order to achieve the aforementioned purpose, the present case provides a power supply circuit, including a de-jitter circuit, which includes: a rectifier unit, including an input end and an output end, the input end receives a first AC signal, the rectifier unit converts the first AC signal and outputs a DC signal at the output end; a determination unit, electrically connected to the output end of the rectifier unit, receives a DC signal and binary encodes the DC signal, and outputs a first jitter signal; and a monostable trigger, which receives a second jitter signal related to the first jitter signal, the second jitter signal includes a positive trigger pulse, and the monostable trigger is triggered by the positive trigger pulse so that the output signal of the monostable trigger remains stable within a set time, and the positive trigger pulse is the first pulse rising edge of the second jitter signal.

[0007] In order to achieve the above-mentioned purpose, the present case further provides a monostable trigger, which is applied to a debouncing circuit. The debouncing circuit receives an AC signal, and the monostable trigger includes: a first NOR gate, wherein the first input end of the first NOR gate receives a DC jitter signal, and the DC jitter signal includes a positive trigger pulse, wherein when the AC signal changes direction, the first input end of the first NOR gate receives the positive trigger pulse, and the positive trigger pulse is the first pulse rising edge of the DC jitter signal; a first capacitor, wherein the first end of the first capacitor is electrically connected to the output end of the first NOR gate; a first resistor, wherein a first end of the first resistor is electrically connected to the second end of the first capacitor, and the first resistor The second end is electrically connected to a positive voltage source; and a first NOT gate, the input end of the first NOT gate is electrically connected to the first end of the first resistor and the second end of the first capacitor, the output end of the first NOT gate is electrically connected to the second input end of the first NOR gate, and the output end of the first NOT gate generates an output signal; wherein when the first input end of the first NOR gate receives a positive trigger pulse, the output end of the first NOR gate is a low level, so that the input end of the first NOR gate is a low level and the output end of the first NOR gate is a high level, and the output end of the first NOR gate is fed back to the second input end of the first NOR gate to form a loop, so that the output signal remains stable within a set time. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A system architecture diagram of a power supply circuit of a preferred embodiment of the present invention;

[0009] Figure 2 for Figure 1 A detailed circuit diagram of a monostable trigger of the debounce circuit shown;

[0010] Figure 3 for Figure 1 The detailed circuit diagram of the determination unit in the first embodiment is shown;

[0011] Figure 4 for Figure 1 The detailed circuit diagram of the determination unit in the second embodiment is shown;

[0012] Figure 5 for Figure 1 The detailed circuit diagram of the main power circuit and the signal sampling circuit shown;

[0013] Figure 6 for Figure 1 The detailed circuit diagram of the hysteresis comparator shown in FIG.

[0014] Figure 7 for Figure 1 A detailed circuit diagram of the first dead zone unit shown;

[0015] Figure 8 for Figure 1 A detailed circuit diagram of the second dead zone unit shown; and

[0016] Fig. 9 Shows Figure 1 Schematic diagram of operating parameters of the power supply circuit shown. DETAILED DESCRIPTION

[0017] Some typical embodiments that embody the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various changes in different implementations, all of which do not depart from the scope of this case, and the descriptions and drawings therein are essentially used for illustrative purposes, rather than for limiting this case. For example, different embodiments of this disclosure may use repeated reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and / or the appearance structures. In addition, when a component is referred to as "connected to" or "coupled to" another component, it may be directly connected to or coupled to another component, or there may be an intervening component. Although the numerical ranges and parameters of the broad scope of this disclosure are approximate values, the numerical values ​​are stated in the specific examples as accurately as possible. In addition, it is understood that although the terms "first", "second", "third", etc. can be used in the claims to describe different components, these components should not be limited by these terms, and the components described in the embodiments are represented by different component symbols. These terms are used to distinguish different components. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the embodiment. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] See also Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 ,in Figure 1 is a system architecture diagram of the power supply circuit of the present embodiment, Figure 2 for Figure 1 The detailed circuit diagram of the monostable trigger of the debounce circuit shown in FIG. Figure 3 for Figure 1 The detailed circuit diagram of the determination unit in the first embodiment is shown. Figure 4 for Figure 1 The detailed circuit diagram of the determination unit in the second embodiment is shown. Figure 5 for Figure 1 The detailed circuit diagram of the main power circuit and signal sampling circuit shown in the figure is as follows: Figure 6 for Figure 1 The detailed circuit diagram of the hysteresis comparator is shown in FIG. Figure 7 for Figure 1 The detailed circuit diagram of the first dead zone unit shown in FIG. Figure 8 for Figure 1 The detailed circuit diagram of the second dead zone unit shown in FIG. Fig. 9 Shows Figure 1 The schematic diagram of the operating parameters of the power supply circuit shown. The power supply circuit 1 of the present case includes a de-jitter circuit 2, which can de-jitter the AC signal collected in the power supply circuit 1 (i.e., eliminate zero-crossing oscillations), and the de-jitter circuit 2 includes a rectifier unit 3, a determination unit 4, and a monostable trigger 5. The rectifier unit 3 includes an input end and an output end, the input end of the rectifier unit 3 receives the first AC signal Vac1, and the rectifier unit 3 converts the first AC signal Vac1 and outputs a DC signal Vdc at the output end of the rectifier unit 3. The rectifier unit 3 of the present case is, for example, a bridge rectifier circuit, a full-wave rectifier circuit, etc., which is not limited in the present case. The determination unit 4 is electrically connected to the output end of the rectifier unit 3 and receives the DC signal Vdc, and the determination unit 4 further binary encodes the DC signal to output the first jitter signal V1.

[0019] The monostable trigger 5 receives the second jitter signal V2, which is a DC jitter signal, wherein the second jitter signal V2 is correlated with the first jitter signal V1, and the correlation between the second jitter signal V2 and the first jitter signal V1 will be described later. The second jitter signal V2 includes a positive trigger pulse, and the monostable trigger 5 can be triggered by the positive trigger pulse, so that the output signal Vo output by the monostable trigger 5 remains stable within the set time T1, wherein the positive trigger pulse can be the first pulse rising edge of the second jitter signal V2.

[0020] In the present embodiment, the monostable trigger 5 includes a first NOR gate 50, a first capacitor C1, a first resistor R1 and a first NOT gate 51. The first input terminal of the first NOR gate 50 receives the second jitter signal V2, and when the first AC signal Vac1 changes direction, the first input terminal of the first NOR gate 50 receives a positive trigger pulse from the second jitter signal V2. The first end of the first capacitor C1 is electrically connected to the output terminal of the first NOR gate 50. The first end of the first resistor R1 is electrically connected to the second end of the first capacitor C1, and the second end of the first resistor R1 is electrically connected to the positive voltage source Vdd. The input terminal of the first NOT gate 51 is electrically connected to the first end of the first resistor R1 and the second end of the first capacitor C1, the output terminal of the first NOT gate 51 is electrically connected to the second input terminal of the first NOR gate 50, and the output terminal of the first NOT gate 51 generates an output signal Vo, wherein the signal waveforms of the second jitter signal V2 and the output voltage Vo are, for example, as shown in FIG. Fig. 9As shown. In addition, it can be understood that the first NOT gate 51 refers to any operator with a negation function, so the first NOT gate 51 can also be replaced by a NOR gate, in which case the two input terminals of the NOR gate are connected in common. It can be understood that since the output terminal of the first NOT gate 51 is electrically connected to the second input terminal of the first NOR gate 50 to form a loop, after the monostable trigger 5 is triggered by a positive trigger pulse, the voltage signal V3 outputted by the output terminal of the first NOR gate 50 also remains stable within the set time T1.

[0021] When the first AC signal Vac1 commutates and generates zero-crossing oscillation, the first input end of the first NOR gate 50 will receive a positive trigger pulse from the second jitter signal V2. At this time, the output end of the first NOR gate 50 is low level, so that the input end of the first NOR gate 51 is low level and the output end of the first NOR gate 51 is high level, and the output end of the first NOR gate 50 will be fed back to the second input end of the first NOR gate 50 to form a loop. In this way, the output signal Vo output by the monostable trigger 5 can be kept stable within the set time, so the situation of the first AC signal Vac1 crossing zero-point oscillation can be solved to improve the control effect of the switch of the power supply circuit 1 and the stability of the operation of the power supply circuit 1. Therefore, once the monostable trigger 5 of the present case is triggered by a positive trigger pulse, even if the second jitter signal V2 has multiple oscillations later, the output signal Vo of the monostable trigger 5 can still remain stable within the set time T1, thereby eliminating the jitter problem within the set time T1.

[0022] In addition, when the first AC signal Vac1 is not commutated and has no zero-crossing oscillation, that is, when the debouncing circuit 2 operates in a steady state, the second end of the first resistor R1 is electrically connected to the positive voltage source Vdd, so that the input end of the first NOT gate 51 is a high level and the output end of the first NOT gate 51 is a low level, and the output end of the first NOT gate 51 is fed back to the second input end of the first NOR gate 50, so that the output end of the first NOR gate 50 is a high level, so the potential of the first end and the second end of the first capacitor C1 will be equal, and there is no voltage drop.

[0023] In some embodiments, such as Figure 3As shown, the determination unit 4 may include a first comparator 40, the positive input terminal of the first comparator 40 receives the DC signal Vdc, the negative input terminal of the first comparator 40 receives the reference voltage Vref, and the first comparator 40 compares the DC signal Vdc with the reference voltage Vref to output a first jitter signal V1 at the output terminal of the first comparator 40, and the first jitter signal V1 and the second jitter signal V2 are the same signal. When the DC signal Vdc is greater than or equal to the reference voltage Vref, the output terminal of the first comparator 40 outputs a high level; when the DC signal Vdc is less than the reference voltage Vref, the output terminal of the first comparator 40 outputs a low level, that is, a zero level, so that the first jitter signal V1 and the second jitter signal V2 are a series of binary codes. In addition, the determination unit 4 may include a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7. The first end of the fourth resistor R4 is electrically connected to the positive voltage source Vdd. A first end of the fifth resistor R5 is electrically connected to the second end of the fourth resistor R4 and the negative input terminal of the first comparator 40, and a second end of the fifth resistor R5 is grounded. A first end of the sixth resistor R6 is electrically connected to the negative input terminal of the first comparator 40, and a second end of the sixth resistor R6 is electrically connected to the output terminal of the first comparator 40. A first end of the seventh resistor R7 is electrically connected to the positive voltage source Vdd, and a second end of the seventh resistor R7 is electrically connected to the output terminal of the first comparator 40. In these embodiments, the monostable trigger 5 directly receives the first jitter signal V1 (i.e., the second jitter signal V2) output by the determination unit 4.

[0024] In some other embodiments, Figure 4 As shown, the determination unit 4 may include a second comparator 41, the negative input terminal of the second comparator 41 receives the DC signal Vdc, the positive input terminal of the second comparator 41 receives the reference voltage Vref, and the second comparator 41 compares the DC signal Vdc with the reference voltage Vref to output the first jitter signal V1 at the output terminal of the second comparator 41. In addition, the determination unit 4 may include an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11. The first end of the eighth resistor R8 is electrically connected to the positive voltage source Vdd. The first end of the ninth resistor R9 is electrically connected to the second end of the eighth resistor R8 and the positive input terminal of the second comparator 41, and the second end of the ninth resistor R9 is electrically grounded. The first end of the tenth resistor R10 is electrically connected to the positive input terminal of the second comparator 41, and the second end of the tenth resistor R10 is electrically connected to the output terminal of the second comparator 41. The first end of the eleventh resistor R11 is electrically connected to the positive voltage source Vdd, and the second end of the eleventh resistor R11 is electrically connected to the output terminal of the second comparator 41.

[0025] In addition, if Figure 1As shown, in these embodiments, the de-jitter circuit 2 further includes a second NOR gate 6, which is electrically connected between the output terminal of the second comparator 41 of the determination unit 4 and the monostable trigger 5. The second NOR gate 6 inverts the first jitter signal V1 and outputs a second jitter signal V2 at the output terminal of the second NOR gate 6. When the DC signal Vdc is less than the reference voltage Vref, the output terminal of the second comparator 41 outputs a high level; when the DC signal Vdc is greater than or equal to the reference voltage Vref, the output terminal of the second comparator 41 outputs a low level, that is, a zero level, so that the first jitter signal V1 is a series of binary codes. Further, the first jitter signal V1 is inverted by the second NOR gate 6 to obtain the second jitter signal V2, and the second jitter signal V2 is also a series of binary codes. It can be understood that the second NOR gate 6 refers to any operator with a negation function, so the second NOR gate 6 can also be a NOT gate, which is not limited in this case.

[0026] In some embodiments, such as Figure 5 As shown, the power supply circuit 1 also includes a main power circuit 7, which includes a transformer T and a first switch bridge arm and a second switch bridge arm electrically connected in parallel. The transformer T includes a primary winding Np and a secondary winding Ns, wherein the primary winding Np is electrically connected to the input end of the main power circuit 7 and receives the second AC signal, and the two ends of the secondary winding Ns are electrically connected to the bridge arm midpoint of the first switch bridge arm and the bridge arm midpoint of the second switch bridge arm, that is, the first end of the secondary winding Ns is electrically connected to the bridge arm midpoint of the first switch bridge arm, and the second end of the secondary winding Ns is electrically connected to the bridge arm midpoint of the second switch bridge arm. The first switch bridge arm includes a first synchronous rectification switch SR1 and a second synchronous rectification switch SR2 electrically connected in series, and the second switch bridge arm includes a third synchronous rectification switch SR3 and a fourth synchronous rectification switch SR4 electrically connected in series. Among them, the second AC signal can be an AC voltage signal or an AC current signal, which is not limited in this case. In some embodiments, the main power circuit 7 also includes an output capacitor Co, which is connected in parallel with the first switch bridge arm.

[0027] In addition, the power supply circuit 1 further includes a signal sampling circuit 8, which collects a first AC signal Vac1 related to the second AC signal in the main power circuit 7. In some embodiments, the first AC signal may be a primary current ip flowing through the primary winding Np, a primary voltage Vab between the two terminals of the primary winding Np, a secondary current is flowing through the secondary winding Ns, or a secondary voltage Vdc between the two terminals of the secondary winding Ns. Therefore, the de-jitter circuit of the present case can detect the jitter signal collected by the signal sampling circuit 8 (for example, the primary current ip flowing through the primary winding Np, the primary voltage Vab between the two terminals of the primary winding Np, the secondary current is flowing through the secondary winding Ns, or the secondary voltage Vdc between the two terminals of the secondary winding Ns). Fig. 9It shows that the secondary current is) flowing through the secondary winding Ns is de-jittered (i.e., the zero-crossing oscillation is eliminated) to improve the control effect of the switch of the power supply circuit 1 and the stability of the operation of the power supply circuit 1.

[0028] In some embodiments, such as Figure 6 As shown, the power supply circuit 1 further includes a hysteresis comparator 9, which can receive the first AC signal Vac1 and output a first direction signal Vd1 accordingly. Fig. 9 As shown, the first direction signal Vd1 is in the same direction as the first AC signal Vac1. Specifically, the hysteresis comparator 9 includes a third comparator 90. When the first AC signal Vac1 is a positive input, the third comparator 90 compares the first AC threshold Vacr1 (positive input terminal) with the second AC threshold Vacr2 (negative input terminal). When the first AC threshold Vacr1 is greater than the second AC threshold Vacr2, the third comparator 90 outputs a high level. When the first AC signal Vac1 is a reverse input, the third comparator 90 compares the first AC threshold Vacr1 (positive input terminal) with the second AC threshold Vacr2 (negative input terminal). When the first AC threshold Vacr1 is less than the second AC threshold Vacr2, the third comparator 90 outputs a low level, that is, a zero level, so that the signal output by the third comparator 90 constitutes the first direction signal Vd1. In some embodiments, the hysteresis comparator 9 further includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a seventeenth resistor R17. The first end of the twelfth resistor R12 is electrically connected to the positive voltage source Vdd. The first end of the thirteenth resistor R13 is electrically connected to the second end of the twelfth resistor R12 and the positive input terminal of the third comparator 90. The first end of the fourteenth resistor R14 is electrically connected to the positive voltage source Vdd. The first end of the fifteenth resistor R15 is electrically connected to the second end of the fourteenth resistor R14 and the negative input terminal of the third comparator 90, and the second end of the fifteenth resistor R15 and the second end of the thirteenth resistor R13 jointly receive the first AC signal Vac1. The first end of the sixteenth resistor R16 is electrically connected to the positive input terminal of the third comparator 90, and the second end of the sixteenth resistor R16 is electrically connected to the output terminal of the third comparator 90. The first end of the seventeenth resistor R17 is electrically connected to the positive voltage source Vdd, and the second end of the seventeenth resistor R17 is electrically connected to the output end of the third comparator 90. It should be noted that the positive voltage source Vdd in this case can be the same voltage source or different voltage sources, which is not limited in this case.

[0029] In some embodiments, such as Figure 7 and Figure 8As shown, the power supply circuit 1 further includes a first dead zone unit 10 and a second dead zone unit 11. The first dead zone unit 10 is electrically connected to the hysteresis comparator 9, and includes a first NAND gate 100, a second resistor R2, a second capacitor C2 and a second NAND gate 101. The first input end of the first NAND gate 100 receives the first direction signal Vd1. The first end of the second resistor R2 is electrically connected to the output end of the first NAND gate 100. The first end of the second capacitor C2 is grounded. The first input end of the second NAND gate 101, the second end of the second resistor R2 and the second end of the second capacitor C2 are connected in common, the second input end of the second NAND gate 101 is electrically connected to the second input end of the first NAND gate 100, and the output end of the second NAND gate 101 outputs the second direction signal Vd2, as shown in FIG. Fig. 9 As shown. The second dead zone unit 11 is electrically connected to the monostable trigger 5, and includes a third NAND gate 110, a third resistor R3, a third capacitor C3 and a fourth NAND gate 111. The first input terminal of the third NAND gate 110 is electrically connected to the output terminal of the first NOR gate 50 of the monostable trigger 5, and the output terminal of the third NAND gate 110 outputs a logic signal VL. The first end of the third resistor R3 is electrically connected to the output terminal of the third NAND gate 110. The first end of the third capacitor C3 is grounded. The first input terminal of the fourth NAND gate 111, the second end of the third resistor R3 and the second end of the third capacitor C3 are connected in common, the second input terminal of the fourth NAND gate 111 is electrically connected to the second input terminal of the third NAND gate 110, and the output terminal of the fourth NAND gate 111 outputs a third direction signal Vd3, as shown. Fig. 9 The power circuit 1 can make the first switch bridge arm and the second switch bridge arm not be turned on at the same time by setting the first dead zone unit 10 and the second dead zone unit 11.

[0030] In some embodiments, the power supply circuit 1 further includes an RS trigger 12, a first input terminal of the RS trigger 12 is electrically connected to an output terminal of the second NAND gate 101 of the first dead zone unit 10 to receive the second direction signal Vd2, a second input terminal of the RS trigger 12 is electrically connected to an output terminal of the fourth NAND gate 111 of the second dead zone unit 11 to receive the third direction signal Vd3, and an output terminal of the RS trigger 12 outputs the first drive signal Vc1 as shown in FIG. Fig. 9 As shown. In addition, the power supply circuit 1 further includes a second NOT gate 13 and an AND gate 14. After the second NOT gate 13 inverts the first drive signal Vc1, it is ANDed with the first direction signal through the AND gate 14 to obtain the second drive signal Vc2, and the second drive signal Vc2 can be used to control the first switch bridge arm and the second switch bridge arm of the main power circuit 7, so as to improve the control effect of the switch of the power supply circuit 1 and the stability of the operation of the power supply circuit 1 by de-jittering the jitter signal collected in the power supply circuit 1 (i.e., eliminating the zero-crossing oscillation).

[0031] In summary, this case provides a monostable trigger and a power supply circuit applicable thereto. When the first AC signal received by the rectifier unit of the power supply circuit oscillates through zero due to commutation, the monostable trigger is triggered by a positive trigger pulse, so that the output signal of the monostable trigger remains stable within a set time. Therefore, the problem of zero-point oscillation of the first AC signal can be solved, so as to improve the control effect of the switch of the power supply circuit and the stability of the operation of the power supply circuit. At the same time, the control strategy of bridge synchronous rectification is realized, and the transmission efficiency of the power supply circuit is improved.

Claims

1. A power supply circuit, comprising a debouncing circuit, characterized in that: The debounce circuit includes: A rectifier unit comprises an input terminal and an output terminal, wherein the input terminal receives a first AC signal, and the rectifier unit converts the first AC signal and outputs a DC signal at the output terminal; a determination unit, electrically connected to the output end of the rectification unit, receiving the DC signal and performing binary encoding on the DC signal, and outputting a first jitter signal; as well as A monostable trigger receives a second jitter signal related to the first jitter signal, wherein the second jitter signal includes a positive trigger pulse. The monostable trigger is triggered by the positive trigger pulse so that an output signal of the monostable trigger remains stable within a set time, and the positive trigger pulse is the first pulse rising edge of the second jitter signal.

2. The power circuit as claimed in claim 1, wherein the monostable trigger comprises: a first NOR gate, a first input terminal of the first NOR gate receiving the second jitter signal, wherein when the first AC signal is switched, the first input terminal of the first NOR gate receives the positive trigger pulse; a first capacitor, a first terminal of the first capacitor being electrically connected to an output terminal of the first NOR gate; a first resistor, a first end of the first resistor being electrically connected to a second end of the first capacitor, and a second end of the first resistor being electrically connected to a positive voltage source; and A first NOT gate, an input end of the first NOT gate is electrically connected to the first end of the first resistor and the second end of the first capacitor, an output end of the first NOT gate is electrically connected to a second input end of the first NOR gate, and the output end of the first NOT gate generates the output signal.

3. The power supply circuit as described in claim 2, wherein when the first input terminal of the first NOR gate receives the positive trigger pulse, the output terminal of the first NOR gate is at a low level, so that the input terminal of the NOR gate is at a low level and the output terminal of the first NOR gate is at a high level, and the output terminal of the first NOR gate is fed back to the second input terminal of the first NOR gate to form a circulation loop, so that the output signal of the monostable trigger remains stable within a set time.

4. The power supply circuit as claimed in claim 1 , wherein the determination unit comprises a first comparator, a positive input terminal of the first comparator receives the DC signal, a negative input terminal of the first comparator receives a reference voltage, the first comparator compares the DC signal with the reference voltage, and outputs the first jitter signal at an output terminal of the first comparator, wherein the first jitter signal and the second jitter signal are the same signal.

5. The power supply circuit as described in claim 4, wherein the determination unit further comprises a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, wherein a first end of the fourth resistor is electrically connected to a positive voltage source, a second end of the fourth resistor, a first end of the fifth resistor, and a first end of the sixth resistor are commonly connected to the negative input terminal of the first comparator, a second end of the sixth resistor and a second end of the seventh resistor are commonly connected to the output terminal of the first comparator, a second end of the fifth resistor is grounded, and a first end of the seventh resistor is electrically connected to the positive voltage source.

6. The power supply circuit as described in claim 1, wherein the determination unit includes a second comparator, a negative input terminal of the second comparator receives the DC signal, a positive input terminal of the second comparator receives a reference voltage, the second comparator compares the DC signal with the reference voltage, and outputs the first jitter signal at an output terminal of the second comparator; the de-jitter circuit also includes a second NOR gate or a third NOR gate, the second NOR gate or the third NOR gate is electrically connected between the determination unit and the monostable trigger, and outputs the second jitter signal at an output terminal of the second NOR gate or the third NOR gate after inverting the first jitter signal.

7. The power supply circuit as described in claim 6, wherein the determination unit further comprises an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor, wherein a first end of the eighth resistor is electrically connected to a positive voltage source, a first end of the ninth resistor, a second end of the eighth resistor, and a first end of the tenth resistor are connected in common to the positive input end of the second comparator, a second end of the tenth resistor and a second end of the eleventh resistor are connected in common to the output end of the second comparator, a second end of the ninth resistor is grounded, and a first end of the eleventh resistor is electrically connected to the positive voltage source.

8. The power supply circuit as described in claim 2, wherein when the debouncing circuit operates in a steady state, the second end of the first resistor is electrically connected to the positive voltage source, so that the input end of the first NOT gate is at a high level and the output end of the first NOT gate is at a low level, and the output end of the first NOT gate is fed back to the second input end of the first NOR gate so that an output end of the first NOR gate is at a high level, so that the potentials at both ends of the first capacitor are equal.

9. The power circuit as claimed in claim 2, wherein the power circuit further comprises: A main power circuit comprises a transformer and a first switch bridge arm and a second switch bridge arm electrically connected in parallel, wherein the transformer comprises a primary winding and a secondary winding, the primary winding is electrically connected to an input end of the main power circuit and receives a second AC signal, and two end points of the secondary winding are electrically connected to the midpoints of the first switch bridge arm and the second switch bridge arm respectively; and A signal sampling circuit collects the first AC signal related to the second AC signal in the main power circuit. 10 . The power circuit as claimed in claim 9 , wherein the first AC signal is a current flowing through the primary winding, a voltage between two terminals of the primary winding, a current flowing through the secondary winding, or a voltage between the two terminals of the secondary winding. 11 . The power circuit as claimed in claim 9 , wherein the second AC signal is an AC voltage signal or an AC current signal.

12. The power circuit as claimed in claim 9, wherein the power circuit further comprises: A hysteresis comparator receives the first AC signal and outputs a first direction signal, wherein the first direction signal is in the same direction as the first AC signal.

13. The power supply circuit as described in claim 12, wherein the hysteresis comparator includes a third comparator, a positive input terminal of the third comparator receives a first AC threshold, and a negative input terminal of the third comparator receives a second AC threshold, wherein when the first AC signal is a positive input, the third comparator compares the first AC threshold with the second AC threshold, and when the first AC threshold is greater than the second AC threshold, an output terminal of the third comparator outputs a high level; when the first AC signal is a reverse input, the third comparator compares the first AC threshold with the second AC threshold, and when the first AC threshold is less than the second AC threshold, the output terminal of the third comparator outputs a low level to constitute the first direction signal.

14. The power supply circuit as claimed in claim 13, wherein the hysteresis comparator further comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor, wherein a first end of the twelfth resistor is electrically connected to a positive voltage source, a first end of the fourteenth resistor is electrically connected to the positive voltage source, a second end of the twelfth resistor, a first end of the thirteenth resistor and a first end of the sixteenth resistor are connected in common with the positive input terminal of the third comparator, a second end of the fourteenth resistor and a first end of the fifteenth resistor are connected in common with the negative input terminal of the third comparator, a second end of the fifteenth resistor and a second end of the thirteenth resistor jointly receive the first AC signal; a second end of the sixteenth resistor and a second end of the seventeenth resistor are connected in common with the output terminal of the third comparator, and a first end of the seventeenth resistor is electrically connected to the positive voltage source.

15. The power circuit as claimed in claim 12, wherein the power circuit further comprises: A first dead zone unit, electrically connected to the hysteresis comparator, comprising: a first NAND gate, a first input terminal of which receives the first direction signal; a second resistor, a first end of the second resistor being electrically connected to an output end of the first NAND gate; a second capacitor, a first terminal of which is grounded; and a second NAND gate, a first input terminal of the second NAND gate, a second terminal of the second resistor, and a second terminal of the second capacitor are commonly connected, a second input terminal of the second NAND gate is electrically connected to a second input terminal of the first NAND gate, and an output terminal of the second NAND gate outputs a second direction signal; and A second dead zone unit, electrically connected to the monostable trigger, comprising: a third NAND gate, a first input terminal of the third NAND gate being electrically connected to the output terminal of the first NOR gate of the monostable trigger; a third resistor, a first end of the third resistor being electrically connected to an output end of the third NAND gate; a third capacitor, a first terminal of the third capacitor being grounded; and a fourth NAND gate, a first input terminal of the fourth NAND gate, a second terminal of the third resistor and a second terminal of the third capacitor are commonly connected, and a second input terminal of the fourth NAND gate is electrically connected to a second input terminal of the third NAND gate; in, By disposing the first dead zone unit and the second dead zone unit, the first switch bridge arm and the second switch bridge arm are not turned on at the same time.

16. The power circuit as claimed in claim 15, wherein the power circuit further comprises an RS trigger, a first input terminal of the RS trigger signal receives the second direction signal, a second input terminal of the RS trigger receives an output terminal of the fourth NAND gate, and an output terminal of the RS trigger outputs a first drive signal.

17. The power supply circuit as described in claim 16 further comprises a second NOT gate and an AND gate, after the second NOT gate inverts the first drive signal, and then obtains the second drive signal through the AND gate and the first direction signal to control the first switch bridge arm and the second switch bridge arm of the main power circuit.

18. A monostable trigger, applied to a debouncing circuit, the debouncing circuit receiving an AC signal, characterized in that: The monostable trigger contains: A first NOR gate, a first input terminal of the first NOR gate receives a DC jitter signal, the DC jitter signal includes a positive trigger pulse, wherein when the AC signal is commutated, the first input terminal of the first NOR gate receives the positive trigger pulse, and the positive trigger pulse is a first pulse rising edge of the DC jitter signal; a first capacitor, a first terminal of the first capacitor being electrically connected to an output terminal of the first NOR gate; a first resistor, a first end of the first resistor being electrically connected to a second end of the first capacitor, and a second end of the first resistor being electrically connected to a positive voltage source; and a first NOT gate, an input terminal of the first NOT gate being electrically connected to the first terminal of the first resistor and the second terminal of the first capacitor, an output terminal of the first NOT gate being electrically connected to a second input terminal of the first NOR gate, and the output terminal of the first NOT gate generating an output signal; When the first input terminal of the first NOR gate receives the positive trigger pulse, the output terminal of the first NOR gate is at a low level, so that the input terminal of the first NOR gate is at a low level and the output terminal of the first NOR gate is at a high level, and the output terminal of the first NOR gate is fed back to the second input terminal of the first NOR gate to form a loop, so that the output signal remains stable within a set time.

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