Charge pump, phase-locked loop, chip and electronic equipment

Abstract

The invention discloses a charge pump, a phase-locked loop, a chip and electronic equipment, and belongs to the technical field of integrated circuits, and the charge pump comprises a bias sub-circuit which is electrically connected with a first current source in an output sub-circuit, and is used for transmitting a first bias signal to the first current source according to an external bias signal; the first current source is kept in a working state under the control of the first bias signal; the output sub-circuit comprises a first branch formed by sequentially connecting a first current source, a first switch assembly and a second current source in series, and a second branch formed by sequentially connecting the first current source, a second switch assembly and the second current source in series; the second current source is kept in a working state under the control of an external bias signal; an amplification module is arranged between the first branch and the second branch; an in-phase input end of the amplification module is electrically connected with a first node in the first switch assembly, and an inverted input end and an output end of the amplification module are electrically connected with a second node in the second switch assembly respectively; the first node is also connected with a load capacitor. A high-speed charge pump is provided.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuits, and specifically relates to a charge pump, a phase-locked loop, a chip and an electronic device. Background Art

[0002] In a phase-locked loop system, a phase frequency detector (PFD) can identify the phase error between the input signal of an external clock source and the feedback signal of a voltage-controlled oscillator (VCO) in the system, and output two output signals, up and dn, to a charge pump (CP).

[0003] The current charge pump generally includes an up current source and a down current source, and two switch tubes are set between the two current sources and connected to the load capacitor. The two switch tubes are controlled by the up signal and the dn signal respectively. The charge pump charges and discharges the load capacitor by detecting the phase difference between the input signals up and dn, thereby changing the output voltage value on the load capacitor.

[0004] However, the internal transistors and switch tubes of the current source use MOS tubes, that is, Metal-Oxide-Semiconductor (MOS) field-effect tubes. When the switch tube is turned off or on, the capacitor of the internal transistor of the current source needs to complete the charging and discharging process before the current source can enter the normal operating point, resulting in the problem of slow speed of the charge pump. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a charge pump, a phase-locked loop, a chip and an electronic device, which can solve the problem of slow charge pump speed.

[0006] In a first aspect, an embodiment of the present application provides a charge pump, the charge pump comprising: an output subcircuit and a bias subcircuit;

[0007] The bias subcircuit is electrically connected to a control end of a first current source in the output subcircuit, and is used to receive an external bias signal, and send a first bias signal to the first current source according to the external bias signal; the first current source maintains a working state under the control of the first bias signal;

[0008] The output subcircuit comprises a first branch formed by the first current source, a first switch component and a second current source connected in series in sequence, and a second branch formed by the first current source, a second switch component and the second current source connected in series in sequence; a control end of the second current source is used to receive the external bias signal, and the second current source maintains a working state under the control of the external bias signal;

[0009] In the output subcircuit, an amplification module is arranged between the first branch and the second branch; a non-inverting input terminal of the amplification module is electrically connected to a first node in the first switch component, and an inverting input terminal and an output terminal are electrically connected to a second node in the second switch component respectively; the first node is also connected to a load capacitor;

[0010] The first switch component is used to control the on-off of the first current source and the first node in response to a first control signal, and to control the on-off of the first node and the second current source in response to a second control signal; the second switch component is used to control the on-off of the first current source and the second node in response to an inverted signal of the first control signal, and to control the on-off of the second node and the second current source in response to an inverted signal of the second control signal.

[0011] Optionally, the first switch component includes: a first switch module and a second switch module connected in series in sequence; an intermediate node between the first switch module and the second switch module is the first node; wherein the first switch module is used to control the on-off of the first current source and the first node in response to the first control signal; and the second switch module is used to control the on-off of the first node and the second current source in response to the second control signal;

[0012] The second switch component includes: a third switch module and a fourth switch module connected in series in sequence; the intermediate node between the third switch module and the fourth switch module is the second node; wherein the third switch module is used to control the on-off of the first current source and the second node in response to the inverted signal of the first control signal; the fourth switch module is used to control the on-off of the second node and the second current source in response to the inverted signal of the second control signal.

[0013] Optionally, the first switch module includes a first transistor and a second transistor, and the first transistor and the second transistor are of opposite types;

[0014] A first electrode of the first transistor is electrically connected to the first node, a second electrode is electrically connected to the first current source, and a control electrode is used to receive a first sub-signal;

[0015] The first electrode of the second transistor is electrically connected to the first current source, the second electrode is electrically connected to the first node, and the control electrode is used to receive a second sub-signal; wherein the second sub-signal is an inverted signal of the first sub-signal; and the first control signal includes the first sub-signal and the second sub-signal.

[0016] Optionally, the second switch module includes a third transistor; a first electrode of the third transistor is electrically connected to the second current source, a second electrode is electrically connected to the first node, and a control electrode is used to receive the second control signal.

[0017] Optionally, the third switch module includes a fourth transistor and a fifth transistor, and the fourth transistor and the fifth transistor are of opposite types;

[0018] The first electrode of the fourth transistor is electrically connected to the second node, the second electrode is electrically connected to the first current source, and the control electrode is used to receive a third sub-signal; wherein the third sub-signal is an inverted signal of the first sub-signal;

[0019] The first electrode of the fifth transistor is electrically connected to the first current source, the second electrode is electrically connected to the second node, and the control electrode is used to receive a fourth sub-signal; wherein the fourth sub-signal is an inverted signal of the second sub-signal; the first control signal includes the first sub-signal and the second sub-signal; and the inverted signal of the first control signal includes the third sub-signal and the fourth sub-signal.

[0020] Optionally, the fourth switch module includes a sixth transistor; the sixth transistor is of the same type as the third transistor;

[0021] The first electrode of the sixth transistor is electrically connected to the second current source, the second electrode is electrically connected to the second node, and the control electrode is used to receive the inverted signal of the second control signal.

[0022] Optionally, the amplification module includes a first amplifier;

[0023] The non-inverting input terminal of the first amplifier is electrically connected to the first node, the inverting input terminal of the first amplifier is electrically connected to the output terminal of the first amplifier, and the output terminal of the first amplifier is electrically connected to the second node; wherein the first amplifier is a unity gain amplifier.

[0024] Optionally, the charge pump further includes:

[0025] A third branch is formed by sequentially connecting the first current source, the fifth switch module, the sixth switch module and the second current source in series; the middle node between the fifth switch module and the sixth switch module is a third node;

[0026] The fifth switch module has the same structure as the third switch module; the fifth switch module is used to control the on / off of the first current source and the third node in response to the inverted signal of the first control signal;

[0027] The sixth switch module has the same structure as the fourth switch module; the sixth switch module is used to control the on-off of the third node and the second current source in response to the inverted signal of the second control signal.

[0028] Optionally, the bias subcircuit includes a plurality of auxiliary branches, each of which includes an upper current source, a switch module and a lower current source connected in series in sequence;

[0029] The middle node between the first switch component and the second current source is a fourth node; the fourth node is electrically connected to a fifth node between the switch module and the lower current source in one of the auxiliary branches; the voltage signals at the fourth node and the fifth node are the first bias signal;

[0030] The control end of the upper current source is electrically connected to the fifth node and is used to receive the first bias signal; the control end of the lower current source is used to receive the external bias signal;

[0031] The switch modules in the plurality of auxiliary branches are used to switch on at least one of the auxiliary branches under the control of the first control signal, the inverted signal of the first control signal, the second control signal and the inverted signal of the second control signal.

[0032] Optionally, the plurality of auxiliary branches include:

[0033] The fourth branch is composed of a third current source, a seventh switch module, an eighth switch module and a fourth current source connected in series in sequence; the middle node between the eighth switch module and the fourth current source is the fifth node; the seventh switch module is used to control the on-off of the third current source and the sixth node in response to the first control signal; the eighth switch module is used to control the on-off of the sixth node and the fourth current source in response to the second control signal; wherein the sixth node is the middle node between the seventh switch module and the eighth switch module;

[0034] The fifth branch is composed of a fifth current source, a ninth switch module, a tenth switch module and the fourth current source connected in series in sequence; the ninth switch module is used to control the fifth current source and the seventh node to remain in a conductive state in response to the first constant signal; the tenth switch module is used to control the on-off of the seventh node and the fourth current source in response to the inverted signal of the second control signal; wherein the seventh node is an intermediate node between the ninth switch module and the tenth switch module;

[0035] a sixth branch, which is composed of the third current source, the eleventh switch module, the twelfth switch module and the sixth current source connected in series in sequence; the eleventh switch module is used to control the on-off of the third current source and the eighth node in response to the inverted signal of the first control signal; the twelfth switch module is used to control the eighth node and the sixth current source to maintain a conducting state in response to the second constant signal; wherein the eighth node is an intermediate node between the eleventh switch module and the twelfth switch module;

[0036] Among them, the upper current source includes the third current source and the fifth current source, and the lower current source includes the fourth current source and the sixth current source; the fifth node is electrically connected to the control end of the third current source and the control end of the fifth current source respectively.

[0037] Optionally, the seventh switch module has the same structure as the first switch module, and the eighth switch module has the same structure as the second switch module;

[0038] The ninth switch module has the same structure as the third switch module, and the tenth switch module has the same structure as the fourth switch module;

[0039] The eleventh switch module has the same structure as the seventh switch module, and the twelfth switch module has the same structure as the eighth switch module.

[0040] In a second aspect, an embodiment of the present application provides a phase-locked loop, which includes a charge pump as described in the first aspect.

[0041] In a third aspect, an embodiment of the present application provides a chip, wherein the chip includes the charge pump as described in the first aspect.

[0042] In a fourth aspect, an embodiment of the present application provides an electronic device, wherein the electronic device comprises the chip as described in the third aspect.

[0043] A charge pump, a phase-locked loop, a chip and an electronic device provided in the embodiments of the present application have at least the following advantages: a first current source in a working state can be connected to at least one of the first node or the second node through a first switch component and a second switch component. Similarly, a second current source in a working state can also be connected to at least one of the first node or the second node through the first switch component and the second switch component, so that there is no process of turning the first current source and the second current source from turning off to turning on, thereby avoiding the problem in the related art that when the switch tube is turned off or on, the capacitance of the transistor inside the current source needs to complete the charging and discharging process before the current source can enter a normal working point, thereby providing a high-speed charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of input signal and output signal of frequency detector and phase detector in the related art;

[0045] Figure 2 This is one of the structural schematic diagrams of a charge pump provided in an embodiment of the present application;

[0046] Figure 3 It is a schematic diagram of the structure of a drain switch charge pump in the related art;

[0047] Figure 4 This is the second structural diagram of a charge pump provided in an embodiment of the present application;

[0048] Figure 5 This is the third structural diagram of a charge pump provided in an embodiment of the present application;

[0049] Figure 6 This is a fourth structural diagram of a charge pump provided in an embodiment of the present application;

[0050] Figure 7 is a structural schematic diagram of a switch module in a charge pump provided in an embodiment of the present application;

[0051] Figure 8 The embodiment of this application provides Figure 6 One of the equivalent circuit diagrams of the charge pump shown;

[0052] Fig. 9 The embodiment of this application provides Figure 6 The second equivalent circuit diagram of the charge pump shown;

[0053] Fig.10 The embodiment of this application provides Figure 6 The equivalent circuit diagram of the charge pump shown in FIG.

[0054] Fig.11 This is the fifth structural diagram of a charge pump provided in an embodiment of the present application;

[0055] Fig.12 This is one of the simulation schematic diagrams of a phase-locked loop provided in an embodiment of the present application;

[0056] Fig.13 This is the second simulation schematic diagram of a phase-locked loop provided in an embodiment of the present application;

[0057] Fig.14 This is a third simulation schematic diagram of a phase-locked loop provided in an embodiment of the present application;

[0058] Fig.15 This is the fourth simulation schematic diagram of a phase-locked loop provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0060] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or at least two. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0061] In the related art, the phase-locked loop system includes a phase frequency detector (PFD), a charge pump, a loop filter (LF) and a voltage-controlled oscillator (VCO) connected in sequence. The output signal of the voltage-controlled oscillator (VCO) is also processed by a frequency divider (FD) and provided to the phase frequency detector (PFD) as a feedback signal. The phase frequency detector (PFD) receives two input signals, one is a reference signal Fref_in from an external clock source, and the other is a feedback signal Fbck_in.

[0062] like Figure 1 As shown, the phase frequency detector PFD identifies the phase error between the reference signal Fref_in and the feedback signal Fbck_in. According to the result of the phase comparison, the phase frequency detector PFD generates two output signals: up and dn, and then transmits the up and dn signals to the charge pump. The charge pump effectively charges and discharges the load capacitor according to the phase difference between the output signals up and dn of the phase frequency detector PFD. The load capacitor can be the capacitor of the loop filter LF. The charge pump converts the output signals up and dn into charge and discharge currents. The net charge and discharge of the capacitor of the loop filter LF will increase or decrease the frequency of the voltage-controlled oscillator VCO until the reference clock frequency is equal to the feedback clock frequency.

[0063] In the following, in conjunction with the accompanying drawings, a charge pump, a phase-locked loop, a chip and an electronic device provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0064] Figure 2 is one of the structural diagrams of a charge pump provided in an embodiment of the present application, such as Figure 2 As shown, the charge pump includes: an output subcircuit 10 and a bias subcircuit 20;

[0065] The bias subcircuit 20 is electrically connected to the control end of the first current source I3 in the output subcircuit 10, and is used to receive an external bias signal bias, and send a first bias signal pbias to the first current source I3 according to the external bias signal bias; the first current source I3 maintains a working state under the control of the first bias signal pbias;

[0066] The output sub-circuit 10 includes a first branch formed by a first current source I3, a first switch component 101 and a second current source I6 connected in series in sequence, and a second branch formed by a first current source I3, a second switch component 102 and a second current source I6 connected in series in sequence; a control end of the second current source I6 is used to receive an external bias signal bias, and the second current source I6 maintains a working state under the control of the external bias signal bias;

[0067] In the output subcircuit 10, an amplifier module 103 is arranged between the first branch and the second branch; the in-phase input terminal of the amplifier module 103 is electrically connected to the first node A in the first switch component 101, and the inverting input terminal and the output terminal are electrically connected to the second node A' in the second switch component 102 respectively; the first node A is also connected to the load capacitor;

[0068] The first switch component 101 is used to control the on-off of the first current source I3 and the first node A in response to the first control signal, and to control the on-off of the first node A and the second current source I6 in response to the second control signal; the second switch component 102 is used to control the on-off of the first current source I3 and the second node A' in response to the inverted signal of the first control signal, and to control the on-off of the second node A' and the second current source I6 in response to the inverted signal of the second control signal.

[0069] In some embodiments, the charge pump can be applied to a phase-locked loop system to receive an output signal up and an output signal dn sent by a phase frequency detector (PFD). The output signal up can be used as the first control signal of an embodiment of the present application, and the output signal dn can be used as the second control signal of an embodiment of the present application. Alternatively, the first control signal may include the output signal up and its inverted signal upb, and the second control signal is the output signal dn. This is merely an example, and the embodiments of the present application are not limited to this. The first node A can be connected to a load capacitor, and the load capacitor can be the capacitor of a loop filter LF. The first node A can be used as the output end of the charge pump to provide a charge and discharge current to the load capacitor.

[0070] In some embodiments, the external bias signal bias is an externally input control signal, and the external bias signal bias is input to the control terminal of the second current source I6, which can keep the second current source I6 in an operating state. For example, the external bias signal bias is input to the control electrode of the internal transistor of the second current source I6, so that the transistor remains in a conductive state, thereby keeping the second current source I6 in an operating state. The external bias signal bias is also input to the bias subcircuit 20, and the bias subcircuit 20 generates a first bias signal pbias according to the external bias signal bias and the circuit self-bias. The bias subcircuit 20 is electrically connected to the control terminal of the first current source I3 in the output subcircuit 10, and can send the first bias signal pbias to the first current source I3, so that the first current source I3 can remain in an operating state. For example, the first bias signal pbias is input to the control electrode of the internal transistor of the first current source I3, so that the transistor remains in a conductive state, thereby keeping the first current source I3 in an operating state.

[0071] In some embodiments, the output subcircuit 10 is used as the core output circuit of the charge pump, and includes two current branches, a first branch and a second branch, wherein the first branch is used as the main current branch and the second branch is used as the replica current branch. The first branch is controlled by the first control signal and the second control signal, and the second branch is controlled by the inverted signal of the first control signal and the inverted signal of the second control signal.

[0072] In some embodiments, the first node A in the first switch component 101 in the first branch is connected to the load capacitor, and the first switch component 101 receives the first control signal and the second control signal, and can control the on-off of the first current source I3 and the first node A in response to the first control signal, and control the on-off of the first node A and the second current source I6 in response to the second control signal. The first current source I3 in the output subcircuit 10 can be connected to the system power supply, and the second current source I6 can be grounded, that is, the first current source I3 and the second current source I6 can be used as the up current source and down current source of the charge pump. When the first current source I3 is turned on with the first node A, the first current source I3 charges the load capacitor, and when the first node A is turned on with the second current source I6, the second current source I6 discharges the load capacitor. In this way, the charge pump can charge and discharge the load capacitor by detecting the phase difference between the first control signal and the second control signal.

[0073] In some embodiments, an amplifier module 103 is provided between the first branch and the second branch, and the amplifier module 103 has two input terminals, namely, a non-inverting input terminal and an inverting input terminal, and an output terminal. The non-inverting input terminal of the amplifier module 103 is electrically connected to the first node A in the first switch component 101, and the inverting input terminal and the output terminal are electrically connected to the second node A' in the second switch component 102, respectively, so that the first node A of the first branch and the second node A' of the second branch are connected together through the amplifier module 103. In addition, the second switch component 102 can receive the inverted signal of the first control signal and the inverted signal of the second control signal, and can control the on-off of the first current source I3 and the second node A' in response to the inverted signal of the first control signal, and control the on-off of the second node A' and the second current source I6 in response to the inverted signal of the second control signal.

[0074] In some embodiments, when the first switch component 101 in the first branch conducts the first current source I3 and the first node A under the control of the first control signal, and disconnects the first node A and the second current source I6 under the control of the second control signal, and the second switch component 102 in the second branch disconnects the first current source I3 and the second node A' under the control of the inverted signal of the first control signal, and conducts the second node A' and the second current source I6 under the control of the inverted signal of the second control signal, the first current source I3 in the working state can charge the load capacitor through the first node A. At the same time, the second current source I6 in the working state is connected to the second node A', and due to the existence of the amplification module 103, the current path from the amplification module 103 to the second node A' and then to the second current source I6 in the second branch is in an open state, so that the second current source I6 does not have a process from closing to opening.

[0075] In some embodiments, when the first switch component 101 in the first branch disconnects the first current source I3 and the first node A under the control of the first control signal, and connects the first node A and the second current source I6 under the control of the second control signal, and the second switch component 102 in the second branch connects the first current source I3 and the second node A' under the control of the inverted signal of the first control signal, and disconnects the second node A' and the second current source I6 under the control of the inverted signal of the second control signal, the second current source I6 in the working state can discharge the load capacitor through the second node A'. At the same time, the first current source I3 in the working state is connected to the second node A', and due to the existence of the amplification module 103, the current path from the first current source I3 to the second node A' and then to the amplification module 103 in the second branch is in an open state, so that the first current source I3 does not have a process from closing to opening.

[0076] In some embodiments, when the first current source I3 in the first branch is turned on to the first node A and the first node A is turned on to the second current source I6, and the first current source I3 in the second branch is turned off to the second node A' and the second node A' is turned off to the second current source I6, or, when the first current source I3 in the first branch is turned off to the first node A and the first node A is turned off to the second current source I6, and the first current source I3 in the second branch is turned on to the second node A' and the second node A' is turned on to the second current source I6, in both cases, the voltage of the first node A remains unchanged, and therefore the charge pump is in a hold state. In this way, the first current source I3 in the working state can be turned on with at least one of the first node A or the second node A' through the first switch component 101 and the second switch component 102. Similarly, the second current source I6 in the working state can also be turned on with at least one of the first node A or the second node A' through the first switch component 101 and the second switch component 102, so that there is no process of turning off and on for the first current source I3 and the second current source I6, avoiding the problem in the related art that when the switch tube is turned off or on, the capacitance of the transistor inside the current source needs to complete the charging and discharging process before the current source can enter the normal working point, thereby providing a high-speed charge pump.

[0077] Optionally, the first switch component 101 includes: a first switch module 1011 and a second switch module 1012 connected in series in sequence; the middle node between the first switch module 1011 and the second switch module 1012 is a first node A; wherein the first switch module 1011 is used to control the on-off of the first current source I3 and the first node A in response to a first control signal; the second switch module 1012 is used to control the on-off of the first node A and the second current source I6 in response to a second control signal;

[0078] The second switch component 102 includes: a third switch module 1021 and a fourth switch module 1022 connected in series in sequence; the middle node between the third switch module 1021 and the fourth switch module 1022 is the second node A'; wherein the third switch module 1021 is used to control the on-off of the first current source I3 and the second node A' in response to the inverted signal of the first control signal; the fourth switch module 1022 is used to control the on-off of the second node A' and the second current source I6 in response to the inverted signal of the second control signal.

[0079] In some embodiments, the second branch is used as a replica current branch, and the second switch component 102 can be obtained by replicating the first switch component 101. Specifically, the first switch component 101 includes a first switch module 1011 and a second switch module 1012 connected in series, and the second switch component 102 includes a third switch module 1021 and a fourth switch module 1022 connected in series. The third switch module 1021 is controlled by an inverted signal of a first control signal corresponding to the first switch module 1011, and the fourth switch module 1022 is controlled by an inverted signal of a second control signal corresponding to the second switch module 1012.

[0080] In this way, between the two paths of the first current source I3 and the first node A or the second node A', one of the paths can be flexibly controlled to be turned on by the first switch module 1011 and the third switch module 1021. Similarly, between the two paths of the second current source I6 and the first node A or the second node A', one of the paths can be flexibly controlled to be turned on by the second switch module 1012 and the fourth switch module 1022, so that there is no process of turning off and on between the first current source I3 and the second current source I6, which has the advantage of a simple circuit structure.

[0081] Optionally, the first switch module 1011 includes a first transistor M14 and a second transistor M15, and the types of the first transistor M14 and the second transistor M15 are opposite;

[0082] The first electrode of the first transistor M14 is electrically connected to the first node A, the second electrode is electrically connected to the first current source I3, and the control electrode is used to receive the first sub-signal;

[0083] The first electrode of the second transistor M15 is electrically connected to the first current source I3, the second electrode is electrically connected to the first node A, and the control electrode is used to receive the second sub-signal; wherein the second sub-signal is an inverted signal of the first sub-signal; and the first control signal includes the first sub-signal and the second sub-signal.

[0084] In some embodiments, the first switch module 1011 may be composed of two opposite-type transistors, a first transistor M14 and a second transistor M15, and the effective levels corresponding to the opposite-type transistors are opposite. The first control signal includes a first sub-signal and a second sub-signal, and the second sub-signal is an inverted signal of the first sub-signal. For example, if the first sub-signal is a high-level signal, the second sub-signal is a low-level signal. For example, the first switch module 1011 may be composed of an N-type MOS tube and a P-type MOS tube, and the N-type MOS tube, i.e., the NMOS tube, is effective at a high level, and the P-type MOS tube, i.e., the PMOS tube, is effective at a low level.

[0085] In some embodiments, the first transistor M14 is an NMOS tube, and the second transistor M15 is a PMOS tube, and the NMOS tube is connected in parallel with the PMOS tube. The first electrode of the first transistor M14 is the source of the NMOS tube and is electrically connected to the first node A, the second electrode is the drain of the NMOS tube and is electrically connected to the first current source I3, and the control electrode is the gate of the NMOS tube. The first electrode of the second transistor M15 is the source of the PMOS tube and is electrically connected to the first current source I3, the second electrode is the drain of the PMOS tube and is electrically connected to the first node A, and the control electrode is the gate of the PMOS tube.

[0086] In some embodiments, the first control signal may include an output signal up of a phase frequency detector PFD, and an inverted signal upb of the output signal up may be obtained through an inverter, wherein the first sub-signal is the output signal up, and the second sub-signal is the inverted signal upb. When the first transistor M14, i.e., the NMOS tube, receives the first sub-signal up, if the first sub-signal up is at a high level, the NMOS tube is turned on, otherwise the NMOS tube is turned off. Similarly, when the second transistor M15, i.e., the PMOS tube, receives the second sub-signal upb, if the second sub-signal upb is at a low level, the PMOS tube is turned on, otherwise the PMOS tube is turned off.

[0087] In this way, the output signal up of the phase frequency detector PFD and its inverted signal upb can control the first transistor M14 and the second transistor M15 to be turned on or off simultaneously, thereby turning on or off the first current source I3 and the first node A. When the first current source I3 is turned on the first node A, for example, when the NMOS tube and the PMOS tube are turned on at the same time, the driving capability can be improved by the parallel NMOS tube and the PMOS tube, that is, the driving capability of the load capacitor can be improved by the first transistor M14 and the second transistor M15.

[0088] Optionally, the third switch module 1021 includes a fourth transistor M16 and a fifth transistor M17, and the fourth transistor M16 and the fifth transistor M17 are of opposite types;

[0089] The first electrode of the fourth transistor M16 is electrically connected to the second node A', the second electrode is electrically connected to the first current source I3, and the control electrode is used to receive the third sub-signal; wherein the third sub-signal is an inverted signal of the first sub-signal;

[0090] The first electrode of the fifth transistor M17 is electrically connected to the first current source I3, the second electrode is electrically connected to the second node A', and the control electrode is used to receive the fourth sub-signal; wherein the fourth sub-signal is an inverted signal of the second sub-signal; the first control signal includes the first sub-signal and the second sub-signal; and the inverted signal of the first control signal includes the third sub-signal and the fourth sub-signal.

[0091] In some embodiments, the third switch module 1021 in the second branch may be obtained by duplicating the first switch module 1011, and the third switch module 1021 includes a fourth transistor M16 and a fifth transistor M17 of opposite types. Since the third switch module 1021 is controlled by the inverted signal of the first control signal, and the first control signal includes the first sub-signal and the second sub-signal, the inverted signal of the first control signal includes the third sub-signal and the fourth sub-signal, wherein the third sub-signal is the inverted signal of the first sub-signal, and the fourth sub-signal is the inverted signal of the second sub-signal. For example, the third switch module 1021 may be composed of an NMOS tube and a PMOS tube, and the NMOS tube and the PMOS tube are connected between the first current source I3 and the second node A'.

[0092] In some embodiments, the fourth transistor M16 is an NMOS transistor, and the fifth transistor M17 is a PMOS transistor, the NMOS transistor is connected in parallel with the PMOS transistor, and the connection method of the NMOS transistor and the PMOS transistor refers to the first switch module 1011. The third sub-signal is the inverted signal upb of the first sub-signal up, and the fourth sub-signal is the inverted signal up of the second sub-signal upb, that is, the first control signal includes the first sub-signal up and the second sub-signal upb, and the inverted signal of the first control signal includes the third sub-signal upb and the fourth sub-signal up. In this way, the output signal up of the phase frequency detector PFD and its inverted signal upb can control the fourth transistor M16 and the fifth transistor M17 to turn on or off at the same time, thereby turning on or off the first current source I3 and the second node A'.

[0093] In the phase-locked loop system, under the control of the output signal up of the phase frequency detector PFD and its inverted signal upb, the first current source I3 in the charge pump is at least connected to one of the nodes between the first node A and the second node A', that is, the first current source I3 in the working state is turned on at least one way in the current path between the first node A and the second node A', and the first current source I3 does not have a process of turning off to turning on. Therefore, the problem that the capacitance of the internal transistor of the current source needs to complete the charging and discharging process when the switch tube is turned off or turned on in the related art can be avoided, and the switching speed of the first switch module 1011 and the switching speed of the third switch module 1021 can be improved, thereby improving the speed of the charge pump.

[0094] Optionally, the second switch module 1012 includes a third transistor M13; a first electrode of the third transistor M13 is electrically connected to the second current source I6, a second electrode is electrically connected to the first node A, and a control electrode is used to receive a second control signal.

[0095] In some embodiments, the second control signal may be an output signal dn of the phase frequency detector PFD. In the phase-locked loop system, the third transistor M13 may be electrically connected to a signal output terminal of the phase frequency detector PFD to receive the second control signal dn sent by the phase frequency detector PFD. The third transistor M13 may be an NMOS transistor or a PMOS transistor, where the NMOS transistor is effective at a high level and the PMOS transistor is effective at a low level. This is merely an example, and the embodiments of the present application are not limited thereto.

[0096] For example, the third transistor M13 may be an NMOS tube, and the high level of the NMOS tube is effective. When the second control signal dn is at a high level, the third transistor M13, that is, the NMOS tube, is turned on, otherwise the NMOS tube is turned off. The first electrode of the third transistor M13 is the source of the NMOS tube and is electrically connected to the first node A, the second electrode is the drain of the NMOS tube and is electrically connected to the second current source I6, and the control electrode is the gate of the NMOS tube, which is used to receive the second control signal dn.

[0097] In some embodiments, the output signal dn of the phase frequency detector PFD can control the third transistor M13 to turn on or off, thereby turning on or off the second current source I6 and the first node A. When the second current source I6 in the working state is grounded, and the third transistor M13 turns on the first node A and the second current source I6, a current path from the first node A to the second current source I6 and then to the ground terminal generates a discharge current, thereby discharging the load capacitor through the first node A.

[0098] Optionally, the fourth switch module 1022 includes a sixth transistor M12; the sixth transistor M12 is of the same type as the third transistor M13;

[0099] A first electrode of the sixth transistor M12 is electrically connected to the second current source I6 , a second electrode is electrically connected to the second node A′, and a control electrode is used to receive an inverted signal of the second control signal.

[0100] In some embodiments, the second control signal may be an output signal dn of a phase frequency detector (PFD), and an inverted signal dnb of the output signal dn may be obtained through an inverter. The fourth switch module 1022 may be obtained by copying the second switch module 1012, and the control electrode of the sixth transistor M12 may be electrically connected to the output terminal of the inverter. The sixth transistor M12 may be an NMOS transistor or a PMOS transistor, and the sixth transistor M12 is of the same type as the third transistor M13. For example, if the third transistor M13 is an NMOS transistor, the sixth transistor M12 is also an NMOS transistor. This is merely an example, and the embodiments of the present application are not limited thereto.

[0101] For example, the sixth transistor M12 is an NMOS tube. When the inverted signal dnb of the second control signal is at a high level, the sixth transistor M12, that is, the NMOS tube, is turned on, otherwise the NMOS tube is turned off. The sixth transistor M12, that is, the NMOS tube, is connected between the second node A' and the second current source I6. The connection method of the NMOS tube can refer to the relevant description of the third transistor M13 being an NMOS tube.

[0102] In some embodiments, when the output signal dn of the phase frequency detector PFD controls the third transistor M13 to turn on, the inverted signal dnb controls the sixth transistor M12 to turn off, so that the first node A is connected to the second current source I6 and the second node A' is disconnected from the second current source I6. Conversely, when the output signal dn of the phase frequency detector PFD controls the third transistor M13 to turn off, the inverted signal dnb controls the sixth transistor M12 to turn on, so that the first node A is disconnected from the second current source I6 and the second node A' is connected to the second current source I6.

[0103] In the phase-locked loop system, under the control of the output signal dn of the phase frequency detector PFD and its inverted signal dnb, the second current source I6 in the charge pump is at least connected to one of the nodes between the first node A and the second node A', that is, the second current source I6 in the working state is turned on at least one way in the current path between the first node A and the second node A', and the second current source I6 does not have a process of turning off to turning on. Therefore, the problem that the capacitance of the internal transistor of the current source needs to complete the charging and discharging process when the switch tube is turned off or turned on in the related art can be avoided, and the switching speed of the second switch module 1012 and the switching speed of the fourth switch module 1022 can be improved, thereby improving the speed of the charge pump.

[0104] Figure 3 is a schematic diagram of a drain switch charge pump in the related art, such as Figure 3 As shown, the charge pump of the drain switch includes: an up current source and a down current source composed of a PMOS current mirror and an NMOS current mirror. The two switch tubes located between the drains of the MOS tubes inside the up and down current sources are an NMOS tube and a PMOS tube, the PMOS switch tube is controlled by an up signal, the NMOS switch tube is controlled by a dn signal, the middle node of the two switch tubes is connected to a load capacitor, and the voltage on the middle node is VCN.

[0105] However, if Figure 3As shown in the figure, when the PMOS switch is turned off, the drain capacitor of the PMOS current mirror will be charged to the system power supply voltage VDD, and when the PMOS switch is turned on, since the output voltage is usually lower than the system power supply voltage VDD, the drain capacitor of the PMOS current mirror will be discharged to the output end. That is, when the PMOS switch is turned off and on, the drain capacitor of the PMOS current mirror needs to complete the charging and discharging process, so that the charge pump can work normally, and change the voltage VCN on the intermediate node by charging and discharging the load capacitor.

[0106] The same is true for the NMOS switch tube. When the NMOS switch tube is turned off, the drain voltage of the NMOS current mirror is zero, causing the drain capacitor to be completely discharged. When the NMOS switch tube is turned on, the drain voltage of the NMOS current mirror will rise to the same voltage as the output terminal, that is, the drain capacitor completes the charging process. Because the current source drain capacitor needs to complete the charging and discharging process when the switch tube is turned off and on before the current source can enter the normal operating point, the switching speed is slow, resulting in the problem of slow charge pump speed.

[0107] The charge pump is very important in the phase-locked loop system. The non-ideal effect of the charge pump determines the size of the spurious signal and also causes longer noise injection, which has a great impact on the entire phase-locked loop system. For example, the current charge pump has a charge sharing problem.

[0108] Charge sharing refers to the phenomenon of charge redistribution. Figure 3 Take the drain switch charge pump shown in the figure as an example. When both switch tubes are turned off, the drain voltages of the transistors in the PMOS current mirror and the NMOS current mirror are VDD and GND respectively, and the voltage of the output node is an uncertain value. When the two switch tubes are turned on at the same time, the drain voltages of the transistors in the two current mirrors are different from the voltage of the output node, which will lead to the need to redistribute the charge. Charge sharing will cause jitter in the charge pump output voltage and deteriorate the phase noise of the phase-locked loop.

[0109] Optionally, the amplification module 103 includes a first amplifier 1031;

[0110] The non-inverting input terminal of the first amplifier 1031 is electrically connected to the first node A, the inverting input terminal of the first amplifier 1031 is electrically connected to the output terminal of the first amplifier 1031, and the output terminal of the first amplifier 1031 is electrically connected to the second node A′; wherein the first amplifier 1031 is a unit gain amplifier.

[0111] In some embodiments, the amplification module 103 uses a unit gain amplifier to solve the charge sharing problem of the charge pump. Specifically, a first amplifier 1031 is connected between the first branch and the second branch, and the first amplifier 1031 is a unit gain amplifier, for example, the first amplifier 1031 can be a unit gain operational amplifier. The in-phase input terminal of the first amplifier 1031 is electrically connected to the first node A, the inverting input terminal of the first amplifier 1031 is electrically connected to the output terminal of the first amplifier 1031, and the output terminal of the first amplifier 1031 is electrically connected to the second node A'.

[0112] Thus, between the first branch and the second branch, due to the presence of the first amplifier 1031, the voltages of the first node A and the second node A' are kept consistent, and the voltage of the first node A is clamped at the output voltage VCN. Therefore, the charge sharing effect originally caused by the constant change of the drain voltage of the switch tube no longer exists, which can effectively solve the charge sharing problem of the charge pump, reduce the output voltage ripple of the charge pump, reduce the noise of the phase-locked loop, and provide a high-speed and low-charge-sharing charge pump.

[0113] Figure 4 This is a second schematic diagram of a charge pump structure provided in an embodiment of the present application. Figure 4 As shown, the first current source I3 includes a PMOS tube M18, the control end of the first current source I3 is the gate of the PMOS tube M18, the gate of the PMOS tube M18 is connected to the bias sub-circuit 20, and can receive the first bias signal pbias sent by the bias sub-circuit 20, and the source of the PMOS tube M18 can be connected to the system power supply. The first bias signal pbias can be a low-level signal, and under the control of the first bias signal pbias, the PMOS tube M18 is in an on state, so that the first current source I3 remains in a working state. The second current source I6 includes an NMOS tube M11, and the control end of the second current source I6 is the gate of the NMOS tube M11, which is used to receive the external bias signal bias, and the source of the NMOS tube M11 can be grounded. The external bias signal bias can be a high-level signal, and under the control of the external bias signal bias, the NMOS tube M11 is in an on state, so that the second current source I6 remains in a working state.

[0114] like Figure 4As shown, the first branch in the output subcircuit 10 includes a first current source I3, namely a PMOS tube M18, a first transistor M14, a second transistor M15, a third transistor M13, and a second current source I6, namely an NMOS tube M11. The first node A in the first branch is connected to the load capacitor C, and an output voltage VCN is generated on the first node A. The second branch in the output subcircuit 10 includes a first current source I3, namely a PMOS tube M18, a fourth transistor M16, a fifth transistor M17, a sixth transistor M12, and a second current source I6, namely an NMOS tube M11. The first amplifier 1031 is connected between the first node A and the second node A', the in-phase input terminal (+) is connected to the first node A, the inverting input terminal (-) is connected to the output terminal, and the output terminal is connected to the second node A'.

[0115] like Figure 4 As shown, when the first node A and the first current source I3 and the second current source I6 in the first branch of the charge pump are all turned on, the second node A' and the first current source I3 and the second current source I6 in the second branch are all disconnected. Due to the existence of the unit gain operational amplifier, the voltage of the second node A' remains equal to the voltage of the first node A. When the first branch is completely turned off, the second node A' and the first current source I3 and the second current source I6 in the second branch are all turned on, and the voltage of the first node A will be consistent with the voltage of the second node A'. In this way, the voltage of the first node A can be clamped at the output voltage VCN by the unit gain operational amplifier, which can effectively solve the charge sharing problem of the charge pump.

[0116] like Figure 1 As shown, the phase frequency detector PFD generates an output signal up and an output signal dn. The inverted signal upb of the output signal up can be obtained through an inverter, and the inverted signal dnb of the output signal dn can be obtained through an inverter. The output signal up and its inverted signal upb are used as the first control signal of the charge pump of this embodiment, and the output signal dn is used as the second control signal of the embodiment of the present application. Figure 1 In the example, the output signal up is a pulse signal, the output signal dn is a square wave signal, and there is a phase difference between the high level of the output signal up and the high level of the output signal dn. Figure 4 The charge pump shown can effectively charge and discharge the load capacitor C according to the length of the up and dn control signals, and has the characteristics of high speed and low charge sharing.

[0117] Optionally, the charge pump further comprises:

[0118] The third branch is composed of the first current source I3, the fifth switch module, the sixth switch module and the second current source I6 connected in series in sequence; the middle node between the fifth switch module and the sixth switch module is the third node;

[0119] The fifth switch module has the same structure as the third switch module 1021; the fifth switch module is used to control the on-off of the first current source I3 and the third node in response to the inverted signal of the first control signal;

[0120] The sixth switch module has the same structure as the fourth switch module 1022 ; the sixth switch module is used to control the on-off of the third node and the second current source I6 in response to the inverted signal of the second control signal.

[0121] In some embodiments, the charge sharing problem can also be solved by a bootstrap circuit. The third branch can be obtained by copying the second branch. Specifically, the third branch includes a first current source I3, a fifth switch module, a sixth switch module and a second current source I6 connected in series in sequence, and the middle node between the fifth switch module and the sixth switch module is the third node. Among them, the fifth switch module has the same structure as the third switch module 1021, and the sixth switch module has the same structure as the fourth switch module 1022.

[0122] For example, the third switch module 1021 adopts Figure 4 The MOS transistor structure shown in FIG. 1 can also be used in the fifth switch module, and can also be controlled by the third sub-signal upb and the fourth sub-signal up that are the same as those of the third switch module 1021. The sixth switch module can be similarly used. Figure 4 The MOS tube structure shown in the fourth switch module 1022 is controlled by the inverted signal dnb of the second control signal.

[0123] Optionally, the bias subcircuit 20 includes a plurality of auxiliary branches, each of which includes an upper current source, a switch module and a lower current source connected in series in sequence;

[0124] The middle node between the first switch component 101 and the second current source I6 is a fourth node B; the fourth node B is electrically connected to a fifth node C between the switch module and the lower current source in an auxiliary branch; the voltage signals at the fourth node B and the fifth node C are the first bias signal pbias;

[0125] The control end of the upper current source is electrically connected to the fifth node C and is used to receive the first bias signal pbias; the control end of the lower current source is used to receive the external bias signal bias;

[0126] The switch modules in the plurality of auxiliary branches are used to conduct at least one auxiliary branch under the control of the first control signal, the inverted signal of the first control signal, the second control signal and the inverted signal of the second control signal.

[0127] In some embodiments, the first bias signal pbias is generated by the bias subcircuit 20 according to the external bias signal bias and the circuit self-bias. Specifically, in the output subcircuit 10 pair of branches, the middle node between the first switch component 101 and the second current source I6 is the fourth node B, and there is an auxiliary branch in the bias subcircuit 20, and the middle node between the switch module and the lower current source in the auxiliary branch is the fifth node C. In this embodiment, the fourth node B is electrically connected to the fifth node C, the fourth node B is grounded after passing through the second current source I6, and the fifth node C is grounded after passing through the lower current source in the auxiliary branch, and a bias voltage is generated at the fourth node B and the fifth node C, and the voltage signal is used as the first bias signal pbias of this embodiment.

[0128] In some embodiments, the structure of the auxiliary branch in the bias subcircuit 20 can refer to the structure of the main circuit branch in the output subcircuit 10, that is, the auxiliary branch is composed of an upper current source, a switch module and a lower current source connected in series in sequence. Among them, the upper current source refers to the first current source I3 in the output subcircuit 10, the control end of the upper current source is electrically connected to the fifth node C, receives the first bias signal pbias, and the upper current source maintains a working state under the control of the first bias signal pbias. The lower current source refers to the second current source I6 in the output subcircuit 10, and the control end of the lower current source is used to receive an external bias signal bias.

[0129] In some embodiments, the switch module in the auxiliary branch may refer to the structure of the switch module in the output sub-circuit 10, for example Figure 4 The MOS tube structure in the charge pump shown. The switch module in the auxiliary branch can be controlled by the first control signal and its inverted signal, and the second control signal and its inverted signal. Moreover, the switch modules in the multiple auxiliary branches are controlled by the first control signal, the inverted signal of the first control signal, the second control signal and the inverted signal of the second control signal, and at least one auxiliary branch in the bias subcircuit 20 is turned on. In this way, the voltage value of the first bias signal pbias can be stabilized near a certain value, so that the output voltage VCN at the first node A in the output subcircuit 10 has the smallest fluctuation, thereby reducing the phase noise and jitter in the phase-locked loop system.

[0130] Optionally, the plurality of auxiliary branches include:

[0131] The fourth branch is composed of the third current source I1, the seventh switch module 2011, the eighth switch module 2012 and the fourth current source I5 connected in series in sequence; the middle node between the eighth switch module 2012 and the fourth current source I5 is the fifth node C; the seventh switch module 2011 is used to control the on-off of the third current source I1 and the sixth node in response to the first control signal; the eighth switch module 2012 is used to control the on-off of the sixth node and the fourth current source I5 in response to the second control signal; wherein the sixth node is the middle node between the seventh switch module 2011 and the eighth switch module 2012;

[0132] The fifth branch is composed of a fifth current source I2, a ninth switch module 2021, a tenth switch module 2022 and a fourth current source I5 connected in series in sequence; the ninth switch module 2021 is used to control the fifth current source I2 and the seventh node to remain in a conductive state in response to the first constant signal; the tenth switch module 2022 is used to control the on-off of the seventh node and the fourth current source I5 in response to the inverted signal of the second control signal; wherein the seventh node is an intermediate node between the ninth switch module 2021 and the tenth switch module 2022;

[0133] The sixth branch is composed of the third current source I1, the eleventh switch module 2031, the twelfth switch module 2032 and the sixth current source I4 connected in series in sequence; the eleventh switch module 2031 is used to control the on-off of the third current source I1 and the eighth node in response to the inverted signal of the first control signal; the twelfth switch module 2032 is used to control the eighth node and the sixth current source I4 to remain in the on state in response to the second constant signal; wherein the eighth node is the middle node between the eleventh switch module 2031 and the twelfth switch module 2032;

[0134] The upper current source includes a third current source I1 and a fifth current source I2, and the lower current source includes a fourth current source I5 and a sixth current source I4; the fifth node C is electrically connected to the control end of the third current source I1 and the control end of the fifth current source I2 respectively.

[0135] In some embodiments, the ninth switch module 2021 and the twelfth switch module keep the connected nodes and the current source in the on state under the control of the constant signal. The level state of the first constant signal and the second constant signal depends on the internal structure of the ninth switch module 2021 and the twelfth switch module. For example, if the ninth switch module 2021 and the twelfth switch module are composed of MOS transistors, the high and low levels of the constant signal are determined by the type of the MOS transistor.

[0136] In some embodiments, the bias subcircuit 20 includes two upper current sources, a third current source I1 and a fifth current source I2, which can be connected to the system power supply together with the first current source I3 in the output subcircuit 10. The control terminals of the first current source I3, the third current source I1 and the fifth current source I2 are electrically connected to the fifth node C in the bias subcircuit 20 and are controlled by the first bias signal pbias. The bias subcircuit 20 includes two lower current sources, a fourth current source I5 and a sixth current source I4, which can be connected to the ground terminal together with the second current source I6 in the output subcircuit 10. The control terminals of the second current source I6, the fourth current source I5 and the sixth current source I4 are used to receive the external bias signal bias.

[0137] In some embodiments, the fourth branch can be obtained by duplicating the first branch in the output sub-circuit 10, and the switch component composed of the seventh switch module 2011 and the eighth switch module 2012 can refer to the relevant description of the first switch component 101. Specifically, the seventh switch module 2011 can respond to the first control signal to control the on-off of the third current source I1 and the sixth node, and the eighth switch module 2012 can respond to the second control signal to control the on-off of the sixth node and the fourth current source I5, similar to the first switch module 1011 and the second switch module 1012 in the first switch component 101 being controlled by the first control signal and the second control signal respectively.

[0138] In some embodiments, the middle node between the eighth switch module 2012 and the fourth current source I5 is a fifth node C, and the fifth node C is electrically connected to the middle node between the first switch component 101 and the second current source I6 in the output sub-circuit 10, that is, the fourth node B. Specifically, the middle node between the second switch module 1012 in the first switch component 101 and the second current source I6 is a fourth node B, and the fourth node B is electrically connected to a fifth node C of an auxiliary branch in the bias sub-circuit 20, that is, the fourth branch.

[0139] The charge pump of this embodiment connects the first branch and the fourth branch together through the fourth node B and the fifth node C. The control end of the second current source I6 and the control end of the fourth current source I5 both receive the external bias signal bias, and generate a bias voltage on the fourth node B and the fifth node C through circuit self-bias, and use this bias voltage as the first bias signal pbias of this embodiment. In this way, only one bias voltage external bias signal bias needs to be input to the charge pump, and the other bias voltage, i.e., the first bias signal pbias, is generated by the bias sub-circuit 20 according to the external bias signal bias.

[0140] In some embodiments, the bias subcircuit 20 further includes a fifth branch, which can be obtained by copying the second branch in the output subcircuit 10, and the structure of the ninth switch module 2021 can refer to the third switch module 1021, and the structure of the tenth switch module 2022 can refer to the fourth switch module 1022. However, the ninth switch module 2021 keeps the current path of the fifth current source I2 and the seventh node always in the on state under the control of the first constant signal, and the tenth switch module 2022 can control the on and off of the seventh node and the fourth current source I5 in response to the inverted signal of the second control signal, so the fifth branch is only controlled by the inverted signal of the second control signal. In this way, under the control of the first control signal, the second control signal and the inverted signal of the second control signal, the fourth branch and the fifth branch can be alternately turned on.

[0141] In some embodiments, the bias subcircuit 20 further includes a sixth branch, which is used to stabilize the voltage Vpb0 of the middle node D between the third current source I1 in the fourth branch and the seventh switch module 2011. Specifically, the sixth branch can be obtained by copying the fourth branch, the structure of the eleventh switch module 2031 can refer to the seventh switch module 2011, and the structure of the twelfth switch module 2032 can refer to the eighth switch module 2012. However, the twelfth switch module 2032 keeps the eighth node and the sixth current source I4 in the conductive state under the second constant signal, and the eleventh switch module 2031 can control the on and off of the third current source I1 and the eighth node in response to the inverted signal of the first control signal, so the sixth current branch is only controlled by the inverted signal of the first control signal. In this way, the fourth branch and the sixth branch can be alternately conductive under the control of the first control signal, the inverted signal of the first control signal, and the second control signal.

[0142] In some embodiments, at least one of the multiple auxiliary branches of the bias subcircuit 20 can be controlled to be turned on through the first control signal, the inverted signal of the first control signal, the second control signal, and the inverted signal of the second control signal, so that the bias subcircuit 20 can generate a stable first bias signal pbias through circuit self-bias according to the external bias signal bias, and provide it to the first current source I3 in the output subcircuit 10, and also provide the first bias signal pbias to the upper current source inside the bias subcircuit 20.

[0143] Optionally, the seventh switch module 2011 has the same structure as the first switch module 1011, and the eighth switch module 2012 has the same structure as the second switch module 1012;

[0144] The ninth switch module 2021 has the same structure as the third switch module 1021 , and the tenth switch module 2022 has the same structure as the fourth switch module 1022 ;

[0145] The eleventh switch module 2031 has the same structure as the seventh switch module 2011 , and the twelfth switch module 2032 has the same structure as the eighth switch module 2012 .

[0146] In some embodiments, the switch module of the auxiliary branch in the bias subcircuit 20 can copy the structure of the switch module in the output subcircuit 10. For example, the switch module of the auxiliary branch can refer to the MOS tube structure of the switch module in the output subcircuit 10. Specifically, the seventh switch module 2011 has the same structure as the first switch module 1011. The seventh switch module 2011 may include a transistor structure such as a first transistor M14 and a second transistor M15. For example, the seventh switch module 2011 includes Figure 4 The NMOS transistor M14 and the PMOS transistor M15 shown in the figure are also controlled by the first sub-signal up and the second sub-signal upb, so that the seventh switch module 2011 and the first switch module 1011 can be turned on and off at the same time. The eighth switch module 2012 has the same structure as the second switch module 1012. The eighth switch module 2012 can include Figure 4 The third transistor M13 shown is also controlled by the second control signal dn, so that the eighth switch module 2012 and the second switch module 1012 can be turned on and off at the same time.

[0147] Specifically, the ninth switch module 2021 has the same structure as the third switch module 1021. The ninth switch module 2021 may include a transistor structure such as a fourth transistor M16 and a fifth transistor M17. For example, the ninth switch module 2021 includes a transistor structure such as a fourth transistor M16 and a fifth transistor M17. Figure 4 However, the ninth switch module 2021 is always turned on by the control of the first constant signal, that is, the control signal received by the ninth switch module 2021 is different from that received by the third switch module 1021. The tenth switch module 2022 has the same structure as the fourth switch module 1022. The eighth switch module 2012 may include Figure 4 The sixth transistor M12 is also controlled by the inverted signal dnb of the second control signal, so that the tenth switch module 2022 and the fourth switch module 1022 can be turned on and off at the same time.

[0148] Specifically, the eleventh switch module 2031 has the same structure as the seventh switch module 2011, and thus the eleventh switch module 2031 can have the same structure as the first switch module 1011. Therefore, the specific structure of the eleventh switch module 2031 can refer to the relevant description of the seventh switch module 2011. However, the control signals received by the eleventh switch module 2031 and the seventh switch module 2011 are different. The eleventh switch module 2031 is controlled by the inverted signal of the first control signal. For example, the first switch module 1011 can be controlled by the third sub-signal upb and the fourth sub-signal up, so that the eleventh switch module 2031 and the seventh switch module 2011 can be turned on alternately. The twelfth switch module 2032 has the same structure as the eighth switch module 2012. The twelfth switch module 2032 may include: Figure 4 The sixth transistor M12 is shown, but the twelfth switch module 2032 is controlled by the second constant signal to be always turned on, that is, the control signal received by the twelfth switch module 2032 is different from that received by the eighth switch module 2012.

[0149] Among them, since the structure of the sixth branch is the same as that of the fourth branch, that is, the current paths of the two are completely consistent, the voltage Vpb0 is not affected by the up and dn signals, and can be always stable near a certain value. By stabilizing the voltage Vpb0 of the intermediate node D between the third current source I1 and the seventh switch module 2011, the bias voltage at the fifth node C, that is, the voltage value of the first bias signal pbias, can be further stabilized. The auxiliary branches of the bias subcircuit 20 all serve the output subcircuit 10. By stabilizing the voltage value of the first bias signal pbias, the voltage value of the output voltage VCN at the first node in the output subcircuit 10 can be reduced, the output voltage fluctuation can be reduced, and the phase noise and jitter of the overall phase-locked loop system can be minimized.

[0150] Figure 5 This is a third schematic diagram of a charge pump structure provided in an embodiment of the present application. Figure 5 As shown, the charge pump includes three auxiliary branches, namely the fourth branch, the fifth branch and the sixth branch. Among them, the upper current source includes the third current source I1 and the fifth current source I2, the third current source I1 includes the PMOS tube M19, and the fifth current source I2 includes the PMOS tube M20. The lower current source includes the fourth current source I5 and the sixth current source I4, the fourth current source I5 includes the NMOS tube M10, and the sixth current source I4 includes the NMOS tube M3.

[0151] like Figure 5As shown, the seventh switch module 2011 has the same structure as the first switch module 1011, and the seventh switch module 2011 includes an NMOS tube M7 and a PMOS tube M8 connected in parallel. The eighth switch module 2012 has the same structure as the second switch module 1012, and the eighth switch module 2012 includes an NMOS tube M9. The ninth switch module 2021 has the same structure as the third switch module 1021, and the ninth switch module 2021 includes an NMOS tube M4 and a PMOS tube M5 connected in parallel, the NMOS tube M4 receives a constant high-level signal cppr and the PMOS tube M5 receives a constant low-level signal cpgd, that is, the first constant signal includes a high-level signal cppr and a low-level signal cpgd. The tenth switch module 2022 has the same structure as the fourth switch module 1022, and the tenth switch module 2022 includes an NMOS tube M6. The eleventh switch module 2031 has the same structure as the seventh switch module 2011, and the eleventh switch module 2031 includes an NMOS tube M0 and a PMOS tube M1 connected in parallel. The twelfth switch module 2032 has the same structure as the eighth switch module 2012 . The twelfth switch module 2032 includes an NMOS transistor M2 . The NMOS transistor receives a constant high-level signal cppr. That is, the second constant signal is a high-level signal cppr.

[0152] like Figure 5 As shown, a bias voltage is generated on the fourth node B and the fifth node C, and this bias voltage signal serves as the first bias signal pbias of the charge pump in this embodiment. The gate of the PMOS tube M18 in the first current source I3, and the gate of the PMOS tube M19 of the upper power supply and the gate of the PMOS tube M20 in the bias subcircuit 20 are all electrically connected to the fifth node C, and can receive the first bias signal pbias, so as to maintain the working state under the control of the first bias signal pbias. The gate of the NMOS tube M11 in the second current source I6, and the gate of the NMOS tube M10 of the lower current source and the gate of the NMOS tube M3 in the bias subcircuit 20 are all used to receive the external bias signal bias. The output subcircuit 10 can refer to Figure 4 The relevant description in will not be repeated here.

[0153] Figure 6 This is a fourth schematic diagram of a charge pump structure provided in an embodiment of the present application. Figure 5 In the charge pump shown, MOS tubes M2, M4 and M5 are kept in the on state under the control of a constant signal. Therefore, Figure 5 The charge pump structure shown can be obtained as Figure 6 Simplified schematic diagram shown. Figure 6 The specific structures of the switch module UP, the switch module UP', the switch module DN and the switch module DN' are as follows: Figure 7 shown. Figure 6The switch module S1 is the twelfth switch module 2032, and the switch module S2 is the ninth switch module 2021. Since the ninth switch module 2021 and the twelfth switch module 2032 are always in the on state, Figure 6 In the figure, S1 and S2 are both closed. Figure 6 Node D is the middle node between the third current source I1 and the seventh switch module 2011 , and the sixth branch is used to stabilize the voltage Vpb0 of the node D in the fourth branch. Node E is the middle node between the first current source I3 and the first switch module 1011 .

[0154] Combine the following Figure 1 The output signal up and output signal dn of the phase frequency detector PFD are shown in FIG. Figure 6 The working state of the charge pump is shown.

[0155] Figure 8 The embodiment of this application provides Figure 6 One of the equivalent circuit diagrams of the charge pump shown is Figure 8 As shown, when the output signal up is at a high level and the output signal dn is at a low level, the charge pump is in a charging state. Specifically, the first switch module 1011 conducts between the node E and the first node A, and the first current source I3 in the working state provides a charging current, that is, charges the load capacitor C through the first node A, so that the output voltage VCN on the first node A increases.

[0156] like Figure 8 As shown, there is a discharge path from the system power supply to the ground, and the fifth current source I2 passes through the closed switch module DN' through the fourth current source I5 and the second current source I6 to the ground, so that the bias voltage at the fourth node B and the fifth node C, that is, the first bias signal pbias, can be stabilized. Figure 8 As shown, the switch module DN in the output sub-circuit 10 is disconnected and the switch module DN' is turned on, the voltage of the first node A and the second node A' remain consistent, and the parasitic capacitance of the NMOS tube in the switch module DN can be stabilized by a unit gain operational amplifier, so that in the next cycle, the parasitic capacitance of the NMOS tube will not affect the output voltage VCN.

[0157] Fig. 9 The embodiment of this application provides Figure 6 The second equivalent circuit diagram of the charge pump shown in FIG. Fig. 9 As shown, when the output signal up is at a low level and the output signal dn is at a high level, the charge pump is in a discharging state. Specifically, the second switch module 1012 conducts the first node A and the fourth node B, and the second current source I6 in the working state provides a discharging current, that is, discharges the load capacitor C through the first node A, so that the output voltage VCN on the first node A is reduced.

[0158] like Fig. 9 As shown, there is a discharge path from the system power supply to the ground, and the third current source I1 passes through the closed switch module UP' and the sixth current source I4 to the ground, so that the voltage Vpb0 of the node D can be stabilized, so that the voltage Vpb0 is not affected by the output signal up and the output signal dn, and the bias voltages on the fourth node B and the fifth node C are also stabilized, that is, the voltage value of the first bias signal pbias is stabilized. Fig. 9 As shown, the switch module UP in the output sub-circuit 10 is disconnected and the switch module UP' is turned on, the voltage of the first node A and the second node A' remain consistent, and the parasitic capacitance of the PMOS tube in the switch module UP can be stabilized by a unit gain operational amplifier, so that in the next cycle, the parasitic capacitance of the PMOS tube will not affect the output voltage VCN.

[0159] In some embodiments, for Figure 6 In the charge pump shown, when the output signal up and the output signal dn are both at high level or both at low level, the output voltage VCN at the first node A remains unchanged.

[0160] Fig.10 The embodiment of this application provides Figure 6 The equivalent circuit diagram of the charge pump shown in Figure 3 is as follows: Fig.10 As shown, when the output signal up and the output signal dn are both at high level, the charge pump is in a hold state. Specifically, the first switch module 1011 conducts between the node E and the first node A, and the first current source I3 in the working state provides a charging current, and the second switch module 1012 conducts between the first node A and the fourth node B, and the second current source I6 in the working state provides a discharging current. At this time, the charging and discharging currents are equal, so that the output voltage VCN on the first node A remains unchanged. Fig.10 As shown, there is a discharge path from the system power supply to the ground, and the third current source I1 passes through the closed switch module UP and the switch module DN, and then through the fourth current source I5 and the second current source I6 to the ground, so that the bias voltage at the fourth node B and the fifth node C, that is, the first bias signal pbias, can be stabilized.

[0161] In some embodiments, the magnitude of the external bias signal Bias is related to the frequency division ratio of the phase-locked loop. In the charge pump of this embodiment, the first bias signal pbias is generated according to the external bias signal Bias, so that the output current of the charge pump is related to the frequency division ratio of the phase-locked loop. Therefore, by adjusting the frequency division ratio of the phase-locked loop, the output current of the charge pump can be optimized, and then the bandwidth of the phase-locked loop can be accurately controlled, so that the phase-locked loop system can adjust the bandwidth more flexibly to meet the requirements of high speed and high stability.

[0162] Fig.11This is a fifth structural diagram of a charge pump provided in an embodiment of the present application, such as Fig.11 As shown, the unit gain amplifier is arranged between the node E and the fourth node B. Specifically, the non-inverting input terminal of the unit gain amplifier is electrically connected to the second node A, the inverting input terminal is electrically connected to the output terminal, the output terminal of the unit gain amplifier is electrically connected to the node E through a switch module UP', and the output terminal of the unit gain amplifier is also electrically connected to the fourth node B through a switch module DN'. In this embodiment, the current path between the node E and the fourth node B through the output terminal of the unit gain amplifier is called the second branch, and the output terminal of the unit gain amplifier is called the second node A'. Therefore, Figure 6 The current path where the second node A' is located corresponds to Fig.11 It is called the third branch.

[0163] like Fig.11 As shown, the third branch includes a first current source I3, a fifth switch module, a sixth switch module and a second current source I6, wherein the fifth switch module is a switch module UP', and the sixth switch module is a switch module DN'. Fig.11 In the second branch shown in FIG. 1 , in fact, the third switch module 1021 is also a switch module UP', and the fourth switch module 1022 is also a switch module DN', that is, the fifth switch module has the same structure as the third switch module 1021, and the sixth switch module has the same structure as the fourth switch module 1022. The specific structures of the switch modules UP' and DN' are as follows: Figure 7 shown.

[0164] like Fig.11 As shown, when the switch module UP in the first branch is disconnected, the switch module UP' is turned on, and the potential of the node E is clamped at the output voltage VCN through the unit gain operational amplifier, so that the charge sharing phenomenon does not occur in the next cycle. Similarly, when the switch module DN in the first branch is disconnected, the switch module DN' is turned on, and the potential of the fourth node B is clamped at the output voltage VCN through the unit gain operational amplifier, so that the charge sharing phenomenon does not occur in the next cycle.

[0165] An embodiment of the present application further provides a phase-locked loop, which includes the charge pump as described in the above embodiment.

[0166] In some embodiments, the phase-locked loop includes a phase frequency detector PFD, a charge pump CP, a loop filter LF and a voltage controlled oscillator VCO connected in sequence, and the output signal of the voltage controlled oscillator VCO is processed by a frequency divider FD and provided to the phase frequency detector PFD as a feedback signal.

[0167] Fig.12 This is one of the simulation schematic diagrams of a phase-locked loop provided in an embodiment of the present application, such as Fig.12As shown, during the charging process of the charge pump, the reference signal Fref_in and the feedback signal Fbck_in received by the phase frequency detector PFD, the output signal up and the output signal dn generated by the phase frequency detector PFD, and the output signal CP_OUT of the charge pump, that is, the output voltage VCN generated by the charge pump at the first node A by detecting the phase difference between the output signal up and the output signal dn. Fig.12 The horizontal axis is time (Time), the unit is nanosecond (ns), the vertical axis is voltage (V), the unit of the output signal CP_OUT is millivolt (mV), and the unit of the reference signal Fref_in, the feedback signal Fbck_in, the output signal up and the output signal dn are all volts (V).

[0168] Fig.12 shows the transient response in the time range of 12.5 to 32.5 ns. Fig.13 It shows the instantaneous response of the reference signal Fref_in, the feedback signal Fbck_in, the output signal up, the output signal dn, and the output signal CP_OUT of the charge pump within the time range of 0 to 900 ns during the charging process of the charge pump.

[0169] Fig.14 This is a third simulation diagram of a phase-locked loop provided in an embodiment of the present application, such as Fig.14 As shown, the reference signal Fref_in, the feedback signal Fbck_in, the output signal up, the output signal dn, and the output signal CP_OUT of the charge pump are shown during the discharge process of the charge pump. Fig.14 shows the transient response in the time range of 12.5 to 32.5 ns. Fig.15 It shows the instantaneous response of the reference signal Fref_in, the feedback signal Fbck_in, the output signal up, the output signal dn, and the output signal CP_OUT of the charge pump within the time range of 0 to 900 ns during the discharge process of the charge pump.

[0170] An embodiment of the present application provides a chip, which includes a charge pump as described in the above embodiment.

[0171] The advantages of this chip compared to the related art and the charge pump of the aforementioned embodiment are the same, which will not be described in detail here.

[0172] An embodiment of the present application provides an electronic device, and the electronic device includes a chip as described in the above embodiment.

[0173] The electronic device has the same advantages as those of the charge pump in the related art and the aforementioned embodiment, which will not be described in detail here.

[0174] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0175] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A charge pump, characterized in that: The charge pump comprises: an output subcircuit and a bias subcircuit; The bias subcircuit is electrically connected to a control end of a first current source in the output subcircuit, and is used to receive an external bias signal, and send a first bias signal to the first current source according to the external bias signal; the first current source maintains a working state under the control of the first bias signal; The output subcircuit comprises a first branch formed by the first current source, a first switch component and a second current source connected in series in sequence, and a second branch formed by the first current source, a second switch component and the second current source connected in series in sequence; a control end of the second current source is used to receive the external bias signal, and the second current source maintains a working state under the control of the external bias signal; In the output subcircuit, an amplification module is arranged between the first branch and the second branch; a non-inverting input terminal of the amplification module is electrically connected to a first node in the first switch component, and an inverting input terminal and an output terminal are electrically connected to a second node in the second switch component respectively; the first node is also connected to a load capacitor; The first switch component is used to control the on-off of the first current source and the first node in response to a first control signal, and to control the on-off of the first node and the second current source in response to a second control signal; the second switch component is used to control the on-off of the first current source and the second node in response to an inverted signal of the first control signal, and to control the on-off of the second node and the second current source in response to an inverted signal of the second control signal.

2. The charge pump according to claim 1, characterized in that The first switch component comprises: a first switch module and a second switch module connected in series in sequence; the middle node between the first switch module and the second switch module is the first node; wherein the first switch module is used to control the on-off of the first current source and the first node in response to the first control signal; and the second switch module is used to control the on-off of the first node and the second current source in response to the second control signal; The second switch component includes: a third switch module and a fourth switch module connected in series in sequence; the intermediate node between the third switch module and the fourth switch module is the second node; wherein the third switch module is used to control the on-off of the first current source and the second node in response to the inverted signal of the first control signal; the fourth switch module is used to control the on-off of the second node and the second current source in response to the inverted signal of the second control signal.

3. The charge pump according to claim 2, characterized in that: The first switch module includes a first transistor and a second transistor, and the first transistor and the second transistor are of opposite types; A first electrode of the first transistor is electrically connected to the first node, a second electrode is electrically connected to the first current source, and a control electrode is used to receive a first sub-signal; The first electrode of the second transistor is electrically connected to the first current source, the second electrode is electrically connected to the first node, and the control electrode is used to receive a second sub-signal; wherein the second sub-signal is an inverted signal of the first sub-signal; and the first control signal includes the first sub-signal and the second sub-signal.

4. The charge pump according to claim 2, characterized in that The second switch module includes a third transistor; a first electrode of the third transistor is electrically connected to the second current source, a second electrode is electrically connected to the first node, and a control electrode is used to receive the second control signal.

5. The charge pump according to claim 2, characterized in that: The third switch module includes a fourth transistor and a fifth transistor, and the fourth transistor and the fifth transistor are of opposite types; The first electrode of the fourth transistor is electrically connected to the second node, the second electrode is electrically connected to the first current source, and the control electrode is used to receive a third sub-signal; wherein the third sub-signal is an inverted signal of the first sub-signal; The first electrode of the fifth transistor is electrically connected to the first current source, the second electrode is electrically connected to the second node, and the control electrode is used to receive a fourth sub-signal; wherein the fourth sub-signal is an inverted signal of the second sub-signal; the first control signal includes the first sub-signal and the second sub-signal; and the inverted signal of the first control signal includes the third sub-signal and the fourth sub-signal.

6. The charge pump according to claim 2, characterized in that The fourth switch module includes a sixth transistor; the sixth transistor is of the same type as the third transistor; The first electrode of the sixth transistor is electrically connected to the second current source, the second electrode is electrically connected to the second node, and the control electrode is used to receive the inverted signal of the second control signal.

7. The charge pump according to claim 1, characterized in that The amplification module includes a first amplifier; The non-inverting input terminal of the first amplifier is electrically connected to the first node, the inverting input terminal of the first amplifier is electrically connected to the output terminal of the first amplifier, and the output terminal of the first amplifier is electrically connected to the second node; wherein the first amplifier is a unity gain amplifier.

8. The charge pump according to claim 7, characterized in that The charge pump further comprises: A third branch is formed by sequentially connecting the first current source, the fifth switch module, the sixth switch module and the second current source in series; the middle node between the fifth switch module and the sixth switch module is a third node; The fifth switch module has the same structure as the third switch module; the fifth switch module is used to control the on / off of the first current source and the third node in response to the inverted signal of the first control signal; The sixth switch module has the same structure as the fourth switch module; the sixth switch module is used to control the on-off of the third node and the second current source in response to the inverted signal of the second control signal.

9. The charge pump according to any one of claims 1 to 8, characterized in that: The bias subcircuit comprises a plurality of auxiliary branches, each of which comprises an upper current source, a switch module and a lower current source connected in series in sequence; The middle node between the first switch component and the second current source is a fourth node; the fourth node is electrically connected to a fifth node between the switch module and the lower current source in one of the auxiliary branches; the voltage signals at the fourth node and the fifth node are the first bias signal; The control end of the upper current source is electrically connected to the fifth node and is used to receive the first bias signal; the control end of the lower current source is used to receive the external bias signal; The switch modules in the plurality of auxiliary branches are used to switch on at least one of the auxiliary branches under the control of the first control signal, the inverted signal of the first control signal, the second control signal and the inverted signal of the second control signal.

10. The charge pump according to claim 9, characterized in that The plurality of auxiliary branches include: The fourth branch is composed of a third current source, a seventh switch module, an eighth switch module and a fourth current source connected in series in sequence; the middle node between the eighth switch module and the fourth current source is the fifth node; the seventh switch module is used to control the on-off of the third current source and the sixth node in response to the first control signal; the eighth switch module is used to control the on-off of the sixth node and the fourth current source in response to the second control signal; wherein the sixth node is the middle node between the seventh switch module and the eighth switch module; The fifth branch is composed of a fifth current source, a ninth switch module, a tenth switch module and the fourth current source connected in series in sequence; the ninth switch module is used to control the fifth current source and the seventh node to remain in a conductive state in response to the first constant signal; the tenth switch module is used to control the on-off of the seventh node and the fourth current source in response to the inverted signal of the second control signal; wherein the seventh node is an intermediate node between the ninth switch module and the tenth switch module; a sixth branch, which is composed of the third current source, the eleventh switch module, the twelfth switch module and the sixth current source connected in series in sequence; the eleventh switch module is used to control the on-off of the third current source and the eighth node in response to the inverted signal of the first control signal; the twelfth switch module is used to control the eighth node and the sixth current source to maintain a conducting state in response to the second constant signal; wherein the eighth node is an intermediate node between the eleventh switch module and the twelfth switch module; Among them, the upper current source includes the third current source and the fifth current source, and the lower current source includes the fourth current source and the sixth current source; the fifth node is electrically connected to the control end of the third current source and the control end of the fifth current source respectively.

11. The charge pump according to claim 10, characterized in that The seventh switch module has the same structure as the first switch module, and the eighth switch module has the same structure as the second switch module; The ninth switch module has the same structure as the third switch module, and the tenth switch module has the same structure as the fourth switch module; The eleventh switch module has the same structure as the seventh switch module, and the twelfth switch module has the same structure as the eighth switch module.

12. A phase-locked loop, characterized in that: The phase-locked loop comprises a charge pump as claimed in any one of claims 1-11.

13. A chip, characterized in that: The chip comprises a charge pump as claimed in any one of claims 1-11.

14. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 13.

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