Phase-locked loop spurious optimization method based on frequency mixing architecture

Abstract

The invention discloses a phase-locked loop spurious optimization method based on a frequency mixing architecture, and the method comprises the steps: determining a frequency dividing ratio set of a first phase-locked loop based on a set output frequency and a frequency range of a synthetic reference signal; the synthetic reference signal is specifically a signal obtained by mixing an output signal of a second phase-locked loop and a fixed reference local oscillator signal; then determining a stray value group corresponding to each frequency dividing ratio in the frequency dividing ratio set, and extracting the worst stray value in each group of stray values to obtain a worst stray value group; and finally, determining an optimal spurious value based on the worst spurious value group, and taking the frequency dividing ratio corresponding to the optimal spurious value as a final frequency dividing ratio, so that spurious in the multi-loop phase-locked loop can be effectively reduced, the cost is reduced, and the performance of the multi-loop phase-locked loop is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a phase-locked loop spurious optimization method based on a frequency mixing architecture. Background Art

[0002] Local oscillator phase noise refers to the phenomenon of signal quality degradation caused by the phase noise of the fixed reference local oscillator signal in the RF transmitter and receiver. The fixed reference local oscillator signal plays a key role in the up and down conversion process. Its phase noise will have a significant impact on the quality of the transmitted and received signals. With the rapid development of electronic technology, the requirements for local oscillator phase noise are getting higher and higher. The prior art provides a circuit of a mixing architecture for ensuring the requirements for the local oscillator phase noise. The mixing architecture in the prior art is a multi-loop technology, which mainly includes a main loop and a bias loop. Its application core mainly includes two schemes. The first scheme is to mix the main loop signal and the bias loop signal to a lower intermediate frequency signal through mixing, and then lock the intermediate frequency signal to the fractional loop frequency reference. The second scheme is to increase the bias loop output signal frequency as the main loop phase detection signal, thereby reducing the main loop division ratio. However, the multi-loop based on the former mixing scheme in the prior art is more complex, has a larger power consumption area, and is more expensive. The multi-loop based on the latter mixing scheme is relatively simple and cost-effective, has lower power consumption, but has spurious problems, which affects performance.

[0003] Therefore, how to reduce the spurious signals in a multi-loop phase-locked loop while ensuring that the cost of the mixing architecture is not high and reduce the cost, thereby improving the performance of the multi-loop phase-locked loop, is a technical problem to be solved by those skilled in the art. Summary of the invention

[0004] The purpose of the present invention is to solve the technical problem of more spurious in the prior art in a relatively low-cost mixing solution, thereby reducing spurious based on a simpler design, lower power consumption, cost, and area.

[0005] To achieve the above technical objectives, on the one hand, the present invention provides a phase-locked loop spurious optimization method based on a mixing frequency architecture, the method comprising: Determine a frequency division ratio set of the first phase-locked loop based on the set output frequency and the frequency range of the synthetic reference signal, wherein the synthetic reference signal is specifically a signal obtained by mixing the output signal of the second phase-locked loop with a fixed reference local oscillator signal; Determine a spurious value group corresponding to each frequency division ratio in the frequency division ratio set, and extract the worst spurious value in each group of spurious values ​​to obtain a worst spurious value group; An optimal spurious value is determined based on the worst spurious value group, and a frequency division ratio corresponding to the optimal spurious value is used as a final frequency division ratio.

[0006] Furthermore, the worst spurious value is a value with the smallest absolute value in each group of spurious values.

[0007] Further, the worst spurious value is extracted by the following process: Divide the spurious values ​​corresponding to the finite higher harmonics of the same fixed reference local oscillator signal in the spurious value group into different subgroups, take the spurious value with the smallest absolute value in each subgroup as the spurious value to be extracted, and group all the spurious values ​​to be extracted and their related parameters into a first list; A worst spurious value is determined based on the first list.

[0008] Further, determining the worst spurious value based on the first list specifically includes: Traversing the first list, and taking the stray value to be extracted of the current item in the traversal as the stray value to be processed; If the spurious value to be processed is less than 1, all spurious values ​​corresponding to the minimum higher harmonic of the fixed reference local oscillator signal in the first list are grouped into a second list, and all spurious values ​​in the second list are normalized, and when there are two or more spurious values ​​in the second list, the spurious value corresponding to the minimum absolute value is used as the worst spurious value to be determined; if the spurious value to be processed is not less than 1, a third list is extracted from the first list, and all spurious values ​​in the third list are normalized, and when there are two or more spurious values ​​in the third list, the spurious value with the minimum absolute value is used as the worst spurious value to be determined, the higher harmonic of the fixed reference local oscillator signal corresponding to any spurious value in the third list is the smallest and the actual spurious difference is less than the expected spurious difference, the actual spurious difference is equal to the spurious value to be processed minus the corresponding spurious value in the third list, and the expected spurious difference is equal to the difference between the higher harmonic of the fixed reference local oscillator signal corresponding to the spurious value to be processed and the higher harmonic of the fixed reference local oscillator signal corresponding to the corresponding spurious value in the third list multiplied by 5; After normalizing all the worst spurious values ​​to be determined, the worst spurious value to be determined with the smallest absolute value is normalized and taken as the worst spurious value.

[0009] Further, determining the optimal spurious value based on the worst spurious value group specifically includes: Arrange the spurious values ​​in the worst spurious value group in order from large to small to form a sequence; The first stray value in the sequence is used as the current stray value, and the second stray value is used as the stray values ​​to be compared, and the stray effects are compared with the current stray value in sequence, wherein when the stray effect of a stray value is better than the current stray value, the corresponding stray value is updated to the current stray value.

[0010] Furthermore, the process of comparing the spurious effects specifically includes: S60, determining whether the value of the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value minus the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared is not less than 2, if so, executing the next comparison, if not, executing S61; S61, judging whether the current item stray value is not less than 1 and the stray value to be compared is less than 1, if so, executing the next comparison, if not, executing S62; S62, determining whether the value obtained by subtracting the higher-order harmonics corresponding to the fixed reference local oscillator signal of the current stray value from the higher-order harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared is equal to 1 and the value of the stray value to be compared minus the current stray value is not greater than 5, if so, executing the next comparison, otherwise executing S63; S63. If the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value are the same as the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is greater than 2, then the current stray value is updated; if the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value are the same as the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is less than 2, and the higher harmonics of the second phase-locked loop output signal corresponding to the stray value to be compared minus the current stray value is less than 2, then the current stray value is updated. If the value of the higher harmonic of the second phase-locked loop output signal corresponding to the previous stray value is greater than 3, the stray value to be compared is updated to the current stray value and then the next comparison is performed. If the higher harmonic corresponding to the fixed reference local oscillator signal of the current stray value is the same as the higher harmonic corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is less than 2, and the value of the higher harmonic of the second phase-locked loop output signal corresponding to the stray value to be compared minus the higher harmonic of the second phase-locked loop output signal corresponding to the current stray value is not greater than 3, then S64 is performed; S64, determining whether the first actual stray difference is less than the first expected stray difference, if so, executing S65, if not and the first actual stray difference is less than 3.5, updating the stray value to be compared to the current item stray value, wherein the first actual stray difference is specifically the difference between the current item stray value and the stray value to be compared, and the first expected stray difference is equal to the difference between the higher harmonics of the fixed reference local oscillator signal corresponding to the current item stray value and the higher harmonics of the fixed reference local oscillator signal corresponding to the stray value to be compared multiplied by 5; S65, judging whether the higher harmonic of the fixed reference local oscillator signal corresponding to the current stray value is not less than 2 and the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value to be compared is not less than 2, if so, executing S66, if not, executing the next comparison; S66, determine whether the absolute value of the current stray value is greater than or equal to 4.5 and the absolute value of the stray value to be compared is less than 5, if yes, execute the next comparison, if not, execute S67; S67, determine whether the difference between the absolute value of the current stray value and the absolute value of the stray value to be compared is less than 1.5 and whether the absolute value of the current stray value and the absolute value of the stray value to be compared are both less than or equal to 3. If so, execute S68; otherwise, execute the next comparison; S68, determining whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current stray value are greater than the higher harmonics of the fixed reference local oscillator signal corresponding to the stray value to be compared, and whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current stray value is equal to 1, if so, executing the next comparison, if not, executing S69; S69, determine whether the current item hash value is greater than the hash value to be compared and the current item hash value is not 1, if so, update the hash value to be compared to the current item hash value and then execute the next comparison, if not, execute the next comparison.

[0011] Furthermore, the fixed reference signal of the second phase-locked loop is frequency-multiplied to obtain a fixed reference local oscillator signal.

[0012] The present invention provides a phase-locked loop spurious optimization method based on a mixing architecture. Compared with the prior art, the method first determines a frequency division ratio set of a first phase-locked loop based on a set output frequency and a frequency range of a synthetic reference signal, wherein the synthetic reference signal is specifically a signal obtained by mixing an output signal of a second phase-locked loop with a fixed reference local oscillator signal; then determines a spurious value group corresponding to each frequency division ratio in the frequency division ratio set, and extracts the worst spurious value in each group of spurious values ​​to obtain a worst spurious value group; finally, determines an optimal spurious value based on the worst spurious value group, and uses the frequency division ratio corresponding to the optimal spurious value as a final frequency division ratio, which can effectively reduce spurious in a multi-loop phase-locked loop and reduce costs, thereby improving the performance of the multi-loop phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 The figure is a flow chart of a phase-locked loop spurious optimization method based on a mixing frequency architecture provided in an embodiment of the present specification; Figure 2 FIG. 1 is a schematic diagram of the structure of the frequency mixing architecture in the embodiment of this specification. DETAILED DESCRIPTION

[0015] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0016] like Figure 1 The flowchart of the phase-locked loop spurious optimization method based on the mixing frequency architecture provided in the embodiment of this specification is shown. Although this specification provides the method operation steps or device structure shown in the following embodiments or drawings, the method or device may include more or fewer operation steps or module units after partial merger based on routine or no creative labor. In the steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure shown in the embodiments of this specification or drawings. When the method or module structure is applied in actual devices, servers or terminal products, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or drawings. The phase-locked loop spurious optimization method based on the mixing frequency architecture provided in the present embodiment can be applied to various mixing frequency architectures, such as Figure 1 As shown, the method specifically comprises the following steps: Step S101, determining a frequency division ratio set of a first phase-locked loop based on a set output frequency and a frequency range of a synthetic reference signal, wherein the synthetic reference signal is specifically a signal obtained by mixing an output signal of a second phase-locked loop with a fixed reference local oscillator signal.

[0017] First, see Figure 2 It is a structural diagram of the mixing architecture, including the second phase-locked loop and the first phase-locked loop. The first phase-locked loop is the main loop that outputs the required frequency. Its input is the synthetic reference signal after the output signal of the second phase-locked loop is mixed with the fixed reference local oscillator signal. The structures of the first phase-locked loop and the second phase-locked loop can be seen Figure 2As shown, the phase-locked loop structure is consistent with the prior art, and the present application scheme does not adjust the multi-loop mixing architecture. The mixing architecture mainly includes a second phase-locked loop or signal generator, a mixing module and a first phase-locked loop. The fractional loop, that is, the second phase-locked loop or DDS module, that is, the signal generator, is responsible for providing a variable reference signal with fine frequency tuning within a certain range; the reference multiplication and mixing module is responsible for multiplying the fixed time base reference frequency, and then extracting the high-order harmonics of the fixed time base reference and mixing it with the aforementioned variable reference signal. After mixing, the intermediate frequency signal also changes within a certain range following the variable reference signal. This intermediate frequency signal is provided as a synthetic reference signal to the main loop, that is, the first phase-locked loop, for phase detection, and the main loop is locked to the intermediate frequency signal. When this intermediate frequency signal changes within a certain design range, the main loop can track and seamlessly lock to the intermediate frequency signal through a continuously changing division ratio D, thereby achieving full-band frequency coverage output. The description is as follows from top to bottom and from left to right: the fractional loop module consists of an input fixed time base reference fREF, a phase detector PFD, a broadband VCO, a frequency divider and a fractional controller and a loop filter. The VCO output is dynamically divided by the frequency divider operated by the fractional controller and then sent to the phase detector for phase detection with the fixed time base reference fREF input from another channel. The output error voltage is sent to the loop filter and the final negative feedback tuning voltage tunes the VCO, thereby finally achieving loop locking. Since this module is a fractional loop, it can provide a fine frequency tuning output, and the same is true for DDS. After the fractional loop output passes through a fixed frequency divider, a limited range continuous tuning frequency output reference signal is obtained, which is also the output signal of the second phase-locked loop. The reference multiplication and mixing module is mainly responsible for extracting the high-order harmonics after the fixed time base reference frequency is multiplied, and then the extracted high-order time base harmonics are mixed with the aforementioned continuous tuning frequency output reference signal, and the corresponding synthetic reference signal is obtained after passing through a bandpass filter. The main loop module is mainly responsible for the final output frequency signal, which is usually a broadband loop or an integrated loop. After obtaining the corresponding reference signal, the main loop corresponding frequency division ratio D is set by controlling the main loop frequency divider to divide the broadband VCO signal and send it to the main loop phase detector to mix with the above-mentioned intermediate frequency, that is, the corresponding reference signal phase detection. After the external loop filter, the broadband VCO is tuned and locked to finally obtain the broadband output frequency.

[0018] Among them, the frequency division ratio set of the first phase-locked loop is determined according to the set output frequency and the frequency range of the synthetic reference signal, and the frequency division ratio D=the output signal frequency of the main phase-locked loop, that is, the first phase-locked loop / synthesized reference frequency, wherein the synthetic reference frequency, that is, the frequency of the synthetic reference signal, is obtained by harmonic mixing of the variable range reference signal output by the FN loop or DDS and the fixed frequency time base reference signal, and each available frequency division value D is calculated to obtain the corresponding synthetic reference frequency (synthesized reference frequency=K*fixed frequency time base reference signal+ / -FN loop or DDS output variable range reference signal, where K is a positive integer).

[0019] For each synthesized reference frequency, it corresponds to a unique FN loop or DDS reference frequency. If the harmonic order of the FN loop or DDS reference frequency is set to M, and the harmonic frequency of the fixed reference local oscillator signal is N, the intermediate frequency signal based on the mixing architecture will produce M*N spurious signals. Therefore, a limited range M*N spurious signal calculation is performed on each FN loop or DDS reference frequency based on the actual spurious attenuation performance (that is, for the mixer input, there are RF input and LO terminals. The signals at these two terminals will produce nonlinear products when the mixer is working, namely M*RF and N*LO, and N*LO + / - M*RF products will be obtained at the final intermediate frequency output. Among these nonlinear products, except for the fundamental product, which is the intermediate frequency we need, other high-order products are unwanted frequencies that may produce spurious signals).

[0020] Step S102: determining a spurious value group corresponding to each frequency division ratio in the frequency division ratio set, and extracting the worst spurious value in each group of spurious values ​​to obtain a worst spurious value group.

[0021] Specifically, the worst spurious value is the value with the smallest absolute value in each group of spurious values. After determining the spurious value group corresponding to each frequency division ratio in the frequency division ratio set, the method further includes normalizing each spurious value based on a weight.

[0022] After obtaining the spurious delta values ​​generated by different M combinations corresponding to the limited range N in turn (the mixer's high-order nonlinear products N*LO + / - M*RF will produce various frequencies, which will be modulated onto the intermediate frequency signal to produce spurious signals. The spurious value represents the frequency difference between it and the main spectrum, that is, the delta value.) As above, the delta value is normalized according to the weight.

[0023] According to the loop bandwidth and roll-off suppression curve, the in-band and out-band up to 10MHz are divided into multiple sections, and the corresponding priority numbers are assigned according to their different suppression degrees. (The loop filter design is divided into in-band and out-band, where the in-band will not have any suppression on spurious; the out-band is divided into standard suppression band and additional suppression band according to the loop design. Each suppression band has a different low-pass suppression rate or roll-off rate according to the specific design, so different suppression bands and suppression degrees can be obtained by calculation.) In theory, more sections will bring better selectivity, but at the same time it will bring the complexity of M*N weight judgment. Therefore, the number of sections needs to comprehensively consider feasibility, accuracy and complexity. The loop is divided into in-band and out-band, where the out-band can be divided into standard suppression band and additional suppression band according to different loop designs. Therefore, the sections can be divided according to the roll-off rates of different suppression bands. In this example, a total of 6 suppression bands are divided according to different roll-off rate designs, namely, in-band, in-band to 1 MHz, 1 MHz to 3 MHz, 3 MHz to 5 MHz, 5 MHz to 10 MHz, and outside 10 MHz. Different weights are set for each suppression band.

[0024] In some embodiments, the worst spurious value may be extracted by the following process: Divide the spurious values ​​corresponding to the finite higher harmonics of the same fixed reference local oscillator signal in the spurious value group into different subgroups, take the spurious value with the smallest absolute value in each subgroup as the spurious value to be extracted, and group all the spurious values ​​to be extracted and their related parameters into a first list; A worst spurious value is determined based on the first list.

[0025] The determining of the worst spurious value based on the first list specifically includes: Traversing the first list, and taking the stray value to be extracted of the current item in the traversal as the stray value to be processed; If the spurious value to be processed is less than 1, all spurious values ​​corresponding to the minimum higher harmonic of the fixed reference local oscillator signal in the first list are grouped into a second list, and all spurious values ​​in the second list are normalized, and when there are two or more spurious values ​​in the second list, the spurious value corresponding to the minimum absolute value is used as the worst spurious value to be determined; if the spurious value to be processed is not less than 1, a third list is extracted from the first list, and all spurious values ​​in the third list are normalized, and when there are two or more spurious values ​​in the third list, the spurious value with the minimum absolute value is used as the worst spurious value to be determined, the higher harmonic of the fixed reference local oscillator signal corresponding to any spurious value in the third list is the smallest and the actual spurious difference is less than the expected spurious difference, the actual spurious difference is equal to the spurious value to be processed minus the corresponding spurious value in the third list, and the expected spurious difference is equal to the difference between the higher harmonic of the fixed reference local oscillator signal corresponding to the spurious value to be processed and the higher harmonic of the fixed reference local oscillator signal corresponding to the corresponding spurious value in the third list multiplied by 5; After normalizing all the worst spurious values ​​to be determined, the worst spurious value to be determined with the smallest absolute value is normalized and taken as the worst spurious value.

[0026] Step S103: determining an optimal spurious value based on the worst spurious value group, and taking a frequency division ratio corresponding to the optimal spurious value as a final frequency division ratio.

[0027] In the embodiment of the present application, determining the optimal spurious value based on the worst spurious value group specifically includes: Arrange the spurious values ​​in the worst spurious value group in order from large to small to form a sequence; The first stray value in the sequence is used as the current stray value, and the second stray value is used as the stray values ​​to be compared, and the stray effects are compared with the current stray value in sequence, wherein when the stray effect of a stray value is better than the current stray value, the corresponding stray value is updated to the current stray value.

[0028] In the embodiment of the present application, the process of comparing the spurious effects specifically includes: S60, determining whether the value of the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value minus the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared is not less than 2, if so, executing the next comparison, if not, executing S61; S61, judging whether the current item stray value is not less than 1 and the stray value to be compared is less than 1, if so, executing the next comparison, if not, executing S62; S62, determining whether the value obtained by subtracting the higher-order harmonics corresponding to the fixed reference local oscillator signal of the current stray value from the higher-order harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared is equal to 1 and the value of the stray value to be compared minus the current stray value is not greater than 5, if so, executing the next comparison, otherwise executing S63; S63. If the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value are the same as the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is greater than 2, then the current stray value is updated; if the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value are the same as the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is less than 2, and the higher harmonics of the second phase-locked loop output signal corresponding to the stray value to be compared minus the current stray value is less than 2, then the current stray value is updated. If the value of the higher harmonic of the second phase-locked loop output signal corresponding to the previous stray value is greater than 3, the stray value to be compared is updated to the current stray value and then the next comparison is performed. If the higher harmonic corresponding to the fixed reference local oscillator signal of the current stray value is the same as the higher harmonic corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is less than 2, and the value of the higher harmonic of the second phase-locked loop output signal corresponding to the stray value to be compared minus the higher harmonic of the second phase-locked loop output signal corresponding to the current stray value is not greater than 3, then S64 is performed; S64, determining whether the first actual stray difference is less than the first expected stray difference, if so, executing S65, if not and the first actual stray difference is less than 3.5, updating the stray value to be compared to the current item stray value, wherein the first actual stray difference is specifically the difference between the current item stray value and the stray value to be compared, and the first expected stray difference is equal to the difference between the higher harmonics of the fixed reference local oscillator signal corresponding to the current item stray value and the higher harmonics of the fixed reference local oscillator signal corresponding to the stray value to be compared multiplied by 5; S65, judging whether the higher harmonic of the fixed reference local oscillator signal corresponding to the current stray value is not less than 2 and the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value to be compared is not less than 2, if so, executing S66, if not, executing the next comparison; S66, determine whether the absolute value of the current stray value is greater than or equal to 4.5 and the absolute value of the stray value to be compared is less than 5, if yes, execute the next comparison, if not, execute S67; S67, determine whether the difference between the absolute value of the current stray value and the absolute value of the stray value to be compared is less than 1.5 and whether the absolute value of the current stray value and the absolute value of the stray value to be compared are both less than or equal to 3. If so, execute S68; otherwise, execute the next comparison; S68, determining whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current stray value are greater than the higher harmonics of the fixed reference local oscillator signal corresponding to the stray value to be compared, and whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current stray value is equal to 1, if so, executing the next comparison, if not, executing S69; S69, determine whether the current item hash value is greater than the hash value to be compared and the current item hash value is not 1, if so, update the hash value to be compared to the current item hash value and then execute the next comparison, if not, execute the next comparison.

[0029] Specifically, the solution of the present application is actually to first determine all the spurious values ​​corresponding to each frequency division ratio, and then determine the worst spurious value in the spurious value group corresponding to each frequency division ratio. The worst spurious value is the spurious value that has the greatest impact on the main frequency signal, and then find the spurious value that has the least impact on the main frequency signal among all the worst spurious values, and use it as the optimal spurious value. This is because the loop has a suppressive effect, and only the spurious within a certain range from the main frequency will have a greater impact on the main frequency signal. Therefore, the conventional solution of finding the optimal spurious value in the spurious value group corresponding to the frequency division ratio is not ideal. Therefore, the worst spurious value corresponding to each frequency division ratio is first determined, and then the optimal spurious value is determined therefrom, thereby determining the optimal frequency division ratio, and finally determining the input signal of the second phase-locked loop.

[0030] Based on the above-mentioned phase-locked loop spurious optimization method based on the mixing frequency architecture, one or more embodiments of this specification also provide a platform and terminal for phase-locked loop spurious optimization based on the mixing frequency architecture. The platform or terminal may include a device, software, module, plug-in, server, client, etc. using the method described in the embodiments of this specification and combined with a device for implementing necessary hardware. Based on the same innovative concept, the system in one or more embodiments provided in the embodiments of this specification is as described in the following embodiments. Since the implementation scheme and method for solving the problem of the system are similar, the implementation of the specific system in the embodiments of this specification can refer to the implementation of the aforementioned method, and the repetitions will not be repeated. The terms "unit" or "module" used below can implement a combination of software and / or hardware with predetermined functions. Although the system described in the following embodiments is preferably implemented in software, hardware and a combination of software and hardware are also possible and conceived.

[0031] The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. There may be other divisions in actual implementation, such as multiple units or plug-ins may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of the device or unit, which may be electrical, mechanical or other forms.

[0032] These computer program instructions may also be loaded onto a computer or other programmable resource data updating device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions executed on the computer or other programmable device for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0033] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. In the description of this specification, the description of the reference term "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0034] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A phase-locked loop spurious optimization method based on a mixing frequency architecture, characterized in that: The method comprises: Determine a frequency division ratio set of the first phase-locked loop based on the set output frequency and the frequency range of the synthetic reference signal, wherein the synthetic reference signal is specifically a signal obtained by mixing the output signal of the second phase-locked loop with a fixed reference local oscillator signal; Determine a spurious value group corresponding to each frequency division ratio in the frequency division ratio set, and after normalizing all spurious values, extract the worst spurious value in each group of spurious values ​​to obtain a worst spurious value group; An optimal spurious value is determined based on the worst spurious value group, and a frequency division ratio corresponding to the optimal spurious value is used as a final frequency division ratio.

2. The phase-locked loop spurious optimization method based on a mixing frequency architecture as claimed in claim 1, characterized in that: The worst spurious value is the value with the smallest absolute value in each group of spurious values.

3. The phase-locked loop spurious optimization method based on a mixing frequency architecture as claimed in claim 2, characterized in that: Or extract the worst spurious value by the following process: Divide the spurious values ​​corresponding to the finite higher harmonics of the same fixed reference local oscillator signal in the spurious value group into different subgroups, take the spurious value with the smallest absolute value in each subgroup as the spurious value to be extracted, and group all the spurious values ​​to be extracted and their related parameters into a first list; A worst spurious value is determined based on the first list.

4. The phase-locked loop spurious optimization method based on a mixing frequency architecture as claimed in claim 3, characterized in that: The determining of the worst spurious value based on the first list specifically includes: Traversing the first list, and taking the stray value to be extracted of the current item in the traversal as the stray value to be processed; If the spurious value to be processed is less than 1, all spurious values ​​corresponding to the minimum higher harmonic of the fixed reference local oscillator signal in the first list are grouped into a second list, and all spurious values ​​in the second list are normalized, and when there are two or more spurious values ​​in the second list, the spurious value corresponding to the minimum absolute value is used as the worst spurious value to be determined; if the spurious value to be processed is not less than 1, a third list is extracted from the first list, and all spurious values ​​in the third list are normalized, and when there are two or more spurious values ​​in the third list, the spurious value with the minimum absolute value is used as the worst spurious value to be determined, the higher harmonic of the fixed reference local oscillator signal corresponding to any spurious value in the third list is the smallest and the actual spurious difference is less than the expected spurious difference, the actual spurious difference is equal to the spurious value to be processed minus the corresponding spurious value in the third list, and the expected spurious difference is equal to the difference between the higher harmonic of the fixed reference local oscillator signal corresponding to the spurious value to be processed and the higher harmonic of the fixed reference local oscillator signal corresponding to the corresponding spurious value in the third list multiplied by 5; After normalizing all the worst spurious values ​​to be determined, the worst spurious value to be determined with the smallest absolute value is normalized and taken as the worst spurious value.

5. The phase-locked loop spurious optimization method based on a mixing frequency architecture as claimed in claim 1, characterized in that: The determining of the optimal spurious value based on the worst spurious value group specifically includes: Arrange the spurious values ​​in the worst spurious value group in order from large to small to form a sequence; The first stray value in the sequence is used as the current stray value, and the second stray value is used as the stray values ​​to be compared, and the stray effects are compared with the current stray value in sequence, wherein when the stray effect of a stray value is better than the current stray value, the corresponding stray value is updated to the current stray value.

6. The phase-locked loop spurious optimization method based on a mixing frequency architecture as claimed in claim 1, characterized in that: The process of comparing the spurious effects specifically includes: S60, determining whether the value of the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value minus the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared is not less than 2, if so, executing the next comparison, if not, executing S61; S61, judging whether the current item stray value is not less than 1 and the stray value to be compared is less than 1, if so, executing the next comparison, if not, executing S62; S62, determining whether the value obtained by subtracting the higher-order harmonics corresponding to the fixed reference local oscillator signal of the current stray value from the higher-order harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared is equal to 1 and the value of the stray value to be compared minus the current stray value is not greater than 5, if so, executing the next comparison, otherwise executing S63; S63. If the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value are the same as the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is greater than 2, then the current stray value is updated; if the higher harmonics corresponding to the fixed reference local oscillator signal of the current stray value are the same as the higher harmonics corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is less than 2, and the higher harmonics of the second phase-locked loop output signal corresponding to the stray value to be compared minus the current stray value is less than 2, then the current stray value is updated. If the value of the higher harmonic of the second phase-locked loop output signal corresponding to the previous stray value is greater than 3, the stray value to be compared is updated to the current stray value and then the next comparison is performed. If the higher harmonic corresponding to the fixed reference local oscillator signal of the current stray value is the same as the higher harmonic corresponding to the fixed reference local oscillator signal of the stray value to be compared, and the value of the stray value to be compared minus the current stray value is less than 2, and the value of the higher harmonic of the second phase-locked loop output signal corresponding to the stray value to be compared minus the higher harmonic of the second phase-locked loop output signal corresponding to the current stray value is not greater than 3, then S64 is performed; S64, determining whether the first actual stray difference is less than the first expected stray difference, if so, executing S65, if not and the first actual stray difference is less than 3.5, updating the stray value to be compared to the current item stray value, wherein the first actual stray difference is specifically the difference between the current item stray value and the stray value to be compared, and the first expected stray difference is equal to the difference between the higher harmonics of the fixed reference local oscillator signal corresponding to the current item stray value and the higher harmonics of the fixed reference local oscillator signal corresponding to the stray value to be compared multiplied by 5; S65, judging whether the higher harmonic of the fixed reference local oscillator signal corresponding to the current stray value is not less than 2 and the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value to be compared is not less than 2, if so, executing S66, if not, executing the next comparison; S66, determine whether the absolute value of the current stray value is greater than or equal to 4.5 and the absolute value of the stray value to be compared is less than 5, if yes, execute the next comparison, if not, execute S67; S67, determine whether the difference between the absolute value of the current stray value and the absolute value of the stray value to be compared is less than 1.5 and whether the absolute value of the current stray value and the absolute value of the stray value to be compared are both less than or equal to 3. If so, execute S68; otherwise, execute the next comparison; S68, determining whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current stray value are greater than the higher harmonics of the fixed reference local oscillator signal corresponding to the stray value to be compared, and whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current stray value is equal to 1, if so, executing the next comparison, if not, executing S69; S69, determine whether the current item hash value is greater than the hash value to be compared and the current item hash value is not 1, if so, update the hash value to be compared to the current item hash value and then execute the next comparison, if not, execute the next comparison.

7. The phase-locked loop spurious optimization method based on a mixing frequency architecture as claimed in claim 1, characterized in that: The fixed reference signal of the second phase-locked loop is frequency-multiplied to obtain a fixed reference local oscillator signal.

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