Five-state comparator with metastability detection correction and five-state quantization successive approximation method

Abstract

The application relates to a five-state comparator with metastable state detection correction, which comprises a front-stage preamplification circuit, a rear-stage latch circuit, a strong metastable state detection and setting circuit, a metastable state detection circuit, a clock circuit and an encoding circuit. The front-stage preamplification circuit is used for pre-amplifying an input differential signal and outputting a signal to the rear-stage latch circuit. The rear-stage latch circuit is used for latching and outputting a comparison result of the comparator through a plurality of MOS tubes. The strong metastable state detection and setting circuit is used for detecting whether the comparator is in a strong metastable state and setting the output of the comparator, and if the strong metastable state is detected, a strong metastable state identification bit is generated. The metastable state detection circuit is used for detecting and identifying whether the comparator is in a metastable state, and if the metastable state is detected, a metastable state identification bit is generated. The clock circuit is used for generating clock signals corresponding to a working clock, a metastable state detection clock and a strong metastable state detection clock of the comparator. The encoding circuit is used for combining the output of the comparator and the metastable state identification bit to output a digital output result. The application can greatly improve quantization efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog integrated circuits, in particular to a five-state comparator with metastable state detection and correction and a five-state quantization successive approximation method. BACKGROUND

[0002] A dynamic comparator is a module that compares the voltage between its two inputs under the control of a clock, and generally has two stages of comparison and reset. In the reset stage, the voltage of the internal node of the circuit is reset, and in the comparison stage, the output node changes after a certain comparison time according to the size of the voltage between the two inputs. An important feature of the comparator is that the time required to obtain the output result of the comparison increases as the difference between the two input voltages decreases. When the voltage difference between the two input voltages is too small, the comparator may not be able to complete the comparison process within the specified comparison stage time, resulting in a metastable state.

[0003] Dynamic comparators are widely used in analog-to-digital converters (ADCs), such as successive approximation register (SAR) ADCs. In high-performance SAR ADCs, a comparator with high speed and high precision is required, but due to the short comparison time allocated to the comparator, the comparator is prone to metastable states, which limits the overall conversion speed and accuracy. In SAR ADCs, when the comparator enters a metastable state, it affects the normal operation of the circuit, resulting in the inability to complete the conversion of all bits, causing the system to produce flicker codes and severely affecting the performance of the ADC.

[0004] Existing metastable state suppression techniques mainly use an XOR operation on the output voltage of the comparator to identify the comparison result, and after a certain time delay of the comparison clock, if the comparator cannot output the correct logic result within the set delay time, the comparison result identification bit is still 0, which is considered to be in a metastable state. Then, through a combination of logic circuits and flip-flops, the output voltage of the comparator in a metastable state is set to 1 and 0 through PMOS and NMOS transistors. This metastable state detection method for the comparator requires an XOR gate, a combination of logic circuits, and a flip-flop before the output result is set, resulting in a large delay in the metastable state detection and setting path. The output voltage of the comparator may complete the flip-flop during the detection and setting process, often resulting in a large error and an inaccurate metastable state detection result. Moreover, setting the output voltage of the comparator in a metastable state to 1 and 0 cannot obtain the input voltage difference information of the comparator in a metastable state, which reduces the accuracy of the comparator. Additionally, the introduction of NMOS and PMOS transistors at both ends of the comparator introduces additional comparator offset voltages.

[0005] In addition, the conventional comparator can only get two output results in one comparison, which limits the SAR ADC to quantize by the two-state bisection successive approximation method. When the analog input continuous signal approaches 1 / 2, 1 / 4, etc., the output decision time of the comparator is obviously prolonged, resulting in longer conversion time of the ADC. Moreover, the two-state successive approximation method of bisection of a voltage region with one reference quantization line is not an efficient quantization method, and the N-time successive approximation can only obtain a quantization precision of 1 / 2 N .

[0006] In summary, the conventional comparator in the prior art can only get two output results in one comparison. When the analog input continuous signal approaches 1 / 2, 1 / 4, etc., the output decision time of the comparator is obviously prolonged, resulting in longer conversion time of the ADC. The applicant made corresponding exploration to solve the problem. SUMMARY

[0007] The present application aims to solve the above problems and provides a five-state comparator with metastable state detection correction, a five-state quantization successive approximation method, an electronic device, a computer device, and a computer readable storage medium.

[0008] To achieve the above purposes, the present application adopts the following technical solutions:

[0009] A five-state comparator with metastable state detection correction is proposed to achieve one of the purposes of the present application, comprising:

[0010] A pre-stage pre-amplification circuit for pre-amplifying the input differential signal and outputting the signal to a post-stage latch circuit;

[0011] A post-stage latch circuit for latching and outputting the comparison result of the comparator through a plurality of MOS tubes;

[0012] A strong metastable state detection and setting circuit for detecting whether the comparator is in a strong metastable state and setting the output of the comparator. If it is detected that the comparator is in a strong metastable state, a strong metastable state identification bit is generated;

[0013] A metastable state detection circuit for detecting and identifying whether the comparator is in a metastable state. If it is detected that the comparator is in a metastable state, a metastable state identification bit is generated;

[0014] A clock circuit for generating clock signals corresponding to the working clock, metastable state detection clock, and strong metastable state detection clock of the comparator;

[0015] A coding circuit combines the output of the comparator and a metastability identification bit to output a digital output result.

[0016] Optionally, the pre-stage pre-amplification circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, wherein the gates of the first MOS transistor and the second MOS transistor are connected to a positive input signal VIP and a negative input signal VIN respectively, and the sources of the first MOS transistor and the second MOS transistor are commonly connected to the ground.

[0017] The drain of the first MOS transistor is connected to the third MOS transistor, and the drain of the second MOS transistor is connected to the fourth MOS transistor.

[0018] The gates of the third MOS transistor and the fourth MOS transistor, and the gates of the fifth MOS transistor and the sixth MOS transistor are commonly connected to a comparison clock signal CLKC.

[0019] The drain of the third MOS transistor is connected to the fifth MOS transistor, the drain of the fourth MOS transistor is connected to the sixth MOS transistor, and the sources of the fifth MOS transistor and the sixth MOS transistor are commonly connected to a power supply voltage.

[0020] Optionally, the post-stage latch circuit comprises a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor and a twenty-second MOS transistor.

[0021] The gates of the seventh MOS transistor and the eighth MOS transistor are connected to the third MOS transistor and the fourth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor, and the fifteenth MOS transistor and the sixteenth MOS transistor respectively.

[0022] The sources of the seventh MOS transistor and the eighth MOS transistor are commonly connected to the nineteenth MOS transistor and the twentieth MOS transistor to a power supply voltage.

[0023] The drain of the seventh MOS transistor is connected to the ninth MOS transistor and the fifteenth MOS transistor respectively, and the drain of the eighth MOS transistor is connected to the tenth MOS transistor and the sixteenth MOS transistor respectively.

[0024] The gate of the ninth MOS transistor is connected to the eleventh MOS transistor, the twelfth MOS transistor and the fourteenth MOS transistor.

[0025] The gate of the tenth MOS is connected with the eleventh MOS, the twelfth MOS and the thirteenth MOS;

[0026] The drain of the ninth MOS is connected with the nineteenth MOS and the twenty first MOS, and the drain of the tenth MOS is connected with the twentieth MOS and the twenty second MOS;

[0027] The sources of the eleventh MOS, the twelfth MOS, the thirteenth MOS, the fourteenth MOS, the fifteenth MOS, the nineteenth MOS, the twentieth MOS, the twenty first MOS and the twenty second MOS are commonly connected to the ground.

[0028] Optionally, the strong metastable state detection and setting circuit comprises a seventeenth MOS, an eighteenth MOS, a twenty third MOS, a twenty fourth MOS, a twenty fifth MOS, a twenty sixth MOS, a twenty seventh MOS, a twenty eighth MOS, a twenty ninth MOS, a thirtieth MOS, a thirty first MOS, a thirty second MOS, a thirty third MOS, a thirty fourth MOS, a thirty fifth MOS and a thirty sixth MOS, wherein the strong metastable state identification bit comprises a P-end strong metastable state identification bit MD_sp and an N-end strong metastable state identification bit MD_sn;

[0029] The drain of the seventeenth MOS is connected with the twenty first MOS, and the drain of the eighteenth MOS is connected with the twenty second MOS;

[0030] The gate of the seventeenth MOS is connected with the twenty ninth MOS, the thirty first MOS, the thirty third MOS and the thirty fifth MOS, and the gate of the eighteenth MOS is connected with the thirtieth MOS, the thirty second MOS, the thirty fourth MOS and the thirty sixth MOS;

[0031] The sources of the seventeenth MOS and the eighteenth MOS are commonly connected to the ground through the twenty seventh MOS, the twenty eighth MOS, the thirty first MOS, the thirty second MOS, the thirty fifth MOS and the thirty sixth MOS;

[0032] The gate of the twenty seventh MOS is connected with the nineteenth MOS and the twenty first MOS, and the gate of the twenty eighth MOS is connected with the twentieth MOS and the twenty second MOS;

[0033] The drain of the twenty-seventh MOS is connected with the twenty-fifth MOS, and the twenty-eighth MOS is connected with the twenty-sixth MOS;

[0034] The gates of the twenty-fifth MOS and the twenty-sixth MOS are commonly connected to a strong metastable detection clock CLKCD_s;

[0035] The drain of the twenty-fifth MOS is connected with the twenty-third MOS, the twenty-ninth MOS, the thirty-first MOS, the thirty-third MOS and the thirty-fifth MOS;

[0036] The drain of the twenty-sixth MOS is connected with the twenty-fourth MOS, the thirtieth MOS, the thirty-second MOS, the thirty-fourth MOS and the thirty-sixth MOS;

[0037] The gates of the twenty-third MOS and the twenty-fourth MOS are commonly connected to a comparison clock signal CLKC, and the sources of the twenty-third MOS and the twenty-fourth MOS are commonly connected with the twenty-ninth MOS, the thirtieth MOS, the thirty-third MOS and the thirty-fourth MOS to a power supply voltage.

[0038] Optionally, the metastable state detection circuit comprises a thirty-seventh MOS, a thirty-eighth MOS, a thirty-ninth MOS, a fortieth MOS, a forty-first MOS, a forty-second MOS, a forty-third MOS M43, a forty-fourth MOS, a forty-fifth MOS, a forty-sixth MOS, a forty-seventh MOS, a forty-eighth MOS, a forty-ninth MOS and a fiftieth MOS, wherein the metastable state identification bit comprises a P-end metastable state identification bit MD_p and an N-end metastable state identification bit MD_n;

[0039] The gate of the forty-first MOS is connected with the nineteenth MOS and the twenty-first MOS, and the forty-second MOS is connected with the twentieth MOS and the twenty-second MOS;

[0040] The drain of the forty-first MOS is connected with the thirty-ninth MOS, and the drain of the forty-second MOS is connected with the fortieth MOS;

[0041] The gate of the thirty-ninth MOS and the gate of the fortieth MOS are commonly connected to a metastable state detection clock CLKCD; the drain of the thirty-ninth MOS is connected with the thirty-seventh MOS, the forty-third MOS, the forty-fifth MOS, the forty-seventh MOS, the forty-ninth MOS; the drain of the fortieth MOS is connected with the thirty-eighth MOS, the forty-fourth MOS, the forty-sixth MOS, the forty-eighth MOS and the fiftieth MOS;

[0042] The gate of the thirty-seventh MOS and the gate of the thirty-eighth MOS are commonly connected to a comparison clock signal CLKC, and the source of the thirty-seventh MOS and the source of the thirty-eighth MOS are commonly connected to a power supply voltage with the forty-third MOS, the forty-fourth MOS, the forty-seventh MOS and the forty-eighth MOS;

[0043] The drain of the forty-fifth MOS is connected with the forty-third MOS, the forty-seventh MOS and the forty-ninth MOS, and the drain of the forty-sixth MOS is connected with the forty-fourth MOS, the forty-eighth MOS and the fiftieth MOS;

[0044] The source of the forty-fifth MOS and the source of the forty-sixth MOS are commonly connected to ground with the forty-first MOS, the forty-second MOS, the forty-ninth MOS and the fiftieth MOS.

[0045] Optionally, the clock circuit comprises a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first delay unit DLY1, a second delay unit DLY2 and a first D flip-flop, wherein,

[0046] The input of the first AND gate AND1 is connected with the output P of the strong metastable state detection and setting circuit, and the input N of the strong metastable state detection and setting circuit is connected with the strong metastable state identification bit MD_sp and the strong metastable state identification bit MD_sn, the output of the first AND gate AND1 is connected with the clock signal end of the first D flip-flop, the input D end of the first D flip-flop is grounded, the reset end of the first D flip-flop is connected with the start clock EN, and the output is the strong metastable state identification bit MD_s;

[0047] When EN is 1, the output MD_s is 1; MD_s and the clock CLK are connected with the input end of the second AND gate AND2, and the output end of the second AND gate AND2 is connected with the comparison clock signal CLKC; the comparison clock signal CLKC is connected with the input end of the first delay unit DLY1 and the input end of the second delay unit DLY2 at the same time, and the outputs are the metastable state detection clock CLKCD and the strong metastable state detection clock CLKCD_s respectively;

[0048] The input of the third AND gate AND3 is connected with the output P metastable identification bit MD_p and the output N metastable identification bit MD_n of the metastable state detection circuit, and the output is connected with the metastable identification bit MD.

[0049] Optionally, the input of the encoding circuit is connected with the output P comparison output TP and the output N comparison output TN of the later stage latch circuit and the metastable identification bit MD in the clock circuit, and the output is a three-bit binary digital output result, from low bit to high bit, DOUT1, DOUT2 and DOUT3, wherein, DOUT1 represents the least significant bit, DOUT2 represents the next lower bit, and DOUT3 represents the most significant bit, DOUT=(TP+TN non)+(TP+TN non)&MD non+MD.

[0050] Another purpose of the present application is to provide a five-state quantization successive approximation method, which is applied to the five-state comparator with metastable state detection and correction.

[0051] Step (1), in the first approximation, the input signal is compared with 1 / 2 of the quantization reference value, if the input signal is greater than 1 / 2+3 / 2 N+3 , it is marked as the first state;

[0052] If the input signal is less than 1 / 2-3 / 2 N+3 , it is marked as the second state;

[0053] If the input signal is between 1 / 2-3 / 2 N+3 and 1 / 2+3 / 2 N+3 , it means that the preliminary interval of the input signal has been found, and the next approximation is not performed, and in the preliminary interval, according to the specific range of the input signal, it is further subdivided into the third state, the fourth state and the fifth state;

[0054] If the input signal is between 1 / 2+1 / 2 N+3 and 1 / 2+3 / 2 N+3 , it is marked as the third state;

[0055] If the input signal is between 1 / 2-3 / 2 N+3 and 1 / 2-1 / 2 N+3 , it is marked as the fourth state,

[0056] If the input signal is between 1 / 2±1 / 2 N+3 , it is marked as the fifth state;

[0057] If the approximation result is the first state or the second state, the next approximation is performed, and step (2) is continued to be executed;

[0058] Step (2), the second successive approximation is performed according to the state of the first successive approximation; if the first successive approximation result is the first state, the input signal is compared with 3 / 4±3 / 2 N+3 and 3 / 4±1 / 2 N+3 interval, to generate one of five approximation states;

[0059] if the first successive approximation result is the second state, the input signal is compared with 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 interval, to generate one of five approximation states;

[0060] if the successive approximation is the third state, the fourth state or the fifth state, it indicates that the signal interval has been found, and the approximation process ends; if the successive approximation is the first state or the second state, the next approximation is continued, and step (3) is entered;

[0061] Step (3), the approximation process is repeated in this way until the Nth successive approximation is completed; if the third state, the fourth state or the fifth state is obtained in the comparison process of a certain successive approximation, it indicates that the signal interval has been determined, and the approximation process ends.

[0062] Optionally, when the i-th conversion does not occur metastable state, i is an integer greater than or equal to 2 and less than or equal to N, then the three-bit binary quantization result D(i) finally output by the bit conversion is equal to DOUT(i);

[0063] if the i-th conversion occurs metastable state, the quantization result D(i) of the current bit and the quantization result D(2) of the next lower bit are both equal to 010, and the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by the comparison of the current bit;

[0064] Finally, the high-bit quantization result is moved two bits to the left, and then added to the low-bit digital result, and N sets of three-bit binary quantization results are obtained through N conversions, and (N+2) effective quantization bits are obtained after the error 2-bit addition.

[0065] Compared with the prior art, the present application can solve the problem that the conventional comparator in the prior art can generally only obtain two output results in one comparison, and when the continuous signal of the analog input approaches 1 / 2, 1 / 4 and other two-equal-division reference quantization lines, the output decision time of the comparator is obviously prolonged, resulting in a long conversion time of the ADC, etc.

[0066] Firstly, the application overcomes the shortcomings of the existing successive approximation type analog-to-digital converter, i.e., the comparator cannot obtain reliable logic results due to metastability, the comparison speed and accuracy are limited, and the quantization of the existing successive approximation type analog-to-digital converter can only perform inefficient two-state quantization because the comparator output has only two states.

[0067] Secondly, the application sets two metastability detection boundary values of 1 / 8LSB and 3 / 8LSB, and divides the metastability region of the comparator into strong metastability and weak metastability, when the differential input of the comparator is less than 1 / 8LSB, it is strong metastability, when the differential input of the comparator is between 1 / 8LSB and 3 / 8LSB, it is weak metastability, and when the differential input of the comparator is greater than 3 / 8LSB, no metastability occurs, compared with the traditional two-state comparator, the application has five effective output results each time, and can suppress metastability while improving accuracy by using metastability information.

[0068] Thirdly, the five-state comparator of the application adopts a fully differential structure, which can directly detect the metastability of the two ends of the comparator output without passing through an XOR gate, and directly set the voltages of the two ends of the comparator output after detecting strong metastability, without setting the voltages of the two ends of the comparator output through combination logic and flip-flop, the metastability detection correction circuit of the application is faster and more accurate.

[0069] Fourthly, the application sets the two ends of the comparator output to the reset state of 11 by using two same NMOS tubes when strong metastability occurs, while the traditional scheme sets the two ends of the comparator output to 10 by using one NMOS and one PMOS tube, which is an invalid output result, the application encodes the output of the comparator after metastability and the metastability identification bit as an effective comparison result by a new simple logic circuit, which overcomes the shortcomings of the traditional two-state comparator that needs to wait for a long comparison decision time when the differential input quantity is very small, and improves the accuracy of the comparator.

[0070] Fifthly, the application proposes a new simple logic circuit, which is composed of a low-cost conventional adder, an inverter and an AND gate, and can obtain the binary effective digital output DOUT=(TP+TN NOT)+(TP+TN NOT)&MD NOT+MD of the comparator output signal TP, TN and the metastability identification bit MD through logic combination, which can realize five effective digital outputs in one comparison, while the conventional comparator has the digital output DOUT=DP or DN NOT, and DN and DN NOT are inverse to each other. The application can also encode the comparison result after metastability of the comparator as an effective digital output result, corresponding to the small input differential voltage value of the comparator.

[0071] Sixthly, the five-state quantization successive approximation method proposed in the application can greatly improve the quantization efficiency compared with the traditional two-state quantization successive approximation method. Once quantization has five different effective quantization results, which can accurately quantize the analog input signal in the full range of 0 to 1 and effectively identify and process metastable states. If the size of the input differential signal in the comparison process of the successive approximation is within 3 / 8 quantization accuracy, it indicates that the signal interval has been determined, and the approximation process ends. N-bit quantization has (2 N+2 -3) quantization results, which can improve the quantization accuracy by nearly 2 bits compared with the traditional two-state quantization. BRIEF DESCRIPTION OF DRAWINGS

[0072] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description, taken in conjunction with the following drawings, in which:

[0073] Figure 1 It is a circuit principle diagram of the five-state comparator with metastable state detection correction in the embodiment of the present application;

[0074] Figure 2 It is a schematic diagram of the working waveform of the five-state comparator with metastable state detection correction in the embodiment of the present application;

[0075] Figure 3 It is a schematic diagram of the five effective digital output results output by the five-state comparator in the embodiment of the present application;

[0076] Figure 4 It is a schematic diagram of the mathematical form comparison of the five-state successive approximation method and the conventional two-state successive approximation method in the embodiment of the present application;

[0077] Figure 5 It is a schematic diagram of the working process of the five-state successive approximation type analog-digital converter in the embodiment of the present application;

[0078] Figure 6 It is a schematic diagram of the simulation result of the traditional two-state approximation type analog-digital converter in the embodiment of the present application;

[0079] Figure 7 It is a schematic diagram of the simulation result of the five-state successive approximation type analog-digital converter in the embodiment of the present application. DETAILED DESCRIPTION

[0080] The embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as a limitation of the present application.

[0081] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is further understood that the terms "comprising," "including," "containing," and "having" and the like, when used in the specification, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is further understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In addition, the word "coupling" or "coupled" as used herein includes the appending of wireless connections or wireless couplings. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0082] Unless otherwise expressly stated, it is anticipated that each recited generic term is a genus of working embodiments which individually disclose each possible sub-genus and species unless otherwise indicated. Unless otherwise indicated, the various embodiments disclosed herein are not mutually exclusive, but can be combined to form alternative embodiments. Accordingly, various features that are described and / or claimed in the foregoing disclosure can be combined in any combination.

[0083] Referring to Figure 1 The five-state comparator with metastable state detection correction of the present application, in one embodiment, comprises:

[0084] A pre-stage pre-amplification circuit 1 for pre-amplifying an input differential signal and outputting the signal to a post-stage latch circuit;

[0085] A post-stage latch circuit 2 for latching and outputting the comparison result of the comparator through a plurality of MOS transistors;

[0086] A strong metastable state detection and setting circuit 3 for detecting whether the comparator is in a strong metastable state and setting the output of the comparator, and generating a strong metastable state identification bit if the strong metastable state is detected;

[0087] A metastable state detection circuit 4 for detecting and identifying whether the comparator is in a metastable state, and generating a metastable state identification bit if the metastable state is detected;

[0088] A clock circuit 5 for generating clock signals corresponding to the working clock, metastable state detection clock, and strong metastable state detection clock of the comparator;

[0089] An encoding circuit 6 for combining the output of the comparator and the metastable state identification bit to output a digital output result.

[0090] In some embodiments, the pre-stage pre-amplification circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, wherein the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected to a positive input signal VIP and a negative input signal VIN, respectively, and the sources of the first MOS transistor M1 and the second MOS transistor M2 are commonly connected to ground;

[0091] The drain of the first MOS transistor M1 is connected to the third MOS transistor M3, and the drain of the second MOS transistor M2 is connected to the fourth MOS transistor M4.

[0092] The gates of the third MOS transistor M3 and the fourth MOS transistor M4, and the gates of the fifth MOS transistor M5 and the sixth MOS transistor M6 are commonly connected to a comparison clock signal CLKC.

[0093] The drain of the third MOS transistor M3 is connected to the fifth MOS transistor M5, and the drain of the fourth MOS transistor M4 is connected to the sixth MOS transistor M6, and the sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are commonly connected to a power supply voltage.

[0094] In some embodiments, the post-stage latch circuit includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, and a twenty-second MOS transistor M22.

[0095] The gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected to the third MOS transistor M3 and the fourth MOS transistor M4, the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14, and the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, respectively.

[0096] The sources of the seventh MOS transistor M7 and the eighth MOS transistor M8 are commonly connected to the nineteenth MOS transistor M19 and the twentieth MOS transistor M20, and a power supply voltage.

[0097] The drain of the seventh MOS transistor M7 is connected to the ninth MOS transistor M9 and the fifteenth MOS transistor M15, respectively, and the drain of the eighth MOS transistor M8 is connected to the tenth MOS transistor M10 and the sixteenth MOS transistor M16, respectively.

[0098] The gate of the ninth MOS M9 is connected with the eleventh MOS M11, the twelfth MOS M12 and the fourteenth MOS M14;

[0099] The gate of the tenth MOS M10 is connected with the eleventh MOS M11, the twelfth MOS M12 and the thirteenth MOS M13;

[0100] The drain of the ninth MOS M9 is connected with the nineteenth MOS M19 and the twenty-first MOS M21, and the drain of the tenth MOS M10 is connected with the twentieth MOS M20 and the twenty-second MOS M22;

[0101] The source of the eleventh MOS M11, the twelfth MOS M12, the thirteenth MOS M13, the fourteenth MOS M14, the fifteenth MOS M15, the nineteenth MOS M19, the twentieth MOS M20, the twenty-first MOS M21 and the twenty-second MOS M22 are commonly connected to the ground.

[0102] In some embodiments, the strong metastable state detection and setting circuit comprises a seventeenth MOS M17, an eighteenth MOS M18, a twenty-third MOS M23, a twenty-fourth MOS M24, a twenty-fifth MOS M25, a twenty-sixth MOS M26, a twenty-seventh MOS M27, a twenty-eighth MOS M28, a twenty-ninth MOS M29, a thirtieth MOS M30, a thirty-first MOS M31, a thirty-second MOS M32, a thirty-third MOS M33, a thirty-fourth MOS M34, a thirty-fifth MOS M35 and a thirty-sixth MOS M36, wherein the strong metastable state identification bit comprises a P-end strong metastable state identification bit MD_sp and an N-end strong metastable state identification bit MD_sn;

[0103] The drain of the seventeenth MOS M17 is connected with the twenty-first MOS M21, and the drain of the eighteenth MOS M18 is connected with the twenty-second MOS M22;

[0104] The gate of the seventeenth MOS M17 is connected with the twenty-ninth MOS M29, the thirty-first MOS M31, the thirty-third MOS M33 and the thirty-fifth MOS M35, and the gate of the eighteenth MOS M18 is connected with the thirtieth MOS M30, the thirty-second MOS M32, the thirty-fourth MOS M34 and the thirty-sixth MOS M36;

[0105] The source of the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18 are commonly connected to ground with the twenty-seventh MOS transistor M27, the twenty-eighth MOS transistor M28, the thirty-first MOS transistor M31, the thirty-second MOS transistor M32, the thirty-fifth MOS transistor M35, and the thirty-sixth MOS transistor M36;

[0106] The gate of the twenty-seventh MOS transistor M27 is connected with the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21, and the gate of the twenty-eighth MOS transistor M28 is connected with the twentieth MOS transistor M20 and the twenty-second MOS transistor M22;

[0107] The drain of the twenty-seventh MOS transistor M27 is connected with the twenty-fifth MOS transistor M25, and the twenty-eighth MOS transistor M28 is connected with the twenty-sixth MOS transistor M26;

[0108] The gates of the twenty-fifth MOS transistor M25 and the twenty-sixth MOS transistor M26 are commonly connected to a strong metastable detection clock CLKCD_s;

[0109] The drain of the twenty-fifth MOS transistor M25 is connected with the twenty-third MOS transistor 23, the twenty-ninth MOS transistor M29, the thirty-first MOS transistor M31, the thirty-third MOS transistor M33, and the thirty-fifth MOS transistor M35;

[0110] The drain of the twenty-sixth MOS transistor M26 is connected with the twenty-fourth MOS transistor M24, the thirtieth MOS transistor M30, the thirty-second MOS transistor M32, the thirty-fourth MOS transistor M34, and the thirty-sixth MOS transistor M36;

[0111] The gates of the twenty-third MOS transistor 23 and the twenty-fourth MOS transistor M24 are commonly connected to a comparison clock signal CLKC, and the sources of the twenty-third MOS transistor 23 and the twenty-fourth MOS transistor M24 are commonly connected to a power supply voltage with the twenty-ninth MOS transistor M29, the thirtieth MOS transistor M30, the thirty-third MOS transistor M33, and the thirty-fourth MOS transistor M34.

[0112] In some embodiments, the metastable state detection circuit includes a thirty-seventh MOS transistor M37, a thirty-eighth MOS transistor M38, a thirty-ninth MOS transistor M39, a fortieth MOS transistor M40, a forty-first MOS transistor M41, a forty-second MOS transistor M42, a forty-third MOS transistor M43, a forty-fourth MOS transistor M44, a forty-fifth MOS transistor M45, a forty-sixth MOS transistor M46, a forty-seventh MOS transistor M47, a forty-eighth MOS transistor M48, a forty-ninth MOS transistor M49, and a fiftieth MOS transistor M50, wherein the metastable state identification bit includes a P-terminal metastable state identification bit MD_p and an N-terminal metastable state identification bit MD_n.

[0113] The gate of the forty-first MOS transistor M41 is connected with the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21, and the forty-second MOS transistor M42 is connected with the twentieth MOS transistor M20 and the twenty-second MOS transistor M22.

[0114] The drain of the forty-first MOS transistor M41 is connected with the thirty-ninth MOS transistor M39, and the drain of the forty-second MOS transistor M42 is connected with the fortieth MOS transistor M40.

[0115] The gates of the thirty-ninth MOS transistor M39 and the fortieth MOS transistor M40 are commonly connected to a metastable state detection clock CLKCD, the drain of the thirty-ninth MOS transistor M39 is connected with the thirty-seventh MOS transistor M37, the forty-third MOS transistor M43, the forty-fifth MOS transistor M45, the forty-seventh MOS transistor M47, and the forty-ninth MOS transistor M49, and the drain of the fortieth MOS transistor M40 is connected with the thirty-eighth MOS transistor M38, the forty-fourth MOS transistor M44, the forty-sixth MOS transistor M46, the forty-eighth MOS transistor M48, and the fiftieth MOS transistor M50.

[0116] The gates of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 are commonly connected to a comparison clock signal CLKC, and the sources of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 are commonly connected to a power supply voltage with the forty-third MOS transistor M43, the forty-fourth MOS transistor M44, the forty-seventh MOS transistor M47, and the forty-eighth MOS transistor M48.

[0117] The drain of the forty-fifth MOS transistor M45 is connected with the forty-third MOS transistor M43, the forty-seventh MOS transistor M47, and the forty-ninth MOS transistor M49, and the drain of the forty-sixth MOS transistor M46 is connected with the forty-fourth MOS transistor M44, the forty-eighth MOS transistor M48, and the fiftieth MOS transistor M50.

[0118] The source of the forty-fifth MOS transistor M45 and the forty-sixth MOS transistor M46 are commonly connected to ground with the forty-first MOS transistor M41, the forty-second MOS transistor M42, the forty-ninth MOS transistor M49 and the fiftieth MOS transistor M50.

[0119] In some embodiments, the clock circuit comprises a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first delay unit DLY1, a second delay unit DLY2 and a first D flip-flop, wherein,

[0120] The input of the first AND gate AND1 is connected with the output P end strong metastable state identification bit MD_sp and the output N end strong metastable state identification bit MD_sn of the strong metastable state detection and setting circuit, the output is connected with the clock signal end of the first D flip-flop, the input D end of the first D flip-flop is grounded, the reset end of the first D flip-flop is connected with the start clock EN, and the output is the strong metastable state identification bit MD_s.

[0121] When EN is 1, the output MD_s is 1; MD_s is connected with the clock CLK to the input end of the second AND gate AND2, the output end of the second AND gate AND2 is connected with the comparison clock signal CLKC; the comparison clock signal CLKC is connected with the input end of the first delay unit DLY1 and the second delay unit DLY2 at the same time, and the outputs thereof are the metastable state detection clock CLKCD and the strong metastable state detection clock CLKCD_s respectively.

[0122] The input of the third AND gate AND3 is connected with the output P end metastable state identification bit MD_p and the output N end metastable state identification bit MD_n of the metastable state detection circuit, and the output is connected with the metastable state identification bit MD.

[0123] In some embodiments, the input of the encoding circuit is connected with the comparison output TP of the output P end and the comparison output TN of the output N end of the subsequent stage latch circuit and the metastable state identification bit MD in the clock circuit, and the output is a three-bit binary digital output result, from low to high, which is DOUT1, DOUT2 and DOUT3 respectively, wherein DOUT1 represents the least significant bit, DOUT2 represents the next low bit, and DOUT3 represents the most significant bit, wherein DOUT=(TP+TN non)+(TP+TN non)&MD non+MD, which can realize five kinds of effective digital outputs in one comparison, while the digital DOUT of the conventional comparator is DP or DN non, and DN and DN non are mutually exclusive.

[0124] From the above embodiments, the application proposes a new simple logic circuit, which is composed of low-cost conventional adder, inverter and AND gate with low speed requirement, and can obtain the final digital output Dout=(DP+DN non)+(DP+DN non)&MD non+MD through logic combination of the comparison output signal TP, TN and metastable state identification bit MD of the comparator, and can realize five effective digital outputs in one comparison, while the conventional comparator has digital Dout=DP or DN non, and DN and DN non are inverse to each other. The application can also encode the comparison result after the metastable state of the comparator as an effective digital output result, corresponding to the small input differential voltage value of the comparator at this time.

[0125] In further embodiments, the working process of the five-state comparator with metastable state detection and correction proposed by the application can be divided into reset phase and comparison phase, which includes:

[0126] In the reset phase, the comparison clock signal CLKC, the metastable state detection clock CLKCD and the strong metastable state detection clock CLKCD_s are all low level; the fifth MOS tube M5 and the sixth MOS tube M6 in the front-stage pre-amplification circuit 1 are turned on, and the third MOS tube M3 and the fourth MOS tube M4 are turned off, and the outputs Vop1 and Von1 are high level; the MOS tubes M7, M8, M9, M10, M11, M12, M21 and M22 in the rear-stage latch circuit 2 are turned off, and the MOS tubes M13, M14, M15, M16, M19 and M20 are turned on, and the outputs TP and TN of the rear-stage latch circuit 2 are both 1. The strong metastable state detection and setting circuit 3 and the metastable state detection circuit 4 also enter the reset state, and the outputs P end strong metastable state identification bit MD_sp, N end strong metastable state identification bit MD_sn, P end metastable state identification bit MD_p and N end metastable state identification bit MD_n are all 0.

[0127] In the comparison phase, the comparison clock signal CLKC starts to rise to high level, the metastable state detection clock CLKCD is the clock of CLKC after delaying the first detection time t, and the strong metastable state detection clock CLKCD_s is the clock of CLKC after delaying the second detection time ts. The first detection time t is the time required for the comparator output result when the comparison input is 1 / 8 LSB, the second detection time ts is the time required for the comparator output result when the comparison input is 3 / 8 LSB, and the size of the second detection time ts is greater than that of the first detection time t. In the comparison phase, the fifth MOS tube M5 and the sixth MOS tube M6 in the 1 front-stage pre-amplification circuit are closed, the third MOS tube M3 and the fourth MOS tube M4 are turned on, the output Vop1 and Von1 thereof are lowered at different rates according to the size of VIP and VIN, and the first-stage pre-amplified signal is latched in the rear-stage latch circuit 2.

[0128] If the comparator outputs TP and TN are flipped before the rising edge of CLKCD arrives, it indicates that the comparison does not appear metastable state, the metastable state identification bit MD is 0, and the strong metastable state identification bit MD_s is 1. At this time, if TP = 1 and TN = 0, the comparison result is VIP-VIN > 3 / 8 LSB, and if TP = 0 and TN = 1, the comparison result is VIP-VIN < -3 / 8 LSB.

[0129] If the comparator outputs TP and TN do not flip at the rising edge of CLKCD, it indicates that the comparator appears metastable state, and the metastable state identification bit MD is 1. Then, if the comparator outputs TP and TN still do not flip at the rising edge of CLKCD_s, it indicates that the metastable state of the comparator is strong metastable state, the strong metastable state identification bit MD_s is 0, the strong metastable state detection and setting circuit 3 quickly sets the output terminals TP and TN of the comparator to 11 through the MOS tubes M17 and M18 without setting through the combination logic and the flip-flop, and resets CLKC to low level through the second AND gate AND2, and the comparison result is -1 / 8 LSB < VIP-VIN < 1 / 8 LSB.

[0130] If the comparator outputs TP and TN do not flip at the rising edge of CLKCD, but flip at the rising edge of CLKCD_s, it indicates that the metastable state of the comparator is weak metastable state, the metastable state identification bit MD is 1, and the strong metastable state identification bit MD_s is also 1. At this time, if TP = 1 and TN = 0, the comparison result is 1 / 8 LSB < VIP-VIN < 3 / 8 LSB, and if TP = 0 and TN = 1, the comparison result is -3 / 8 LSB < VIP-VIN < -1 / 8 LSB.

[0131] In some embodiments, please refer to Figure 2 The operating waveforms of the main node voltages of the five-state comparator with metastable detection and correction in this application under different input signal conditions are as follows: Figure 2 As shown, EN is the system reset clock, CLK is the comparator enable clock, CLKC is the comparator clock, VIN is the N-terminal input signal of the comparator, VIP is the P-terminal input signal of the comparator, CLKCD is the metastability detection clock, CLKCD_s is the strong metastability detection clock, TP is the P-terminal output signal of the comparator, TN is the N-terminal output signal of the comparator, MD is the metastability flag signal, and MD_s is the strong metastability flag signal. The metastability detection time t is the delay between the rising edge of the comparator clock CLKC and the metastability detection clock CLKCD, and the strong metastability detection time ts is the delay between the rising edge of the comparator clock CLKC and the strong metastability detection clock CLKCD_s.

[0132] For further embodiments, please refer to Figure 1 and Figure 2 The operating states of the five-state comparator with metastable detection and correction in this application when it produces five different output results are described, including:

[0133] When the system reset signal EN is high, such as Figure 1 As shown in clock circuit 5, the high-level EN signal sets the strong metastability flag MD_s to 1 through a D flip-flop. Then, when the first rising edge of the comparator enable clock CLK arrives, CLKC goes high, starting the first comparison cycle. After the first rising edge of CLKC, the comparator performs its first comparison. When the first rising edge of the metastability detection clock CLKCD arrives, the comparator outputs TP and TN are 0, indicating that the first comparison result has been output. This means that no metastability has occurred. Figure 1 The metastability detection circuit 4 outputs MD_p and MD_n as 0, and the metastability flag MD after the AND gate is 0; when the first rising edge of the strong metastability detection clock CLKCD_s arrives, the comparator outputs TP as 0 and TN as 1. Figure 1 The strong metastability detection and setting circuit 3 outputs MD_p as 0 and MD_n as 1. After passing through the AND gate, MD_spn is 0, and no trigger is performed. Figure 1 In the clock circuit 5, the D flip-flop has its strong metastability flag MD_s still set to 1, and the corresponding input signal range is VIP-VI N<-0.375LSB.

[0134] Similarly, when the second rising edge of the comparison enable clock CLK arrives, the second comparison period starts, and the comparator performs the second comparison after the second rising edge of the CLKC arrives. When the second rising edge of the metastability detection clock CLKCD arrives, the output TP of the comparator is 1, and the output TN of the comparator is 0, and the second comparison has output the result, which indicates that the second comparison does not have the metastability, the metastability identification bit MD is 0, and the strong metastability identification bit MD_s is 1, and the corresponding input signal interval is VIP-VIN>0.375LSB.

[0135] In the third comparison period, when the third rising edge of the metastability detection clock CLKCD arrives, the output TP of the comparator is 1, and the output TN of the comparator is 1, and the third comparison has not output the result, which indicates that the third comparison has the metastability, the metastability identification bit MD is 0, and when the third rising edge of the strong metastability detection clock CLKCD_s arrives, the output TP of the comparator is 0, and the output TN of the comparator is 1, the metastability of the comparator is weak, and the strong metastability identification bit MD_s is 1, and the corresponding input signal interval is -0.375LSB<VIP-VIN<0.125LSB.

[0136] In the fourth comparison period, when the fourth rising edge of the metastability detection clock CLKCD arrives, the output TP of the comparator is 1, and the output TN of the comparator is 1, and the fourth comparison has not output the result, which indicates that the fourth comparison has the metastability, the metastability identification bit MD is 0, and when the fourth rising edge of the strong metastability detection clock CLKCD_s arrives, the output TP of the comparator is 1, and the output TN of the comparator is 0, the metastability of the comparator is weak, and the strong metastability identification bit MD_s is 1, and the corresponding input signal interval is 0.125LSB<VIP-VIN<0.375LSB.

[0137] In the fifth comparison period, when the fifth rising edge of the metastability detection clock CLKCD arrives, the output TP of the comparator is 1, and the output TN of the comparator is 1, and the fifth comparison has not output the result, which indicates that the fifth comparison has the metastability, the metastability identification bit MD is 1, and when the fifth rising edge of the strong metastability detection clock CLKCD_s arrives, the output TP of the comparator is 1, and the output TN of the comparator is 1, Figure 1 the strong metastability detection and setting circuit 3 in the strong metastability detection and setting circuit 3 outputs MD_sp as 1, and MD_sn as 1, so that Figure 1 the strong metastability detection and setting circuit 3 in the strong metastability detection and setting circuit 3 Figure 1 the strong metastability detection and setting circuit 3 in the strong metastability detection and setting circuit 3 Figure 3The D flip-flop of the 5 clock circuit in the figure, the strong metastable state identification bit MD_s is 0, CLKC will be reset to low level, the comparator also enters the reset state as a whole, the metastable state generated by the comparator is strong metastable state, at this time the corresponding input signal interval is 0.125LSB

[0138] The three output signals obtained by one comparison of the comparator, i.e. the comparison output signals TP, TN and the metastable state identification bit MD, are combined by a new simple logic to obtain the digital output Dout=(DP+DN non)+(DP+DN non)&MD non+MD, which can realize five effective digital outputs in one comparison. For further illustration, the relationship and conversion between the five comparison outputs, comparison results and digital outputs are shown in the following table: Figure 4 The digital output of the conventional comparator can only be Dout=DP or DN non, and DN and DN non are inverse to each other.

[0139] A five-state quantization successive approximation method is proposed to adapt to one of the purposes of the present application, which is applied to the five-state comparator with metastable state detection and correction described in any one of the above, comprising:

[0140] Step (1), in the first approximation, the input signal is compared with 1 / 2 of the quantization reference value, if the input signal is greater than 1 / 2+3 / 2 N+3 , it is marked as the first state;

[0141] If the input signal is less than 1 / 2-3 / 2 N+3 , it is marked as the second state;

[0142] If the input signal is between 1 / 2-3 / 2 N+3 and 1 / 2+3 / 2 N+3 , it means that the preliminary interval of the input signal has been found, and the next approximation will not be performed, and according to the specific range of the input signal, the preliminary interval is further subdivided into the third state, the fourth state and the fifth state in the preliminary interval;

[0143] If the input signal is between 1 / 2+1 / 2 N+3 and 1 / 2+3 / 2 N+3 , it is marked as the third state;

[0144] If the input signal is between 1 / 2-3 / 2 N+3 and 1 / 2-1 / 2 N+3 , it is marked as the fourth state,

[0145] If the input signal is between 1 / 2±1 / 2 N+3 , it is marked as the fifth state;

[0146] If the approximation result is the first state or the second state, the next approximation is performed, and step (2) is continued.

[0147] Step (2), second successive approximation is performed according to the state of the first successive approximation; if the first successive approximation result is the first state, the input signal is compared with 3 / 4±3 / 2 N+3 and 3 / 4±1 / 2 N+3 interval, one of the five approximation states is generated;

[0148] If the first successive approximation result is the second state, the input signal is compared with 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 interval, one of the five approximation states is generated;

[0149] If the successive approximation is the third state, the fourth state or the fifth state, it indicates that the signal interval has been found, and the approximation process is ended; if the successive approximation is the first state or the second state, the next approximation is continued, and step (3) is entered.

[0150] Step (3), the above approximation process is repeated by analogy, until the Nth successive approximation is completed; if the third state, the fourth state or the fifth state is generated in the comparison process of a certain successive approximation, it indicates that the signal interval is determined, and the approximation process is ended.

[0151] Specifically, based on the aforementioned five-state comparator with metastable state detection and correction, further, the application provides a five-state quantization successive approximation method which can be applied in N-bit successive approximation ADC, the method can accurately quantize the analog input signal in the full range of 0 to 1, and effectively identify and process metastable state, including the following steps:

[0152] Step 100, in the first approximation, the input signal is compared with 1 / 2 of the quantization reference value:

[0153] If the input signal is greater than 1 / 2 plus an offset adjusted according to N (specifically 3 / 2 N+3 ), it is marked as state one; if the signal is less than 1 / 2-3 / 2 N+3 interval, it is marked as state two; if the signal is between 1 / 2 plus the offset and 1 / 2, i.e. the signal is in the interval of 1 / 2±3 / 2 N+3 interval, it indicates that the interval of the signal has been found, and the next approximation is not performed, in this interval, according to the specific range of the signal, it is further subdivided into state three, state four and state five. At this time, if the input signal is greater than 1 / 2+1 / 2 N+3 and less than 1 / 2+3 / 2 N+3 , it is marked as state three, at this time, if the input signal is greater than 1 / 2-3 / 2N+3 and less than 1 / 2-1 / 2 N+3 If the input signal is in the interval of 1 / 2±1 / 2, then it is marked as state four, and if the input signal is in the interval of 1 / 2±1 / 2, then it is marked as state five. N+3 If the input signal is in the interval of 1 / 2±1 / 2, then it is marked as state four, and if the input signal is in the interval of 1 / 2±1 / 2, then it is marked as state five.

[0154] If the approximation result is state one or state two, the next approximation is performed, and the process returns to step 200.

[0155] Step 200: The second successive approximation is performed according to the state of the first successive approximation. If the result of the first successive approximation is state one, the signal is compared with the two boundary values of 3 / 4±3 / 2, i.e. 3 / 4 plus and minus the offset value. N+3 and 3 / 4±1 / 2 N+3 The interval comparison produces one of the five possible approximation states. If the result of the first successive approximation is state two, the signal continues to be compared with the interval of 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 The interval comparison produces one of the five possible approximation states. If the result of the successive approximation is state three, state four or state five, it indicates that the signal interval has been found, and the approximation process ends. If the result of the successive approximation is state one or state two, the next approximation is continued.

[0156] Step 300: The approximation process is repeated in this way until the Nth successive approximation is completed. If the result of the comparison process of a certain successive approximation is state three, state four or state five, it indicates that the signal interval has been determined, and the approximation process ends.

[0157] In some embodiments, when the i-th conversion does not occur in a metastable state, i is an integer greater than or equal to 2 and less than or equal to N, then the three-bit binary quantization result D(i) of the final output of the bit conversion is equal to DOUT(i);

[0158] If the i-th conversion occurs in a metastable state, then the quantization result D(i) of the current bit and the quantization result D(2) of the next lower bit are both equal to 010, and the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by the comparison of the current bit;

[0159] Finally, the high-bit quantization result is shifted left by two bits, and then added to the low-bit digital result. N times of conversion obtains N groups of three-bit binary quantization results, which are added by 2 bits to obtain (N+2) valid quantization bits.

[0160] The above method can produce 2 N+2- Three different quantization results; for input signal in the range of 0 to 1, it provides more refined quantization mapping. For input signal in the range of 0 to 1, its corresponding digital mapping is 000…000, 000…001, …, 111…100 (N+2-bit binary output) in turn, and the corresponding digital output is (N+2)-bit binary code, and its quantization signal-to-noise ratio is 20*log(2 N+2 -3), close to the quantization signal-to-noise ratio (20*log(2 N+2 )) of N+2-bit two-state successive approximation, so as to process the metastable state while realizing higher precision and higher speed analog-to-digital conversion.

[0161] In some embodiments, the above method is further illustrated by taking N=2 as an example, as shown in Figure 4 Figure 5 The five-state quantization successive approximation method proposed in this application and the traditional two-state quantization successive approximation method when N=2, i.e., the mathematical form diagram of the two approximation processes. It can be seen that the traditional two-state quantization successive approximation method needs to strictly use a single reference quantization line for approximation in each conversion, i.e., 1 / 2, 1 / 4 and 3 / 4, and needs to complete complete 2 times of successive approximation, and a total of 00, 01, 10, 11, 4 kinds of comparison results are generated. The five-state quantization successive approximation method proposed in this application approximates the interval of the reference quantization line, and finds the signal interval when the reference quantization line 1 / 16 is approximated, without the need for the next approximation, and a total of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 13 kinds of comparison results are generated.

[0162] As Figure 6 ​As shown, it is a working flow chart of the five-state SAR ADC of the embodiment of the application. For the five-state SAR ADC of N bits, after sampling, comparison is started. In the kth comparison, whether the comparator has metastability is judged according to whether the comparison time tcomp is greater than the metastability detection time tw. If tcomp is less than tw, the comparison does not have metastability, MD(k) is 0, TP(k) is not equal to TN(k), TP(k) and TN(k) are not set, and TP(k) and TN(k) are the corresponding comparison results. If tcomp is greater than tw, the next comparison is not performed, MD(k) is 1, whether the metastability of the comparator is strong metastability is further judged according to whether the comparison time tcomp is greater than the strong metastability detection time ts. If tcomp is greater than tw and less than ts, the metastability of the comparison is weak metastability, the next comparison is not performed, TP(k) is not equal to TN(k), TP(k) and TN(k) are not set, and TP(k) and TN(k) are the corresponding comparison results. If tcomp is greater than tw and greater than ts, the metastability of the comparison is strong metastability, the next comparison is not performed, TP(k) and TN(k) are set, and TP(k) and TN(k) are both set to 1.

[0163] For the digital output encoding of the five-state SAR ADC of the embodiment of the application, a new combination logic circuit is adopted. The three-bit binary digital result DOUT(k) obtained by the kth conversion is D(k) = (DP(k) + DN(k) NOT) & (DP(k) + DN(k) NOT) & MD(k) NOT + MD(k). If the i th conversion does not have metastability, i is an integer greater than or equal to 2 and less than or equal to N, the three-bit binary quantization result D(i) of the bit conversion finally output is equal to DOUT(i); if the i th conversion has metastability, the quantization result D(i) of the current bit to the quantization result D(2) of the next lower bit are all equal to 010, and the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by the comparison of the current bit. Finally, the high-bit quantization result is moved left by two bits, and then added with the low-bit digital result. N times of conversion obtain N groups of three-bit binary quantization results, and after adding by 2 bits, (N+2) bits of effective quantization bits are obtained.

[0164] To further verify the technical effect of the present application, as another embodiment, the inventors made the following experiment. In a 40nm CMOS process, a 7-bit SAR ADC with a 600MHz sampling rate was designed, and the same simulation experiment was performed on the traditional two-state comparator and two-state quantization circuit and the five-state comparator with metastable state detection correction and five-state quantization circuit according to the present application. The same simulation conditions, the same part of the tube such as the input / output tube, the same size, and the same load capacitor were used. The simulation results of the two structures are shown in Figure 7 and Figure 6 . It can be known from Figure 7 that the signal to noise and distortion ratio (SNDR) of the traditional two-state comparator and two-state quantization circuit is 39.65dB, and the spurious free dynamic range (SFDR) is 53.79dB; it can be known from ​ that after using the five-state comparator and five-state quantization circuit according to the present application, the SNDR is 53.90dB, and the SFDR is 72.06dB. It can be seen that after using the present application, the SNDR is improved by 14.25dB, which shows that this technology can suppress metastable state while reducing the influence of comparator noise performance, and effectively quantize and encode using metastable state information, improving nearly 2-bit quantization accuracy.

[0165] It can be known from the above embodiment that, compared with the prior art, the present application can overcome the problem that the conventional comparator in the prior art can usually only get two output results in one comparison, and when the continuous signal of the analog input approaches 1 / 2, 1 / 4, and other halved reference quantization lines, the output decision time of the comparator will be significantly prolonged, resulting in a longer conversion time of the ADC. The present application includes but is not limited to the following beneficial effects:

[0166] Firstly, the present application overcomes the shortcomings that the comparator in the existing successive approximation type analog-digital converter cannot obtain reliable logic results due to metastable state, and the comparison speed and accuracy are limited. The present application overcomes the problem that the quantization of the existing successive approximation type analog-digital converter can only be inefficient two-state quantization because the comparator output has only two states;

[0167] Secondly, the application sets two metastable state detection boundary values of 1 / 8LSB and 3 / 8LSB, and divides the metastable state region of the comparator into strong metastable state and weak metastable state, the strong metastable state occurs when the differential input of the comparator is less than 1 / 8LSB, the weak metastable state occurs when the differential input of the comparator is between 1 / 8LSB and 3 / 8LSB, and no metastable state occurs when the differential input of the comparator is greater than 3 / 8LSB, compared with the traditional two-state comparator, the application has five kinds of effective output results each time, and can suppress metastable state and improve precision by using metastable state information.

[0168] Thirdly, the five-state comparator of the application adopts a full differential structure, can directly detect the metastable state of both ends of the comparator output without passing through an XOR gate, and can directly set the voltage of both ends of the comparator output after detecting the strong metastable state, without setting the voltage of both ends of the comparator output through combination logic and flip-flop, the metastable state detection correction circuit of the application is faster and more accurate.

[0169] Fourthly, the application sets the output of both ends of the comparator to the reset state of 11 by using two same NMOS tubes when the strong metastable state occurs, while the traditional scheme sets the output of both ends of the comparator to the reset state of 10 by using one NMOS and one PMOS, which is an invalid output result, the application encodes the output of the comparator after the metastable state and the metastable state identification bit as an effective comparison result by a new simple logic circuit, and overcomes the disadvantage of the traditional two-state comparator that needs to wait for a long comparison decision time when the differential input is very small, and can correct the metastable state detection while not introducing additional offset voltage and improving the precision of the comparator.

[0170] Fifthly, the application proposes a new simple logic circuit composed of a low-cost conventional adder, an inverter and an AND gate, which can obtain the binary effective digital output DOUT=(TP+TN non)+(TP+TN non)&MD non+MD of the comparator by logic combination of the comparison output signal TP, TN and the metastable state identification bit MD, and can realize five kinds of effective digital output in one comparison, while the conventional comparator has the digital output DOUT=DP or DN non, and DN and DN non are inverse to each other. The application can also encode the comparison result after the metastable state of the comparator as an effective digital output result, corresponding to the small input differential voltage of the comparator.

[0171] Sixth, the five-state quantization successive approximation method proposed in the application can greatly improve the quantization efficiency compared with the traditional two-state quantization successive approximation method. Once quantization has five different effective quantization results, which can accurately quantize the analog input signal in the full range of 0 to 1 and effectively identify and process metastable states. If the input differential signal size is within 3 / 8 quantization accuracy during the comparison process of each successive approximation, it indicates that the signal interval has been determined, and the approximation process is over. N-bit quantization has (2N+2-3) quantization results, which can improve the quantization accuracy by nearly 2 bits compared with the traditional two-state quantization.

[0172] The above only describes some embodiments of the application. It should be pointed out that for ordinary skilled persons in the technical field, some improvements and refinements can be made without departing from the principles of the application, and these improvements and refinements should also be considered as the protection scope of the application.

Claims

1. A five-state comparator with metastable detection and correction, characterized in that, include: The preamplifier circuit is used to preamplify the input differential signal and output the signal to the subsequent latch circuit. The subsequent latch circuit uses multiple MOSFETs to latch and output the comparison result of the comparator; A strong metastable state detection and setting circuit is used to detect whether the comparator is in a strong metastable state and to set the output of the comparator. If a strong metastable state is detected, a strong metastable state flag bit is generated. Metastability detection circuit, which is used to detect and identify whether the comparator is in a metastable state; if a metastable state is detected, a metastable flag bit is generated. A clock circuit is used to generate clock signals corresponding to the comparator's operating clock, metastable detection clock, and strongly metastable detection clock. An encoding circuit is used to combine the output of the comparator with the metastable flag bit to output a digital output result.

2. A five-state comparator with metastable detection and correction according to claim 1, characterized in that, The preamplifier circuit includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET. The gates of the first MOSFET and the second MOSFET are connected to the positive input signal VIP and the negative input signal VIN, respectively. The sources of the first MOSFET and the second MOSFET are connected to ground. The drain of the first MOSFET is connected to the third MOSFET, and the drain of the second MOSFET is connected to the fourth MOSFET. The gates of the third and fourth MOS transistors, and the gates of the fifth and sixth MOS transistors are all connected to the comparator clock signal CLKC; The drain of the third MOS transistor is connected to the fifth MOS transistor, the drain of the fourth MOS transistor is connected to the sixth MOS transistor, and the sources of the fifth and sixth MOS transistors are connected to the power supply voltage.

3. A five-state comparator with metastable detection and correction according to claim 1, characterized in that, The subsequent latching circuit includes a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, and a twenty-second MOSFET; The gates of the seventh MOS transistor and the eighth MOS transistor are respectively connected to the third MOS transistor and the fourth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor, and the fifteenth MOS transistor and the sixteenth MOS transistor; The sources of the seventh and eighth MOS transistors are connected to the power supply voltage together with the nineteenth and twentieth MOS transistors. The drain of the seventh MOS transistor is connected to the ninth MOS transistor and the fifteenth MOS transistor, respectively; the drain of the eighth MOS transistor is connected to the tenth MOS transistor and the sixteenth MOS transistor, respectively. The gate of the ninth MOS transistor is connected to the eleventh MOS transistor, the twelfth MOS transistor, and the fourteenth MOS transistor; The gate of the tenth MOS transistor is connected to the eleventh MOS transistor, the twelfth MOS transistor, and the thirteenth MOS transistor; The drain of the ninth MOS transistor is connected to the nineteenth and twenty-first MOS transistors, and the drain of the tenth MOS transistor is connected to the twentieth and twenty-second MOS transistors. The sources of the eleventh, twelfth, thirteenth, fourteenth, fifteenth, nineteenth, twentieth, twenty-first, and twenty-second MOS transistors are all connected to ground.

4. A five-state comparator with metastable detection and correction according to claim 1, characterized in that, The strong metastability detection and setting circuit includes the seventeenth MOSFET, the eighteenth MOSFET, the twenty-third MOSFET, the twenty-fourth MOSFET, the twenty-fifth MOSFET, the twenty-sixth MOSFET, the twenty-seventh MOSFET, the twenty-eighth MOSFET, the twenty-ninth MOSFET, the thirtieth MOSFET, the thirty-first MOSFET, the thirty-second MOSFET, the thirty-third MOSFET, the thirty-fourth MOSFET, the thirty-fifth MOSFET, and the thirty-sixth MOSFET. The strong metastability flag includes the P-terminal strong metastability flag MD_sp and the N-terminal strong metastability flag MD_sn. The drain of the seventeenth MOS transistor is connected to the twenty-first MOS transistor, and the drain of the eighteenth MOS transistor is connected to the twenty-second MOS transistor. The gate of the seventeenth MOS transistor is connected to the twenty-ninth MOS transistor, the thirty-first MOS transistor, the thirty-third MOS transistor, and the thirty-fifth MOS transistor, and the gate of the eighteenth MOS transistor is connected to the thirtieth MOS transistor, the thirty-second MOS transistor, the thirty-fourth MOS transistor, and the thirty-sixth MOS transistor; The sources of the seventeenth and eighteenth MOS transistors are connected to ground together with the twenty-seventh, twenty-eighth, thirty-first, thirty-second, thirty-fifth, and thirty-sixth MOS transistors. The gate of the 27th MOSFET is connected to the 19th and 21st MOSFETs, and the gate of the 28th MOSFET is connected to the 20th and 22nd MOSFETs. The drain of the 27th MOSFET is connected to the 25th MOSFET, and the 28th MOSFET is connected to the 26th MOSFET; The gates of the 25th and 26th MOSFETs are connected together to the strongly metastable detection clock CLKCD_s; The drain of the 25th MOSFET is connected to the 23rd MOSFET, the 29th MOSFET, the 31st MOSFET, the 33rd MOSFET, and the 35th MOSFET; The drain of the 26th MOSFET is connected to the 24th MOSFET, the 30th MOSFET, the 32nd MOSFET, the 34th MOSFET, and the 36th MOSFET; The gates of the 23rd and 24th MOSFETs are connected to the comparator clock signal CLKC, and the sources of the 23rd and 24th MOSFETs are connected to the power supply voltage along with the 29th, 30th, 33rd, and 34th MOSFETs.

5. A five-state comparator with metastable detection and correction according to claim 1, characterized in that, The metastable detection circuit includes the 37th MOS transistor, the 38th MOS transistor, the 39th MOS transistor, the 40th MOS transistor, the 41st MOS transistor, the 42nd MOS transistor, the 43rd MOS transistor, the 44th MOS transistor, the 45th MOS transistor, the 46th MOS transistor, the 47th MOS transistor, the 48th MOS transistor, the 49th MOS transistor, and the 50th MOS transistor, wherein the metastable flag includes a P-terminal metastable flag MD_p and an N-terminal metastable flag MD_n; The gate of the forty-first MOS transistor is connected to the nineteenth MOS transistor and the twenty-first MOS transistor, and the forty-second MOS transistor is connected to the twentieth MOS transistor and the twenty-second MOS transistor. The drain of the forty-first MOS transistor is connected to the thirty-ninth MOS transistor, and the drain of the forty-second MOS transistor is connected to the fortieth MOS transistor. The gates of the thirty-ninth MOS transistor and the fortieth MOS transistor are connected together to the metastable detection clock CLKCD; the drain of the thirty-ninth MOS transistor is connected to the thirty-seventh MOS transistor, the forty-third MOS transistor, the forty-fifth MOS transistor, the forty-seventh MOS transistor, and the forty-ninth MOS transistor; the drain of the fortieth MOS transistor is connected to the thirty-eighth MOS transistor, the forty-fourth MOS transistor, the forty-sixth MOS transistor, the forty-eighth MOS transistor, and the fiftieth MOS transistor. The gates of the 37th and 38th MOS transistors are connected to the comparator clock signal CLKC, and the sources of the 37th and 38th MOS transistors are connected to the power supply voltage along with the 43rd, 44th, 47th, and 48th MOS transistors. The drain of the forty-fifth MOS transistor is connected to the forty-third MOS transistor, the forty-seventh MOS transistor, and the forty-ninth MOS transistor, and the drain of the forty-sixth MOS transistor is connected to the forty-fourth MOS transistor, the forty-eighth MOS transistor, and the fiftieth MOS transistor; The sources of the forty-fifth and forty-sixth MOS transistors are connected to ground together with the forty-first, forty-second, forty-ninth, and fiftieth MOS transistors.

6. A five-state comparator with metastable detection and correction according to any one of claims 1 to 5, characterized in that, The clock circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first delay unit DLY1, a second delay unit DLY2, and a first D flip-flop. The input of the first AND gate AND1 is connected to the output of the strong metastability detection and set circuit. The output of the strong metastability detection and set circuit includes a P-terminal strong metastability flag MD_sp and an N-terminal strong metastability flag MD_sn. The output is connected to the clock signal terminal of the first D flip-flop. The D-terminal input of the first D flip-flop is grounded. The reset terminal of the first D flip-flop is connected to the start clock EN, and its output is the strong metastability flag MD_s. When EN is 1, its output MD_s is 1; MD_s is connected to the input of the second AND gate AND2 together with the clock CLK, and the output of the second AND gate AND2 is connected to the comparison clock signal CLKC; the comparison clock signal CLKC is connected to the input of the first delay unit DLY1 and the second delay unit DLY2, and its outputs are the metastable detection clock CLKCD and the strong metastable detection clock CLKCD_s, respectively; The input of the third AND gate AND3 is connected to the output of the metastable detection circuit. The output of the metastable detection circuit includes a P-terminal metastable flag MD_p and an N-terminal metastable flag MD_n, and the output is connected to the metastable flag MD.

7. A five-state comparator with metastable detection and correction according to any one of claims 1 to 5, characterized in that, The input of the encoding circuit is connected to the output of the subsequent latch circuit and the metastable flag bit MD in the clock circuit. The output of the subsequent latch circuit includes a P-terminal comparison output TP and an N-terminal comparison output TN. The output is a three-bit binary number, with DOUT1, DOUT2 and DOUT3 from least significant bit to most significant bit. DOUT1 represents the least significant bit, DOUT2 represents the second least significant bit, and DOUT3 represents the most significant bit. DOUT = (TP + TN NOT) + (TP + TN NOT) & MD NOT + MD.

8. A five-state quantization successive approximation method, applied to a five-state comparator with metastable state detection and correction as described in any one of claims 1 to 7, characterized in that, include: Step (1): During the first approximation, compare the input signal with half of the quantization reference value. If the input signal is greater than 1 / 2 + 3 / 2... N+3 If so, then it is marked as the first state; If the input signal is less than 1 / 2-3 / 2 N+3 If so, it is marked as the second state; If the input signal is in the range of 1 / 2-3 / 2 N+3 To 1 / 2 + 3 / 2 N+3 If the range is between 1 and 2, it means that the initial range of the input signal has been found and no further approximation will be performed. Within the initial range, the range of the input signal is further subdivided into the third state, the fourth state, and the fifth state. Wherein, if the input signal is in 1 / 2+1 / 2 N+3 To 1 / 2 + 3 / 2 N+3 Between these states, it is marked as the third state; If the input signal is between 1 / 2 and 3 / 2 N+3 To 1 / 2-1 / 2 N+3 Between these states, it is marked as the fourth state. If the input signal is within 1 / 2 ± 1 / 2 N+3 If so, it is marked as the fifth state; If the approximation result is the first state or the second state, then proceed to the next approximation and continue to execute step (2); Step (2): Perform a second successive approximation based on the state of the first successive approximation; if the result of the first successive approximation is the first state, then the input signal is compared with 3 / 4 ± 3 / 2. N+3 and 3 / 4±1 / 2 N+3 Interval comparisons yield one of five approximation states; If the result of the first successive approximation is the second state, then the input signal and 1 / 4 ± 3 / 2 N+3 With 1 / 4 ± 1 / 2 N+3 Interval comparison yields one of five approximation states; If the successive approximation results in the third, fourth, or fifth state, it indicates that the signal interval has been found and the approximation process ends; if the successive approximation results in the first or second state, the next approximation continues and the process proceeds to step (3). Step (3): Repeat the above approximation process until the Nth successive approximation is completed. If the signal range is determined in the third, fourth or fifth state during a certain successive approximation comparison process, the approximation process ends.

9. The five-state quantization successive approximation method according to claim 8, characterized in that, include: If no metastability occurs during the i-th conversion, i is an integer greater than or equal to 2 and less than or equal to N. Then, the final three-bit binary quantization result D(i) of the bit conversion is equal to DOUT(i). If metastability occurs during the i-th conversion, the quantization result D(i) of the current bit to the quantization result D(2) of the next lowest bit are all equal to 010, while the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by comparing the current bit. Finally, shift the high-order quantization result two bits to the left and add it to the low-order result. After N conversions, N sets of three-bit binary quantization results are obtained. After adding them with a 2-bit shift, (N+2) valid quantization bits are obtained.

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