Memory and method for manufacturing the same, electronic device

Abstract

Embodiments of the present application provide a memory and a manufacturing method thereof, and an electronic device. The memory comprises a substrate and a plurality of memory cells, the memory cell comprising a transistor, the transistor comprising a gate electrode, a gate insulating layer, a channel region and two first protection structures. The gate insulating layer and the channel region are sequentially arranged at the outer periphery of the gate electrode; the gate insulating layer and the gate electrode both extend along a first direction perpendicular to the substrate; the first protection structure is arranged on at least one side of the channel region along a second direction, the second direction being parallel to the substrate; and the etching rate of the material of the channel region is greater than the etching rate of the material of the first protection structure. The channel region and the first protection structure can form a relatively obvious etching selectivity ratio, and the first protection structure can protect the channel region when etching the parasitic channel region, which is conducive to improving the performance stability of the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a memory and its manufacturing method, and an electronic device. Background Technology

[0002] In current memory technologies, the demand for memory density is constantly increasing. To improve integration capabilities and reduce cell area, enabling the fabrication of more memory cells within the same chip area, the size of memory cells needs to be continuously miniaturized with technological advancements. However, as memory density increases and the size of individual memory cells decreases, more problems are also likely to arise. Summary of the Invention

[0003] This application discloses a memory, a method for manufacturing the same, and an electronic device.

[0004] In a first aspect, some embodiments of this application provide a memory comprising: a substrate and a plurality of memory cells, each memory cell including a transistor, the transistor comprising:

[0005] The system comprises a gate electrode, a gate insulating layer, and a channel region, wherein the gate insulating layer and the channel region are sequentially disposed on the outer periphery of the gate electrode; both the gate insulating layer and the gate electrode extend along a first direction perpendicular to the substrate.

[0006] A first protective structure is disposed on at least one side of the channel region along a second direction, the second direction being parallel to the substrate; the etching rate of the material in the channel region is greater than the etching rate of the material in the first protective structure.

[0007] Secondly, some embodiments of this application provide an electronic device, including: the memory of the first aspect.

[0008] Thirdly, some embodiments of this application provide a method for manufacturing a memory, including:

[0009] A first storage structure with multiple phase-insulating arrays is fabricated on one side of a substrate. The first storage structure includes multiple first trenches arranged in an array in a plane parallel to the substrate and multiple first sacrificial layers spaced apart along a first direction perpendicular to the substrate around the outer periphery of the first trenches, and a first protective structure disposed on at least one side of the first trenches along a second direction parallel to the substrate.

[0010] Laterally etch the first sacrificial structure through the first trench to remove part of the first sacrificial structure, forming a second sacrificial structure, and forming a second trench from the first trench;

[0011] A semiconductor layer, a gate insulating layer, and a word line are sequentially conformally fabricated within the second trench, with the word line filling the second trench.

[0012] Remove the second sacrificial structure to expose a portion of the semiconductor layer; using the first protective structure as a mask, remove the exposed semiconductor layer, and the remaining semiconductor layer forms a channel region. The etching rate of the material in the channel region is greater than the etching rate of the material in the first protective structure.

[0013] The beneficial technical effects of the technical solutions provided in some embodiments of this application include:

[0014] If the etching rate of the material in the first protective structure outside the channel region is less than that of the material in the channel region, then the channel region and the first protective structure can form a more obvious etching selectivity, which is beneficial for protecting the channel region when removing the semiconductor layer connecting the channel region.

[0015] For the fabrication of multilayered memory, the first protective structure protects the channel region, preventing damage caused by the different etching rates at the top and bottom due to the reduced etchant concentration at the bottom. In other words, even if the etchant concentration at the bottom of the trench is lower than that at the top, when the etchant at the bottom removes the parasitic channel region of the parasitic transistor at the bottom, the channel regions of other (non-parasitic) transistors are still covered by the first protective structure and are not damaged by the etchant. This is beneficial for improving the structural integrity of the transistors and enhancing the structural stability of the multilayered memory. Moreover, it can improve the removal rate of the channel region of parasitic transistors, reduce the impact of parasitic transistors, and ensure or improve the performance of the transistors.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0017] Figure 1 A schematic cross-sectional view of a memory provided for some embodiments of this application, perpendicular to the substrate and parallel to both a first direction and a third direction;

[0018] Figure 2 A schematic cross-sectional view of a memory provided for some embodiments of this application, perpendicular to the substrate and parallel to both the first and second directions;

[0019] Figure 3 A top view schematic diagram of a memory provided for some embodiments of this application;

[0020] Figure 4 for Figure 3 A schematic diagram of a cross-section perpendicular to the substrate at point AA in the middle;

[0021] Figure 5 for Figure 3 A schematic diagram of a cross-section perpendicular to the substrate at point BB;

[0022] Figure 6 for Figure 3 A schematic diagram of a cross-section perpendicular to the substrate at the C-junction.

[0023] Figure 7 for Figure 3 A schematic diagram of a cross-section perpendicular to the substrate at point DD;

[0024] Figure 8 A schematic flowchart illustrating a method for manufacturing a memory according to some embodiments of this application;

[0025] Figure 9 This is a schematic flowchart illustrating a method for manufacturing a memory in some embodiments of this application, in which a first memory structure with multiple phase-insulated arrays is fabricated on one side of a substrate.

[0026] Figures 10 to 75 This is a schematic cross-sectional view perpendicular to the substrate obtained from each step of a method for manufacturing a memory according to some embodiments of this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 1-Substrate; 11-Gate electrode; 12-Gate insulating layer; 13-Channel region; 14-First protective structure; 15-Source; 16-Drain; 17-Third insulating layer;

[0029] 2-Memory structure; 21-Word line; 211-Connection line; 22-Bit line;

[0030] 31-First trench; 32-Second trench; 33-First sacrificial layer; 34-Second sacrificial structure; 35-Semiconductor layer; 36-Blank area; 37-Fourth trench; 38-Fifth trench; 39-Sixth trench;

[0031] 41-First insulating layer; 42-Replacement layer; 43-First character slot; 44-Second character slot; 45-Sacrificial character line; 451-First sacrificial layer; 46-First dielectric layer; 47-Second dielectric layer; 48-Third dielectric layer;

[0032] 51-First isolation trench; 52-Second isolation trench; 53-First isolation layer;

[0033] 61-Replacement groove; 62-Initial metal layer; 63-Transition metal layer / first capacitor electrode; 64-Metal layer; 65-Third trench; 66-Second isolation layer; 67-Second insulating layer; 68-Third letter groove; 69-Fourth letter groove;

[0034] 71 - Third isolation layer;

[0035] 81-Capacitor trench;

[0036] 91-Capacitor insulating layer; 92-First electrode layer; 93-Series structure. Detailed Implementation

[0037] Some embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions used to explain the technical solutions of some embodiments of this application, and do not constitute a limitation on the technical solutions of some embodiments of this application.

[0038] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0040] The technical solutions of this application and how they solve the aforementioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, learned from, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0041] Some embodiments of this application provide a memory, which includes a substrate 1 and a plurality of memory cells. Each memory cell includes a transistor, and a schematic diagram of the transistor structure is shown below. Figure 1 and Figure 2 As shown. The transistor includes: a gate electrode 11, a gate insulating layer 12, a channel region 13, and two first protective structures 14.

[0042] The gate insulating layer 12 and the channel region 13 are sequentially disposed on the outer periphery of the gate electrode 11; both the gate insulating layer 12 and the gate electrode 11 extend along a first direction perpendicular to the substrate 1.

[0043] The first protective structure 14 is disposed on at least one side of the channel region 13 along a second direction, the second direction being parallel to the substrate 1; the etching rate of the material in the channel region 13 is greater than the etching rate of the material in the first protective structure 14.

[0044] In some embodiments of this application, the etching rate of the material of the first protective structure 14 outside the channel region 13 is less than the etching rate of the material of the channel region 13, which can protect the channel region 13 when the semiconductor layer 53 connecting the channel region 13 (parasitic channel region) is removed.

[0045] For the fabrication of multilayered memory, the first protective structure 14 protects the channel region 13, preventing damage to the channel region 13 due to the difference in etching rates between the top and bottom caused by the decrease in etchant concentration from the top to the bottom. In other words, even if the etchant concentration at the bottom of the trench is lower than that at the top, when the etchant at the bottom removes the parasitic channel region of the parasitic transistor at the bottom, the channel regions of other (non-parasitic) transistors are still covered by the first protective structure and are not damaged by the etchant. This is beneficial to improving the structural integrity of the transistors and enhancing the structural stability of the multilayered memory. Moreover, it can improve the removal rate of the channel region of parasitic transistors, reduce the influence of parasitic transistors, and ensure or improve the performance of the transistors.

[0046] It should be noted that the first protective structure 14 may be provided only on one side of the trench area 13 along the second direction; or, the first protective structure 14 may be provided on both sides of the trench area 13 along the second direction.

[0047] Optionally, the material of the channel region 13 includes metal oxides, and the material of the first protective structure 14 includes nitrides.

[0048] In some embodiments of this application, the first protective structure 14 containing nitrides forms a more significant etching selectivity with the channel region 13 containing metal oxides, thereby avoiding damage to the top channel region 13 when etching the parasitic channel region at the bottom, which can improve the stability and process stability of the memory including the transistor stack.

[0049] Specifically, the material of the channel region 13 can be IGZO (indium gallium zinc oxide), and the material of the first protective structure 14 can be silicon nitride.

[0050] In some embodiments, the material of the metal oxide semiconductor layer or channel region may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0051] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is small, which can improve the performance of dynamic memory.

[0052] The above-mentioned materials for metal oxide semiconductor layers or channel regions only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0053] Optionally, refer to Figure 1 The transistor also includes a source 15 and a drain 16, which are respectively disposed on opposite sides of the channel region 13 along a third direction; the third direction is parallel to the substrate 1 and intersects with the second direction.

[0054] In some embodiments of this application, the channel region 13 is disposed along a first direction perpendicular to the substrate 1, and the source 15 and drain 16 are disposed along a third direction parallel to the substrate 1.

[0055] Optionally, refer to Figure 2 In a cross-section parallel to both the first and second directions, the channel area 13 contacts the first protective structure 14 on at least one side along the second direction.

[0056] And / or, see reference Figure 1 In a cross-section parallel to both the first and third directions, the channel region 13 contacts the source electrode 15 and the drain electrode 16 on both sides along the third direction.

[0057] In some embodiments of this application, because the first protective structure 14, the source 15, and the drain 16 protect the channel region 13, the channel region 13 will not be damaged when etching the semiconductor layer 53 connecting the channel region 13. Moreover, because the channel region 13 is located further inside than the semiconductor layer 53 connecting the channel region 13, the channel region 13 is protected to a greater extent during the removal of the semiconductor layer 53 connecting the channel region 13.

[0058] Optionally, refer to Figure 2 The first protective structure 14 has a bottom surface close to the substrate 1 and a top surface away from the substrate 1, as well as a side surface between the top surface and the bottom surface; the channel region 13 is in contact with the top surface, bottom surface and side surface of the first protective structure 14.

[0059] In some embodiments of this application, the channel area 14 is in contact with the top surface, bottom surface and side surface of the first protective structure 14, so that the first protective structure 14 can further protect the channel area 14.

[0060] Optionally, refer to Figure 3 and Figure 4 Multiple transistors are stacked along a first direction perpendicular to substrate 1 and arranged in an array in a plane parallel to substrate 1.

[0061] The drain 16 has a bottom surface close to the substrate 1 and a top surface away from the substrate 1, as well as a side surface between the top and bottom surfaces. The channel region 13 is in contact with the top, bottom and side surfaces of the drain 16.

[0062] In some embodiments of this application, the channel region 13 is in contact with the top, bottom and side surfaces of the drain electrode 16, so the drain electrode 16 can further protect the channel region 14.

[0063] Optionally, the source 15 has a bottom surface near the substrate 1 and a top surface away from the substrate 1, as well as a side surface between the top and bottom surfaces. The channel region 13 is in contact with the top, bottom, and side surfaces of the source 15.

[0064] In some embodiments of this application, the channel region 13 is in contact with the top, bottom and side surfaces of the source electrode 15, so the source electrode 15 can further protect the channel region 14.

[0065] Optionally, refer to Figure 4 Along the first direction, the gate electrodes 11 of two adjacent transistors are connected by a connecting line 211 to form a word line 21.

[0066] Optionally, along the second direction, the width of the connecting line 211 is greater than the width of the gate electrode 11.

[0067] In some embodiments of this application, along the second direction, the width of the connecting line 211 is greater than the width of the gate electrode 11, which allows the parasitic channel region to be further out than the channel region 13, thus helping to protect the channel region 13 when removing the parasitic channel region.

[0068] Optionally, refer to Figure 3 Along the third direction, a bit line 22 is provided between the drain 16 of one transistor and the drain 16 of another transistor in the same row, and the bit line 22 extends along the second direction.

[0069] In some embodiments of this application, two transistors share a single bit line 22, which enables the memory to be more integrated and helps to reduce the cell area.

[0070] Optionally, the memory also includes a capacitor structure disposed on the side of the source 15 away from the drain 16.

[0071] Optionally, the capacitor structure includes a second electrode layer sequentially disposed on one side of the source electrode 15, and a capacitor insulating layer 91, a first electrode layer 92, and a series structure 93 on the outer periphery of the second electrode layer. The second electrode layer can be a phase-separated structure with a different material from the source electrode 15, or it can be an integrally formed structure with the same material as the source electrode 15.

[0072] Based on the same inventive concept, some embodiments of this application provide an electronic device that includes the memory provided in the above embodiments.

[0073] In some embodiments of this application, since the electronic device uses any of the memory provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0074] Optionally, the electronic device may include a smartphone, computer, tablet, artificial intelligence device, wearable device, or smart mobile terminal.

[0075] It should be noted that electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the memory provided in the above-mentioned embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in some embodiments of this application.

[0076] Based on the same inventive concept, some embodiments of this application provide a method for manufacturing a memory, the flowchart of which is shown below. Figure 8 As shown, the method includes steps S1 to S4:

[0077] S1: A first storage structure with multiple phase-insulated arrays is fabricated on one side of substrate 1. The first storage structure includes multiple first trenches 31 arranged in an array in a plane parallel to substrate 1 and multiple first sacrificial layers 33 spaced apart along a first direction perpendicular to substrate 1 around the outer periphery of the first trenches 31. A first protective structure 14 is disposed on at least one side of the first trenches 31 along a second direction parallel to substrate 1.

[0078] In some embodiments of this application, Figure 64 A schematic cross-sectional view of point AA perpendicular to substrate 1 obtained after fabricating a first storage structure with multiple phase-insulated arrays on one side of substrate 1. Figure 65 A schematic cross-sectional view of the CC section perpendicular to the substrate 1 obtained after fabricating a first storage structure with multiple phase-insulated arrays on one side of the substrate 1.

[0079] S2: Laterally etch the first sacrificial structure 33 through the first trench 31 to remove part of the first sacrificial structure 33, forming the second sacrificial structure 34, and forming the second trench 32 from the first trench 31.

[0080] In some embodiments of this application, Figure 66 A schematic diagram of a cross section perpendicular to the substrate 1 at point AA after the second trench 32 is formed by laterally etching the first sacrificial structure 33 through the first trench 31 to remove part of the first sacrificial structure 33 and form the second sacrificial structure 34; Figure 67 The diagram shows a cross-sectional view of the first sacrificial structure 33 perpendicular to the substrate 1 obtained by laterally etching the first sacrificial structure 33 through the first trench 31 to remove part of the first sacrificial structure 33 and form the second sacrificial structure 34, and the second trench 32 formed by the first trench 31.

[0081] S3: Semiconductor layer 35, gate insulating layer 12 and word line 21 are sequentially conformally fabricated in the second trench 32.

[0082] In some embodiments of this application, Figure 68 A schematic diagram of a cross section perpendicular to the substrate 1 at point AA is obtained after the word line 21 fills the second trench 32, in which a semiconductor layer 35, a gate insulating layer 12 and a word line 21 are sequentially conformally fabricated in the second trench 32. Figure 69 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position obtained after the word line 21 fills the second trench 32, in which a semiconductor layer 35, a gate insulating layer 12, and a word line 21 are sequentially conformally fabricated in the second trench 32.

[0083] Optionally, after step S3 and before step S4, the manufacturing method further includes: along the second direction, removing the structure between two adjacent columns of the second sacrificial structure 34 to form a fourth groove 37.

[0084] In some embodiments of this application, Figure 70 A schematic diagram of a cross-section perpendicular to the substrate 1 at BB after removing the structure between two adjacent columns of the second sacrificial structure 34 along the second direction to form the fourth trench 37. Figure 71 This is a schematic cross-sectional view perpendicular to the substrate 1 at the CC position, obtained after removing the structure between two adjacent columns of the second sacrificial structures 34 along the second direction to form the fourth trench 37. (Reference) Figure 70 and Figure 71 The purpose of removing the structure between two adjacent columns of the second sacrificial structure 34 along the second direction is to expose the second sacrificial structure 34, so as to facilitate the subsequent removal of the second sacrificial structure 34.

[0085] S4: Remove the second sacrificial structure 34 to expose a portion of the semiconductor layer 35; using the first protective structure 14 as a mask, remove the exposed semiconductor layer 35, and the remaining semiconductor layer 35 forms a channel region 13. The etching rate of the material in the channel region 13 is greater than the etching rate of the material in the first protective structure 14.

[0086] In some embodiments of this application, Figure 72 A schematic diagram of a cross-section perpendicular to the substrate 1 at point AA after removing the second sacrificial structure 34 and exposing a portion of the semiconductor layer 35. Figure 73 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC region obtained after removing the second sacrificial structure 34 and exposing a portion of the semiconductor layer 35. Figure 74 A schematic diagram of a cross section perpendicular to the substrate 1 at point AA, obtained by removing the exposed semiconductor layer 35 using the first protective structure 14 as a mask, and the remaining semiconductor layer 35 forming the channel region 13. Figure 75 This is a cross-sectional view perpendicular to the substrate 1 at the CC region, obtained after removing the exposed semiconductor layer 35 using the first protective structure 14 as a mask, and the remaining semiconductor layer 35 forming the channel region 13. In this application, the etching rate of the material of the first protective structure 14 outside the channel region 13 is lower than that of the material of the channel region 13, which can protect the channel region 13 when removing the semiconductor layer 53 connecting the channel region 13. For the fabrication of stacked memory, because the first protective structure 14 protects the channel region 13, it can prevent damage to the channel region 13 due to the difference in etching rates between the top and bottom caused by the decrease in etchant concentration from the top to the bottom, which is beneficial to improving the structural stability of the stacked memory.

[0087] refer to Figure 73 After removing the second sacrificial structure 34, the fourth groove 37 forms the fifth groove 38. (See reference) Figure 75 After removing the exposed semiconductor layer 35, the fifth trench 38 forms the sixth trench 39.

[0088] Optionally, after step S4, the manufacturing method further includes: manufacturing a third insulating layer 17 within the sixth trench 39.

[0089] In some embodiments of this application, a schematic diagram of the structure obtained after fabricating the third insulating layer 17 within the sixth trench 39 is shown below. Figures 4 to 7 .

[0090] Optionally, prior to step S1, the manufacturing method further includes:

[0091] An alternating first insulating layer 41 and a replacement layer 42 are fabricated on one side of the substrate 1.

[0092] Each first insulating layer 41 and each replacement layer 42 are patterned to form a plurality of first word grooves 43 arranged in an array in a plane parallel to the substrate 1; each first insulating layer 41 is laterally etched through the first word grooves 43 to obtain a second word groove 44 formed by the first word grooves 43.

[0093] Sacrificial letter lines 45 are manufactured within the second letter line groove 44.

[0094] In some embodiments of this application, the width of the first word groove 44 along the second direction is a third width, and the width of the first word groove 44 along the third direction is a first width. The third width is less than the width of the subsequently manufactured gate electrode 11 along the second direction; specifically, the third width is 50% to 80% (including the two endpoint values) of the width of the gate electrode 11 along the second direction. The first width is less than the width of the subsequently manufactured gate electrode 11 along the third direction; specifically, the first width is 50% to 80% (including the two endpoint values) of the width of the gate electrode 11 along the third direction. After lateral etching of each first insulating layer 41, the width along the second direction between two adjacent first insulating layers 41 in the same layer of the second word groove 44 is a fourth width, and the width along the third direction between two adjacent first insulating layers 41 in the same layer of the second word groove 44 is a fifth width. The fourth width is greater than the width of the subsequently manufactured gate electrode 11 along the second direction, and the fifth width is greater than the width of the subsequently manufactured gate electrode 11 along the third direction. Specifically, the fourth width can be 120% to 140% of the width of the gate electrode 11 along the second direction (including the two endpoint values), and the fifth width can be 120% to 140% of the width of the gate electrode 11 along the third direction (including the two endpoint values).

[0095] Specifically, Figure 10 A schematic cross-sectional view perpendicular to substrate 1 at point AA, obtained after alternating first insulating layer 41 and replacement layer 42 are fabricated on one side of substrate 1. Figure 11 A schematic cross-sectional view of the BB section perpendicular to the substrate 1 after alternating first insulating layer 41 and replacement layer 42 are fabricated on one side of substrate 1. Figure 12A schematic cross-sectional view of the CC section perpendicular to the substrate 1 obtained after fabricating an alternating first insulating layer 41 and a replacement layer 42 on one side of the substrate 1. Figure 13 This is a schematic cross-sectional view of the DD section perpendicular to the substrate 1, obtained after fabricating an alternating first insulating layer 41 and a replacement layer 42 on one side of the substrate 1.

[0096] Figure 14 A schematic cross-sectional view perpendicular to the substrate 1 is obtained by patterning each first insulating layer 41 and each replacement layer 42 to form multiple first word grooves 43 arranged in an array in a plane parallel to the substrate 1. Figure 15 A schematic cross-sectional view perpendicular to the substrate 1 is obtained by patterning each first insulating layer 41 and each replacement layer 42 to form multiple first word grooves 43 arranged in an array in a plane parallel to the substrate 1.

[0097] Figure 16 A schematic diagram of a cross section perpendicular to the substrate 1 obtained by laterally etching each of the first insulating layers 41 through the first word groove 43 to obtain the second word groove 44 formed by the first word groove 43; Figure 17 A schematic diagram of a cross-section perpendicular to the substrate 1 obtained by laterally etching each of the first insulating layers 41 through the first word groove 43 to obtain the second word groove 44 formed by the first word groove 43.

[0098] Figure 18 A schematic diagram of a cross-section perpendicular to the substrate 1 at point AA obtained after manufacturing the sacrificial word line 45 in the second word line groove 44. Figure 19 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position obtained after manufacturing the sacrificial word line 45 in the second word line groove 44.

[0099] Optionally, after the sacrificial word line 45 is manufactured in the second word line slot 44, and before the first memory structure with a plurality of phase-insulated arrays arranged on one side of the substrate 1 is manufactured in step S1, the manufacturing method further includes:

[0100] The first insulating layer 41 and the replacement layer 42 are patterned to form an array of first storage structure regions, resulting in a first isolation trench 51 between adjacent first storage structure regions.

[0101] The first insulating layer 41 is laterally etched through the first isolation trench 51 to form the second isolation trench 52; the first isolation layer 53 is manufactured in the second isolation trench 52 to obtain the initial first storage structure with phase-insulated array arrangement.

[0102] In some embodiments of this application, the first isolation layer 53 can isolate two adjacent initial first storage structures to avoid signal crosstalk.

[0103] Figure 22A schematic diagram of a cross section perpendicular to the substrate 1 is obtained at point AA after patterning the entire substrate 1 to form an array of first memory structure regions and obtaining the first isolation trench 51 between adjacent first memory structure regions. Figure 23 A cross-sectional view perpendicular to the substrate 1 is obtained at BB after patterning the entire substrate 1 to form the first memory structure region arranged in an array and obtaining the first isolation trench 51 between adjacent first memory structure regions.

[0104] Figure 24 This is a schematic diagram of a cross-section perpendicular to the substrate 1 at point AA, obtained after the second isolation trench 52 is formed by lateral etching of each first insulating layer 41 through the first isolation trench 51. Figure 25 This is a schematic diagram of a cross-section perpendicular to the substrate 1 at the BB location, obtained after the second isolation trench 52 is formed by lateral etching of each first insulating layer 41 through the first isolation trench 51.

[0105] Figure 26 A cross-sectional view perpendicular to the substrate 1 at point AA, obtained after fabricating the first isolation layer 53 in the second isolation trench 52 and obtaining the initial first storage structure with phase-insulated array arrangement. Figure 27 A schematic cross-sectional view of the substrate 1 at point BB after the initial first storage structure with phase insulation array arrangement is obtained by fabricating the first isolation layer 53 in the second isolation trench 52.

[0106] Optionally, before patterning the entire substrate 1 to form the first memory structure region of the array arrangement, the method further includes: fabricating a first dielectric layer 46 on the entire upper surface of the substrate, such that the first dielectric layer 46 covers the first insulating layer 41 and the sacrificial word line 45.

[0107] In some embodiments of this application, Figure 20 A schematic cross-sectional view of the substrate 1 at point AA, perpendicular to the substrate 1, obtained after fabricating the first dielectric layer 46 on the entire upper surface of the substrate. Figure 21 A schematic cross-sectional view of the CC section perpendicular to the substrate 1 obtained after fabricating the first dielectric layer 46 on the entire upper surface of the substrate.

[0108] Optionally, in step S1, a first memory structure with multiple phase-insulated arrays is fabricated on one side of substrate 1, including steps S11 to S18 below. A schematic flow chart of this fabrication process is shown below. Figure 9 As shown.

[0109] S11: Remove the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction to form a replacement groove 61; the third direction is parallel to the substrate 1 and intersects with the second direction.

[0110] In some embodiments of this application, the replacement layer 42 can be replaced with metal via the replacement groove 61. Specifically, the replacement layer 42 is silicon nitride. Figure 28 A schematic cross-sectional view of the substrate 1 at point AA after forming a replacement groove 61 by removing the first insulating layer 41 and replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction. Figure 29 A schematic cross-sectional view of the CC section perpendicular to the substrate 1 obtained after forming a replacement groove 61 by removing the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction. Figure 30 A schematic cross-sectional view of the substrate 1 at the DD position obtained after removing the first insulating layer 41 and the replacement layer 42 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction to form a replacement groove 61.

[0111] S12: The replacement layer 42 is removed laterally through the replacement slot 61 to create an area that fills the replacement layer 42 and the initial metal layer 62 of the replacement slot 61.

[0112] In some embodiments of this application, the material of the first dielectric layer 46 is the same as that of the replacement layer 42, both of which can be silicon nitride. While removing the replacement layer 42, the first dielectric layer 46 is also removed, and an initial metal layer 62 is also formed in the region where the first dielectric layer 46 is located.

[0113] Figure 31 A cross-sectional view perpendicular to the substrate 1 at point AA is obtained after the replacement layer 42 is removed laterally through the replacement trench 61, and the area filled with the replacement layer 42 and the initial metal layer 62 of the replacement trench 61 are created. Figure 32 A schematic diagram of a cross-section perpendicular to the substrate 1 at BB obtained after the replacement layer 42 is laterally removed through the replacement trench 61, the area filled with the replacement layer 42 and the initial metal layer 62 of the replacement trench 61 are created. Figure 33 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position obtained after the replacement layer 42 is laterally removed through the replacement trench 61, the area filled with the replacement layer 42 and the initial metal layer 62 of the replacement trench 61 are manufactured. Figure 34 This is a schematic cross-sectional view of the DD section perpendicular to the substrate 1, obtained by laterally removing the replacement layer 42 through the replacement trench 61, creating a region filled with the replacement layer 42 and the initial metal layer 62 of the replacement trench 61.

[0114] S13: Remove the portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction, forming a transition metal layer 63 and a third trench 65.

[0115] In some embodiments of this application, Figure 35A schematic cross-sectional view perpendicular to the substrate 1 at point AA after removing the portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction, forming a transition metal layer 63 and a third trench 65.

[0116] Figure 36 A schematic cross-sectional view of the substrate 1 at BB obtained after removing the portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction, forming a transition metal layer 63 and a third trench 65. Figure 37 A schematic cross-sectional view of the CC section perpendicular to the substrate 1 obtained after removing the portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction, forming a transition metal layer 63 and a third trench 65. Figure 38 A schematic cross-sectional view of the substrate 1 at the DD location obtained after removing the portion of the initial metal layer 62 extending along the third direction between any two adjacent sacrificial word lines 45 located in the same column along the second direction, forming a transition metal layer 63 and a third trench 65.

[0117] S14: Conform a second insulating layer 66 along the third trench 65; Conform a second insulating layer 67 within the third trench 65.

[0118] In some embodiments of this application, the second insulating layer 66 is able to prevent the oxygen used in manufacturing the second insulating layer 67 from affecting the sacrificial word line 45. Figure 39 A schematic cross-sectional view of the substrate 1 at point AA after conformally fabricating the second isolation layer 66 along the third trench 65. Figure 40 A schematic diagram of a cross-section perpendicular to the substrate 1 at BB after conformally fabricating the second isolation layer 66 along the third trench 65. Figure 41 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position obtained after conformally fabricating the second isolation layer 66 along the third trench 65; Figure 42 A schematic cross-sectional view of the DD section perpendicular to the substrate 1, obtained by conformally fabricating the second isolation layer 66 along the third trench 65.

[0119] Figure 43 A schematic cross-sectional view of the AA section perpendicular to the substrate 1 obtained after the second insulating layer 67 is fabricated in the third trench 65. Figure 44 A schematic cross-sectional view of the BB section perpendicular to the substrate 1 after the second insulating layer 67 is fabricated in the third trench 65. Figure 45 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC region obtained after fabricating the second insulating layer 67 within the third trench 65. Figure 46 This is a schematic cross-sectional view of the DD section perpendicular to the substrate 1 obtained after the second insulating layer 67 is fabricated in the third trench 65.

[0120] Optionally, after step S14 and before step S15, the manufacturing method further includes:

[0121] The second insulating layer 67, the second isolation layer 66, and the first insulating layer 41 in the capacitor region are removed in sequence to expose the first capacitor electrode 63 located in the capacitor region, forming a capacitor trench 81.

[0122] A capacitor insulating layer 91, a first electrode layer 92, and a series structure 93 are sequentially fabricated on the outer periphery of the exposed first capacitor electrode 63 and along the capacitor trench 81.

[0123] Remove the series structure in the transistor region 93.

[0124] In some embodiments of this application, Figure 47 A schematic cross-sectional view of the AA section perpendicular to the substrate 1 is obtained after removing the first insulating layer 41, the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 located in the capacitor region and forming the capacitor trench 81. Figure 48 A schematic cross-sectional view of the BB section perpendicular to the substrate 1 obtained after removing the first insulating layer 41, the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 located in the capacitor region and forming the capacitor trench 81. Figure 49 A schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position after removing the first insulating layer 41, the second insulating layer 67 and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 located in the capacitor region and forming the capacitor trench 81. Figure 50 A schematic cross-sectional view of the DD section perpendicular to the substrate 1 is obtained after removing the first insulating layer 41, the second insulating layer 67, and the second isolation layer 66 in the capacitor region to expose the first capacitor electrode 63 located in the capacitor region and forming the capacitor trench 81.

[0125] Figure 51 A schematic cross-sectional view perpendicular to the substrate 1 at point AA, obtained after sequentially fabricating a capacitor insulating layer 91, a first electrode layer 92, and a series structure 93 on the outer periphery of the exposed first capacitor electrode 63 and along the capacitor trench 81. Figure 52 A schematic cross-sectional view perpendicular to the substrate 1 at point BB, obtained after sequentially fabricating a capacitor insulating layer 91, a first electrode layer 92, and a series structure 93 on the outer periphery of the exposed first capacitor electrode 63 and along the capacitor trench 81. Figure 53 A schematic cross-sectional view perpendicular to the substrate 1 at the CC position obtained after sequentially fabricating a capacitor insulating layer 91, a first electrode layer 92, and a series structure 93 on the outer periphery of the exposed first capacitor electrode 63 and along the capacitor trench 81. Figure 54This is a schematic cross-sectional view of the substrate 1 at the DD position obtained after sequentially fabricating a capacitor insulating layer 91, a first electrode layer 92, and a series structure 93 on the outer periphery of the exposed first capacitor electrode 63 and along the capacitor trench 81.

[0126] Optionally, after removing the series structure 93 of the transistor region and before step S15, the manufacturing method further includes: manufacturing a third dielectric layer 48 in the region of the removed series structure 93.

[0127] In some embodiments of this application, replacing the series structure 93 of the transistor region with the third dielectric layer 48 can prevent the series structure 93 of the capacitor region from being affected when the sacrificial word line 45 is subsequently patterned.

[0128] In some embodiments of this application, Figure 55 A schematic cross-sectional view of the substrate 1 at point AA after fabricating the third dielectric layer 48 in the region of the removed tandem structure 93. Figure 56 A schematic diagram of a cross-section perpendicular to the substrate 1 at BB, obtained after fabricating the third dielectric layer 48 in the region of the removed tandem structure 93. Figure 57 A schematic cross-sectional view of the CC region perpendicular to the substrate 1 obtained after fabricating the third dielectric layer 48 in the region of the removed tandem structure 93.

[0129] S15: Pattern the sacrificial character line 45 to obtain a third character line groove 68 with the same size as the first character line groove 43.

[0130] In some embodiments of this application, along the second direction, the width of the third character groove 68 is equal to the third width of the first character groove 43; along the third direction, the width of the third character groove 68 is equal to the first width of the first character groove 43. Figure 58 A cross-sectional view of the AA section perpendicular to the substrate 1 is obtained after patterning the sacrificial character line 45 to obtain a third character line groove 68 with the same size as the first character line groove 43. Figure 59 A cross-sectional view of the CC section perpendicular to the substrate 1 is obtained after patterning the sacrificial character line 45 to obtain a third character line groove 68 with the same size as the first character line groove 43.

[0131] S16: The transition metal layer 63 is etched laterally through the third word slot 68 to remove the transition metal layer 63 located on both sides of the third word slot 68 along the second direction, thereby obtaining the fourth word slot 69 formed by the third word slot 68 and the metal layer 64 obtained by the transition metal layer 63; the metal layer 64 includes a bit line 22 located between two adjacent columns of sacrificial word lines 45 along the third direction and extending along the second direction, a drain 16 disposed on one side of the sacrificial word line 45 and connected to the bit line 22, and a source 15 located on the other side of the sacrificial word line 45.

[0132] In some embodiments of this application, Figure 60 This is a schematic diagram of a cross-section perpendicular to the substrate 1 at point AA obtained after lateral etching of the transition metal layer 63 through the third groove 68. Figure 61 This is a schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position obtained after lateral etching of the transition metal layer 63 through the third letter groove 68.

[0133] Optionally, in step S16, the transition metal layer 63 is etched laterally through the third word groove 68 to remove the transition metal layer 63 located on both sides of the third word groove 68 along the second direction, thereby obtaining the fourth word groove 69 formed by the third word groove 68. This includes removing a portion of the transition metal layer 63 located on both sides of the third word groove 68 along the third direction, such that the width between two adjacent transition metal layers 63 along the third direction is changed from a first width to a second width.

[0134] In some embodiments of this application, the width of the third word groove along a third direction is a first width. The second width is the width of the gate electrode 11 manufactured subsequently.

[0135] S17: Create a third isolation layer 71 within the fourth letter groove 69.

[0136] In some embodiments of this application, Figure 62 A schematic cross-sectional view of the AA section perpendicular to the substrate 1 obtained after the third isolation layer 71 is manufactured in the fourth groove 69. Figure 63 This is a schematic diagram of a cross-section perpendicular to the substrate 1 at the CC position obtained after the third isolation layer 71 is manufactured in the fourth letter groove 69.

[0137] S18: Pattern the third isolation layer 71 to obtain a first groove 31 and a first protective structure 14 with a width along the second direction equal to the width of the third letter groove 68.

[0138] In some embodiments of this application, Figure 65 The width of the first trench 31 along the second direction is less than the width of the gate electrode 11 along the second direction. Specifically, the width of the first trench 31 along the second direction is 50% to 80% of the width of the gate electrode along the second direction (including the two endpoint values).

[0139] Optionally, in step S18, the third isolation layer 71 is patterned to obtain a first groove 31 with a width along the second direction equal to the width of the third letter groove 68, including: patterning the third isolation layer 71 to obtain a first groove 31 with a width along the third direction equal to the second width.

[0140] In some embodiments of this application, Figure 64 The width of the first trench 31 along the third direction is the second width, which is the width of the gate electrode 11.

[0141] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0142] 1. In some embodiments of this application, the etching rate of the material of the first protective structure outside the channel region is less than the etching rate of the material of the channel region. Therefore, the channel region and the first protective structure can form a more obvious etching selectivity, which is beneficial to protect the channel region when removing the semiconductor layer connecting the channel region.

[0143] 2. In some embodiments of this application, for the fabrication of stacked memory, because the first protective structure protects the channel region, it can prevent damage to the channel region due to the difference in etching rates between the top and bottom caused by the decrease in etchant concentration from the top to the bottom, which is beneficial to improving the structural stability of the stacked memory.

[0144] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0145] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0146] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0147] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0148] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0149] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0150] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A memory, characterized in that, include: A substrate and multiple memory cells, each memory cell including a transistor and a capacitor structure, the transistor including: The system comprises a gate electrode, a gate insulating layer, and a channel region, wherein the gate insulating layer and the channel region are sequentially disposed on the outer periphery of the gate electrode; both the gate insulating layer and the gate electrode extend along a first direction perpendicular to the substrate. A first protective structure is disposed on at least one side of the channel region along a second direction, the second direction being parallel to the substrate; the etching rate of the material in the channel region is greater than the etching rate of the material in the first protective structure; Source pole; The capacitor structure includes a second electrode layer disposed sequentially on one side of the source electrode, a capacitor insulating layer, a first electrode layer, and a series structure on the outer periphery of the second electrode layer; The capacitor insulating layer wraps around the opposite sides of the second electrode layer along the first direction and the opposite sides along the second direction; the first electrode layer and the series structure sequentially cover the capacitor insulating layer.

2. The memory according to claim 1, characterized in that, The material of the channel region includes metal oxides, and the material of the first protective structure includes nitrides.

3. The memory according to claim 1, characterized in that, The transistor further includes a drain, and the source and the drain are respectively disposed on opposite sides of the channel region along a third direction; the third direction is parallel to the substrate and intersects the second direction.

4. The memory according to claim 3, characterized in that, In a cross-section parallel to both the first and second directions, the channel area contacts the first protective structure on at least one side along the second direction; And / or, in a cross-section parallel to both the first direction and the third direction, the channel region contacts the source and the drain on both sides of the third direction, respectively.

5. The memory according to claim 4, characterized in that, The first protective structure has a bottom surface near the substrate and a top surface away from the substrate, as well as a side surface between the top surface and the bottom surface; the channel region is in contact with the top surface, bottom surface and side surface of the first protective structure.

6. The memory according to claim 3, characterized in that, The transistors are stacked along a first direction perpendicular to the substrate and arranged in an array in a plane parallel to the substrate; The drain of the transistor has a bottom surface near the substrate, a top surface away from the substrate, and a side surface between the top surface and the bottom surface, and the channel region is in contact with the top surface, bottom surface and side surface of the drain.

7. The memory according to claim 6, characterized in that, Along the first direction, the gate electrodes of two adjacent transistors are connected by a connecting line to form a word line.

8. The memory according to claim 7, characterized in that, Along the second direction, the width of the connecting line is greater than the width of the gate electrode.

9. The memory according to claim 6, characterized in that, Along a third direction, a bit line is provided between the drain of one transistor and the drain of another transistor, the bit line extending along the second direction.

10. An electronic device, characterized in that, Includes the memory as described in any one of claims 1-9.

11. A method for manufacturing a memory, characterized in that, include: A first storage structure with multiple phase-insulating arrays is fabricated on one side of a substrate. The first storage structure includes multiple first trenches arranged in an array in a plane parallel to the substrate, multiple first sacrificial structures spaced apart along a first direction perpendicular to the substrate around the outer periphery of the first trenches, and a first protective structure disposed on at least one side of the first trenches along a second direction. The second direction is parallel to the substrate; Laterally etch the first sacrificial structure through the first trench to remove part of the first sacrificial structure, forming a second sacrificial structure, and forming a second trench from the first trench; A semiconductor layer, a gate insulating layer, and a word line are sequentially conformally fabricated within the second trench; Remove the second sacrificial structure to expose a portion of the semiconductor layer; Using the first protective structure as a mask, the exposed semiconductor layer is removed, and the remaining semiconductor layer forms a channel region. The etching rate of the material in the channel region is greater than the etching rate of the material in the first protective structure.

12. The manufacturing method according to claim 11, characterized in that, Before fabricating a first memory structure with multiple phase-insulated arrays arranged on one side of the substrate, the process also includes: An alternating first insulating layer and a replacement layer are fabricated on one side of the substrate; Each of the first insulating layers and each of the replacement layers is patterned to form a plurality of first word grooves arranged in an array in a plane parallel to the substrate; each of the first insulating layers is laterally etched through the first word grooves to obtain second word grooves formed by the first word grooves. Sacrificial letter lines are manufactured within the second letter line groove.

13. The manufacturing method according to claim 12, characterized in that, After fabricating the sacrificial word line within the second word line slot and before fabricating a first memory structure with a plurality of phase-insulated arrays on one side of the substrate, the method further includes: The first insulating layer and the replacement layer are patterned to form an array of first storage structure regions, resulting in a first isolation trench between adjacent first storage structure regions. Laterally etch each of the first insulating layers through the first isolation trench to form a second isolation trench; fabricate a first isolation layer in the second isolation trench to obtain an initial first storage structure with phase-insulated array arrangement.

14. The manufacturing method according to claim 13, characterized in that, A first memory structure comprising an array of multiple phase-insulated components is fabricated on one side of a substrate, including: The first insulating layer and the replacement layer extending along a third direction between any two adjacent sacrificial word lines located in the same column along the second direction are removed to form a replacement groove; the third direction is parallel to the substrate and intersects the second direction; The replacement layer is removed laterally through the replacement slot to create an area filled with the replacement layer and an initial metal layer in the replacement slot; Remove the portion of the initial metal layer extending along the third direction between any two adjacent sacrificial word lines in the same column along the second direction to form a transition metal layer and a third trench; A second insulating layer is formed along the third trench; a second insulating layer is formed within the third trench; The sacrificial character line is patterned to obtain a third character line groove of the same size as the first character line groove; The transition metal layer is etched laterally through the third word slot to remove the transition metal layer located on both sides of the third word slot along the second direction, thereby obtaining a fourth word slot formed by the third word slot and a metal layer obtained by the transition metal layer; the metal layer includes a bit line located between two adjacent columns of sacrificial word lines along the third direction and extending along the second direction, a drain disposed on one side of the sacrificial word line and connected to the bit line, and a source located on the other side of the sacrificial word line; A third isolation layer is manufactured within the fourth groove; The third isolation layer is patterned to obtain the first groove and the first protective structure, whose width along the second direction is equal to the width of the third letter groove.

15. The manufacturing method according to claim 14, characterized in that, The transition metal layer is laterally etched through the third groove to remove the transition metal layer located on both sides of the third groove along the second direction, thereby obtaining a fourth groove formed by the third groove, including: Remove a portion of the transition metal layer located on both sides of the third character groove along the third direction, such that the width between two adjacent transition metal layers along the third direction is formed from a first width to a second width; Patterning the third isolation layer yields a first groove and a first protective structure with a width along the second direction equal to the width of the third letter groove, comprising: The third isolation layer is patterned to obtain the first trench with a width of the second width along the third direction.

16. The manufacturing method according to claim 14, characterized in that, After the second insulating layer is formed in the third trench and before the sacrificial letter line is patterned, the method further includes: Remove the first insulating layer, the second insulating layer, and the second isolation layer in the capacitor region to expose the transition metal layer located in the capacitor region, forming a capacitor trench; A capacitor insulating layer, a first electrode layer, and a series structure are sequentially fabricated on the outer periphery of the exposed transition metal layer and along the capacitor trench. Remove the series structure in the transistor region.

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