A method for reducing parasitic capacitance in a high-voltage SOI BCD process

Abstract

The application discloses a method for reducing the parasitic capacitance of a high-voltage SOI BCD process, and comprises the following steps: manufacturing a Trench isolation groove and filling the groove with SiO2 medium; manufacturing a Trench connecting groove and filling the groove with polycrystalline silicon; performing P-well photolithography, implantation and push-well on the high-voltage tube area and the low-voltage tube area respectively; manufacturing an LDD N-drift area on the high-voltage tube area; performing photolithography and etching of a field plate to complete high-voltage tube polycrystalline field plate modulation of an electric field; growing gate oxide SiO2 medium, and performing deposition and etching of a gate polycrystalline control area; performing N+ and P+ photolithography, implantation and annealing activation on the high-voltage tube and the low-voltage tube; growing a SiO2 medium layer to perform overall covering, performing photolithography and dry etching of a contact hole, and performing body area P+ implantation to form tungsten in the contact hole; completing metal deposition, photolithography and etching, and then performing chemical deposition, photolithography and etching of a passivation medium layer to protect the device. The application can cut off the leakage path after the total dose test, and realizes the total dose hardening function of a shield gate VDMOS.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a preparation method for reducing the parasitic capacitance of a high-voltage SOI BCD process. BACKGROUND

[0002] SOI (Silicon on Insulator) refers to a manufacturing method of forming a semiconductor device in a semiconductor thin film material (device layer) above an insulator (buried oxygen insulating layer), and the semiconductor thin film material below the buried oxygen insulating layer is referred to as a substrate layer.

[0003] Compared with the same body silicon (without an intermediate buried oxygen insulating layer) process, the device manufactured by the SOI process has certain advantages: a steeper sub-value slope, higher transconductance and current driving capability, a smaller sensitive volume for reducing single particle transient and single particle flip effect, stronger anti-radiation performance, no latch-up effect, etc. However, in a high-voltage SOI process manufacturing process platform, it is found that the device layer brings parasitic resistance and capacitance to the low-voltage tube while meeting the high-voltage tube voltage resistance, because the device layer thickness required by the high-voltage tube is much larger than that of the low-voltage tube, which causes the low-voltage tube, especially the low-voltage NMOS tube, to introduce unnecessary parasitic resistance and capacitance in the device layer, and the original SOI process low parasitic capacitance advantage cannot be realized.

[0004] Therefore, how to reduce the parasitic capacitance of the high-voltage SOI process by a convenient preparation process is a technical problem to be solved at present. SUMMARY

[0005] The purpose of the present application is to provide a preparation method for reducing the parasitic capacitance of a high-voltage SOI BCD process to solve the problems in the background art.

[0006] To solve the above technical problems, the present application provides a preparation method for reducing the parasitic capacitance of a high-voltage SOI BCD process, comprising:

[0007] A Trench isolation groove is made on the device layer, SiO2 dielectric is grown and deposited in the Trench isolation groove, Trench groove filling is completed, and the voltage resistance requirement between different tubes is met;

[0008] Photoetching and etching of the Trench connecting groove are performed, the buried oxygen insulating layer of the low-voltage NMOS tube area is opened, the device layer and the substrate layer are connected, and the upper and lower zero voltage difference is realized,

[0009] Polysilicon is grown and deposited in the Trench connecting groove, Trench connecting groove filling is completed, and polysilicon interconnection of the upper and lower two layers is realized;

[0010] P well photoetching, implantation and push well are carried out in the high-voltage tube area and the low-voltage tube area to form high-voltage tube P well and low-voltage tube P well, and realize NMOS tube voltage resistance and isolation.

[0011] LDD N-drift area is made in the high-voltage tube area, and photoetching, implantation and annealing of LDD N-drift area are completed; field plate photoetching and etching are carried out, and high-voltage tube polycrystal field plate modulation electric field is completed.

[0012] Gate oxide SiO2 dielectric is grown, and gate polycrystal control area deposition and etching are carried out, which are used as gate control end of high-voltage tube and low-voltage tube.

[0013] N+ and P+ photoetching, implantation and annealing activation are carried out for high-voltage tube and low-voltage tube to form source, drain and body area.

[0014] SiO2 dielectric layer is grown to be fully covered, contact hole photoetching and dry etching are carried out, and body area P+ implantation is carried out, tungsten is formed in the contact hole, and gate polycrystal control end, source body contact end and source polycrystal control end are led out respectively.

[0015] Metal deposition, photoetching and etching are completed, and on the basis of the above functional design and production, chemical deposition, photoetching and etching of a layer of passivation dielectric are carried out to protect the device.

[0016] In an embodiment, the Trench isolation groove is formed by photoetching and etching to have a required topography, the depth of the Trench isolation groove is 3 μm-50 μm, the width is 2 μm-5 μm, and the inclination angle and bottom topography of the Trench isolation groove are well controlled.

[0017] In an embodiment, the thickness of SiO2 dielectric in the Trench isolation groove is 1.5 μm-3.5 μm, which can completely fill the Trench isolation groove and realize full coverage.

[0018] In an embodiment, the width of the Trench connection groove is 1 μm-3 μm, and the depth of the Trench connection groove depends on the depth of the buried oxygen insulation layer and is more than 1 μm deeper than the buried oxygen insulation layer.

[0019] In an embodiment, the P well implantation impurities for forming high-voltage tube P well and low-voltage tube P well include P-type impurities such as B, BF2 and BF3, the P well implantation energy is 50 keV-100 keV, the implantation dose is 5E13-5E14, and voltage resistance and isolation area are formed.

[0020] In one embodiment, the fabrication of LDD N-drift region in high-voltage tube area includes: firstly, performing lithography, implantation and annealing of drift region LDD N-, N-impurity implantation As or P, LDD implantation energy is 50keV-100keV, implantation dose is 1E13-1E14, forming voltage resistance and connection area.

[0021] In one embodiment, the fabrication of polycrystalline field plate includes: field oxidation SiO2 medium deposition, lithography, etching to form required topography, thickness of field oxidation SiO2 medium is 350nm-1500nm.

[0022] In one embodiment, thickness of gate oxide SiO2 medium is 30nm-80nm, thickness of gate polycrystalline is 0.5μm-1.0μm, forming device gate control end.

[0023] In one embodiment, N+ and P+ lithography, implantation and annealing activation are performed on high-voltage and low-voltage tubes, wherein N+ implantation, N-type impurity implantation energy is 40keV-80keV, N-type impurity implantation dose is 1E15-1E16; P+ implantation is performed, P-type impurity implantation energy is 20keV-60keV, P-type impurity implantation dose is 1E15-5E15.

[0024] In one embodiment, the SiO2 medium layer is formed by chemical deposition, thickness of the SiO2 medium layer is 0.6μm-0.8μm; size of the contact hole is 150nm-300nm.

[0025] In one embodiment, thickness of the metal is 0.7μm-1.5μm, connected with the contact hole, used for chip function connection and subsequent bonding; the passivation medium is SiO2 or SiO2+Si3N4, thickness is 0.5μm-1.0μm, used for device isolation and protection.

[0026] The application provides a preparation method for reducing high-voltage SOI BCD process parasitic capacitance.

[0027] Beneficial effects:

[0028] (1) The low-voltage NMOS tube device layer is connected with the substrate layer, which guarantees that the high-voltage and low-voltage tubes are not damaged by voltage resistance, gives the same upper and lower potentials to the low-voltage NMOS tube, eliminates the parasitic resistance and capacitance of the low-voltage NMOS tube, and realizes reduction of high-voltage SOI process parasitic capacitance.

[0029] (2) The ordinary semiconductor device manufacturing process and process method are adopted; the fabrication method is simple and has strong operability. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a preparation method flow chart of reducing high-voltage SOI BCD process parasitic capacitance provided by the present application;

[0031] Figure 2 is a schematic diagram of manufacturing high-voltage and low-voltage tube Trench isolation groove on the device layer;

[0032] Figure 3 is a schematic diagram of growing and depositing SiO2 medium in the Trench isolation groove;

[0033] Figure 4 is a schematic diagram of photoetching and etching of the Trench connection groove;

[0034] Figure 5 is a schematic diagram of polycrystalline deposition in the Trench connection groove;

[0035] Figure 6 is a schematic diagram of manufacturing high-voltage and low-voltage tube P-well;

[0036] Figure 7 is a schematic diagram of manufacturing high-voltage tube LDD N-drift region;

[0037] Figure 8 is a schematic diagram of manufacturing high-voltage tube polycrystalline field plate;

[0038] Figure 9 is a schematic diagram of manufacturing gate oxide SiO2 medium and gate polycrystalline control region deposition and etching;

[0039] Figure 10 is a schematic diagram of manufacturing N+ and P+ photoetching and implantation;

[0040] Figure 11 is a schematic diagram of manufacturing contact hole and completing tungsten plug;

[0041] Figure 12 is a schematic diagram of manufacturing metal AlSiCu and passivation layer SiO2 medium. DETAILED DESCRIPTION

[0042] The present application provides a preparation method of reducing high-voltage SOI BCD process parasitic capacitance, and the flow chart is shown in

[0043] The present application provides a preparation method of reducing high-voltage SOI BCD process parasitic capacitance, and the flow chart is shown in Figure 1 The steps include:

[0044] Step Sll, making high and low voltage tube Trench isolation groove;

[0045] Step S12, making low voltage NMOS tube area Trench connection groove;

[0046] Step S13, making high and low voltage tube P well and high voltage tube LDD N-voltage drift region;

[0047] Step S14, making high voltage tube polycrystalline field plate;

[0048] Step S15, making gate oxide and gate polycrystalline;

[0049] Step S16, making N+, P+ and contact hole;

[0050] Step S17, making metal and passivation layer.

[0051] The specific step process is as follows:

[0052] First, a photo mask 4 (PHOTO) is formed on the surface of the device layer 3 (N-EPI) of the Si substrate 1 (N+SUB), and a Trench isolation groove 5 is made at the exposed part of the photo mask 4, which is used to isolate the high voltage tube and the low voltage tube in the high voltage area, and the voltage resistance between the low voltage tubes; the isolation ring isolated to the buried oxygen insulating layer is formed by photoetching and etching through the Trench isolation groove 5; the depth of the Trench isolation groove 5 is 3 μm to 50 μm, and at most to the upper surface of the buried oxygen insulating layer 2, the width is 2 μm to 5 μm, and the inclination angle and bottom morphology of the Trench isolation groove 5 are well controlled, as shown in Figure 2 The cross-sectional view after this step is shown in

[0053] The photo mask 4 (PHOTO) is removed, and SiO2 medium 6 is deposited in the Trench isolation groove 5, as shown in Figure 3 Since the high voltage tube is made, it will inevitably cause the low voltage tube area to increase the additional resistance and capacitance, in order to reduce the parasitic resistance and capacitance in the low voltage NMOS tube area, the Trench connection groove 7 is made, which makes the upper and lower resistances in the low voltage tube pass through the polycrystalline connection later, at the same time realizes that there is no voltage difference between the device layer and the substrate layer, and eliminates the parasitic capacitance brought by the buried oxygen insulating layer 2. The width of the Trench connection groove 7 is 1 μm to 3 μm, the depth of the Trench connection groove 7 depends on the depth of the buried oxygen insulating layer 2, and is more than 1 μm deeper than the buried oxygen insulating layer 2, that is, the Trench connection groove 7 penetrates the buried oxygen insulating layer 2 and contacts the Si substrate 1, as shown in Figure 4 The cross-sectional view after this step is shown in

[0054] Polycrystalline 8 is deposited in the Trench connection groove 7, and the deposition thickness is 0.75 μm to 2 μm, as shown in Figure 5The cross-sectional view after this step is shown in the figure;

[0055] The high-voltage tube P-well 9 and the low-voltage tube P-well 10 are made, and the implanted impurities of the high-voltage tube P-well 9 and the low-voltage tube P-well 10 are P-type impurities such as B / BF2 / BF3, the implantation energy of the high-voltage tube P-well 9 and the low-voltage tube P-well 10 is 50keV-100keV, and the implantation dose is 5E13-5E14, so as to form the voltage-resistant and isolation regions, as shown in the figure; Figure 6 The cross-sectional view after this step is shown in the figure;

[0056] The high-voltage tube LDD N-drift region 11 is made, and first, the high-voltage tube LDD N-drift region 11 is subjected to photoetching, implantation and annealing, the N-impurity is implanted with N-type impurities such as As or P, the implantation energy of the LDD is 50keV-100keV, the implantation dose is 1E13-1E14, so as to form the voltage-resistant and connection regions, as shown in the figure; Figure 7 The cross-sectional view after this step is shown in the figure;

[0057] The polycrystal field plate is made, the field oxide SiO2 dielectric 12 is deposited, photoetched and etched to form the required shape, and the thickness of the field oxide SiO2 dielectric 12 is 350nm-1500nm, as shown in the figure; Figure 8 The cross-sectional view after this step is shown in the figure;

[0058] The gate oxide SiO2 dielectric 13 is made on the surface, the thickness of the gate oxide SiO2 dielectric 13 is 30nm-80nm, and the gate polycrystal 14 control region is deposited, photoetched and etched on the surface of the gate oxide SiO2 dielectric 13, the thickness of the gate polycrystal 14 is 0.5μm-1.0μm, so as to form the device gate control end, as shown in the figure; Figure 9 The cross-sectional view after this step is shown in the figure;

[0059] The N+15 and P+16 photoetching and implantation are performed, wherein the N+15 implantation is implanted with N-type impurities such as As or P, the N-type impurity implantation energy is 40keV-80keV, and the implantation dose is 1E15-1E16; the P+16 implantation is performed, the P-type impurity is B or BF2 or BF3, the P-type impurity implantation energy is 20keV-60keV, and the implantation dose is 1E15-5E15, as shown in the figure; Figure 10 The cross-sectional view after this step is shown in the figure;

[0060] The SiO2 dielectric layer is grown by chemical deposition as a full coverage of the isolation layer, the thickness of the SiO2 dielectric layer 17 is 0.6μm-0.8μm, the contact hole 18 is photoetched and dry-etched, the design size of the contact hole 18 is 150nm-300nm, and tungsten is formed in the contact hole 18 by chemical vapor deposition, so as to lead out the gate, drain, source and body regions of the high-voltage tube and the low-voltage tube from the contact hole 18 to realize the connection function, as shown in the figure;Figure 11 Fig. 4 shows a cross-sectional view after this step is completed;

[0061] After the deposition, photoetching and etching of the metal are completed, the thickness of the metal 19 is 0.7-1.5 μm, which is connected with the contact hole 19 and used for chip function connection and subsequent bonding; then a chemical deposition, photoetching and etching of a passivation medium is performed, the passivation medium 20 is SiO2 or SiO2+Si3N4, and the thickness is 0.5-1.0 μm, which completes device isolation and protection, such as Figure 12 Fig. 5 shows a cross-sectional view after this step is completed.

[0062] The above-mentioned main design method forms a preparation method for reducing the parasitic capacitance of a high-voltage SOI BCD process. According to the present application, the device layer 3 and the substrate layer 1 are connected through the polycrystal 8, so that the potential difference between the upper and lower layers is zero, which shields the inherent series resistance in the thick device layer 3 and eliminates the parasitic capacitance of the buried oxygen insulation layer 2, thereby improving the working frequency and dv / dt capability of the circuit using the high-voltage SOI process. The present application can realize the total dose hardening capability of the device without adding any new process procedure.

[0063] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for reducing parasitic capacitance in high-voltage SOI BCD process, characterized in that, include: Trench isolation trenches are fabricated on the device layer, and SiO2 dielectric is grown and deposited inside the trenches to complete the filling of the trenches and meet the withstand voltage requirements between different tubes. Photolithography and etching of trenches are performed to open the buried oxide insulating layer in the low-voltage NMOS transistor region, connecting the device layer and the substrate layer to achieve zero voltage difference between the top and bottom layers. Polycrystalline silicon is grown and deposited in the Trench interconnect to complete the filling of the Trench interconnect and realize the polycrystalline interconnect between the upper and lower layers. P-well photolithography, implantation, and push-well are performed in the high-voltage and low-voltage regions of the device to form the high-voltage P-well and low-voltage P-well respectively, thereby achieving the voltage withstand and isolation of the NMOS transistor; In the high-voltage tube region, the LDD N-drift region is fabricated, and the LDD N-drift region is photolithography, implantation and annealing are completed; the field plate is photolithography and etching are performed to complete the modulation electric field of the high-voltage tube polycrystalline field plate; A gate oxide SiO2 dielectric is grown, and the gate polycrystalline control region is deposited and etched to serve as the gate control terminal for high- and low-voltage transistors. Both high-voltage and low-voltage transistors are subjected to N+ and P+ photolithography, implantation, and annealing activation to form source, drain, and body regions; A SiO2 dielectric layer is grown for full coverage, photolithography and dry etching are performed on the contact holes, and P+ implantation is performed in the body region to form tungsten in the contact holes. The gate polycrystalline control terminal, the source body contact terminal, and the source polycrystalline control terminal are then brought out. After completing metal deposition, photolithography, and etching, a passivation medium is chemically deposited, photolithographically etched, and etched to protect the device, based on the functional design and fabrication above.

2. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The Trench isolation trench is formed to the required morphology through photolithography and etching. The depth of the Trench isolation trench is 3μm~50μm and the width is 2μm~5μm. The tilt angle and bottom morphology of the Trench isolation trench are well controlled.

3. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The thickness of the SiO2 medium in the Trench isolation groove is 1.5μm~3.5μm, which can completely fill the Trench isolation groove and achieve full coverage.

4. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The width of the Trench connection groove is 1μm to 3μm, and the depth of the Trench connection groove depends on the depth of the buried oxygen insulation layer, and is more than 1μm deeper than the buried oxygen insulation layer.

5. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The process involves forming a high-pressure tube P-well and a low-pressure tube P-well. The injected impurities in the P-well are P-type impurities including B, BF2, and BF3. The injection energy of the P-well is 50keV to 100keV, and the injection dose is 5E13 to 5E14, forming a pressure-resistant and isolation zone.

6. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The fabrication of the LDD N-drift region in the high-voltage pipeline area includes: firstly, photolithography, implantation, and annealing of the drift region LDD N-, then implanting N- impurities as As or P, with the LDD implantation energy being 50keV~100keV and the implantation dose being 1E13~1E14, to form the withstand voltage and connection region.

7. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The fabrication of the polycrystalline field plate includes: deposition of field oxygen SiO2 dielectric, photolithography, and etching to form the required morphology, with the thickness of the field oxygen SiO2 dielectric being 350nm~1500nm.

8. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The thickness of the gate oxide SiO2 dielectric is 30nm~80nm, and the thickness of the gate polycrystalline is 0.5μm~1.0μm, forming the gate control terminal of the device.

9. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, Both high-voltage and low-voltage transistors undergo N+ and P+ photolithography, implantation, and annealing activation. N+ implantation involves implanting As or P as the N-type impurity, with an implantation energy of 40 keV to 80 keV and an implantation dose of 1E15-1E16. P+ implantation involves implanting B, BF2, or BF3 as the P-type impurity, with an implantation energy of 20 keV to 60 keV and an implantation dose of 1E15-5E15.

10. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The SiO2 dielectric layer is grown by chemical deposition, and the thickness of the SiO2 dielectric layer is 0.6μm~0.8μm; the size of the contact hole is 150nm~300nm.

11. The method for reducing parasitic capacitance in high-voltage SOI BCD process as described in claim 1, characterized in that, The metal has a thickness of 0.7μm to 1.5μm and is connected to the contact hole for chip functional connection and subsequent bonding; the passivation medium is SiO2 or SiO2+Si3N4 with a thickness of 0.5μm to 1.0μm and is used for device isolation and protection.

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