Semiconductor structure, forming method, device and electronic device

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a forming method, a device and an electronic device. The structure comprises a supporting substrate, a trap-rich layer, a buried oxide layer and a silicon thin film layer, the rich trap layer is formed on the surface of the supporting substrate, the buried oxide layer is formed on the surface of the rich trap layer, and the silicon thin film layer is formed on the surface of the buried oxide layer; at least one gap structure is formed between the buried oxide layer and the rich trap layer, and the gap structure is used for reducing the contact area between the buried oxide layer and the rich trap layer. Due to the existence of the gap structure, the surface parasitic conducting layer is cut into a plurality of independent surface parasitic conducting layers with lower resistance values, so that the resistance values of the surface parasitic conducting layers can be improved, the influence of the low-resistance surface parasitic conducting layers on radio-frequency signals can be further reduced, and the structural performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a formation method, a device and an electronic apparatus. Background Art

[0002] Silicon-On-Insulator (SOI) wafers have a high resistance supporting substrate, so when used as substrates for RF devices, they have obvious advantages over bulk silicon wafers in terms of signal transmission efficiency and harmonic power. Using SOI wafers to make RF devices, such as RF switch devices, can have smaller signal transmission losses and lower harmonic power levels than bulk silicon wafer substrates. Using SOI wafers to make low noise amplifier (LNA) devices can have lower noise when made on SOI wafers.

[0003] However, between the insulating layer and the supporting substrate in the SOI wafer, due to the presence of fixed positive charges in the insulating layer near the interface, a surface parasitic conductive layer will be induced at high frequencies. Since the resistance of this surface parasitic conductive layer is very low, it will reduce the equivalent resistance of the supporting substrate, causing greater loss of RF signals during transmission, and ultimately leading to the deterioration of RF device performance. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a semiconductor structure, a formation method, a device and an electronic apparatus.

[0005] In a first aspect, an embodiment of the present application discloses a semiconductor structure, comprising: a supporting substrate, a trap-rich layer, a buried oxide layer, and a silicon thin film layer;

[0006] A trap-rich layer is formed on the surface of the supporting substrate, a buried oxide layer is formed on the surface of the trap-rich layer, and a silicon thin film layer is formed on the surface of the buried oxide layer;

[0007] At least one gap structure is formed between the buried oxide layer and the trap-rich layer, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer.

[0008] In a second aspect, an embodiment of the present application discloses a method for forming a semiconductor structure, the method comprising:

[0009] providing a supporting substrate and a single crystal silicon substrate;

[0010] forming a trap-rich layer on a supporting substrate to obtain a first multi-layer structure;

[0011] forming a buried oxide layer on the single crystal silicon substrate to obtain a second multilayer structure;

[0012] Using the surface of the buried oxide layer as an ion implantation surface, ion implantation is performed on the second multilayer structure to form a defect layer in the single crystal silicon substrate;

[0013] Etching the surface of the buried oxide layer to form at least one first groove / protrusion;

[0014] The first multilayer structure and the second multilayer structure are bonded to obtain a semiconductor structure; wherein, after the surface of the buried oxide layer contacts the surface of the trap-rich layer, at least one gap structure is obtained, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer.

[0015] In a third aspect, an embodiment of the present application discloses a method for forming a semiconductor structure, the method comprising:

[0016] providing a supporting substrate;

[0017] forming a trap-rich layer on a supporting substrate;

[0018] Etching the surface of the trap-rich layer to form at least one second groove / protrusion;

[0019] forming a buried oxide layer on the trap-rich layer; wherein, after the surface of the buried oxide layer contacts the surface of the trap-rich layer, at least one gap structure is obtained, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer;

[0020] A silicon thin film layer is formed on the buried oxide layer to obtain a semiconductor structure.

[0021] In a fourth aspect, an embodiment of the present application discloses a radio frequency device, which includes the semiconductor structure as described above.

[0022] In a fifth aspect, an embodiment of the present application discloses an electronic device, which includes the storage device described above.

[0023] The technical solution provided by this application has the following technical effects:

[0024] The semiconductor structure, formation method, device and electronic device described in the embodiments of the present application, by setting a trap-rich layer between the supporting substrate and the buried oxide layer, due to the presence of numerous defect states in the trap-rich layer, the resistance of the supporting substrate is prevented from being greatly reduced due to the surface parasitic conductive layer. At least one gap structure is formed between the buried oxide layer and the trap-rich layer, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer, thereby reducing the area of ​​the surface parasitic conductive layer, that is, reducing the coupling area between the radio frequency signal and the surface parasitic conductive layer during the transmission of the device. Moreover, due to the existence of the gap structure, the surface parasitic conductive layer is cut into many independent surface parasitic conductive layers with lower resistance, which can increase the resistance value of the surface parasitic conductive layer, thereby further reducing the influence of the low-resistance surface parasitic conductive layer on the radio frequency signal, and improving the device structure performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment;

[0027] Figure 2 is a schematic structural diagram of a radio frequency device for generating a surface parasitic conductive layer according to an exemplary embodiment;

[0028] Figure 3 is a schematic structural diagram of another semiconductor structure according to an exemplary embodiment;

[0029] Figure 4 is a schematic flow chart of a method for forming a conductor structure according to an exemplary embodiment;

[0030] Figure 5-Figure 9 is a structural schematic diagram showing a semiconductor structure forming process according to an example embodiment;

[0031] Fig.10 is a schematic flow chart of another method for forming a conductor structure according to an exemplary embodiment;

[0032] Figure 11-Figure 12 is a schematic structural diagram showing another semiconductor structure forming process according to an example embodiment.

[0033] The following is a supplementary description of the attached drawings:

[0034] 110-support substrate; 120-trap-rich layer; 121-second groove / protrusion; 130-buried oxide layer; 131-first groove / protrusion; 140-silicon thin film layer; 150-gap structure; 160-device structure layer; 170-metal wiring layer; 180-single crystal silicon substrate; 181-defect layer; 190-stress balance layer. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0036] It should be noted that the "one embodiment" or "embodiment" referred to in the specification of the embodiment of the present application refers to a specific feature, structure or characteristic that can be included in at least one implementation of the present application. It should be understood that in the specification and claims of the embodiment of the present application and the above-mentioned drawings, the orientation or position relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, in the description of the present embodiment, unless otherwise specified, "plurality" means two or more. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system or product including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] In order to make the purpose, technical solution and advantages disclosed in the embodiments of the present application more clearly understood, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and are not used to limit the embodiments of the present application.

[0038] In SOI wafers, the resistance of the high-resistance silicon substrate will be affected by the surface parasitic conductive layer formed at the interface between the buried oxide layer and the high-resistance silicon substrate. + The fixed positive charges in the form of SiO2-Si interface attract electrons to form a parasitic conductive layer on the surface. Due to the high carrier concentration in the parasitic conductive layer, its resistance is much lower than that of the high-resistance silicon substrate, which will cause the equivalent resistance of the high-resistance silicon substrate to decrease, thereby reducing the equivalent resistance of the substrate and deteriorating the RF performance of the device prepared using the SOI wafer.

[0039] In view of this, the embodiments of the present application provide a semiconductor structure, a formation method, a device and an electronic device, by setting a trap-rich layer between the supporting substrate and the buried oxide layer, due to the presence of numerous defect states in the trap-rich layer, the resistance of the supporting substrate is prevented from being greatly reduced due to the surface parasitic conductive layer. At least one gap structure is formed between the buried oxide layer and the trap-rich layer, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer, thereby reducing the area of ​​the surface parasitic conductive layer, that is, reducing the coupling area between the radio frequency signal and the surface parasitic conductive layer during the transmission of the device. Moreover, due to the existence of the gap structure, the surface parasitic conductive layer is cut into many independent surface parasitic conductive layers with lower resistance, which can increase the resistance value of the surface parasitic conductive layer, thereby further reducing the influence of the low-resistance surface parasitic conductive layer on the radio frequency signal and improving the device structure performance.

[0040] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 1 As shown, the semiconductor structure may include: a supporting substrate 110 , a trap-rich layer 120 , a buried oxide layer 130 and a silicon thin film layer 140 .

[0041] In the embodiment of the present application, the support substrate 110 is used to support each semiconductor structure layer formed thereon. The support substrate 110 has a relatively high resistance value. Optionally, the support substrate 110 may be, but is not limited to, a silicon substrate, a silicon oxide substrate, a sapphire substrate, a silicon carbide substrate, a quartz substrate, an aluminum nitride substrate, or a diamond substrate. Among them, the silicon substrate may be a high-resistance silicon substrate.

[0042] In the embodiment of the present application, the trap-rich layer 120 is formed on the supporting substrate 110. There are many defects in the trap-rich layer 120, which can be used as traps to capture free carriers, thereby reducing the carrier concentration and increasing the equivalent resistance of the supporting substrate 110. Optionally, the material of the trap-rich layer 120 can be amorphous silicon or polycrystalline silicon, such as porous silicon. As an optional embodiment, the material of the trap-rich layer 120 is polycrystalline silicon, and the grains in the trap-rich layer 120 are columnar grains preferentially oriented in the vertical direction. The vertical direction refers to the direction vertical to the surface of the supporting substrate 110. The columnar grains preferentially oriented in the vertical direction can increase the number of grain boundaries, thereby providing more carrier traps. Optionally, the thickness of the trap-rich layer 120 is 1μm-3μm, for example, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, etc.

[0043] In the embodiment of the present application, a trap-rich layer 120 is inserted between the supporting substrate 110 and the buried oxide layer 130. Since the trap-rich layer 120 contains many defect states, even if a surface parasitic conductive layer is formed at the interface between the trap-rich layer 120 and the buried oxide layer 130, due to the large number of defect states in the trap-rich layer 120, the resistance of the surface parasitic conductive layer is relatively large, which does not significantly reduce the equivalent resistance of the substrate. Optionally, when preparing the trap-rich layer 120, the preparation process can be selected to make the obtained trap-rich layer 120 have a higher porosity to increase the interface surface area in the trap-rich layer 120, and the increase in the interface surface area can create more interface traps, and the increase in interface traps can further increase the resistance of the trap-rich layer 120, thereby increasing the resistance of the surface parasitic conductive layer.

[0044] In an embodiment of the present application, a buried oxide layer 130 is formed on the surface of the trap-rich layer 120. The buried oxide layer 130 serves as an isolation layer between the silicon film layer 140 and the supporting substrate 110, and has good insulation properties. The material of the buried oxide layer 130 is silicon dioxide. Optionally, the buried oxide layer 130 can be obtained by deposition, or by first forming a polysilicon layer on the trap-rich layer 120 and then thermally oxidizing the polysilicon layer. Optionally, the thickness of the buried oxide layer 130 is 1000 angstroms to 6000 angstroms, for example, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, etc.

[0045] In an embodiment of the present application, a silicon thin film layer 140 is formed on the surface of the buried oxide layer 130. The silicon thin film layer 140 can be obtained by peeling off a pre-doped single crystal silicon wafer. Optionally, the doping type of the single crystal silicon wafer can be N-type doping or P-type doping. By processing the silicon thin film layer 140, an electronic device structure with a designed function can be formed thereon. Optionally, the thickness of the silicon thin film layer 140 is 500 angstroms to 1400 angstroms, for example, 500 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, etc.

[0046] In the embodiment of the present application, a surface parasitic conductive layer is generated between the bonding interface of the trap-rich layer 120 and the buried oxide layer 130 . Figure 2 is a schematic structural diagram of a radio frequency device for generating a surface parasitic conductive layer according to an exemplary embodiment. Figure 2 As shown, the device structure layer 160 of the RF device can be obtained by processing the silicon thin film layer 140, and the connection between the RF device and the external circuit is realized by arranging a metal wiring layer 170 on the device structure layer 160. In the RF device, since the material of the trap-rich layer 120 is polysilicon, the material of the buried oxide layer 130 is silicon dioxide, and there is usually Si at the interface between SiO2 and Si + The fixed positive charges in the form of SiO2-Si interface attract electrons to form a surface parasitic conductive layer. Since the resistance of the surface parasitic conductive layer is lower than the resistance of the supporting substrate 110, the equivalent resistance of the supporting substrate 110 is reduced. In order to improve this situation, at least one gap structure 150 can be formed between the buried oxide layer 130 and the trap-rich layer 120, and the gap structure 150 is used to reduce the contact area between the buried oxide layer 130 and the trap-rich layer 120.

[0047] like Figure 2As shown, when the RF signal is transmitted in the RF device, a parasitic capacitance will be coupled between the signal transmission path and the supporting substrate 110. The smaller the coupled parasitic capacitance is, the smaller the harmonic signal generated by the RF device is, and thus the loss of the RF signal is smaller. The gap structure 150 is provided between the buried oxide layer 130 and the rich trap layer 120, which can reduce the area of ​​direct contact between the buried oxide layer 130 and the rich trap layer 120, thereby reducing the area of ​​the surface parasitic conductive layer, that is, reducing the coupling area of ​​the RF signal with the surface parasitic conductive layer during the transmission of the device, so that the capacitance value of the parasitic capacitance in the RF device is reduced, thereby reducing the loss of the RF signal. In addition, the gap structure 150 is provided between the buried oxide layer 130 and the rich trap layer 120, and the surface parasitic conductive layer is cut into many independent surface parasitic conductive layers with lower resistance, which can reduce the amount of carriers in the surface parasitic conductive layer, thereby increasing the resistance value of the surface parasitic conductive layer, and further reducing the influence of the low-resistance surface parasitic conductive layer on the RF signal, such as reducing the RF signal loss and avoiding harmonic deterioration.

[0048] In an embodiment of the present application, the number of gap structures 150 may be one or more. When a plurality of gap structures 150 are included in a semiconductor structure, the spacing between adjacent gap structures 150 may be uniform or non-uniform. The cross-sectional shape of the gap structure 150 may be a regular shape such as a trapezoid, a rectangle, a semicircle, a triangle, or an irregular shape. When a plurality of gap structures 150 are included in a semiconductor structure, the cross-sectional shapes of the gap structures 150 may be the same or different. Optionally, the gap structure 150 between the buried oxide layer 130 and the trap-rich layer 120 may be obtained by etching a groove or a protruding structure on one film layer, and then bonding the groove or the protruding structure to another film layer. The gap structure 150 between the buried oxide layer 130 and the trap-rich layer 120 may also be obtained by etching a groove or a protruding structure on both film layers, and then bonding the groove or the protruding structure on the two film layers. Optionally, when a groove or a convex structure is etched on both film layers, the groove structure may be etched on one film layer and the convex structure may be etched on the other film layer. In this case, the positions of the groove structure and the convex structure do not correspond, or the shapes or sizes of the groove structure and the convex structure do not match. When a groove or a convex structure is etched on both film layers, the groove structure may be etched on one film layer and the groove structure may be etched on the other film layer. When a groove or a convex structure is etched on both film layers, the convex structure may be etched on one film layer and the convex structure may be etched on the other film layer.

[0049] As an optional implementation, Figure 1As shown, a first groove / protrusion 131 is formed on the surface of the buried oxide layer 130 in contact with the trap-rich layer 120, and the first groove / protrusion 131 contacts the trap-rich layer 120 to form a gap structure 150. In this embodiment, the number of first grooves / protrusions 131 etched in the buried oxide layer 130 can be one or more. The cross-sectional width of each first groove / protrusion 131 can be 100nm-1cm, that is, the cross-sectional width of each gap structure 150 is 100nm-1cm, for example, 100nm-1000nm, 1000nm-10000nm, 10 4 nm-10 5 nm, 10 5 nm-10 6 nm, 10 6 nm-10 7 In order to ensure the structural strength and performance of the semiconductor structure, the depth / height of the first groove / protrusion 131 does not exceed half of the thickness of the buried oxide layer 130 .

[0050] As another optional implementation, Figure 3 is a schematic structural diagram of another semiconductor structure according to an exemplary embodiment. Figure 3 As shown, a second groove / protrusion 121 is formed on the surface of the trap-rich layer 120 in contact with the buried oxide layer 130, and the second groove / protrusion 121 contacts the buried oxide layer 130 to form a gap structure 150. In this embodiment, the number of second grooves / protrusions 121 etched in the trap-rich layer 120 can be one or more. The cross-sectional width of each second groove / protrusion 121 can be 100nm-1cm, that is, the cross-sectional width of each gap structure 150 is 100nm-1cm, for example, 100nm-1000nm, 1000nm-10000nm, 10 4 nm-10 5 nm, 10 5 nm-10 6 nm, 10 6 nm-10 7 In order to ensure the structural strength and performance of the semiconductor structure, the depth / height of the second groove / protrusion 121 does not exceed half of the thickness of the trap-rich layer 120 .

[0051] In the embodiment of the present application, when the thickness of the buried oxide layer 130 is relatively thick, for example, when the thickness of the buried oxide layer 130 exceeds 4000 angstroms, there will be a large stress in the buried oxide layer 130, and under the action of the stress, the entire semiconductor structure will bend. Therefore, in order to balance the stress in the buried oxide layer 130 to avoid bending of the semiconductor structure, the stress in the buried oxide layer 130 can be balanced. Specifically, the semiconductor structure also includes a stress balancing layer 190, and the stress balancing layer 190 is formed on the surface of the supporting substrate 110 away from the trap-rich layer 120. Optionally, the material of the stress balancing layer 190 is silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride and the like. The thickness of the stress balancing layer 190 can be selected according to the material of the stress balancing layer 190 and the thickness of the buried oxide layer 130. For example, when the material of the stress balancing layer 190 is silicon dioxide, the thickness of the stress balancing layer 190 can be the same as the thickness of the buried oxide layer 130.

[0052] The present application also provides a method for forming a semiconductor structure. Figure 4 is a flow chart of a method for forming a conductor structure according to an exemplary embodiment. Figure 4 As shown, the method includes:

[0053] S201 : providing a support substrate 110 and a single crystal silicon substrate 180 .

[0054] In the embodiment of the present application, the support substrate 110 is used to support each semiconductor structure layer formed thereon. Optionally, the support substrate 110 may be, but is not limited to, a silicon substrate, a silicon oxide substrate, a sapphire substrate, a silicon carbide substrate, a quartz substrate, an aluminum nitride substrate, or a diamond substrate. The single crystal silicon substrate 180 is used as a donor substrate for the silicon thin film layer 140. The single crystal silicon substrate 180 may be pre-doped, and optionally, the doping type of the single crystal silicon substrate 180 may be N-type doping or P-type doping.

[0055] S203: forming a trap-rich layer 120 on the support substrate 110 to obtain a first multi-layer structure.

[0056] In the embodiment of the present application, the material of the trap-rich layer 120 may be amorphous silicon or polycrystalline silicon. The trap-rich layer 120 may be formed on the supporting substrate 110 by chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), etc. Figure 5 is a schematic structural diagram of a first multi-layer structure according to an exemplary embodiment. Figure 5 As shown, the trap-rich layer 120 may be formed on one surface of the support substrate 110 by vapor deposition, thereby obtaining a first multi-layer structure.

[0057] S205: forming a buried oxide layer 130 on the single crystal silicon substrate 180 to obtain a second multi-layer structure.

[0058] In the embodiment of the present application, Figure 6 is a schematic structural diagram of a second multi-layer structure according to an exemplary embodiment. Figure 6 As shown, the buried oxide layer 130 is formed on a surface of the single crystal silicon substrate 180. Optionally, the buried oxide layer 130 can be obtained by deposition, or by first forming a polysilicon layer on the trap-rich layer 120 and then thermally oxidizing the polysilicon layer.

[0059] S207 : using the surface of the buried oxide layer 130 as an ion implantation surface, ion implantation is performed on the second multi-layer structure to form a defect layer 181 in the single crystal silicon substrate 180 .

[0060] In the embodiment of the present application, Figure 7 is a schematic diagram of a structure of a second multilayer structure after ion implantation according to an exemplary embodiment. Figure 7 As shown, when ion implantation is performed on the second multilayer structure, the exposed surface of the buried oxide layer 130 can be used as the ion implantation surface to implant ions into the second multilayer structure, so as to form a defect layer 181 in the single crystal silicon substrate 180 in the second multilayer structure. Optionally, the implanted ions can be hydrogen ions, helium ions, or hydrogen and helium ions can be implanted together. The energy and ion implantation dose of the ion implantation can be selected independently as needed, and no excessive restrictions are imposed here.

[0061] In some embodiments, ion implantation may also be performed before forming the buried oxide layer 130 on the single crystal silicon substrate 180, that is, ion implantation is performed on the single crystal silicon substrate 180 with one surface of the single crystal silicon substrate 180 as the ion implantation surface, and then the buried oxide layer 130 is formed on the ion implantation surface.

[0062] S209 : etching the surface of the buried oxide layer 130 to form at least one first groove / protrusion 131 .

[0063] In the embodiment of the present application, after ion implantation is performed on the second multilayer structure, the exposed surface of the buried oxide layer 130 may be etched to form at least one first groove / protrusion 131. Optionally, the method for etching the buried oxide layer 130 may be dry etching or wet etching. As an example, Figure 8 FIG. 1 is a schematic diagram showing a structure after etching the surface of the buried oxide layer 130 according to an exemplary embodiment. Figure 8 As shown, the exposed surface of the buried oxide layer 130 may be photolithographically processed, and the photolithographic pattern may be rectangular or circular. Then, the surface of the buried oxide layer 130 after photolithography may be dry-etched or wet-etched to form the first groove / protrusion 131. Optionally, the cross-sectional shape of the first groove / protrusion 131 may be a regular shape such as a trapezoid, rectangle, semicircle, triangle, etc., or may be an irregular shape.

[0064] S211: Bonding the first multilayer structure and the second multilayer structure to obtain a semiconductor structure; wherein, after the surface of the buried oxide layer 130 contacts the surface of the trap-rich layer 120, at least one gap structure 150 is obtained, and the gap structure 150 is used to reduce the contact area between the buried oxide layer 130 and the trap-rich layer 120.

[0065] In the embodiment of the present application, when the first multilayer structure and the second multilayer structure are bonded to obtain a semiconductor structure, the first multilayer structure and the second multilayer structure can be bonded to obtain a third multilayer structure. The third multilayer structure is then heat treated to separate the single crystal silicon substrate in the third multilayer structure along the defect layer to obtain a semiconductor structure.

[0066] In the embodiment of the present application, Fig. 9 is a schematic structural diagram of a third multi-layer structure according to an exemplary embodiment. Fig. 9As shown, after the etching of the buried oxide layer 130 is completed, the first multilayer structure and the second multilayer structure can be bonded to obtain a third multilayer structure. When the first multilayer structure and the second multilayer structure are bonded, the surface of the buried oxide layer 130 is bonded to the surface of the trap-rich layer 120. Optionally, the bonding method includes but is not limited to hydrophilic direct bonding, dielectric layer indirect bonding, surface activation bonding, etc. After the first multilayer structure and the second multilayer structure are bonded, at least one gap structure 150 appears in the obtained third multilayer structure.

[0067] In some embodiments, before bonding the first multi-layer structure and the second multi-layer structure, the surface of the trap-rich layer 120 in the first multi-layer structure may be etched to form at least one second groove / protrusion 121 .

[0068] In some other embodiments, before bonding the first multilayer structure and the second multilayer structure, a stress balancing layer 190 may be formed on the supporting substrate 110 in the first multilayer structure. The stress balancing layer 190 is formed on a surface of the supporting substrate 110 away from the trap-rich layer 120 .

[0069] In the embodiment of the present application, after obtaining the third multilayer structure, the third multilayer structure can be heat treated to obtain Figure 1 Specifically, the third multilayer structure is subjected to an annealing treatment once, so that the single crystal silicon substrate 180 in the third multilayer structure is separated along the defect layer 181, thereby obtaining an initial semiconductor structure. Then, the initial semiconductor structure is subjected to a secondary annealing treatment, thereby obtaining a semiconductor structure.

[0070] In the embodiment of the present application, when the third multilayer structure is subjected to an annealing treatment, the annealing treatment can be carried out in a vacuum environment or in a protective atmosphere, such as a protective atmosphere such as nitrogen, argon, or hydrogen. The temperature of the annealing treatment can be 200°C-900°C, such as 200°C, 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, etc. The annealing treatment time can be 1min-24h. By performing an annealing treatment on the third multilayer structure, recrystallization and defect merging can occur in the ion implantation area, and the hydrogen or helium pressure formed in the hole obtained by defect merging will cause the single crystal silicon substrate 180 to split into two parts, one part is a single crystal silicon thin film bonded to the buried oxide layer 130, and the other part is the single crystal silicon substrate 180 residual material.

[0071] In some embodiments, after obtaining the initial semiconductor structure, the defect layer 181 on the surface of the single crystal silicon film in the initial semiconductor structure can also be removed to obtain the silicon film layer 140 bonded to the buried oxide layer 130. Optionally, the method for removing the defect layer 181 on the surface of the single crystal silicon film can be a combination of one or more of chemical mechanical polishing, ion beam etching, mechanical grinding, chemical wet etching, etc. For the remaining single crystal silicon substrate 180 after stripping the single crystal silicon film, the stripping surface can be surface treated so that it can be recycled, and the remaining single crystal silicon substrate 180 can be reused to strip the single crystal silicon film later, thereby reducing the process cost.

[0072] In the embodiment of the present application, when the initial semiconductor structure is subjected to a secondary annealing treatment, the annealing temperature may be 1000° C.-1300° C., such as 1000° C., 1050° C., 1100° C., 1150° C., 1200° C., 1250° C., 1300° C., etc. By performing a secondary annealing treatment on the initial semiconductor structure, the bonding strength between the buried oxide layer 130 and the trap-rich layer 120 may be enhanced.

[0073] The present application also provides another method for forming a semiconductor structure. Fig.10 is a flow chart of another method for forming a conductor structure according to an exemplary embodiment. Fig.10 As shown, the method includes:

[0074] S301 : providing a supporting substrate 110 .

[0075] In the embodiment of the present application, the support substrate 110 is used to support each semiconductor structure layer formed thereon. Optionally, the support substrate 110 may be, but is not limited to, a silicon substrate, a silicon oxide substrate, a sapphire substrate, a silicon carbide substrate, a quartz substrate, an aluminum nitride substrate, or a diamond substrate.

[0076] S303 : forming a trap-rich layer 120 on the support substrate 110 .

[0077] In the embodiment of the present application, the material of the trap-rich layer 120 may be amorphous silicon or polycrystalline silicon. The trap-rich layer 120 may be formed on the support substrate 110 by vapor deposition, such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, etc.

[0078] In other embodiments, Fig.11 1 is a schematic diagram showing a structure of forming a trap-rich layer 120 and a stress-balancing layer 190 on a support substrate 110 according to an exemplary embodiment. Fig.11As shown, before forming the trap-rich layer 120 on the support substrate 110 , a stress-balancing layer 190 may be formed on one surface of the support substrate 110 . Then, the trap-rich layer 120 is formed on another surface of the support substrate 110 , that is, the surface away from the stress-balancing layer 190 .

[0079] In some embodiments, the trap-rich layer 120 may be formed on one side of the support substrate 110 first, and then the stress-balancing layer 190 may be formed on the other surface of the support substrate 110 .

[0080] S305 : etching the surface of the trap-rich layer 120 to form at least one second groove / protrusion 121 .

[0081] In the embodiment of the present application, Fig.12 FIG. 1 is a schematic diagram showing a structure after etching the surface of the trap-rich layer 120 according to an exemplary embodiment. Fig.12 As shown, after forming the rich trap layer 120 on the supporting substrate 110, the exposed surface of the rich trap layer 120 can be etched to form at least one second groove / protrusion 121. Optionally, the method for etching the rich trap layer 120 can be dry etching or wet etching. As an example, the exposed surface of the rich trap layer 120 can be photolithography first, and the photolithography pattern can be rectangular or circular. Then, the surface of the rich trap layer 120 after photolithography is dry-etched or wet-etched to form the second groove / protrusion 121. The cross-sectional shape of the second groove / protrusion 121 can be a regular shape such as a trapezoid, a rectangle, a semicircle, a triangle, etc., or it can be an irregular shape.

[0082] S307 : forming a buried oxide layer 130 on the trap-rich layer 120 ; wherein, after the surface of the buried oxide layer 130 contacts the surface of the trap-rich layer 120 , at least one gap structure 150 is obtained, and the gap structure 150 is used to reduce the contact area between the buried oxide layer 130 and the trap-rich layer 120 .

[0083] In the embodiment of the present application, after the etching of the trap-rich layer 120 is completed, a buried oxide layer 130 may be formed on the trap-rich layer 120. Optionally, the buried oxide layer 130 may be formed by deposition, or by first forming a polysilicon layer on the trap-rich layer 120 and then thermally oxidizing the polysilicon layer.

[0084] In some embodiments, the buried oxide layer 130 may also be bonded to the trap-rich layer 120 by bonding. For example, the buried oxide layer 130 may be first formed on another substrate, and then the exposed surface of the buried oxide layer 130 may be bonded to the trap-rich layer 120. Then, the substrate is removed to form the buried oxide layer 130 on the trap-rich layer 120. Optionally, the substrate may be a supporting substrate 110 after ion implantation, which may serve as a donor substrate for the silicon thin film layer 140. Optionally, before the exposed surface of the buried oxide layer 130 is bonded to the trap-rich layer 120, the exposed surface of the buried oxide layer 130 may be etched to form at least one first groove / protrusion 131.

[0085] In the embodiment of the present application, after the buried oxide layer 130 is formed on the trap-rich layer 120 , at least one gap structure 150 may be formed.

[0086] S309: forming a silicon thin film layer 140 on the buried oxide layer 130 to obtain a semiconductor structure.

[0087] In the embodiment of the present application, after forming the buried oxide layer 130 on the trap-rich layer 120, a silicon thin film layer 140 may be formed on the buried oxide layer 130 to obtain Figure 3 The semiconductor structure shown in FIG. 1 is a semiconductor structure shown in FIG. 1. Optionally, the silicon thin film layer 140 formed on the buried oxide layer 130 may be obtained by deposition or by silicon thin film stripping.

[0088] As an optional embodiment, when forming the silicon thin film layer 140 on the buried oxide layer 130, a single crystal silicon substrate 180 may be provided first, and the single crystal silicon substrate 180 is used as a donor substrate for the silicon thin film layer 140. The single crystal silicon substrate 180 may be doped in advance, and optionally, the doping type of the single crystal silicon substrate 180 may be N-type doping or P-type doping. Then, ion implantation is performed on the single crystal silicon substrate 180 to form a defect layer 181 in the single crystal silicon substrate 180. Optionally, the implanted ions may be hydrogen ions, helium ions, or hydrogen and helium ions may be implanted together. The energy and ion implantation dose of the ion implantation may be selected independently as needed, and are not restricted too much here. Then, the ion implantation surface in the single crystal silicon substrate 180 is bonded to the buried oxide layer 130 to obtain a bonding structure. Optionally, the bonding method includes but is not limited to hydrophilic direct bonding, dielectric layer indirect bonding, surface activation bonding, etc. Then, the semiconductor structure is obtained by heat treating the bonding structure.

[0089] In the embodiment of the present application, when the bonding structure is subjected to heat treatment, the bonding structure may be subjected to an annealing treatment to separate the single crystal silicon substrate 180 in the bonding structure along the defect layer 181 to obtain an initial semiconductor structure. The initial semiconductor structure is then subjected to a secondary annealing to obtain a semiconductor structure.

[0090] In the embodiment of the present application, when the bonding structure is subjected to an annealing treatment, the annealing treatment can be performed in a vacuum environment or in a protective atmosphere, such as nitrogen, argon, hydrogen and other protective atmospheres. The temperature of the annealing treatment can be 200°C-900°C, such as 200°C, 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, etc. The annealing treatment time can be 1min-24h. By performing an annealing treatment on the bonding structure once, recrystallization and defect merging can occur in the ion implantation area. The hydrogen or helium pressure formed in the hole obtained by defect merging will cause the single crystal silicon substrate 180 to split into two parts, one part is the single crystal silicon film bonded to the buried oxide layer 130, and the other part is the single crystal silicon substrate 180 residual material.

[0091] In some embodiments, after obtaining the initial semiconductor structure, the defect layer 181 on the surface of the single crystal silicon film in the initial semiconductor structure can be removed to obtain the silicon film layer 140 bonded to the buried oxide layer 130. Then, by performing a secondary annealing treatment on the initial semiconductor structure, the bonding strength between the buried oxide layer 130 and the trap-rich layer 120 can be enhanced.

[0092] An embodiment of the present application also provides a radio frequency device, which includes the semiconductor structure as described above.

[0093] The radio frequency device described in the embodiment of the present application may be a radio frequency switch tube, a low noise amplifier (LNA) and other devices. The radio frequency device, because it includes the above-mentioned semiconductor structure, is provided with a rich trap layer between the supporting substrate and the buried oxide layer in the semiconductor structure. Because there are many defect states in the rich trap layer, the resistance of the supporting substrate is greatly reduced due to the surface parasitic conductive layer. And at least one gap structure is formed between the buried oxide layer and the rich trap layer, and the gap structure is used to reduce the contact area between the buried oxide layer and the rich trap layer, thereby reducing the area of ​​the surface parasitic conductive layer, that is, reducing the coupling area of ​​the radio frequency signal with the surface parasitic conductive layer during the transmission process in the device. Moreover, due to the presence of the gap structure, the surface parasitic conductive layer is cut into many independent surface parasitic conductive layers with lower resistance, which can increase the resistance value of the surface parasitic conductive layer, thereby further reducing the influence of the low-resistance surface parasitic conductive layer on the radio frequency signal. Therefore, the radio frequency device also has similar advantages.

[0094] An embodiment of the present application further provides an electronic device, which includes the radio frequency device as described above.

[0095] The electronic device described in the embodiments of the present application may be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, an intelligent voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, or any intermediate product including the above-mentioned storage device.

[0096] The electronic device described in the embodiment of the present application includes the above-mentioned radio frequency device, and the radio frequency device includes the above-mentioned semiconductor structure. In the semiconductor structure, a trap-rich layer is provided between the supporting substrate and the buried oxide layer. Since there are many defect states in the trap-rich layer, the resistance of the supporting substrate is prevented from being greatly reduced due to the surface parasitic conductive layer. At least one gap structure is formed between the buried oxide layer and the trap-rich layer. The gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer, thereby reducing the area of ​​the surface parasitic conductive layer, that is, reducing the coupling area between the radio frequency signal and the surface parasitic conductive layer during the transmission process in the device. Moreover, due to the existence of the gap structure, the surface parasitic conductive layer is cut into many independent surface parasitic conductive layers with lower resistance, which can increase the resistance value of the surface parasitic conductive layer, thereby further reducing the influence of the low-resistance surface parasitic conductive layer on the radio frequency signal. Therefore, the electronic device also has similar advantages.

[0097] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0098] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0099] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0100] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: supporting substrate, trap-rich layer, buried oxide layer and silicon thin film layer; The trap-rich layer is formed on the surface of the support substrate, the buried oxide layer is formed on the surface of the trap-rich layer, and the silicon thin film layer is formed on the surface of the buried oxide layer; At least one gap structure is formed between the buried oxide layer and the trap-rich layer, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer.

2. The semiconductor structure according to claim 1, characterized in that: A first groove / protrusion is formed on the surface of the buried oxide layer in contact with the trap-rich layer, and the first groove / protrusion is in contact with the trap-rich layer to form the gap structure.

3. The semiconductor structure according to claim 1, characterized in that: A second groove / protrusion is formed on the surface of the trap-rich layer in contact with the buried oxide layer, and the second groove / protrusion is in contact with the buried oxide layer to form the gap structure.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The cross-sectional shape of the gap structure includes at least one of a trapezoid, a rectangle, a semicircle, and a triangle.

5. The semiconductor structure according to claim 4, characterized in that: The cross-sectional width of a single gap structure is 100 nm-1 cm.

6. The semiconductor structure according to claim 1, characterized in that The thickness of the trap-rich layer is 1.5 μm-3 μm; the thickness of the buried oxide layer is 1000 angstroms-6000 angstroms; and the thickness of the silicon thin film layer is 500 angstroms-1400 angstroms.

7. The semiconductor structure according to claim 1, characterized in that: The support substrate is one of a silicon substrate, a silicon oxide substrate, a sapphire substrate, a silicon carbide substrate, a quartz substrate, an aluminum nitride substrate, and a diamond substrate.

8. The semiconductor structure according to claim 1 or 7, characterized in that: The trap-rich layer is made of amorphous silicon or polycrystalline silicon.

9. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a stress-balancing layer formed on a surface of the supporting substrate away from the trap-rich layer.

10. The semiconductor structure according to claim 9, characterized in that: The material of the stress balance layer is silicon oxide or silicon nitride.

11. A method for forming a semiconductor structure, characterized in that: include: providing a supporting substrate and a single crystal silicon substrate; forming a trap-rich layer on the supporting substrate to obtain a first multilayer structure; forming a buried oxide layer on the single crystal silicon substrate to obtain a second multilayer structure; Using the surface of the buried oxide layer as an ion implantation surface, ion implantation is performed on the second multilayer structure to form a defect layer in the single crystal silicon substrate; Etching the surface of the buried oxide layer to form at least one first groove / protrusion; The first multilayer structure and the second multilayer structure are bonded to obtain a semiconductor structure; wherein, after the surface of the buried oxide layer contacts the surface of the trap-rich layer, at least one gap structure is obtained, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer.

12. The method according to claim 11, characterized in that Before bonding the first multilayer structure and the second multilayer structure to obtain a third multilayer structure, the method further includes: A stress-balancing layer is formed on a supporting substrate in the first multi-layer structure; the stress-balancing layer is formed on a surface of the supporting substrate away from the trap-rich layer.

13. The method according to claim 11 or 12, characterized in that: The step of bonding the first multilayer structure and the second multilayer structure to obtain a semiconductor structure comprises: bonding the first multilayer structure and the second multilayer structure to obtain a third multilayer structure; The third multi-layer structure is subjected to heat treatment so that the single crystal silicon substrate in the third multi-layer structure is separated along the defective layer to obtain a semiconductor structure.

14. The method according to claim 13, characterized in that The step of heat-treating the third multilayer structure so as to separate the single crystal silicon substrate in the third multilayer structure along the defective layer to obtain a semiconductor structure comprises: Performing an annealing treatment on the third multilayer structure so as to separate the single crystal silicon substrate in the third multilayer structure along the defective layer to obtain an initial semiconductor structure; The initial semiconductor structure is subjected to secondary annealing to obtain the semiconductor structure.

15. A method for forming a semiconductor structure, characterized in that: include: providing a supporting substrate; forming a trap-rich layer on the supporting substrate; Etching the surface of the trap-rich layer to form at least one second groove / protrusion; forming a buried oxide layer on the trap-rich layer; wherein, after the surface of the buried oxide layer contacts the surface of the trap-rich layer, at least one gap structure is obtained, and the gap structure is used to reduce the contact area between the buried oxide layer and the trap-rich layer; A silicon thin film layer is formed on the buried oxide layer to obtain a semiconductor structure.

16. The method according to claim 15, characterized in that The step of forming a silicon thin film layer on the buried oxide layer to obtain a semiconductor structure comprises: Providing a single crystal silicon substrate; Performing ion implantation on the single crystal silicon substrate to form a defect layer in the single crystal silicon substrate; Bonding the single crystal silicon substrate and the buried oxide layer to obtain a bonding structure; The bonding structure is subjected to heat treatment so that the single crystal silicon substrate in the bonding structure is separated along the defect layer to obtain a semiconductor structure.

17. A radio frequency device, characterized in that: The radio frequency device comprises the semiconductor structure according to any one of claims 1 to 10.

18. An electronic device, characterized in that: The electronic device comprises the radio frequency device as claimed in claim 17.

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