Image sensor

Abstract

The invention relates to an image sensor comprising a plurality of pixels (100) formed inside and on top of a semiconductor substrate (104), each pixel comprising:-a photosensitive region (102) formed in the semiconductor substrate (104); -a peripheral insulating trench (106) extending vertically in the semiconductor substrate (104) from an upper surface of the semiconductor substrate and laterally defining the photosensitive region (102); -a charge collection region (110); -a transfer region (114) located in the semiconductor substrate (104) and extending vertically between the charge collection region (110) and the photosensitive region (102); and a transfer gate (108) extending vertically in the semiconductor substrate (104) from an upper surface of the semiconductor substrate and an interior of the peripheral insulating trench (106), the peripheral insulating trench (106) being deeper than the charge collection region (110), in which the transfer region (114) is doped with the same first conductivity type as the photosensitive region (102) and has a doping level lower than that of the photosensitive region.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices and, more particularly, to image sensor pixels. Background Art

[0002] Image sensor pixels have been provided, each pixel comprising a photosensitive region formed in a semiconductor substrate, adapted to convert light into electron-hole pairs. During an exposure phase of the sensor, photogenerated charges (electrons or holes) accumulate in the photosensitive region. During a subsequent readout phase, a charge transfer device is controlled to transfer the photogenerated charges accumulated in the photosensitive region to a charge collection region.

[0003] U.S. Patent Application 2021 / 0020675 describes an example of such a pixel. In this application, each pixel more precisely includes a photosensitive region formed in a semiconductor substrate and laterally bounded by a peripheral insulating trench. Each pixel also includes a charge collection region laterally inserted between a vertical transfer gate formed in the peripheral insulating trench and an injection region formed in the semiconductor substrate above the photosensitive region. The photosensitive region and the charge collection region are P-type doped, and the injection region is N-type doped. In this example, a P-doped transfer region with a doping level equal to the doping level of the photosensitive region is vertically inserted between the photosensitive region and the charge collection region. By applying an electric potential to the vertical transfer gate of the pixel, a potential barrier can be formed in the transfer region between the vertical transfer gate and the injected N-type region. However, this image sensor pixel exhibits various disadvantages, in particular due to the difficulty in forming the N-type injection region in a precise manner. This complicates the reduction of the pixel pitch of the image sensor. In addition, this type of pixel has a relatively high dark current, which will need to be reduced. Summary of the invention

[0004] There is a need to overcome all or some of the disadvantages of image sensor pixels and known image sensors. It is particularly desirable to reduce pixel size to enable the formation of image sensors having a pixel pitch that is smaller than the pixel pitch of existing image sensors.

[0005] To this end, one embodiment provides an image sensor comprising a plurality of pixels formed within and on top of a semiconductor substrate, each pixel comprising:

[0006] - a photosensitive region formed in a semiconductor substrate;

[0007] - a peripheral insulating trench extending vertically in the semiconductor substrate from an upper surface of the semiconductor substrate and laterally delimiting the photosensitive area;

[0008] - Charge collection area;

[0009] - a transfer region located in the semiconductor substrate and extending vertically between the charge collection region and the photosensitive region; and

[0010] - a transfer gate extending vertically from an upper surface of the semiconductor substrate and inside a peripheral insulating trench (deeper than the charge collection region) in the semiconductor substrate,

[0011] The transfer region is doped with the same first conductivity type as the photosensitive region and has a doping level lower than the doping level of the photosensitive region.

[0012] According to one embodiment, the transfer gate extends vertically downward in the semiconductor substrate to a depth substantially equal to the depth of the transfer region.

[0013] According to one embodiment, the photosensitive region and the transfer region have a substantially horizontal interface.

[0014] According to one embodiment, the charge collecting region is doped with the first conductivity type and has a doping level that is higher than the doping level of the transfer region.

[0015] According to one embodiment, the sensor further includes a doped well of a second conductivity type opposite to the first conductivity type extending vertically in the semiconductor substrate from an upper surface of the semiconductor substrate down to a depth less than a depth of the transfer gate.

[0016] According to one embodiment, the sensor further comprises an electrically insulating trench laterally interposed between the charge collecting region and the well.

[0017] According to one embodiment, the electrically insulating trench extends vertically in the semiconductor substrate, from an upper surface of the semiconductor substrate, downwardly to a depth greater than a depth of the charge collecting region.

[0018] According to one embodiment, the charge collecting region and the well are adjacent.

[0019] According to one embodiment, the peripheral isolation trench and the transfer gate include a first conductive region and a second conductive region, respectively, the first conductive region being electrically insulated from the second conductive region.

[0020] According to one embodiment, the second conductive region is flush with the upper surface of the semiconductor substrate.

[0021] According to one embodiment, the second conductive region is separated from the upper surface of the semiconductor substrate by a non-zero thickness of insulating material.

[0022] According to one embodiment, the transfer gate is common to both pixels.

[0023] According to one embodiment, the transfer gate is common to four pixels.

[0024] According to one embodiment, the first conductivity type is N-type.

[0025] According to one embodiment, the sensor further comprises a control circuit configured to alternately apply to the transfer gate:

[0026] - a first potential adapted to prevent the transfer of charges from the photosensitive region to the charge collection region; and

[0027] - a second electrical potential, different from the first electrical potential, adapted to allow transfer of charges from the photosensitive region to the charge collecting region. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above features and advantages and other features and advantages will be described in detail in the remainder of the specific embodiments which are given by way of example and not limitation and with reference to the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B 1 is a simplified view and a partial view of an example of an image sensor pixel according to an embodiment, a top view and a view along the Figure 1A A cross-sectional view of plane BB;

[0030] Figure 2A and Figure 2B 1 is a simplified view and a partial view of an example of an image sensor pixel according to an embodiment, a top view and a view along the Figure 2A A cross-sectional view of plane BB;

[0031] Figure 3A and Figure 3B 1 is a simplified view and a partial view of an example of an image sensor pixel according to an embodiment, a top view and a view along the Figure 3A A cross-sectional view of plane BB;

[0032] Figure 4 is a simplified and partial top view of an arrangement of two adjacent pixels according to an embodiment; and

[0033] Figure 5 is a simplified and partial top view of an arrangement of four adjacent pixels according to an embodiment. DETAILED DESCRIPTION

[0034] In the various drawings, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and may be provided with the same structure, dimensions, and material properties.

[0035] For the sake of clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail. In particular, the method of manufacturing image sensor pixels has not been described in detail, and the described embodiments and variants are compatible with conventional image sensor pixel manufacturing methods. In addition, the circuitry (transistors and connections) of the pixels has not been described in detail, and the described embodiments and variants are compatible with conventional pixel circuitry. In addition, the readout circuitry or column decoders, control circuitry or row decoders, and applications that can provide image sensors have not been described in detail, and the described embodiments and variants are compatible with conventional image sensor readout circuitry and control circuitry and conventional applications for implementing image sensors.

[0036] Unless otherwise stated, when referring to two elements being connected together, this means a direct connection without any intervening elements other than conductors, and when referring to two elements being coupled together, this means the two elements can be connected, or they can be coupled via one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers (such as “front”, “back”, “up”, “down”, “left”, “right”, etc.), or relative position qualifiers (such as “top”, “bottom”, “above” and “below”, etc.), or orientation qualifiers (such as “horizontal”, “vertical”, etc.), reference is made to the orientation of the drawing unless otherwise specified.

[0038] Unless otherwise specified, the words "approximately," "substantially," and "about" mean plus or minus 10%, preferably plus or minus 5%.

[0039] Figure 1A and Figure 1B are simplified views and partial views of an example of an image sensor pixel 100 according to an embodiment, a top view and a view along the Figure 1A Cross-sectional view of plane BB.

[0040] In the example shown, the pixel 100 comprises a photosensitive region 102 or a photoconversion region. The photosensitive region 102 is intended, for example, to collect photons during an illumination phase of an image sensor having the pixel 100 belonging thereto and to convert these photons into electron-hole pairs. In a top view, the photosensitive region 102 is located in the center of the pixel 100 and has a substantially square periphery. However, this example is not limiting and, as a variant, the photosensitive region 102 may have a periphery of any shape, for example a rectangle or a circle.

[0041] The photosensitive region 102 is formed in a substrate 104. The substrate 104 is made of a semiconductor material, such as silicon. As an example, the substrate 104 is formed by epitaxial growth or epitaxy of a layer made of a semiconductor material on a surface of a wafer or one side of a piece of a wafer of semiconductor material (such as silicon). As an example, the substrate 104 has a thickness in the range from 1 to 20 μm.

[0042] The substrate 104 is doped with a first conductivity type, such as an N-type. In this case, the substrate 104 is doped with arsenic atoms, for example. As an example, the doping level or doping rate of the substrate 104 is in the range of 1×10 10 Up to 1x10 18 at. / cm 3 within the range.

[0043] The photosensitive area is intended to be, for example, from the bottom side of the substrate 104 in a Figure 1B As a variant, the photosensitive area can be directed from the upper side of the substrate 104 in a Figure 1B Directional irradiation. Figure 1B Although not shown, the underside of the substrate 104 may be coated with one or more passivation layers. In addition, the pixel 100 may include optical elements, such as filters (eg, color filters) and / or microlenses, on the lower surface side of the substrate 104.

[0044] In the example shown, the pixel 100 includes a peripheral insulating trench 106, such as a capacitive insulating trench, which laterally delimits the photosensitive area 102. As an example, the peripheral insulating trench 106 is a trench of the capacitive deep trench insulation (CDTI) type. In a top view, the peripheral insulating trench 106 has an annular shape that completely surrounds the photosensitive area 102 on all its side walls or flanks. The peripheral insulating trench 106 has a periphery with the same shape as the photosensitive area 102, i.e. a square in the example shown. However, this example is not restrictive, and as a variant, the peripheral insulating trench 106 can have a periphery of any shape, such as a rectangle or a circle. In the example shown, the peripheral insulating trench 106 includes four parts corresponding to the four sides of the square formed by the trench 106, respectively.

[0045] The peripheral insulating trench 106 is particularly capable of electrically insulating the photosensitive region 102 of the pixel 100 from the photosensitive regions of adjacent pixels. Figure 1A and 1B The peripheral insulation trench 106 is formed in, for example, the substrate 104. Figure 1B In the direction of , the peripheral insulation trench 106 extends vertically through the thickness of the substrate 104, from the upper surface of the substrate 104 to the lower surface of the substrate 104. In other words, in this example, the peripheral insulation trench 106 extends vertically through the entire thickness of the substrate 104.

[0046] The peripheral insulation trench 106 has, for example, a width in the range from 20 nm to 300 nm, for example equal to about 160 nm, and a depth in the range from 10 nm to 20 μm. Figure 1B In the example shown, the peripheral isolation trench 106 has a depth equal to the thickness of the substrate 104 .

[0047] In the example shown, the peripheral insulating trench 106 includes a conductive region 106C. As an example, the conductive region 106C of the peripheral insulating trench 106 is made of polysilicon, metal (e.g., copper), or a metal alloy. In the case where the region 106C is made of polysilicon, the region 106C has, for example, a doping rate greater than or equal to 1×10 18 at. / cm 3 .

[0048] In this example, the peripheral isolation trench 106 further includes an electrical insulation layer 106I coating the sidewalls of the conductive region 106C. The electrical insulation layer 106I electrically insulates the conductive region 106C from the substrate 104. As an example, the electrical insulation layer 106I is made of a dielectric material, such as silicon oxide.

[0049] In the example shown, the pixel 100 also includes a vertical transfer gate 108 formed inside the peripheral insulating trench 106. In a top view, the vertical transfer gate 108 is, for example, located on one side of the square formed by the peripheral insulating trench 106 ( Figure 1B ). In the example shown, the vertical transfer gate 108 includes a conductive region 108C extending vertically through the thickness of the substrate 104, from the upper surface of the substrate 104, down to a depth less than the depth of the peripheral isolation trench 106. As an example, the vertical transfer gate 108 has a depth or height in the range from 0.2 μm to 1.5 μm.

[0050] The conductive region 108C of the vertical transfer gate 108 is electrically insulated from the conductive region 106C of the peripheral insulation trench 106. In the example shown, the sidewalls and the bottom of the conductive region 108C of the vertical transfer gate 108 are coated with the electrical insulation layer 106I of the peripheral insulation trench 106. In addition, in this example, the conductive region 108C of the vertical transfer gate 108 is flush with the upper surface of the substrate 104. As an example, the conductive region 108C of the vertical transfer gate 108 is made of polysilicon, a metal (e.g., copper), or a metal alloy. In the case where the region 108C is made of polysilicon, the region 108C, for example, has a doping level greater than or equal to 1×10 18 at. / cm 3 .

[0051] In the example shown, the pixel 100 also includes a charge collection region 110 extending vertically in the semiconductor substrate 104, extending from its upper surface downwardly to a depth that is less than the depth of the conductive region 108C of the vertical transfer gate 108. In the example shown, the charge collection region 110 has a substantially square periphery in a top view. However, this example is not limiting, and as a variant, the charge collection region 110 may include a periphery having any shape, such as a rectangle or a circle. As an example, the square formed by the charge collection region 110 has a side length in the range from 100 nm to 200 nm, for example equal to about 170 nm.

[0052] In the example shown, the charge collecting region 110 is surrounded by an electrically insulating trench 112. The insulating trench 112 extends vertically in the semiconductor substrate 104, extending from its upper surface downwardly to a depth greater than the depth of the charge collecting region 110 and less than the depth of the conductive region 108C of the vertical transfer gate 108. In the example shown, the electrically insulating trench 112 coats three of the four side surfaces of the charge collecting region 110, the fourth side surface of the charge collecting region 110 being covered by the electrically insulating layer 106I of the peripheral insulating trench 106. The insulating trench 112 is, for example, based on an oxide, such as silicon oxide. As an example, the insulating trench 112 has a width equal to about 40 nm.

[0053] The charge collection region 110 is doped with a first conductivity type (in this example, N-type) and has, for example, a doping level higher than that of the photosensitive region 102. As an example, the doping level of the charge collection region 110 is in the range of 1×10 16 Up to 5x10 20 at. / cm 3 within the range.

[0054] In the example shown, the pixel 100 also includes a transfer region 114 formed in the substrate 104 and extending vertically between the charge collection region 110 and the photosensitive region 102. The transfer region 114 extends, for example, through the thickness of the substrate 104, down to a depth substantially equal to the depth of the conductive region 108C of the transfer gate 108. In the example shown, the transfer region 114 has a substantially square periphery in a top view. However, this example is not limiting, and as a variant, the transfer region 114 may include a periphery having any shape, such as a rectangle or a circle. In the example shown, three of the four sides of the square formed by the transfer region 114 are laterally bounded by the peripheral insulating trench 106, and the fourth side of the transfer region 114 is substantially laterally bounded by the vertical transfer gate 108.

[0055] According to one embodiment, the transfer region 114 is doped with a first conductivity type (in this example, N-type) and has a doping level lower than the doping level of the photosensitive region 102. In addition, the doping level of the transfer region 114 is, for example, lower than the doping level of the charge collection region 110. As an example, the transfer region 114 has a doping level ranging from 1×10 10 Up to 9x10 17 at. / cm 3 within the range.

[0056] Advantageously, the highest possible doping level gradient is formed at the interface between the photosensitive region 102 and the transfer region 114 (the so-called "abrupt" interface). Furthermore, in the example shown, the interface between the transfer region 114 and the photosensitive region 102 is substantially horizontal and is located at a depth approximately equal to the depth to which the vertical transfer gate 108 extends downward. N-type doping of the photosensitive region 102, the transfer region 114 and the charge collection region 110 is preferred because the atoms used to obtain the N-type doping (e.g., arsenic atoms) diffuse less than the atoms used to obtain the P-type doping (e.g., boron atoms). The fact that the photosensitive region 102, the transfer region 114 and the charge collection region 110 are arranged as N-type doping advantageously enables the interface between the photosensitive region 102 and the transfer region 114 to be more abrupt than in the case of P-type doping. However, the diffusion of boron atoms can be limited by using a reduced thermal budget in the manufacture of the pixel 100, or by introducing chemical elements that can prevent the diffusion of boron atoms.

[0057] In the example shown, the pixel 100 further comprises a well 116 extending vertically through the thickness of the substrate 104, from its upper surface, downwardly to a depth less than the depth of the vertical transfer gate 108, for example downwardly to a depth substantially equal to the depth of the charge collection region 110. In the example shown, the well 116 is laterally delimited by the peripheral insulating trench 106 and the insulating trench 112, the insulating trench being laterally inserted between the charge collection region 110 and the well 116. The well 116 is doped with a second conductivity type (in this example, P-type) opposite to the first conductivity type. In the case where the well 116 is doped with P-type, the doping is obtained, for example, by boron atoms. As an example, the well 116 has a doping level ranging from 1×10 16 Up to 1x10 19 at. / cm 3 within the range.

[0058] In the example shown, the insulating trench 112 advantageously enables avoiding or attenuating field effects between the charge collection region 110 and the well 116 .

[0059] In the example shown, the pixel 100 includes another well 118 formed in the well 116 and extending vertically through the thickness of the substrate 104, from its upper surface, downwardly to a depth less than the depth of the well 116. The well 118 is formed in one of the corners of the well 116 opposite the vertical transfer gate 108. In practice, the well 118 may extend laterally inside the peripheral insulating trench 106, as in the example shown. The well 118 is doped with a second conductivity type (in this example, P-type) and has a higher doping level than the doping level of the well 116. As an example, the doping level of the well 118 ranges from 1x10 17 Up to 5x10 20 at. / cm 3 within the range.

[0060] In the example shown, the pixel 100 also includes contact elements 120A, 120B, 120C and 120D, such as conductive pads, formed on and in contact with the top of the conductive region 106C of the peripheral insulating trench 106, the conductive region 108C of the vertical transfer gate 108, the charge collection region 110 and the well 118, respectively. In the example shown, each contact element 120A, 120B, 120C, 120D has a substantially square periphery in a top view. However, this example is not restrictive, and as a variant, each contact element 120A, 120B, 120C, 120D can have a periphery of any shape, such as a rectangle or a circle. The contact elements 120A, 120B, 120C and 120D are made of a conductive material, such as a metal (e.g., copper) or a metal alloy. As an example, each contact element 120A, 120B, 120C, 120D has a maximum lateral dimension (eg, side length in the illustrated example where each contact element is square) equal to approximately 90 nm.

[0061] During the exposure or accumulation phase of the pixel 100, electron-hole pairs are created, for example, in the photosensitive region 102. During this phase, the conductive region 106C of the peripheral insulating trench 106 and the conductive region 108C of the vertical transfer gate 108 are taken to the potentials V_CDTI and V_TG_OFF, respectively. In the example shown, the potentials V_CDTI and V_TG_OFF are applied by contact elements 120A and 120B, respectively. The potential V_TG_OFF is, for example, substantially equal to the potential V_CDTI. During the exposure phase, the application of the potentials V_CDTI and V_TG_OFF to the conductive regions 106C and 108C enables the formation of a potential barrier in a transfer region 114 between the photosensitive region 102 and the charge collection region 110. In the example shown, the transfer region 114 is defined by the inner sidewalls of the peripheral insulating trench 106 and the vertical transfer gate 108 and extends vertically through the thickness of the substrate 104 below the charge collection region 110. In other words, in top view, the potential barrier formed by the peripheral isolation trench 106 and the vertical transfer gate 108 extends laterally over the entire surface of the transfer region 114 .

[0062] The presence of a potential barrier in the transfer region 114 makes it possible to prevent the transfer of photogenerated carriers (electrons in the case where the photosensitive region 102, the transfer region 114 and the charge collection region 110 are N-type) from the photosensitive region 102 to the charge collection region 110 during the exposure phase. The potential barrier is created by the presence of an inversion layer along the sidewalls of the peripheral insulating trench 106 and the transfer gate 108, which attracts the opposite type of carriers towards the substrate (holes in this example).

[0063] During the exposure phase, the charge collection region 110 and the well 118 are taken to the potentials V_SN and V_WELL, respectively. In the example shown, the potentials V_SN and V_WELL are applied by contact elements 120C and 120D, respectively. For example, the contact element 120D can supply charge carriers, thereby forming a potential barrier in the transfer region 114 during the exposure phase.

[0064] During the readout phase after the exposure phase, the conductive region 108C of the vertical transfer gate 108 is, for example, taken to a potential V_TG_ON different from the potential V_TG_OFF, and the conductive region 106C of the peripheral insulating trench 106 is kept at the potential V_CDTI. During the readout phase, applying the potential V_TG_ON to the conductive region 106C can reduce or even eliminate the potential barrier in the transfer region 114 between the photosensitive region 102 and the charge collection region 110. The disappearance of the potential barrier enables the transfer of photogenerated charges from the photosensitive region 102 to the charge collection region 110 during the readout phase.

[0065] As an example, an image sensor including pixel 100 further includes a control circuit configured to alternately apply to contact element 120B connected to conductive region 108C of transfer gate 108:

[0066] a potential V_TG_OFF suitable for preventing the transfer of charges from the photosensitive region 102 to the charge collecting region 110 ; and

[0067] A potential V_TG_ON suitable for allowing the transfer of charges from the photosensitive region 102 to the charge collecting region 110 .

[0068] During the readout phase, the charge collection region 110 and the well 118 are maintained at potentials V_SN and V_WELL, respectively, for example. Figure 1A and 1B Although not described in detail, the contact element 120C is connected to a readout circuit, for example, located on the upper surface side of the substrate 104. The contact element 120C is more specifically connected to a sensing node (not shown), for example, and can transfer the charge accumulated in the charge collection region 110 to the sensing node.

[0069] As an example:

[0070] - In the case where the photosensitive region 102, the transfer region 114 and the charge collection region 110 are of N-type and the wells 116 and 118 are of P-type:

[0071] The potential V_TG_ON is equal to about 1.8 V;

[0072] The potential V_TG_OFF is equal to about -0.5 V;

[0073] The potential V_CDTI is equal to about -0.5 V;

[0074] The potential V_WELL is equal to about 0.2V; and

[0075] The potential V_SN is equal to about 1.8 V, and

[0076] - In the case where the photosensitive region 102, the transfer region 114 and the charge collection region 110 are of P type and the wells 116 and 118 are of N type:

[0077] The potential V_TG_ON is equal to 0V;

[0078] The potential V_TG_OFF is equal to about 1.8 V;

[0079] The potential V_CDTI is equal to about 1.8 V;

[0080] The potential V_WELL is equal to about 1.5V; and

[0081] The potential V_SN is equal to about 0.5V.

[0082] In the above example, the potential V_TG_ON is equal to the potential V_SN. However, this example is not restrictive, and as a variant, the potential V_TG_ON may be different from the potential V_SN.

[0083] In a sensor comprising a plurality of pixels arranged in an array of rows and columns, the center-to-center distance between two adjacent pixels in the row or column direction is designated as the “pixel pitch.” The pixel pitch in the row or column direction substantially corresponds to the lateral dimension of the pixels in said direction.

[0084] An advantage of a sensor integrating pixels of the type described above with pixel 100 is that it may have a pixel pitch in the row and column directions that is smaller than the pixel pitch of existing sensors, for example smaller than 1 μm, for example in the range from 0.6 μm to 0.8 μm.

[0085] Figure 2A and Figure 2B are simplified views and partial views of an example of an image sensor pixel 200 according to an embodiment, a top view and a view along the Figure 2A Cross-sectional view of plane BB.

[0086] Figure 2A and Figure 2B The pixel 200 includes Figure 1A and Figure 1B The common elements of the pixels 100 are the same as those of the pixels 100. These common elements will not be described in detail below. Figure 2A and Figure 2B The pixels are 200 and Figure 1A and Figure 1B The pixel 200 differs from the pixel 100 in that the pixel 200 does not include the electrically insulating trench 112. This simplifies the formation of the pixel 200 compared to the pixel 100.

[0087] In this example, the charge collection region 110 and the well 116 are adjacent. However, this example is not limiting and, as a variant, the charge collection region 110 may be separated from the well 116 by a portion of the transfer region 114 extending laterally between the region 110 and the well 116. This advantage enables the reduction of electric fields that induce dark currents.

[0088] Figure 3A and Figure 3B 3 is a simplified view and a partial view of an example of an image sensor pixel 300 according to an embodiment, a top view and a view along the Figure 3A Cross-sectional view of plane BB.

[0089] Figure 3A and Figure 3B The pixel 300 includes Figure 1A and Figure 1B The common elements of the pixels 100 are the same as those of the pixels 100. These common elements will not be described in detail below. Figure 3A and Figure 3B 300 pixels and Figure 1A and Figure 1B The pixel 100 of the embodiment of the present invention is different in that the conductive region 108C of the vertical transfer gate 108 of the pixel 300 is separated from the upper surface of the substrate 104 by a non-zero thickness of an electrically insulating material, such as an oxide, such as the material of the insulating layer 106I of the peripheral insulating trench 106. In other words, the conductive region 108C of the transfer gate 108 of the pixel 300 is not flush with the upper surface of the substrate 104. This advantageously enables a reduction in the capacitance between the conductive region 108C of the vertical transfer gate 108 and the charge collection region 110 as compared to the case of the pixel 100.

[0090] Figure 4 is a simplified and partial top view of an arrangement 400 of two adjacent pixels 100 according to an embodiment.

[0091] In the example shown, two pixels 100 are juxtaposed so that they share a portion of the peripheral insulating trench 106. Figure 4 In the direction of , the left pixel 100 is symmetrical with the right pixel 100 with respect to the vertical axis. The vertical transfer gate 108 is formed in the portion of the peripheral insulation trench 106 common to the two pixels 100. This makes it possible to reduce the surface area occupied by the pixels of the image sensor.

[0092] In the example shown, the insulating trench 112 is common to both pixels 100 and surrounds a contact element 120B located in the center of the arrangement 400 and two contact elements 120C located on either side of the vertical transfer gate 108. Furthermore, both pixels 100 of the arrangement 400 comprise, for example, a single conductive pad 120A.

[0093] exist Figure 4 In the arrangement 400 , the transfer gate 108 is common to both pixels 100 and allows the charge photogenerated in these pixels to be blocked and transferred from the photosensitive region 102 to the charge collection region 110 of the pixel 100 simultaneously.

[0094] Figure 5 is a simplified and partial top view of an arrangement 500 of four adjacent 100 pixels, according to an embodiment.

[0095] In the example shown, four pixels 100 are juxtaposed so that they share a portion of the peripheral insulating trench 106. Figure 5In the direction of , the left pixel 100 is symmetrical with the right pixel 100 with respect to the vertical axis, and the upper pixel 100 is symmetrical with the lower pixel 100 with respect to the horizontal axis. The vertical transfer gate 108 is formed in a portion of the peripheral insulation trench 106 shared by the four pixels 100, and has a cross shape (+) in a top view. This makes it possible to further reduce the surface area occupied by the image sensor pixels.

[0096] In the example shown, the insulating trench 112 is common to the four pixels 100 and surrounds a contact element 120B located in the center of the arrangement 500 and four contact elements 120C. Furthermore, the four pixels 100 of the arrangement 500 comprise, for example, a single conductive pad 120A.

[0097] exist Figure 5 In the arrangement 500 , the transfer gate 108 is common to four pixels 100 and allows the charge photogenerated in these pixels to be blocked and transferred from the photosensitive region 102 to the charge collection region 110 of the pixel 100 simultaneously.

[0098] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that those skilled in the art will discover other variations. In particular, Figure 2A and Figure 2B An embodiment of the pixel 200 and Figure 3A and Figure 3B Embodiments of pixel 300 may be combined to obtain a pixel that does not include insulating trench 112 and in which conductive region 108C of vertical transfer gate 108 is separated from the upper surface of substrate 104 by a non-zero thickness of electrically insulating material.

[0099] Furthermore, although arrangements 400 and 500 are described above in the context of including pixel 100, as indicated above, similar arrangements may also be provided by pixel 200, pixel 300, or a pixel combining the characteristics of pixel 200 and pixel 300. Such arrangements are within the capabilities of those skilled in the art based on the teachings of the present disclosure.

[0100] In addition, although the described embodiments take the case where the photosensitive region 102, the transfer region 114 and the charge collection region 110 are N-type doped and the wells 116 and 118 are P-type doped as an example, those skilled in the art are able to convert these embodiments to the case where the doping types are opposite, that is, the photosensitive region 102, the transfer region 114, the charge collection region 110 are P-type doped and the wells 116 and 118 are N-type doped based on the instructions of the present disclosure.

[0101] Finally, based on the functional indications given above, the actual implementation of the embodiments and variants is within the capabilities of a person skilled in the art.In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this disclosure.

Claims

1. An image sensor, the image sensor comprising a plurality of pixels (100; 200; 300) formed inside and on top of a semiconductor substrate (104), each pixel comprising: - a photosensitive region (102) formed in the semiconductor substrate (104); - a peripheral insulating trench (106), the peripheral insulating trench (106) extending vertically in the semiconductor substrate (104) from the upper surface of the semiconductor substrate and laterally delimiting the photosensitive area (102); - a charge collection region (110); - a transfer region (114), the transfer region (114) being located in the semiconductor substrate (104) and extending vertically between the charge collection region (110) and the photosensitive region (102); and - a transfer gate (108) extending vertically in the semiconductor substrate (104) from the upper surface of the semiconductor substrate and inside the peripheral insulation trench (106), the peripheral insulation trench (108) being deeper than the charge collection region (110), The transfer region (114) is doped with the same first conductivity type as the photosensitive region (102) and has a doping level lower than that of the photosensitive region.

2. The sensor (100; 200; 300) according to claim 1, wherein: The transfer gate (108) extends vertically in the semiconductor substrate (104) down to a depth substantially equal to the depth of the transfer region (114).

3. The sensor (100; 200; 300) according to claim 1 or 2, wherein: The photosensitive region (102) and the transfer region (114) have a substantially horizontal interface.

4. The sensor (100; 200; 300) according to claim 1 or 2, wherein: The charge collection region (110) is doped with the first conductivity type and has a doping level that is higher than the doping level of the transfer region (114).

5. The sensor (100; 200; 300) according to claim 1 or 2, further comprising a doped well (116) of a second conductivity type opposite to the first conductivity type, the well extending vertically in the semiconductor substrate (104), extending downward from the upper surface of the semiconductor substrate to a depth less than the depth of the transfer gate (108).

6. The sensor (100; 300) according to claim 5, further comprising an electrically insulating trench (112) laterally interposed between the charge collecting region (110) and the well (116).

7. The sensor according to claim 6, wherein: The electrically insulating trench (112) extends vertically in the semiconductor substrate (104), from an upper surface of the semiconductor substrate, downwardly to a depth greater than a depth of the charge collection region (110).

8. The sensor (200) according to claim 5, wherein: The charge collection region (110) and the well (116) are adjacent.

9. The sensor (100; 200; 300) according to claim 1 or 2, wherein: The peripheral insulating trench (106) and the transfer gate (108) respectively include a first conductive region (106C) and a second conductive region (108C), and the first conductive region (106C) is electrically insulated from the second conductive region (108C).

10. The sensor (100; 200) according to claim 9, wherein: The second conductive region (108C) is flush with the upper surface of the semiconductor substrate (104).

11. The sensor (300) according to claim 9, wherein: The second conductive region (108C) is separated from the upper surface of the semiconductor substrate (104) by a non-zero thickness of insulating material.

12. The sensor according to claim 1 or 2, wherein: The transfer gate (108) is common to two pixels (100; 200; 300).

13. The sensor according to claim 1 or 2, wherein: The transfer gate (108) is common to four pixels (100; 200; 300).

14. The sensor according to claim 1 or 2, wherein: The first conductivity type is N type.

15. The sensor according to claim 1 or 2, further comprising a control circuit configured to alternately apply to the transfer gate (108): - a first electrical potential adapted to prevent the transfer of charges from the photosensitive region (102) to the charge collecting region (110); and - a second electrical potential, different from said first electrical potential, adapted to allow the transfer of charges from said photosensitive region (102) to said charge collecting region (110).

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