Array substrate, display panel, display module and manufacturing method of display module

Abstract

The embodiment of the invention provides an array substrate, a display panel, a display module and a manufacturing method of the display module, the array substrate comprises a substrate and an array circuit layer, the substrate comprises a first flexible layer, a plurality of first conductive structures and an interval insulating layer, the first flexible layer is provided with a first surface and a second surface which are opposite to each other, and the first conductive structures are arranged on the first flexible layer; the first flexible layer is provided with at least one connecting groove extending from the first surface to the second surface, at least part of the plurality of first conductive structures is located in the at least one connecting groove and is exposed from the second surface, the interval insulating layer is arranged on the first surface and covers the plurality of first conductive structures, and the interval insulating layer is provided with a plurality of first via holes; the array circuit layer is arranged on the side, away from the first flexible layer and the multiple first conductive structures, of the interval insulating layer and comprises multiple driving signal lines, the driving signal lines are electrically connected with the corresponding first conductive structures through the corresponding first via holes, and when the array substrate is manufactured to form a display panel, the screen-to-body ratio can be increased.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate, a display panel, a display module, and a method for manufacturing the display module. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel, a display module and a method for manufacturing the display module, aiming to improve the performance of display products.

[0005] An embodiment of the first aspect of the present application provides an array substrate, comprising a substrate and an array circuit layer, wherein the substrate comprises a first flexible layer, a plurality of first conductive structures and a spacing insulating layer, wherein the first flexible layer has a first surface and a second surface opposite to each other, the first flexible layer is provided with at least one connecting groove extending from the first surface to the second surface, at least part of the plurality of first conductive structures is located in the at least one connecting groove and exposed from the second surface, the spacing insulating layer is provided on the first surface and covers the plurality of first conductive structures, and the spacing insulating layer is provided with a plurality of first vias; the array circuit layer is provided on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures, and comprises a plurality of driving signal lines, and the driving signal lines are electrically connected to the corresponding first conductive structures through the corresponding first vias.

[0006] According to an embodiment of the present application, the plurality of first conductive structures include at least one first conductive substructure and at least one second conductive substructure, at least one first conductive substructure is located in at least one connecting groove and exposed from the second surface, and at least one second conductive substructure is located on the first surface and connected to at least one first conductive substructure.

[0007] According to an embodiment of the present application, the substrate has a first symmetry axis and a second symmetry axis parallel to the plane where the substrate is located, and includes a middle area passing through the first symmetry axis and the second symmetry axis, and at least one connecting groove is located in the middle area.

[0008] According to an embodiment of the present application, at least one connection groove includes a plurality of connection grooves, at least one first conductive substructure includes a plurality of first conductive substructures, and the plurality of first conductive substructures are arranged in a one-to-one correspondence with the plurality of connection grooves.

[0009] According to an embodiment of the present application, the array substrate further includes a plurality of second conductive structures, a second flexible layer and a buffer layer, wherein: the plurality of second conductive structures are arranged on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures; the second flexible layer covers the plurality of second conductive structures and is provided with a plurality of second vias; the buffer layer is arranged on a side of the second flexible layer away from the spacing insulating layer and is provided with a plurality of third vias, and the third vias are connected to the corresponding second vias; the array circuit layer is arranged on a side of the buffer layer away from the spacing insulating layer, and the driving signal line is electrically connected to the corresponding first conductive structure through the corresponding third vias, the second vias, the second conductive structures and the first vias;

[0010] According to an embodiment of the present application, orthographic projections of the plurality of first conductive structures on the second flexible layer at least partially overlap with orthographic projections of the plurality of second conductive structures on the second flexible layer.

[0011] According to an embodiment of the present application, there are multiple shift register units, and the shift register units include parts of multiple first conductive structures and / or parts of multiple second conductive structures.

[0012] According to an embodiment of the present application, a plurality of shift register units are located in the middle area.

[0013] According to an embodiment of the present application, the shift register unit includes a low temperature polysilicon transistor.

[0014] According to an embodiment of the present application, the plurality of driving signal lines include a plurality of first connecting wires extending along a second direction parallel to the substrate, and the shift register unit is electrically connected to portions of the corresponding first connecting wires located in the middle region.

[0015] According to an embodiment of the present application, a plurality of first connecting wires are arranged along a first direction parallel to the substrate, the first direction is perpendicular to the second direction, and a plurality of shift register units are arranged along the first direction.

[0016] According to an embodiment of the present application, the plurality of first connecting wires include scan lines, the plurality of shift register units include scan shift register units, and the scan shift register units are electrically connected to portions of corresponding scan lines located in the middle area.

[0017] According to an embodiment of the present application, the plurality of first connecting wires include light emitting control lines, the plurality of shift register units include light emitting shift register units, and the light emitting shift register units are electrically connected to portions of corresponding light emitting control lines located in the middle area.

[0018] According to an embodiment of the present application, the plurality of driving signal lines further include a plurality of second connecting wires extending along a first direction parallel to the substrate, the first direction is perpendicular to the second direction, and the second connecting wires are electrically connected to the corresponding first conductive structure and / or second conductive structure.

[0019] According to an embodiment of the present application, the plurality of second connecting wires include data signal lines and / or power supply voltage lines.

[0020] A second aspect of the present application provides a display panel, comprising: an array substrate according to any one of the first aspect embodiments; and a plurality of light-emitting devices located on a side of the array substrate away from the second surface.

[0021] According to an embodiment of the present application, the display panel includes a display area, the display area includes a display center, and at least one connecting groove is located in the display center.

[0022] According to an embodiment of the present application, the display panel further includes an encapsulation layer located on a side of the plurality of light-emitting devices away from the array substrate.

[0023] According to an embodiment of the present application, the array substrate includes a low-temperature polycrystalline oxide transistor, and the low-temperature polycrystalline oxide transistor is used to drive the light-emitting device to emit light.

[0024] A third aspect of the present application provides a display module, including:

[0025] The display panel of any one of the embodiments of the second aspect above; and a flip chip film, which is located on the second surface and electrically connected to the first conductive structure exposed from the second surface.

[0026] A fourth aspect of the present application provides a method for manufacturing a display module, comprising:

[0027] At least one connecting groove is formed in the first flexible layer, the first flexible layer has a first surface and a second surface opposite to each other, and the at least one connecting groove extends from the first surface to the second surface;

[0028] forming a plurality of first conductive structures on the first flexible layer, wherein at least a portion of the plurality of first conductive structures is located in at least one connecting groove and exposed from the second surface;

[0029] forming a spacing insulating layer on the first surface, wherein the spacing insulating layer covers the plurality of first conductive structures;

[0030] Opening a plurality of first via holes in the spacing insulating layer;

[0031] An array circuit layer is formed on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures. The array circuit layer includes a plurality of drive signal lines. The drive signal lines are electrically connected to the corresponding first conductive structures through corresponding first vias.

[0032] According to an embodiment of the present application, before the step of forming an array circuit layer on a side of the spacer insulating layer away from the first flexible layer and the plurality of first conductive structures, the method includes:

[0033] A plurality of second conductive structures are formed on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures, wherein the second conductive structures are electrically connected to the corresponding first conductive structures through a plurality of first vias;

[0034] forming a second flexible layer on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures, the second flexible layer covering the plurality of second conductive structures, and the second flexible layer being provided with a plurality of second vias;

[0035] A buffer layer is formed on a side of the second flexible layer away from the spacing insulating layer, wherein the buffer layer is provided with a plurality of third via holes, and the third via holes are connected to the corresponding second via holes;

[0036] The step of forming an array circuit layer on a side of the spacer insulating layer away from the first flexible layer and the plurality of first conductive structures comprises:

[0037] An array circuit layer is formed on a side of the buffer layer away from the second flexible layer, and a driving signal line is electrically connected to the corresponding first conductive structure through the corresponding third via hole, the second via hole, the second conductive structure and the first via hole;

[0038] According to an embodiment of the present application, the manufacturing method further includes: disposing a chip-on-chip film on the second surface, the chip-on-chip film being electrically connected to the first conductive structure through a connecting groove;

[0039] According to an embodiment of the present application, before the step of providing a flip chip film on the second surface, the method further includes:

[0040] A protection layer is disposed on a side of the array circuit layer away from the second surface.

[0041] According to an embodiment of the present application, after the step of providing a chip-on-film on the second surface, the method further includes: removing the protective layer.

[0042] In this embodiment, at least part of the multiple first conductive structures are located in at least one connecting groove, so that the first conductive structure can be exposed to the second surface through the connecting groove, and the spacing insulating layer is provided with multiple first vias. The driving signal line is electrically connected to the corresponding first conductive structure through the corresponding first via holes to transmit the electrical signal in the driving signal line to the second surface, thereby reducing the routing of the driving signal line through the edge area of ​​the array substrate. When the array substrate is manufactured to form a display panel, it is beneficial to increase the screen-to-body ratio of the display panel and improve the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0044] Figure 1 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0045] Figure 2 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0046] Figure 3 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0047] Figure 4 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0048] Figure 5 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0049] Figure 6 is a structural schematic diagram of another array substrate provided in an embodiment of the present application;

[0050] Figure 7 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0051] Figures 8 to 10 It is a schematic diagram of a manufacturing method of a display module provided in an embodiment of the present application;

[0052] Fig.11 This is a flow chart of another method for manufacturing an array substrate provided in an embodiment of the present application.

[0053] Explanation of reference numerals: AA, display area; 10, first symmetry axis; 20, second symmetry axis; 30, light-emitting device; 40, glass substrate; 100, first flexible layer; 101, first surface; 102, second surface; 110, connection groove; 210, first conductive structure; 211, first conductive substructure; 212, second conductive substructure; 220, second conductive structure; 300, spacing insulating layer; 310, first via hole; 400, driving signal line; 410, first connecting wire; 411, scanning line; 412, light-emitting control line; 420, second connecting wire; 500, shift register unit; 510, scanning shift register unit; 520, light-emitting shift register unit; 600, flip chip film; 700, second flexible layer; 710, second via hole; 800, buffer layer; 810, third via hole; X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0054] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0055] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0056] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0057] like Figure 1As shown, an array substrate provided by an embodiment of the first aspect of the present application includes: a substrate and an array circuit layer, the substrate includes a first flexible layer 100, a plurality of first conductive structures 210 and a spacing insulating layer 300, wherein the first flexible layer 100 has a first surface 101 and a second surface 102 opposite to each other, the first flexible layer 100 is provided with at least one connecting groove 110 extending from the first surface 101 to the second surface 102, at least part of the plurality of first conductive structures 210 is located in the at least one connecting groove 110 and exposed from the second surface 102, the spacing insulating layer 300 is provided on the first surface 101 and covers the plurality of first conductive structures 210, and the spacing insulating layer 300 is provided with a plurality of first vias 310; the array circuit layer is provided on a side of the spacing insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210, and includes a plurality of driving signal lines 400, and the driving signal lines 400 are electrically connected to the corresponding first conductive structures 210 through the corresponding first vias 310.

[0058] In this embodiment, the first flexible layer 100 has a first surface 101 and a second surface 102 relative to each other. The first flexible layer 100 is provided with at least one connecting groove 110 extending from the first surface 101 to the second surface 102. The connecting groove 110 penetrates the first flexible layer 100 along the thickness direction Z of the array substrate. At least part of the plurality of first conductive structures 210 is located in the at least one connecting groove 110, so that the first conductive structure 210 can be exposed to the second surface 102 through the connecting groove 110. The spacing insulating layer 300 is provided with a plurality of first via holes 310. The driving signal line 400 is electrically connected to the corresponding first conductive structure 210 through the corresponding first via holes 310 to transmit the electrical signal in the driving signal line 400 to the second surface 102.

[0059] In some embodiments, Figure 1 As shown, a COF 600 may be disposed on the second surface 102, and the COF 600 is electrically connected to the drive signal line 400 through the first conductive structure 210 to transmit an electrical signal to the drive signal line 400, thereby reducing the number of drive signal lines 400 that need to be routed through the edge area of ​​the array substrate. When the array substrate is manufactured to form a display panel, it is beneficial to increase the screen-to-body ratio of the display panel and improve the performance of the display panel. Figure 1 The array substrate does not include the chip-on-film 600. Figure 1 The chip-on-film 600 in the figure is only used to show the connection relationship with the first conductive structure 210 .

[0060] Optionally, the first flexible layer 100 may be made of polyimide (PI) material, so that the array substrate can be used to manufacture a flexible display panel.

[0061] like Figure 2As shown, in some optional embodiments, the multiple first conductive structures 210 include at least one first conductive substructure 211 and at least one second conductive substructure 212, at least one first conductive substructure 211 is located in at least one connecting groove 110 and exposed from the second surface 102, and at least one second conductive substructure 212 is located on the first surface 101 and connected to at least one first conductive substructure 211.

[0062] In these optional embodiments, the first conductive substructure 211 is located in the connecting groove 110 for connecting the flip chip film 600, the second conductive substructure 212 is connected to the first conductive substructure 211 and is located on the first surface 101 of the first flexible layer 100, and the second conductive substructure 212 is located outside the connecting groove 110, thereby increasing the layout area of ​​the second conductive substructure 212, which can help simplify the solution of connecting the driving signal line 400 to the first conductive structure 210 through the first via 310, that is, the driving signal line 400 can be connected to different positions of the first conductive structure 210.

[0063] Optional, such as Figure 2 As shown, the drive signal line 400 is connected to the first conductive substructure 211 or the second conductive substructure 212 through the first via 310. The drive signal line 400 can be directly connected to the first conductive substructure 211 to electrically connect to the chip-on-chip film 600. The drive signal line 400 can be connected to the second conductive substructure 212 through the first via 310, and connected to the first conductive substructure 211 through the second conductive substructure 212 to electrically connect to the chip-on-chip film 600.

[0064] Optional, such as Figure 2 As shown, the driving signal line 400 is connected to the first conductive substructure 211 and the second conductive substructure 212 through the first via 310. According to the line arrangement of the driving signal line 400, part of the driving signal line 400 is connected to the first conductive substructure 211 through the first via 310, and part of the driving signal line 400 is connected to the second conductive substructure 212 through the first via 310, so that the wiring process of the driving signal line 400 can be simplified.

[0065] Optional, such as Figure 3As shown, the substrate has a first symmetry axis 10 and a second symmetry axis 20 parallel to the plane where the substrate is located, and includes an intermediate area passing through the first symmetry axis 10 and the second symmetry axis 20, at least one connecting groove 110 is located in the intermediate area, and the flip chip film 600 is connected to the drive signal line 400 through the first conductive structure 210 in the connecting groove 110 located in the intermediate area. The load of the drive signal line 400 is relatively even, which can improve the voltage drop difference of the array substrate. Because the connecting groove 110 is symmetrical relative to the center of the array substrate, the drive signal line 400 of the array substrate is symmetrical, the number of the drive signal lines 400 can be reduced, and there is no need to consider the routing layout of the edge arc angle area.

[0066] Optionally, at least one connection slot 110 includes a plurality of connection slots 110, at least one first conductive substructure 211 includes a plurality of first conductive substructures 211, and the plurality of first conductive substructures 211 are arranged in one-to-one correspondence with the plurality of connection slots 110. There are a plurality of connection slots 110, each connection slot 110 corresponds to a portion of pins connected to the COF 600, and the plurality of first conductive substructures 211 are arranged in one-to-one correspondence with the plurality of connection slots 110, and the pins of the COF 600 are electrically connected through each connection slot 110 to transmit electrical signals.

[0067] like Figure 4 As shown, in some optional embodiments, the array substrate further includes a plurality of second conductive structures 220, a second flexible layer 700 and a buffer layer 800, wherein: the plurality of second conductive structures 220 are arranged on a side of the spacing insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210; the second flexible layer 700 covers the plurality of second conductive structures 220 and is provided with a plurality of second vias 710; the buffer layer 800 is arranged on a side of the second flexible layer 700 away from the spacing insulating layer 300, is provided with a plurality of third vias 810, and the third vias 810 are connected to the corresponding second vias 710; the array circuit layer is arranged on a side of the buffer layer 800 away from the spacing insulating layer 300, and the driving signal line 400 is electrically connected to the corresponding first conductive structure 210 through the corresponding third vias 810, the second vias 710, the second conductive structure 220 and the first vias 310.

[0068] In these optional embodiments, the plurality of second conductive structures 220 are disposed on a side of the spacing insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210, and the distance between the second conductive structure 220 and the driving signal line 400 is closer than the distance between the first conductive structure 210 and the driving signal line 400, and the driving signal line 400 is connected to the second conductive structure 220 through the corresponding third via 810 and the second via 710, thereby reducing the via depth of the driving signal line 400 connected to the first conductive structure 210 through the via, and the driving signal line 400 is connected to the first conductive structure 210 by connecting to the first conductive structure 210, or by connecting to the first conductive structure 210 through the second conductive structure 220, which is conducive to reducing the wiring difficulty of the driving signal line 400.

[0069] like Figure 4 As shown, in some optional embodiments, the orthographic projections of the plurality of first conductive structures 210 on the second flexible layer 700 at least partially overlap with the orthographic projections of the plurality of second conductive structures 220 on the second flexible layer 700 .

[0070] In these optional embodiments, the orthographic projections of the plurality of first conductive structures 210 on the second flexible layer 700 at least partially overlap with the orthographic projections of the plurality of second conductive structures 220 on the second flexible layer 700, the first vias 310 are disposed between the first conductive structures 210 and the second conductive structures 220, the second conductive structures 220, the first vias 310, and the orthographic projections of the first conductive structures 210 on the second flexible layer 700 at least partially overlap, and the second conductive structures 220 are connected to the first conductive structures 210 through the first vias 310.

[0071] Optional, such as Figure 4 and Figure 5 As shown, the second conductive structure 220 is connected to the first conductive substructure 211 or the second conductive substructure 212 through the first via 310 .

[0072] In these optional embodiments, the orthographic projection of the first via 310 on the second flexible layer 700 may at least partially overlap with the orthographic projection of the first conductive substructure 211 on the second flexible layer 700, and the second conductive structure 220 is connected to the first conductive substructure 211 through the first via 310; or, the orthographic projection of the first via 310 on the second flexible layer 700 may at least partially overlap with the orthographic projection of the second conductive substructure 212 on the second flexible layer 700, and the second conductive structure 220 is connected to the second conductive substructure 212 through the first via 310.

[0073] Optional, such as Figure 4 and Figure 5As shown, the array substrate includes a plurality of stacked driving signal lines 400, so that it is convenient to arrange connecting wires on each driving signal line 400. Each driving signal line 400 is connected to the first conductive structure 210 and / or the second conductive structure 220 through a via hole.

[0074] like Figure 3 and Figure 4 As shown, in some optional embodiments, the array substrate includes a plurality of shift register units 500 , and the shift register units 500 include portions of a plurality of first conductive structures 210 and / or portions of a plurality of second conductive structures 220 .

[0075] In these optional embodiments, when the shift register unit 500 includes a portion of a plurality of first conductive structures 210, the driving signal line 400 is connected to the shift register unit 500 in the first conductive structure 210, and the driving signal line 400 is connected to the COF 600 through the shift register unit 500. When the shift register unit 500 includes a portion of a plurality of second conductive structures 220, the driving signal line 400 is connected to the shift register unit 500, and the shift register unit 500 in the second conductive structure 220 is electrically connected to the first conductive structure 210 to connect to the COF 600.

[0076] In some embodiments, the array substrate includes a display area and a frame area arranged around the display area, the driving signal line extends along the second direction, the shift register unit is arranged in the frame area on both sides of the second direction of the array substrate and connected to both ends of the driving signal line, and when the array substrate forms a display panel, the shift register unit occupies the position of the frame area on both sides of the second direction of the array substrate, so that the frame of the display panel is larger. In this embodiment, the shift register unit 500 is arranged in the first conductive structure 210 or the second conductive structure 220, that is, the shift register unit 500 is located in the display area AA and does not occupy the frame area of ​​the array substrate along the second direction Y, which is conducive to reducing the frame size of the display panel.

[0077] Optionally, the shift register unit 500 adopts an LTPS (Low Temperature Poly-Silicon) circuit, and the low-temperature polysilicon transistor of the shift register unit 500 and the low-temperature polycrystalline oxide transistor in the array substrate achieve spatial overlap along the thickness direction Z of the array substrate, thereby reducing space and achieving a high screen-to-body ratio.

[0078] Optionally, multiple shift register units 500 are located in the middle area, and the drive signal line 400 is connected to the shift register unit 500 located in the middle area. The arrangement of the drive signal line 400 is symmetrical, and the load of the drive signal line 400 connected to the shift register unit 500 is relatively even, which can improve the voltage drop difference of the array substrate and reduce the number of drive signal lines 400, and there is no need to consider the routing layout of the edge arc angle area.

[0079] like Figure 3 As shown, in some optional embodiments, the plurality of driving signal lines 400 include a plurality of first connecting wires 410, the first connecting wires 410 extend along a second direction Y parallel to the substrate, and the shift register unit 500 electrically connects the corresponding first connecting wires 410 located in the middle area.

[0080] In these optional embodiments, the first connecting conductor 410 is extended and formed along the second direction Y, the shift register unit 500 is electrically connected to the corresponding part of the first connecting conductor 410 located in the middle area, and the electrical signal is transmitted from the middle of the first connecting conductor 410 to both sides of the first connecting conductor 410 along the second direction Y, and the single-sided drive can achieve the effect of double-sided hedge drive.

[0081] Optional, such as Figure 3 As shown, the orthographic projection of the shift register unit 500 on the first flexible layer 100 at least partially overlaps with the orthographic projection of the first connecting wire 410 on the first flexible layer 100. Alternatively, the orthographic projection of the shift register unit 500 on the first flexible layer 100 does not overlap with the orthographic projection of the first connecting wire 410 on the first flexible layer 100. The shift register unit 500 is correspondingly arranged in the middle of the first connecting wire 410 along the second direction Y, and the shift register unit 500 is electrically connected to the middle of the first connecting wire 410 along the second direction Y.

[0082] Optional, such as Figure 3 As shown, a plurality of first connecting wires 410 are arranged along a first direction X parallel to the substrate, the first direction X is perpendicular to the second direction Y, a plurality of shift register units 500 are arranged along the first direction X, and each first connecting wire 410 is electrically connected to each shift register unit 500 along the middle of the second direction Y.

[0083] A plurality of first connecting wires 410 extend along the second direction Y and are arranged side by side along the first direction X, and a plurality of shift register units 500 are arranged side by side along the first direction X, so that each first connecting wire 410 corresponds to each shift register unit 500, so that each first connecting wire 410 is electrically connected to each shift register unit 500 at the shortest distance.

[0084] Optional, such as Figure 3 As shown, the plurality of first connecting wires 410 include scan lines 411, and the plurality of shift register units 500 include scan shift register units 510, and the scan shift register units 510 are electrically connected to the corresponding scan lines 411 located in the middle area. The scan shift register units 510 receive clock signals, scan start signals, etc. from the timing controller in the chip-on-film 600 to generate scan signals provided to the scan lines 411. The arrangement of the scan lines 411 is symmetrical, and the load of the scan lines 411 connected to the scan shift register units 510 is relatively even.

[0085] Optional, such as Figure 3 As shown, the plurality of first connecting wires 410 include light-emitting control lines 412, and the plurality of shift register units 500 include light-emitting shift register units 520, which are electrically connected to the corresponding light-emitting control lines 412 located in the middle area.

[0086] The light emitting shift register unit 520 can generate an emission signal provided to the light emitting control line 412 by receiving a clock signal, an emission stop signal, etc. from a timing controller in the flip chip film 600. The light emitting shift register unit 520 is electrically connected to the portion of the corresponding light emitting control line 412 located in the middle area, and the arrangement of the light emitting control line 412 is symmetrical, and the load of the light emitting control line 412 connecting the light emitting shift register unit 520 is relatively even.

[0087] Optional, such as Figure 3 As shown, the plurality of driving signal lines 400 further include a plurality of second connecting wires 420 extending along a first direction X parallel to the substrate, the first direction X is perpendicular to the second direction Y, and the second connecting wires 420 are electrically connected to the corresponding first conductive structures 210 and / or second conductive structures 220 .

[0088] In these optional embodiments, the second connecting wire 420 is electrically connected to the first conductive structure 210 and the second conductive structure 220, or the second connecting wire 420 is electrically connected to the first conductive structure 210 or the second conductive structure 220. When the second connecting wire 420 is directly connected to the first conductive structure 210, the electrical signal is transmitted from the first conductive structure 210 to the second connecting wire 420, and when the second connecting wire 420 is connected to the second conductive structure 220, the electrical signal is transmitted to the second connecting wire 420 through the first conductive structure 210 and the second conductive structure 220.

[0089] Optionally, the second connecting wire 420 may include a data signal line for transmitting a data signal and / or a power supply voltage line for transmitting a power supply voltage signal.

[0090] like Figure 4 and Figure 6 As shown, the embodiment of the second aspect of the present application further provides a display panel, comprising the array substrate in any embodiment of the first aspect, the display panel further comprising a plurality of light emitting devices 30, the light emitting devices 30 being located on a side of the array substrate away from the second surface 102. The array substrate is used to drive the light emitting devices 30 to emit light.

[0091] Optional, such as Figure 6 As shown, the display panel includes a display area AA, the display area AA includes a display center, and at least one connecting groove 110 is located in the display center.

[0092] Optionally, the display panel further includes an encapsulation layer located on a side of the plurality of light emitting devices 30 away from the array substrate. The encapsulation layer is used to encapsulate the light emitting devices 30 to reduce the intrusion of water, oxygen, etc. into the light emitting devices 30.

[0093] The embodiment of the third aspect of the present application further provides a display module, comprising a display panel as in any embodiment of the second aspect above; Figure 4 As shown, the display module further includes a COF 600 located on the second surface 102 and electrically connected to the first conductive structure 210 exposed from the second surface 102 .

[0094] In this embodiment, the flip chip film 600 is arranged on the second surface 102 and electrically connected to the first conductive structure 210 through the connecting groove 110 to electrically connect the driving signal line 400, thereby reducing the space occupied by the flip chip film 600 in the display area AA domain, and the driving signal line 400 is electrically connected to the first conductive structure 210 and connected to the flip chip film 600 through the connecting groove 110, which is beneficial to improving the screen-to-body ratio of the display panel.

[0095] The pixel circuit in the array substrate adopts LTPO (Low Temperature Poly-silicon Oxide, low temperature polycrystalline silicon oxide circuit), and the array substrate includes low temperature polycrystalline oxide transistors, which are used to drive the light emitting device 30 to emit light.

[0096] The fourth aspect of the present application also provides a method for manufacturing a display module. Figure 7 As shown, including:

[0097] Step S01: Figure 8 As shown, at least one connecting groove 110 is formed in the first flexible layer 100 . The first flexible layer 100 has a first surface 101 and a second surface 102 opposite to each other. The at least one connecting groove 110 extends from the first surface 101 to the second surface 102 .

[0098] Step S02: Fig. 9 As shown, a plurality of first conductive structures 210 are formed on the first flexible layer 100 , and at least a portion of the plurality of first conductive structures 210 are located in at least one connecting groove 110 and exposed from the second surface 102 .

[0099] Step S03: Fig.10 As shown, a spacer insulating layer 300 is formed on the first surface 101 , and the spacer insulating layer 300 covers the plurality of first conductive structures 210 .

[0100] Step S04: Fig.10 As shown, a plurality of first via holes 310 are opened in the spacer insulating layer 300 .

[0101] Step S05: Figure 2 As shown, an array circuit layer is formed on the side of the spacing insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210 , and the array circuit layer includes a plurality of driving signal lines 400 , which are electrically connected to the corresponding first conductive structures 210 through the corresponding first vias 310 .

[0102] In the present embodiment, at least part of the plurality of first conductive structures 210 is located in at least one connection groove 110, so that the first conductive structure 210 can be exposed to the second surface 102 through the connection groove 110, and the spacing insulating layer 300 is provided with a plurality of first via holes 310, and the driving signal line 400 is electrically connected to the corresponding first conductive structure 210 through the corresponding first via holes 310 to transmit the electrical signal in the driving signal line 400 to the second surface 102. In some embodiments, a chip-on-film 600 can be provided on the second surface 102, and the chip-on-film 600 is electrically connected to the driving signal line 400 through the first conductive structure 210 to transmit the electrical signal to the driving signal line 400, thereby reducing the routing of the driving signal line 400 through the edge area of ​​the array substrate, which is conducive to increasing the screen-to-body ratio of the display module and improving the performance of the display module.

[0103] Optional, such as Figure 8 As shown, the step of forming the connection groove 110 on the first flexible layer 100 includes: disposing the first flexible layer 100 on the glass substrate 40 and forming the connection groove 110 by an etching process.

[0104] Optional, such as Figure 8 As shown, the step of forming the connection groove 110 on the first flexible layer 100 includes: forming the first flexible layer 100 with the connection groove 110 on the transfer layer, and then transferring the first flexible layer 100 with the connection groove 110 to the glass substrate 40 .

[0105] In some optional embodiments, before step S05, as Fig.11 As shown, including:

[0106] Step S021: Figure 4 As shown, a plurality of second conductive structures 220 are formed on a side of the spacer insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210 , and the second conductive structures 220 are electrically connected to the corresponding first conductive structures 210 through a plurality of first vias 310 .

[0107] Step S022: Figure 4 As shown, a second flexible layer 700 is formed on a side of the spacer insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210 . The second flexible layer 700 covers the plurality of second conductive structures 220 . The second flexible layer 700 is provided with a plurality of second vias 710 .

[0108] Step S023: Figure 4 As shown, a buffer layer 800 is formed on the side of the second flexible layer 700 away from the spacing insulating layer 300 , and the buffer layer 800 is provided with a plurality of third via holes 810 , which are connected to the corresponding second via holes 710 .

[0109] In step S05, it includes: step S024: Figure 4 As shown, an array circuit layer is formed on the side of the buffer layer 800 away from the second flexible layer 700 , and the driving signal line 400 is electrically connected to the corresponding first conductive structure 210 through the corresponding third via 810 , the second via 710 , the second conductive structure 220 and the first via 310 .

[0110] In these optional embodiments, the plurality of second conductive structures 220 are disposed on a side of the spacing insulating layer 300 away from the first flexible layer 100 and the plurality of first conductive structures 210, and the distance between the second conductive structure 220 and the driving signal line 400 is closer than the distance between the first conductive structure 210 and the driving signal line 400, and the driving signal line 400 is connected to the second conductive structure 220 through the corresponding third via 810 and the second via 710, thereby reducing the via depth of the driving signal line 400 connected to the first conductive structure 210 through the via, and the driving signal line 400 is connected to the first conductive structure 210 by connecting to the first conductive structure 210, or by connecting to the first conductive structure 210 through the second conductive structure 220, which is conducive to reducing the wiring difficulty of the driving signal line 400.

[0111] Optional, such as Figure 4 As shown, the manufacturing method further includes: disposing a chip-on-film 600 on the second surface 102 , and the chip-on-film 600 is electrically connected to the first conductive structure 210 through the connecting groove 110 .

[0112] The COF 600 is electrically connected to the first conductive structure 210 through the connection groove 110 to transmit electrical signals to the driving signal line 400, thereby reducing the number of driving signal lines 400 that need to be routed through the edge area of ​​the display module, thereby improving the screen-to-body ratio of the display module.

[0113] In some optional embodiments, before the step of disposing the COF 600 on the second surface 102 , the step includes: disposing a protection layer on a side of the array circuit layer away from the second surface 102 .

[0114] In these optional embodiments, during the step of installing the COF 600 , the driving signal line 400 needs to be oriented toward the base. To reduce the pressure and scratches on the driving signal line 400 , a protective layer needs to be provided on the side of the array circuit layer away from the second surface 102 .

[0115] In some optional embodiments, after the step of disposing the chip-on-film 600 on the second surface 102 , the step further includes: removing the protective layer.

[0116] In these optional embodiments, the protective layer can be removed after the chip on film 600 is installed.

[0117] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: include: A substrate, comprising a first flexible layer, a plurality of first conductive structures and a spacing insulating layer, wherein the first flexible layer has a first surface and a second surface opposite to each other, the first flexible layer is provided with at least one connecting groove extending from the first surface to the second surface, at least part of the plurality of first conductive structures is located in the at least one connecting groove and exposed from the second surface, the spacing insulating layer is provided on the first surface and covers the plurality of first conductive structures, and the spacing insulating layer is provided with a plurality of first via holes; The array circuit layer is disposed on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures, and includes a plurality of drive signal lines, wherein the drive signal lines are electrically connected to the corresponding first conductive structures through the corresponding first vias.

2. The array substrate according to claim 1, characterized in that: The plurality of first conductive structures include at least one first conductive substructure and at least one second conductive substructure, wherein the at least one first conductive substructure is located in the at least one connecting groove and exposed from the second surface, and the at least one second conductive substructure is located on the first surface and connected to the at least one first conductive substructure; Preferably, the substrate has a first symmetry axis and a second symmetry axis parallel to the plane where the substrate is located, and includes a middle area passing through the first symmetry axis and the second symmetry axis, and the at least one connecting groove is located in the middle area; Preferably, the at least one connecting groove comprises a plurality of connecting grooves, the at least one first conductive substructure comprises a plurality of first conductive substructures, and the plurality of first conductive substructures are arranged in a one-to-one correspondence with the plurality of connecting grooves.

3. The array substrate according to claim 2, characterized in that: The array substrate further includes a plurality of second conductive structures, a second flexible layer and a buffer layer, wherein: The plurality of second conductive structures are disposed on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures; The second flexible layer covers the plurality of second conductive structures and is provided with a plurality of second via holes; The buffer layer is arranged on a side of the second flexible layer away from the spacing insulating layer, and is provided with a plurality of third via holes, wherein the third via holes are connected to the corresponding second via holes; The array circuit layer is arranged on a side of the buffer layer away from the spacing insulating layer, and the driving signal line is electrically connected to the corresponding first conductive structure through the corresponding third via hole, the second via hole, the second conductive structure and the first via hole; Preferably, the orthographic projections of the plurality of first conductive structures on the second flexible layer at least partially overlap with the orthographic projections of the plurality of second conductive structures on the second flexible layer.

4. The array substrate according to claim 3, characterized in that: Also includes: a plurality of shift register units, wherein the shift register units include a portion of the plurality of first conductive structures and / or a portion of the plurality of second conductive structures; Preferably, the plurality of shift register units are located in the middle area; Preferably, the shift register unit includes the low temperature polysilicon transistor.

5. The array substrate according to claim 4, characterized in that: The plurality of driving signal lines include a plurality of first connecting wires, the first connecting wires extend along a second direction parallel to the substrate, and the shift register unit is electrically connected to a portion of the corresponding first connecting wire located in the middle area; Preferably, the plurality of first connecting wires are arranged along a first direction parallel to the substrate, the first direction is perpendicular to the second direction, and the plurality of shift register units are arranged along the first direction; Preferably, the plurality of first connecting wires include scan lines, the plurality of shift register units include scan shift register units, and the scan shift register units are electrically connected to portions of the corresponding scan lines located in the middle area; Preferably, the plurality of first connecting wires include light-emitting control lines, the plurality of shift register units include light-emitting shift register units, and the light-emitting shift register units are electrically connected to portions of the corresponding light-emitting control lines located in the middle area.

6. The array substrate according to claim 3, characterized in that: The plurality of driving signal lines further include a plurality of second connecting wires extending along a first direction parallel to the substrate, the first direction being perpendicular to the second direction, and the second connecting wires being electrically connected to the corresponding first conductive structure and / or second conductive structure; Preferably, the plurality of second connecting wires include data signal lines and / or power supply voltage lines.

7. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 6; A plurality of light emitting devices are located on a side of the array substrate away from the second surface.

8. The display panel according to claim 7, characterized in that: The display panel comprises a display area, the display area comprises a display center, and the at least one connection slot is located at the display center; Preferably, the display panel further comprises an encapsulation layer, which is located on a side of the plurality of light-emitting devices away from the array substrate; Preferably, the array substrate comprises a low temperature polycrystalline oxide transistor, and the low temperature polycrystalline oxide transistor is used to drive the light emitting device to emit light.

9. A display module, characterized in that: include: The display panel according to any one of claims 7 to 8; The flip chip film is located on the second surface and electrically connected to the first conductive structure exposed from the second surface.

10. A method for manufacturing a display module, characterized in that: include: At least one connecting groove is formed in the first flexible layer, the first flexible layer having a first surface and a second surface opposite to each other, the at least one connecting groove extending from the first surface to the second surface; forming a plurality of first conductive structures on the first flexible layer, wherein at least a portion of the plurality of first conductive structures is located in the at least one connecting groove and exposed from the second surface; forming a spacing insulating layer on the first surface, wherein the spacing insulating layer covers the plurality of first conductive structures; Opening a plurality of first via holes in the spacing insulating layer; An array circuit layer is formed on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures. The array circuit layer includes a plurality of drive signal lines. The drive signal lines are electrically connected to the corresponding first conductive structures through the corresponding first vias.

11. The manufacturing method according to claim 10, characterized in that: Before the step of forming an array circuit layer on a side of the spacer insulating layer away from the first flexible layer and the plurality of first conductive structures, the method comprises: A plurality of second conductive structures are formed on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures, wherein the second conductive structures are electrically connected to corresponding first conductive structures through a plurality of the first vias; forming a second flexible layer on a side of the spacing insulating layer away from the first flexible layer and the plurality of first conductive structures, the second flexible layer covering the plurality of second conductive structures, and the second flexible layer being provided with a plurality of second vias; A buffer layer is formed on a side of the second flexible layer away from the spacing insulating layer, wherein the buffer layer is provided with a plurality of third via holes, and the third via holes are connected to the corresponding second via holes; The step of forming an array circuit layer on a side of the spacer insulating layer away from the first flexible layer and the plurality of first conductive structures comprises: The array circuit layer is formed on a side of the buffer layer away from the second flexible layer, and the drive signal line is electrically connected to the corresponding first conductive structure through the corresponding third via hole, the second via hole, the second conductive structure and the first via hole; Preferably, the manufacturing method further comprises: providing a chip-on-chip film on the second surface, wherein the chip-on-chip film is electrically connected to the first conductive structure through the connecting groove; Preferably, before the step of providing a chip-on-film on the second surface, the method further comprises: Disposing a protective layer on a side of the array circuit layer away from the second surface; Preferably, after the step of providing a chip-on-film on the second surface, the method further comprises: The protective layer is removed.

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