Semiconductor substrate, semiconductor device and manufacturing method thereof
By forming a conductive type impurity concentration gradient between the multilayer silicon carbide layers and heat-treated diffused impurities, the problem of high on-resistance of semiconductor substrates and devices in the prior art is solved, and the effect of few defects and low on-resistance is achieved.
Patent Information
- Application Number
- CN202480004025.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-18
- Filing Date
- 2024-04-03
- Publication Date
- 2025-05-06
AI Technical Summary
The prior art is difficult to provide semiconductor substrates and semiconductor devices with few defects and low on-resistance.
The conductive type impurity concentration gradient is formed between the multilayer silicon carbide layers by epitaxial growth method, and heat treatment is performed to diffuse impurities to form a semiconductor substrate with low on-resistance.
Semiconductor substrates and semiconductor devices with few defects and low on-resistance are realized, and the performance and reliability of the device are improved.
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Figure CN119948599A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a semiconductor substrate, a semiconductor device, and a method for manufacturing the same. Background Art
[0002] As a material for the next generation of semiconductor devices, SiC (silicon carbide) is expected. Compared with Si (silicon), silicon carbide has a band gap of about 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. Therefore, by using SiC, semiconductor devices with low loss and high temperature operation can be realized.
[0003] Prior art literature
[0004] Patent Literature
[0005] Patent Document 1: Japanese Patent Application Publication No. 2009-088223
[0006] Non-patent literature
[0007] Non-patent document 1: Fuji Electric Technical Report 2017 Vol. 90 No. 4 Summary of the invention
[0008] Problem that the invention aims to solve
[0009] The problem to be solved by the present invention is to provide a semiconductor substrate with few defects and low on-resistance, a semiconductor device and a method for manufacturing the same.
[0010] Means used to solve problems
[0011] The method for manufacturing a semiconductor substrate of the embodiment comprises the following steps: forming a second silicon carbide layer on the first silicon carbide layer by an epitaxial growth method, wherein the second silicon carbide layer has a lower first conductivity type impurity concentration than the first silicon carbide layer, and the first conductivity type impurity concentration is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 The film thickness is 0.001 μm or more and 0.1 μm or less; a step of forming a third silicon carbide layer on the second silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the third silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3, the film thickness is greater than 0.5μm and less than 20μm; a process of forming a fourth silicon carbide layer on the third silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the fourth silicon carbide layer is lower than that of the third silicon carbide layer; and a process of heat treating the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.
[0012] Effects of the Invention
[0013] According to the present invention, a semiconductor substrate having few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to the first embodiment.
[0015] Figure 2 Schematic cross-sectional views showing the manufacturing process of the semiconductor substrate and the semiconductor device according to the first embodiment.
[0016] Figure 3 Schematic cross-sectional views showing the manufacturing process of the semiconductor substrate and the semiconductor device according to the first embodiment.
[0017] Figure 4 It is a flowchart of the manufacturing process of the semiconductor substrate and the semiconductor device according to the first embodiment.
[0018] Figure 5 It is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a second embodiment.
[0019] Figure 6 Schematic cross-sectional views showing the manufacturing process of the semiconductor substrate and the semiconductor device according to the second embodiment.
[0020] Figure 7 It is a flowchart of the manufacturing process of the semiconductor substrate and the semiconductor device according to the second embodiment.
[0021] Figure 8 It is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a third embodiment.
[0022] Fig. 9 It is a flowchart of the manufacturing process of the semiconductor substrate and the semiconductor device according to the third embodiment.
[0023] Fig.10 It is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a fourth embodiment.
[0024] Fig.11 It is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION
[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are given to the same components and the like, and the description of the components and the like that have been described once will be appropriately omitted.
[0026] In the following instructions, when using n + 、n、n - and p + ,p,p - In the case of expressions such as n, these expressions indicate the relative high and low impurity concentrations in each conductivity type. + Compared with n, the impurity concentration of n-type is relatively high. - Indicates that the impurity concentration of n-type is relatively lower than that of n-type. + Compared with p type, the impurity concentration of p type is relatively high. - Indicates that the p-type impurity concentration is relatively lower than that of the p-type. + Type, n - The type is abbreviated as n type, and p + Type, p - The type is abbreviated as p-type.
[0027] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). In addition, the relative level of the impurity concentration can also be determined, for example, based on the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). In addition, the depth and distance of the impurity region can be obtained, for example, by SIMS. In addition, the width and depth of the impurity region can be obtained, for example, based on the SCM image.
[0028] Defect evaluation can be performed, for example, by KOH etching, reflection X-ray morphology, transmission X-ray morphology, TEM (Transmission Electron Microscope), or photoluminescence imaging.
[0029] Hereinafter, the first conductivity type is referred to as n-type, and the second conductivity type is referred to as p-type.
[0030] In this specification, in order to indicate the positional relationship of components, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms indicating the relationship with the direction of gravity.
[0031] (First Embodiment)
[0032] The method for manufacturing a semiconductor substrate of the present embodiment comprises the following steps: forming a second silicon carbide layer on the first silicon carbide layer by epitaxial growth, wherein the second silicon carbide layer has a lower first conductivity type impurity concentration than the first silicon carbide layer, and the first conductivity type impurity concentration is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 The film thickness is 0.001 μm or more and 0.1 μm or less; a step of forming a third silicon carbide layer on the second silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the third silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 , the film thickness is greater than 0.5μm and less than 20μm; a process of forming a fourth silicon carbide layer on the third silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the fourth silicon carbide layer is lower than that of the third silicon carbide layer; and a process of heat treating the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.
[0033] The manufacturing method of the semiconductor device of this embodiment includes the following steps: a step of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate of this embodiment; a step of forming a first electrode under the first silicon carbide layer; and a step of forming a second electrode on the ninth silicon carbide layer.
[0034] The semiconductor substrate of this embodiment includes: a first silicon carbide layer; and a fifth silicon carbide layer provided on the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 17 cm -3 atoms / cm 3 More than and less than 1×10 19 cm -3 atoms / cm 3 ; A third silicon carbide layer, which is disposed on the fifth silicon carbide layer, and the first conductive type impurity concentration is 5×10 17 cm - 3 atoms / cm 3 More than and less than 1×10 20 cm -3 atoms / cm 3, with a film thickness of not less than 0.5 μm and not more than 20 μm; and a fourth silicon carbide layer, which is arranged on the third silicon carbide layer and has a lower concentration of first conductive type impurities than the third silicon carbide layer; in a direction from the first silicon carbide layer toward the fifth silicon carbide layer in a region including the first silicon carbide layer and the fifth silicon carbide layer, the concentration gradient of the first conductive type impurities is different from the concentration gradient of impurities different from the first conductive type impurities.
[0035] In addition, the semiconductor substrate of the present embodiment includes: a first silicon carbide layer; and a fifth silicon carbide layer provided on the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 17 cm -3 atoms / cm 3 More than and less than 1×10 19 cm - 3 atoms / cm 3 ; A third silicon carbide layer, which is disposed on the fifth silicon carbide layer, and the first conductive type impurity concentration is 5×10 17 cm -3 atoms / cm 3 More than and less than 1×10 20 cm -3 atoms / cm 3 , with a film thickness of not less than 0.5 μm and not more than 20 μm; and a fourth silicon carbide layer, which is disposed on the third silicon carbide layer and has a first conductivity type impurity concentration lower than that of the third silicon carbide layer; a BPD (Basal plane dislocation) density of the first silicon carbide layer is 10 / cm 2 The BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 / cm 2 the following.
[0036] Figure 1 AB is a schematic cross-sectional view of the semiconductor wafer 100 and the semiconductor device 200 according to the present embodiment. Figure 1 A is a schematic cross-sectional view of the semiconductor wafer 100 and the semiconductor device 200 according to the present embodiment. Figure 1 B is a schematic diagram showing the impurity concentration in the Z direction of the semiconductor device 200 .
[0037] The semiconductor substrate 100 includes a first silicon carbide layer 4 , a fifth silicon carbide layer 12 , a third silicon carbide layer 8 , and a fourth silicon carbide layer 10 .
[0038] The semiconductor device 200 includes a semiconductor substrate 100 , a first electrode 60 , a ninth silicon carbide layer 20 , and a second electrode 62 .
[0039] The semiconductor device 200 of this embodiment is a PIN diode.
[0040] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The first silicon carbide layer 4, the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are arranged in parallel in the XY plane. The Z direction is a direction in which the first electrode 60, the first silicon carbide layer 4, the fifth silicon carbide layer 12, the third silicon carbide layer 8, the fourth silicon carbide layer 10, and the second electrode 62 are stacked. The Z direction is a direction from the first electrode 60 toward the second electrode 62.
[0041] n + The first silicon carbide layer 4 of the type includes, for example, 1×10 18 atoms / cm 3 Above and 1×10 19 atoms / cm 3 The following n-type impurities. The n-type impurities are, for example, N (nitrogen). However, the n-type impurities may also be, for example, P (phosphorus). In addition, the n-type impurities may also be both N (nitrogen) and P (phosphorus). The first silicon carbide layer 4 is, for example, Figure 1 The silicon carbide layer is formed by epitaxial growth using CVD (Chemical Vapor Deposition) on a substrate such as a silicon carbide substrate not shown in AB. However, the first silicon carbide layer 4 may be, for example, a silicon carbide substrate. The first silicon carbide layer 4 is, for example, a cathode layer of a PIN diode.
[0042] The n-type fifth silicon carbide layer 12 is provided on the first silicon carbide layer 4. The fifth silicon carbide layer 12 includes, for example, 1×10 17 atoms / cm 3 More than and less than 1×10 19 atoms / cm 3 Alternatively, the n-type impurity concentration of the fifth silicon carbide layer 12 is less than half of the n-type impurity concentration of the first silicon carbide layer 4 or the n-type impurity concentration of the third silicon carbide layer 8. The film thickness of the fifth silicon carbide layer 12 is preferably, for example, not less than 0.001 μm and not more than 0.1 μm.
[0043] n + The third silicon carbide layer 8 of type is provided on the fifth silicon carbide layer 12. The third silicon carbide layer 8 includes, for example, 5×10 17 atoms / cm 3 Above and 1×10 20 atoms / cm 3The thickness of the third silicon carbide layer 8 is, for example, 0.5 μm to 20 μm. The third silicon carbide layer 8 is, for example, a layer for promoting recombination of holes and electrons so that holes do not reach the silicon carbide substrate when the semiconductor device 200 is bipolarly powered.
[0044] The fifth silicon carbide layer 12 is formed, for example, by forming a second silicon carbide layer 6 described later on the first silicon carbide layer 4, and after forming a third silicon carbide layer 8 on the second silicon carbide layer 6, by using impurity diffusion using heat treatment to diffuse n-type impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 into the second silicon carbide layer 6.
[0045] The third silicon carbide layer 8 is, for example, a silicon carbide layer formed on the second silicon carbide layer 6 described later by an epitaxial growth method using a CVD method.
[0046] In the case of epitaxial growth using the CVD method, the n-type impurity concentration of each silicon carbide layer is adjusted by the flow rate of the impurity gas (e.g., nitrogen), and the n-type impurity concentration near the interface of at least each silicon carbide layer has a concentration gradient according to the flow rate change time, but the concentration gradient changes in the subsequent impurity diffusion using heat treatment. After the heat treatment, the concentration gradient usually becomes gentle.
[0047] In addition to n-type impurities, impurities unintentionally added from the furnace components of the epitaxial growth device may be mixed in. For example, Al (aluminum), B (boron), P (phosphorus), Fe (iron), Cr (chromium), Ni (nickel), Zn (zinc), Ta (tantalum), etc. can be mentioned.
[0048] The diffusion coefficient of impurities in SiC differs depending on the element. Therefore, the concentration gradient of the n-type impurity accompanying the diffusion of the impurity using the heat treatment is different from the concentration gradient of the impurities other than the n-type impurity that are not intentionally added.
[0049] in addition, Figure 1 The impurity concentration shown in (b) is only an example. Therefore, the impurity concentrations of the semiconductor wafer 100 and the semiconductor device 200 of this embodiment are not limited to Figure 1 (b) as shown.
[0050] n - The fourth silicon carbide layer 10 of type is provided on the third silicon carbide layer 8. The fourth silicon carbide layer 10 includes, for example, 1×10 15 atoms / cm 3 Above and 5×10 16 atoms / cm 3 The n-type impurity concentration of the fourth silicon carbide layer 10 is lower than the impurity concentration of the third silicon carbide layer 8. The film thickness of the fourth silicon carbide layer 10 is, for example, not less than 4 μm and not more than 50 μm.
[0051] The BPD density of the first silicon carbide layer 4 is 10 / cm 2 In addition, the BPD density of the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 is 0.1 pieces / cm 2 the following.
[0052] The p-type ninth silicon carbide layer 20 is disposed on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 includes, for example, 1×10 17 atoms / cm 3 Above and 1×10 20 atoms / cm 3 The p-type impurity is, for example, Al (aluminum). The film thickness of the ninth silicon carbide layer 20 is, for example, 0.1 μm or more and 2.0 μm or less. The ninth silicon carbide layer 20 is, for example, an anode layer of a PIN diode.
[0053] The first electrode 60 is disposed under the first silicon carbide layer 4. The first electrode 60 is, for example, in contact with the first silicon carbide layer 4. The first electrode 60 includes, for example, a metal or a metal semiconductor compound. The first electrode 60 includes, for example, Ni (nickel). In addition, the Ni included in the first electrode 60 may react with the first silicon carbide layer 4 to form a layer including NiSi or Ni2Si (nickel silicide). In addition, the first electrode 60 may also have a layer including Ti (titanium), Ni (nickel), Ag (silver) or Au (gold) under the layer including NiSi or Ni2Si. The first electrode 60 is a cathode electrode.
[0054] The second electrode 62 is provided on the ninth silicon carbide layer 20. The second electrode 62 is, for example, in contact with the ninth silicon carbide layer 20. The second electrode 62 has, for example, a laminated structure of a barrier metal layer containing Ti (titanium) in contact with the ninth silicon carbide layer 20 and a metal layer containing Al (aluminum) provided on the barrier metal layer. In addition, the second electrode 62 may also have, for example, a layer containing a metal silicide such as NiSi in a portion in contact with the ninth silicon carbide layer 20.
[0055] Figure 2 AB and Figure 3 AB is a schematic cross-sectional view showing the manufacturing process of the semiconductor wafer 100 and the semiconductor device 200 according to the present embodiment. Figure 4 It is a flowchart of the manufacturing process of the semiconductor wafer 100 and the semiconductor device 200 according to the present embodiment.
[0056] First, an epitaxial growth method with an n-type impurity concentration of 1×10 14atoms / cm 3 Above and 1×10 17 atoms / cm 3 The second silicon carbide layer 6 ( Figure 4 The n-type impurity concentration of the second silicon carbide layer 6 is lower than the n-type impurity concentration of the first silicon carbide layer 4. For example, SiH4 is used as a raw material of Si (silicon), C3H8 or C2H2 is used as a raw material of C (carbon), N (nitrogen) is used as an n-type dopant, and H2 (hydrogen) is used as a carrier gas.
[0057] The second silicon carbide layer 6 is, for example, a layer for converting BPD of SiC into TED (Threading Edge dislocation).
[0058] Next, an epitaxial growth method using a CVD method (Chemical Vapor Deposition method) is used to form a 5×10 17 atoms / cm 3 Above and 1×10 20 atoms / cm 3 The third silicon carbide layer 8 ( Figure 4 S104).
[0059] Next, an epitaxial growth method using a CVD method (Chemical Vapor Deposition method) is used on the third silicon carbide layer 8 to form, for example, a first conductivity type impurity concentration of 1×10 15 cm -3 atoms / cm 3 More than and less than 5×10 16 cm -3 atoms / cm 3 , the fourth silicon carbide layer 10 ( Figure 2 AB, Figure 4 S106).
[0060] Next, an n-type impurity concentration of 1×10 17 atoms / cm 3 More than and less than 1×10 19 atoms / cm 3The fifth silicon carbide layer 12 is formed. The fifth silicon carbide layer 12 is formed, for example, by a process of diffusing impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 to the second silicon carbide layer 6 using a heat treatment. Specifically, the first silicon carbide layer 4, the second silicon carbide layer 6, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are heated, for example, in a temperature range of not less than 1100°C and not more than 1700°C for more than 30 minutes. Thus, by diffusing n-type impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 having a relatively high n-type impurity concentration to the second silicon carbide layer 6 having a relatively low n-type impurity concentration, the n-type impurity concentration of the second silicon carbide layer 6 can be increased. Therefore, the fifth silicon carbide layer 12 can be formed between the first silicon carbide layer 4 and the third silicon carbide layer 8. Thus, the semiconductor substrate 100 of the present embodiment is obtained. ( Figure 3 AB, Figure 4 S108).
[0061] The distance of n-type impurity diffusion varies depending on the heat treatment conditions. For example, when the n-type impurity is N (nitrogen), it diffuses by about 50 nm by heat treatment at 1300°C for 1 hour. The distance of n-type impurity diffusion can be further extended by adjusting the heat treatment temperature and heat treatment time. For example, the n-type impurity concentration of the fifth silicon carbide layer 12 can be set to about 1 / 10 to about 1 / 2 of the first silicon carbide layer 4 and the third silicon carbide layer 8.
[0062] Next, an epitaxial growth method using a CVD method (Chemical Vapor Deposition method) is used to form, for example, 1×10 17 atoms / cm 3 Above and 1×10 20 atoms / cm 3 The following p-type impurity is used to form the p-type ninth silicon carbide layer 20 with a film thickness of 0.1 μm or more and 2.0 μm. As the p-type dopant, for example, (CH 3 ) 3 Al is used.
[0063] Next, the first electrode 60 is formed under the first silicon carbide layer 4. Furthermore, the second electrode 62 is formed on the ninth silicon carbide layer 20. Thus, the semiconductor device 200 of the present embodiment is obtained.
[0064] In addition, the impurity diffusion step using heat treatment and the epitaxial growth step may be performed in the same apparatus. In addition, the impurity diffusion step using heat treatment and the epitaxial growth step may be performed in different apparatuses.
[0065] Next, the effects of the semiconductor substrate and the semiconductor device according to the present embodiment will be described.
[0066] When a semiconductor substrate is manufactured by forming a silicon carbide layer on a silicon carbide layer including a silicon carbide substrate, dislocations or stacking faults occur in the formed silicon carbide layer due to dislocations in the silicon carbide substrate, damage to the silicon carbide substrate during substrate processing, etc. When such a semiconductor substrate is used to manufacture a semiconductor device, this causes a decrease in the yield of the semiconductor device, which is a problem.
[0067] The BPD in the dislocation of the silicon carbide substrate expands into a stacking fault when bipolar power is applied, causing changes in device characteristics. As a method to suppress this situation, it is considered to set a silicon carbide layer with a high impurity concentration between the silicon carbide substrate and the drift layer so that holes do not reach the silicon carbide substrate when bipolar power is applied. However, since BPD is easily transferred from the silicon carbide substrate to the silicon carbide layer with a high impurity concentration, there is a problem that holes reach the transferred BPD and the BPD expands to the stacking fault.
[0068] In addition, in order to reduce BPD, it is considered to set a silicon carbide layer with a low impurity concentration between the silicon carbide substrate and the drift layer, and convert BPD to TED. This is because the change caused by TED to the device characteristics is smaller than that of BPD. However, if a silicon carbide layer with a low impurity concentration is set, there is a problem that the resistance of the device becomes higher.
[0069] Therefore, the method for manufacturing a semiconductor substrate of the present embodiment includes the following steps: forming a second silicon carbide layer on the first silicon carbide layer by epitaxial growth, wherein the second silicon carbide layer has a lower first conductivity type impurity concentration than the first silicon carbide layer, and the first conductivity type impurity concentration is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 The film thickness is 0.001 μm or more and 0.1 μm or less; a step of forming a third silicon carbide layer on the second silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the third silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 , the film thickness is greater than 0.5μm and less than 20μm; the process of forming a fourth silicon carbide layer having a first conductive type impurity concentration lower than that of the third silicon carbide layer on the third silicon carbide layer by an epitaxial growth method; and the process of heat treating the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.
[0070] By providing the second silicon carbide layer 6 , the BPD of the first silicon carbide layer 4 is efficiently converted into TED in a layer above the first silicon carbide layer 4 .
[0071] Furthermore, by providing the third silicon carbide layer 8, recombination of holes and electrons is promoted, so that holes can be prevented from reaching the first silicon carbide layer 4. Therefore, the expansion of BPD to the stacking fault can be suppressed.
[0072] In addition, by diffusion of impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 to the second silicon carbide layer 6, the fifth silicon carbide layer 12 having a higher n-type impurity concentration than the second silicon carbide layer 6 is formed. The film thickness of the second silicon carbide layer 6 is thin, being 0.1 μm or less. Therefore, the impurity diffusion from the first silicon carbide layer 4 and the third silicon carbide layer 8 to the second silicon carbide layer 6 is sufficiently performed, so that the resistance increase of the semiconductor substrate 100 can be suppressed. In addition, if the film thickness of the second silicon carbide layer 6 is 0.001 μm or more, the BPD of the first silicon carbide layer 4 can be converted into TED.
[0073] Furthermore, for example, the BPD density of the first silicon carbide layer 4 is 10 pieces / cm 2 In the above case, the BPD density of the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 can be set to 0.1 pieces / cm 2 the following.
[0074] Second silicon carbide layer 6 and third silicon carbide layer 8 are preferably formed by epitaxial growth because impurities introduced by ion implantation are difficult to diffuse by heat treatment.
[0075] According to the present embodiment, a semiconductor substrate having few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same can be provided.
[0076] (Second Embodiment)
[0077] The method for manufacturing a semiconductor substrate of the present embodiment is different from the method for manufacturing a semiconductor substrate of the first embodiment in that after the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer, the method further comprises the step of forming a first conductive type impurity concentration of 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 , a sixth silicon carbide layer having a film thickness of 0.5 μm or more and 20 μm or less; and forming a first conductivity type impurity concentration of 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 The following is a step of forming the seventh silicon carbide layer with a film thickness of 0.001 μm or more and 0.1 μm or less.
[0078] Here, description of contents overlapping with those of the first embodiment will be omitted.
[0079] Figure 5 AB is a schematic cross-sectional view of the semiconductor substrate 110 and the semiconductor device 210 according to the present embodiment.
[0080] The sixth silicon carbide layer 14 is disposed between the fifth silicon carbide layer 12 and the third silicon carbide layer 8. The sixth silicon carbide layer 14 includes, for example, 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 The sixth silicon carbide layer 14 has a thickness of 0.5 μm to 20 μm. The sixth silicon carbide layer 14 is a layer for promoting recombination of holes and electrons in a manner such that holes do not reach the silicon carbide substrate when the semiconductor device 200 is bipolarly powered, for example.
[0081] The eighth silicon carbide layer 18 is disposed between the sixth silicon carbide layer 14 and the third silicon carbide layer 8. The eighth silicon carbide layer 18 includes, for example, 1×10 17 atoms / cm 3 More than and less than 1×10 19 atoms / cm 3 Alternatively, the n-type impurity concentration of the eighth silicon carbide layer 18 is less than half of the n-type impurity concentration of the sixth silicon carbide layer 14 or the n-type impurity concentration of the third silicon carbide layer 8. In addition, the n-type impurity concentration of the fifth silicon carbide layer 12 of the present embodiment may be less than half of the n-type impurity concentration of the first silicon carbide layer 4 or the n-type impurity concentration of the sixth silicon carbide layer 14. The film thickness of the eighth silicon carbide layer 18 is greater than or equal to 0.001 μm and less than or equal to 0.1 μm.
[0082] Figure 6 AB is a schematic cross-sectional view showing the manufacturing process of the semiconductor substrate 110 and the semiconductor device 210 according to the present embodiment. Figure 7 Schematic cross-sectional views showing the manufacturing process of the semiconductor substrate 110 and the semiconductor device 210 according to the present embodiment.
[0083] In the method for manufacturing the semiconductor substrate 110 of the present embodiment, the second silicon carbide layer 6 is formed on the first silicon carbide layer 4 ( Figure 7 S202), forming a sixth silicon carbide layer 14 on the second silicon carbide layer 6 ( Figure 7 S204), forming a seventh silicon carbide layer 16 on the sixth silicon carbide layer 14 ( Figure 7 S206), forming a third silicon carbide layer 8 on the seventh silicon carbide layer 16 ( Figure 7S208), forming a fourth silicon carbide layer 10 on the third silicon carbide layer 8 ( Figure 7 Then, by using impurity diffusion by heat treatment, a fifth silicon carbide layer 12 is formed between the first silicon carbide layer 4 and the sixth silicon carbide layer 14, and an eighth silicon carbide layer 18 is formed between the sixth silicon carbide layer 14 and the third silicon carbide layer 8 ( Figure 7 S212).
[0084] In the present embodiment, by using the second silicon carbide layer 6 and the seventh silicon carbide layer 16, it can be considered that a plurality of second silicon carbide layers 6 are used. Therefore, the conversion efficiency from BPD to TED can be improved.
[0085] In addition, the case where the first silicon carbide layer 4 is a silicon carbide substrate is particularly considered. In this case, the substrate in-plane deviation of the n-type impurity in the silicon carbide substrate is very large. Therefore, when the n-type impurity is diffused from the first silicon carbide layer 4 as the silicon carbide substrate to the second silicon carbide layer 6, the XY in-plane deviation of the resistance of the fifth silicon carbide layer 12 becomes larger. In addition, the XY in-plane deviation of the BPD conversion efficiency becomes larger. In the present embodiment, it is considered that the diffusion of the n-type impurity from the sixth silicon carbide layer 14 to the second silicon carbide layer 6 has a smaller in-plane deviation than the diffusion of the n-type impurity from the first silicon carbide layer 4 as the silicon carbide substrate to the second silicon carbide layer 6. In addition, it is considered that the diffusion of the n-type impurity from the sixth silicon carbide layer 14 to the seventh silicon carbide layer 16 and the diffusion of the n-type impurity from the third silicon carbide layer 8 to the seventh silicon carbide layer 16 have a smaller in-plane deviation than the diffusion of the n-type impurity from the first silicon carbide layer 4 as the silicon carbide substrate to the second silicon carbide layer 6. This can reduce the XY in-plane variation of the resistance component and the XY in-plane variation of the BPD conversion efficiency.
[0086] In addition, for example, by reducing the thickness of the second silicon carbide layer 6 and the seventh silicon carbide layer 16, even if the heat treatment temperature for impurity diffusion is lowered or the heat treatment time is shortened, the n-type impurity concentration of the fifth silicon carbide layer 12 and the eighth silicon carbide layer 18 can be sufficiently increased. Therefore, the semiconductor substrate 110 and the semiconductor device 210 can be manufactured more easily.
[0087] In addition, when the n-type impurity concentration of the second silicon carbide layer 6 is too low, the difference in n-type impurity concentration between the first silicon carbide layer 4 or the third silicon carbide layer 8 and the second silicon carbide layer 6 is too large, and therefore, stress associated with the difference in lattice constant between the first silicon carbide layer 4 or the third silicon carbide layer 8 may occur, and dislocations may be newly generated. Therefore, for example, it is considered that the n-type impurity concentration of the second silicon carbide layer 6 is set to 1×10 16 atoms / cm 3 Above and 1×10 18 atoms / cm 3In addition to the second silicon carbide layer 6, it is also conceivable to use, for example, an n-type impurity density of 1×10 16 atoms / cm 3 Above and 1×10 18 atoms / cm 3 The seventh silicon carbide layer 16 is as follows. As a result, a lattice constant difference can be tolerated, so that the generation of new dislocations can be suppressed and the BPD conversion efficiency can be improved.
[0088] According to the present embodiment, it is also possible to provide a semiconductor substrate, a semiconductor device and a method for manufacturing the same which have few defects and low on-resistance.
[0089] (Third Embodiment)
[0090] The semiconductor substrate of the present embodiment is different from the semiconductor substrates of the first and second embodiments in that the semiconductor substrate further includes a silicon carbide substrate 2 and a first silicon carbide layer 4 is provided on the silicon carbide substrate 2 .
[0091] The semiconductor device of the present embodiment is different from the semiconductor substrates of the first and second embodiments in that a silicon carbide substrate 2 is provided between a first electrode 60 and a first silicon carbide layer 4 .
[0092] The method for manufacturing a semiconductor substrate of the present embodiment further comprises a step of forming a first silicon carbide layer 4 on a silicon carbide substrate 2 by an epitaxial growth method before the step of forming a second silicon carbide layer 6, which is different from the method for manufacturing a semiconductor substrate of the first embodiment and the second embodiment. In addition, the method for manufacturing a semiconductor substrate of the present embodiment is equivalent to the case where the first silicon carbide layer 4 is formed on the silicon carbide substrate 2 by an epitaxial growth method in the first embodiment.
[0093] Here, description of contents overlapping with those of the first embodiment and the second embodiment will be omitted.
[0094] Figure 8 AB is a schematic cross-sectional view of the semiconductor substrate 120 and the semiconductor device 220 according to the present embodiment. Fig. 9 FIG. 2 is a flowchart of the manufacturing process of the semiconductor substrate 120 and the semiconductor device 220 according to the present embodiment. Fig. 9 The flowchart shown is similar to Figure 4 The difference is that, Fig. 9 The method comprises the step of forming a first silicon carbide layer on a silicon carbide substrate. Fig. 9 302 in ). In addition, Fig. 9 S304, S306, S308 and S310 are respectively Figure 4 The same steps as S102, S104, S106 and S108.
[0095] The substrate surface deviation of the n-type impurity in the silicon carbide substrate 2 is very large. Therefore, when the n-type impurity is diffused directly from the silicon carbide substrate 2 to the second silicon carbide layer 6, the substrate surface deviation of the resistance of the fifth silicon carbide layer 12 becomes larger. In addition, the substrate surface deviation of the BPD conversion efficiency becomes larger. In this embodiment, by providing the first silicon carbide layer 4 between the silicon carbide substrate 2 and the second silicon carbide layer 6, their deviation can be reduced.
[0096] According to the present embodiment, it is also possible to provide a semiconductor substrate, a semiconductor device and a method for manufacturing the same which have few defects and low on-resistance.
[0097] (Fourth Embodiment)
[0098] The semiconductor device of this embodiment includes: a ninth silicon carbide layer of the second conductivity type arranged on a fourth silicon carbide layer of a semiconductor substrate; a tenth silicon carbide layer of the first conductivity type arranged on the ninth silicon carbide layer; a third electrode arranged on the ninth silicon carbide layer via a first insulating film in a groove reaching from the tenth silicon carbide layer to the fourth silicon carbide layer; a second insulating film arranged on the third electrode; and a second electrode arranged on the tenth silicon carbide layer and the second insulating film.
[0099] The manufacturing method of the semiconductor device of the present embodiment comprises: a process of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate; a process of forming a tenth silicon carbide layer of the first conductivity type on the ninth silicon carbide layer; a process of forming a groove reaching the fourth silicon carbide layer from the tenth silicon carbide layer; a process of forming a first insulating film in the groove; a process of forming a third electrode in the groove and arranged on the ninth silicon carbide layer via the first insulating film; a process of forming a second insulating film on the third electrode; and a process of forming a second electrode on the tenth silicon carbide layer and the second insulating film.
[0100] Here, description of contents overlapping with those of the first to third embodiments will be omitted.
[0101] Fig.10 It is a schematic cross-sectional view of the semiconductor device according to this embodiment.
[0102] The semiconductor device of this embodiment is a trench MOSFET.
[0103] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 functions as a base of the MOSFET. Figure 7 , a ninth silicon carbide layer 20a, a ninth silicon carbide layer 20b, and a ninth silicon carbide layer 20c are shown.
[0104] The n-type tenth silicon carbide layer 40 is provided on the ninth silicon carbide layer 20. The tenth silicon carbide layer 40 functions as a source of the MOSFET. Figure 7 , a tenth silicon carbide layer 40a, a tenth silicon carbide layer 40b, a tenth silicon carbide layer 40c, and a tenth silicon carbide layer 40d are illustrated.
[0105] The trench 70 reaches the fourth silicon carbide layer 10 from the tenth silicon carbide layer 40 . Figure 7 , the groove 70a and the groove 70b are shown.
[0106] The first insulating film 72 is provided in the trench 70. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulating material such as silicon oxide, for example. Figure 7 , the first insulating film 72a and the first insulating film 72b are shown.
[0107] The third electrode 74 is provided on the ninth silicon carbide layer 20 in the trench 70 so as to face the ninth silicon carbide layer 20 via the first insulating film 72. The third electrode 74 is a gate electrode of the MOSFET and is made of a conductive material such as conductive polysilicon containing impurities. Figure 7 In the figure, the third electrode 74a and the third electrode 74b are shown.
[0108] The second insulating film 76 is provided on the third electrode 74. The second insulating film 76 includes an insulating material such as silicon oxide. Figure 7 , the second insulating film 76a and the second insulating film 76b are shown.
[0109] p + The eleventh silicon carbide layer 42 of p-type is provided on the ninth silicon carbide layer 20. The p-type impurity concentration of the eleventh silicon carbide layer 42 is higher than that of the ninth silicon carbide layer 20. The eleventh silicon carbide layer 42 is a contact region of the MOSFET. Figure 7 , the eleventh silicon carbide layer 42a, the eleventh silicon carbide layer 42b, and the eleventh silicon carbide layer 42c are shown.
[0110] The second electrode 62 is provided on the tenth silicon carbide layer 40 and the second insulating film 76. The second electrode 62 is a source electrode of the MOSFET.
[0111] Furthermore, the first electrode 60 is a drain electrode of the MOSFET.
[0112] Since a semiconductor substrate having few defects and low on-resistance is used, according to the present embodiment, a semiconductor device having few defects and low on-resistance and a method for manufacturing the same can be provided.
[0113] (Fifth Embodiment)
[0114] The semiconductor device of this embodiment includes: a ninth silicon carbide layer of the second conductivity type arranged on the fourth silicon carbide layer of the semiconductor substrate; a tenth silicon carbide layer of the first conductivity type arranged on the ninth silicon carbide layer; a third electrode arranged on the ninth silicon carbide layer; a first insulating film arranged between the ninth silicon carbide layer and the third electrode; a second electrode arranged on the tenth silicon carbide layer and the third electrode; and a second insulating film arranged between the second electrode and the third electrode.
[0115] The manufacturing method of the semiconductor device of the present embodiment further comprises: a process of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate of the first to third embodiments; a process of forming a tenth silicon carbide layer of the first conductivity type on the ninth silicon carbide layer; a process of forming a first insulating film on the ninth silicon carbide layer; a process of forming a third electrode on the first insulating film; a process of forming a second insulating film on the third electrode; and a process of forming a second electrode on the third electrode, the second insulating film and the tenth silicon carbide layer.
[0116] Here, description of contents overlapping with those of the first to third embodiments will be omitted.
[0117] Fig.11 4 is a schematic cross-sectional view of a semiconductor device 400 according to the present embodiment.
[0118] The semiconductor device of this embodiment is a planar MOSFET.
[0119] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 functions as a base of the MOSFET. Figure 8 , the ninth silicon carbide layer 20a and the ninth silicon carbide layer 20b are shown. The ninth silicon carbide layer 20a and the ninth silicon carbide layer 20b are provided, for example, separately from each other.
[0120] The n-type tenth silicon carbide layer 40 is provided on the ninth silicon carbide layer 20. The tenth silicon carbide layer 40 functions as a source of the MOSFET. Figure 8 10th silicon carbide layer 40a and tenth silicon carbide layer 40b are shown in the figure. Tenth silicon carbide layer 40a and tenth silicon carbide layer 40b are provided, for example, separately from each other.
[0121] The third electrode 74 is provided on the ninth silicon carbide layer 20a and the ninth silicon carbide layer 20b. The third electrode 74 is a gate electrode of the MOSFET. The third electrode 74 is made of a conductive material such as conductive polysilicon containing impurities.
[0122] The first insulating film 72 is provided between the ninth silicon carbide layer 20 and the third electrode 74. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulating material such as silicon oxide, for example.
[0123] The second electrode 62 is provided on the tenth silicon carbide layer 40 and the third electrode 74. The second electrode 62 is a source electrode of the MOSFET.
[0124] The second insulating film 76 is provided between the second electrode 62 and the third electrode 74. The second insulating film 76 includes an insulating material such as silicon oxide.
[0125] Furthermore, the first electrode 60 is a drain electrode of the MOSFET.
[0126] Since a semiconductor substrate having few defects and low on-resistance is used, according to the present embodiment, a semiconductor device having few defects and low on-resistance and a method for manufacturing the same can be provided.
[0127] Several embodiments and examples of the present invention have been described, but these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.
[0128] Furthermore, the above-mentioned embodiments can be summarized as the following technical solutions.
[0129] (Technical Solution 1)
[0130] A method for manufacturing a semiconductor substrate comprises the following steps:
[0131] A step of forming a second silicon carbide layer on the first silicon carbide layer by epitaxial growth, wherein the second silicon carbide layer has a lower first conductivity type impurity concentration than the first silicon carbide layer, and the first conductivity type impurity concentration is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 Below, the film thickness is 0.001 μm or more and 0.1 μm or less;
[0132] The step of forming a third silicon carbide layer on the second silicon carbide layer by epitaxial growth, wherein the first conductive type impurity concentration of the third silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3, the film thickness is 0.5 μm or more and 20 μm or less;
[0133] forming a fourth silicon carbide layer on the third silicon carbide layer by epitaxial growth, wherein the fourth silicon carbide layer has a lower first conductivity type impurity concentration than the third silicon carbide layer; and
[0134] A step of performing a heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer.
[0135] (Technical Solution 2)
[0136] According to the method for manufacturing a semiconductor substrate according to technical solution 1, in the step of performing the heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer,
[0137] A first conductive type impurity concentration of 1×10 17 atoms / cm 3 Above and 1×10 18 atoms / cm 3 The following is the fifth silicon carbide layer.
[0138] (Technical Solution 3)
[0139] The method for manufacturing a semiconductor substrate according to Technical Solution 1 or Technical Solution 2, further comprising the following step after the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer:
[0140] A step of forming a sixth silicon carbide layer on the second silicon carbide layer by epitaxial growth, wherein the first conductive type impurity concentration of the sixth silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; and
[0141] A step of forming a seventh silicon carbide layer on the sixth silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the seventh silicon carbide layer is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 The film thickness is 0.001 μm or more and 0.1 μm or less.
[0142] (Technical Solution 4)
[0143] The method for manufacturing a semiconductor substrate according to any one of Technical Solutions 1 to 3, further comprising the step of forming the first silicon carbide layer on a silicon carbide substrate by an epitaxial growth method before the step of forming the second silicon carbide layer.
[0144] (Technical Solution 5)
[0145] The method for manufacturing a semiconductor substrate according to any one of technical solutions 1 to 4, wherein the first conductivity type impurity concentration of the first silicon carbide layer is 5×10 17 atoms / cm 3 Above and 1×10 19 atoms / cm 3 the following.
[0146] (Technical Solution 6)
[0147] A method for manufacturing a semiconductor device further comprises the following steps:
[0148] A step of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of Technical Solution 1 to Technical Solution 5;
[0149] forming a first electrode under the first silicon carbide layer; and
[0150] The step of forming a second electrode on the ninth silicon carbide layer.
[0151] (Technical Solution 7)
[0152] A method for manufacturing a semiconductor device further comprises the following steps:
[0153] A step of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of Technical Solution 1 to Technical Solution 5;
[0154] forming a tenth silicon carbide layer of the first conductivity type on the ninth silicon carbide layer;
[0155] forming a first electrode under the first silicon carbide layer;
[0156] forming a groove from the tenth silicon carbide layer to the fourth silicon carbide layer;
[0157] forming a first insulating film in the trench;
[0158] forming a third electrode provided on the ninth silicon carbide layer via the first insulating film in the trench; and
[0159] The step of forming a second electrode on the tenth silicon carbide layer.
[0160] (Technical Solution 8)
[0161] A method for manufacturing a semiconductor device further comprises the following steps:
[0162] A step of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of Technical Solution 1 to Technical Solution 5;
[0163] forming a tenth silicon carbide layer of the first conductivity type on the ninth silicon carbide layer;
[0164] forming a first insulating film on the ninth silicon carbide layer;
[0165] forming a third electrode on the first insulating film;
[0166] forming a second insulating film on the third electrode; and
[0167] and forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer.
[0168] (Technical Solution 9)
[0169] A semiconductor substrate comprising:
[0170] a first silicon carbide layer;
[0171] A fifth silicon carbide layer is provided on the first silicon carbide layer, and the first conductive type impurity concentration is 1×10 17 cm -3 atoms / cm 3 More than and less than 1×10 19 cm -3 atoms / cm 3 ;
[0172] The third silicon carbide layer is disposed on the fifth silicon carbide layer and has a first conductive type impurity concentration of 5×10 17 cm -3 atoms / cm 3 More than and less than 1×10 20 cm -3 atom / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; and
[0173] a fourth silicon carbide layer, which is disposed on the third silicon carbide layer and has a lower first conductivity type impurity concentration than the third silicon carbide layer;
[0174] In a region including the first silicon carbide layer and the fifth silicon carbide layer, in a direction from the first silicon carbide layer toward the fifth silicon carbide layer, a concentration gradient of a first conductivity type impurity is different from a concentration gradient of an impurity different from the first conductivity type impurity.
[0175] (Technical Solution 10)
[0176] A semiconductor substrate comprising:
[0177] a first silicon carbide layer;
[0178] A fifth silicon carbide layer is provided on the first silicon carbide layer, and the first conductive type impurity concentration is 1×10 17 cm -3 atoms / cm 3 More than and less than 1×10 19 cm -3 atoms / cm 3 ;
[0179] The third silicon carbide layer is disposed on the fifth silicon carbide layer and has a first conductive type impurity concentration of 5×10 17 cm -3 atoms / cm 3 More than and less than 1×10 20 cm -3 atom / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; and
[0180] a fourth silicon carbide layer, which is disposed on the third silicon carbide layer and has a lower first conductivity type impurity concentration than the third silicon carbide layer;
[0181] The BPD density of the first silicon carbide layer is 10 / cm 2 above,
[0182] The BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 / cm 2 the following.
[0183] Description of Reference Numerals
[0184] 2: Silicon carbide substrate
[0185] 4: First silicon carbide layer
[0186] 6: Second silicon carbide layer
[0187] 8: The third silicon carbide layer
[0188] 10: Fourth silicon carbide layer
[0189] 12: Fifth silicon carbide layer
[0190] 14: Sixth silicon carbide layer
[0191] 16: Seventh silicon carbide layer
[0192] 18: The eighth silicon carbide layer
[0193] 20: Ninth silicon carbide layer
[0194] 20a: Ninth silicon carbide layer
[0195] 20b: Ninth silicon carbide layer
[0196] 20c: Ninth silicon carbide layer
[0197] 40: Tenth silicon carbide layer
[0198] 42: Eleventh silicon carbide layer
[0199] 60: First electrode
[0200] 62: Second electrode
[0201] 70: Groove
[0202] 72: First insulating film
[0203] 74: The third electrode
[0204] 76: Second insulating film
[0205] 100: Semiconductor substrate
[0206] 110: Semiconductor substrate
[0207] 120: Semiconductor substrate
[0208] 200: Semiconductor devices
[0209] 210: Semiconductor devices
[0210] 220: Semiconductor devices
[0211] 400: Semiconductor devices
Claims
1. A method for manufacturing a semiconductor substrate, comprising the following steps: A step of forming a second silicon carbide layer on the first silicon carbide layer by epitaxial growth, wherein the second silicon carbide layer has a lower first conductivity type impurity concentration than the first silicon carbide layer, and the first conductivity type impurity concentration is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 Below, the film thickness is 0.001 μm or more and 0.1 μm or less; The step of forming a third silicon carbide layer on the second silicon carbide layer by epitaxial growth, wherein the first conductive type impurity concentration of the third silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; forming a fourth silicon carbide layer on the third silicon carbide layer by epitaxial growth, wherein the fourth silicon carbide layer has a lower first conductivity type impurity concentration than the third silicon carbide layer; and A step of performing a heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer.
2. The method for manufacturing a semiconductor substrate according to claim 1, wherein: In the step of performing the heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer, A first conductive type impurity concentration of 1×10 17 atoms / cm 3 Above and 1×10 18 atoms / cm 3 The following is the fifth silicon carbide layer.
3. The method for manufacturing a semiconductor substrate according to claim 1, wherein: After the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer, the following step is further included: A step of forming a sixth silicon carbide layer on the second silicon carbide layer by epitaxial growth, wherein the first conductive type impurity concentration of the sixth silicon carbide layer is 5×10 17 atoms / cm 3 More than and less than 1×10 20 atoms / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; and A step of forming a seventh silicon carbide layer on the sixth silicon carbide layer by an epitaxial growth method, wherein the first conductive type impurity concentration of the seventh silicon carbide layer is 1×10 14 atoms / cm 3 Above and 1×10 17 atoms / cm 3 Below, the film thickness is 0.001 μm or more and 0.1 μm or less.
4. The method for manufacturing a semiconductor substrate according to claim 1, wherein: Before the step of forming the second silicon carbide layer, the method further includes forming the first silicon carbide layer on the silicon carbide substrate by an epitaxial growth method.
5. The method for manufacturing a semiconductor substrate according to claim 1, wherein: The first conductivity type impurity concentration of the first silicon carbide layer is 5×10 17 atoms / cm 3 Above and 1×10 19 atoms / cm 3 the following.
6. A method for manufacturing a semiconductor device, further comprising the following steps: forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a first electrode under the first silicon carbide layer; and The step of forming a second electrode on the ninth silicon carbide layer.
7. A method for manufacturing a semiconductor device, further comprising the following steps: forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a tenth silicon carbide layer of the first conductivity type on the ninth silicon carbide layer; forming a first electrode under the first silicon carbide layer; forming a groove from the tenth silicon carbide layer to the fourth silicon carbide layer; forming a first insulating film in the trench; forming a third electrode in the trench and disposed on the ninth silicon carbide layer via the first insulating film; as well as The step of forming a second electrode on the tenth silicon carbide layer.
8. A method for manufacturing a semiconductor device, further comprising the following steps: forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a tenth silicon carbide layer of the first conductivity type on the ninth silicon carbide layer; forming a first insulating film on the ninth silicon carbide layer; forming a third electrode on the first insulating film; forming a second insulating film on the third electrode; as well as and forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer.
9. A semiconductor substrate comprising: a first silicon carbide layer; A fifth silicon carbide layer is provided on the first silicon carbide layer, and the first conductive type impurity concentration is 1×10 17 cm - 3 atoms / cm 3 More than and less than 1×10 19 cm -3 atoms / cm 3 ; The third silicon carbide layer is disposed on the fifth silicon carbide layer and has a first conductive type impurity concentration of 5×10 17 cm - 3 atoms / cm 3 More than and less than 1×10 20 cm -3 atom / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; and a fourth silicon carbide layer, which is disposed on the third silicon carbide layer and has a lower first conductivity type impurity concentration than the third silicon carbide layer; In a region including the first silicon carbide layer and the fifth silicon carbide layer, in a direction from the first silicon carbide layer toward the fifth silicon carbide layer, a concentration gradient of a first conductivity type impurity is different from a concentration gradient of an impurity different from the first conductivity type impurity.
10. A semiconductor substrate comprising: a first silicon carbide layer; A fifth silicon carbide layer is provided on the first silicon carbide layer, and the first conductive type impurity concentration is 1×10 17 cm - 3 atoms / cm 3 More than and less than 1×10 19 cm -3 atoms / cm 3 ; The third silicon carbide layer is disposed on the fifth silicon carbide layer and has a first conductive type impurity concentration of 5×10 17 cm - 3 atoms / cm 3 More than and less than 1×10 20 cm -3 atom / cm 3 , the film thickness is 0.5 μm or more and 20 μm or less; and a fourth silicon carbide layer, which is disposed on the third silicon carbide layer and has a lower first conductivity type impurity concentration than the third silicon carbide layer; The BPD density of the first silicon carbide layer is 10 / cm 2 above, The BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 / cm 2 the following.
Citation Information
Patent Citations
Silicon carbide semiconductor substrate and silicon carbide semiconductor device using the same
JP2009088223A