Manufacturing method of semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device. A method for manufacturing a semiconductor device according to one embodiment of the present invention may comprise the steps of: forming a thin film structure on a substrate; forming a through hole penetrating the thin film structure; forming a channel layer covering at least a portion of the through hole; performing a high-pressure surface treatment process on the channel layer; and performing an insulating layer forming step on the channel layer.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] Semiconductor devices are mainly used as components of devices similar to electronic circuits that utilize the conductive properties of semiconductors. Semiconductors can be divided into memory semiconductors and non-memory semiconductors. Memory semiconductors can be divided into volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM) and non-volatile memories such as mask read-only memory (Mask ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory.

[0003] Figure 1 and Figure 2 The manufacturing process of a general semiconductor device is shown.

[0004] First, refer to Figure 1 The thin film structure TS can be formed by repeatedly and alternately evaporating the insulating layer 110 and the gate electrode layer 112 on the substrate 100 .

[0005] Next, a through hole H exposing the substrate 100 may be formed through the thin film structure TS. In a planar view, the through hole H may be two-dimensionally formed on the upper surface of the thin film structure TS.

[0006] Subsequently, a semiconductor pattern SP covering at least a portion of the through hole H and exposing the substrate 100 may be formed. The semiconductor pattern SP may include a blocking layer 120 covering at least a portion of the through hole H, a charge storage layer 130 formed on the blocking layer 120, and a first insulating layer 140 formed on the charge storage layer 130.

[0007] like Figure 1 As shown, after forming the semiconductor pattern SP, a channel layer 150 covering the semiconductor pattern SP and the substrate 100 may be formed. The channel layer 150 may be a semiconductor material formed by using one of the techniques of atomic layer deposition (ALD) or chemical vapor deposition (CVD). As an example, the channel layer 150 may be a polycrystalline silicon film. According to an embodiment of the present invention, when evaporating, the channel layer 150 may be amorphous, but may be crystallized by an annealing process or the like. According to an embodiment of the present invention, the channel layer 150 may expose the substrate 100.

[0008] Then, the channel layer 150 may be patterned to form a trench pattern T inside the channel layer 150 .

[0009] Then, if Figure 2As shown, an insulating layer forming process may be performed on the channel layer 150 to form the second insulating layer 160 inside the trench pattern T of the channel layer 150. However, during the formation of the second insulating layer 160, if the channel layer 150 is not protected, a portion of the channel layer 150 may be consumed if the second insulating layer 160 is formed, that is, a consumption region 170 may be generated during the formation of the second insulating layer 160.

[0010] As described above, during the manufacturing process of the semiconductor device, as the consumption region 170 is generated, if the thickness of the channel layer 150 cannot meet the specified level, the electrical characteristics of the semiconductor device (for example, V T Distribution (V T distribution)) is reduced.

[0011] Furthermore, during the manufacturing process of the semiconductor device, the generation of the consumption region 170 not only reduces the conformality of the channel layer 150, but also may cause the electrical characteristics of the semiconductor device (for example, V T Distribution (V T distribution)) is reduced. Summary of the invention

[0012] Technical issues

[0013] The object of the present invention is to provide a method for manufacturing a semiconductor device, which can reduce the consumption area of ​​the channel layer and improve the conformality of the channel layer during the process of forming an insulating layer after forming the channel layer, thereby improving the electrical characteristics of the semiconductor device.

[0014] The purpose of the present invention is not limited to the purpose mentioned above, and other purposes and advantages not mentioned can be further clearly understood through the embodiments of the present invention described below. In addition, the purpose and advantages of the present invention can be achieved based on multiple structural elements and their combinations recorded in the scope of protection of the invention.

[0015] Technical Solution

[0016] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the following steps: forming a thin film structure on a substrate; forming a through hole penetrating the thin film structure; forming a channel layer covering at least a portion of the through hole; performing a high-voltage surface treatment process on the channel layer; and performing an insulating layer forming process on the channel layer.

[0017] In one embodiment of the present invention, the step of performing the high pressure surface treatment process may include the step of performing a high pressure nitridation (HPN) process or the step of performing a high pressure fluorination (HPF) process.

[0018] In one embodiment of the present invention, the high pressure surface treatment process may be performed in an inert atmosphere in a treatment device injected with a nitrogen-containing reactive gas or a fluorine-containing reactive gas.

[0019] In one embodiment of the present invention, when the high pressure surface treatment process is performed, the concentration of the reactive gas in the treatment device may be greater than 1%.

[0020] In one embodiment of the present invention, when the high pressure surface treatment process is performed, the internal pressure of the treatment device can be maintained at 2 atmospheres to 100 atmospheres.

[0021] In one embodiment of the present invention, when the high pressure surface treatment process is performed, the internal temperature of the treatment device may be maintained at 200° C. to 1000° C.

[0022] In one embodiment of the present invention, a groove pattern may be formed inside the channel layer.

[0023] In one embodiment of the present invention, a second insulating layer may be formed inside the trench pattern by performing an insulating layer forming process on the channel layer.

[0024] In one embodiment of the present invention, the method for manufacturing a semiconductor device may further include a step of forming a semiconductor pattern between the through hole and the channel layer.

[0025] In one embodiment of the present invention, the semiconductor pattern may include: a blocking layer covering at least a portion of the through hole; a charge storage layer formed on the blocking layer; and a first insulating layer formed on the charge storage layer.

[0026] Effects of the Invention

[0027] According to an embodiment of the present invention, a method for manufacturing a semiconductor device has the following effect, namely, during the manufacturing process of the semiconductor device, after forming a channel layer, during the process of forming an insulating layer, the consumption area of ​​the channel layer can be reduced and the conformality of the channel layer can be improved, thereby improving the electrical characteristics of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 and Figure 2 A diagram showing a manufacturing process of a general semiconductor device.

[0029] Figures 3 to 5 FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0030] Figure 6 The graphs respectively show the thickness of the channel layer of a semiconductor device prepared based on a common semiconductor device manufacturing method and the thickness of the channel layer of a semiconductor device prepared based on a semiconductor device manufacturing method according to an embodiment of the present invention.

[0031] Figure 7 The graphs respectively show the conformality of the channel layer of a semiconductor device prepared based on a common semiconductor device manufacturing method and the conformality of the channel layer of a semiconductor device prepared based on a semiconductor device manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] With reference to the accompanying drawings, the above-mentioned objects, features and advantages will be described in detail, so that ordinary technicians in the technical field to which the present invention belongs can easily implement the embodiments of the present invention. In the process of describing this specification, when it is judged that the specific description of the known technology may confuse the main purpose of the present invention, its detailed description will be omitted. Hereinafter, with reference to the accompanying drawings, the preferred embodiments of the present invention will be described in detail. In the accompanying drawings, the same reference numerals represent the same or similar structural elements.

[0033] Figures 3 to 5 The invention shows a process for manufacturing a semiconductor device according to an embodiment of the present invention.

[0034] First, refer to Figure 3 The thin film structure TS can be formed by repeatedly and alternately evaporating the insulating layer 210 and the gate electrode layer 212 on the substrate 200 .

[0035] In one embodiment of the present invention, the substrate 200 may be a silicon substrate, a germanium substrate or a silicon germanium substrate.

[0036] In one embodiment of the present invention, the insulating layer 210 may be a silicon oxide film formed by a thermal oxidation process or a silicon oxide film formed by an evaporation technique. In one embodiment of the present invention, the plurality of insulating layers 210 may have the same thickness. In another embodiment of the present invention, some of the plurality of insulating layers 210 may also have different thicknesses.

[0037] In one embodiment of the present invention, the gate layer 212 may be a polysilicon film made of a conductive material, and according to the present invention, may include materials such as silicide or polycide. In another embodiment of the present invention, the gate layer 212 may also include metal materials such as aluminum (Al), copper (Cu), and tungsten (W).

[0038] In one embodiment of the present invention, the insulating layer 210 and the gate layer 212 may be formed by thermal chemical vapor deposition (ThermalCVD), plasma enhanced CVD, physical CVD or atomic layer deposition (ALD, Atomic Layer Deposition) processes.

[0039] Next, a through hole H exposing the substrate 200 may be formed through the thin film structure TS. In a planar perspective, the through hole H may be formed two-dimensionally on the upper surface of the thin film structure TS. The step of forming the through hole H may include the following steps: forming a first mask pattern (not shown) on the thin film structure TS, the first mask pattern having a plurality of openings for defining a formation area of ​​the through hole H; and anisotropically etching the thin film structure TS using the first mask pattern as an etching mask. The first mask pattern may be formed of a material that is selective to the insulating layer 210 and the gate layer 212. The upper portion of the substrate 200 may be recessed by over-etching the upper surface of the substrate 200 through an etching process.

[0040] Subsequently, a semiconductor pattern SP covering at least a portion of the through hole H and exposing the substrate 100 may be formed. The semiconductor pattern SP may include: a blocking layer 220 covering at least a portion of the through hole H; a charge storage layer 230 formed on the blocking layer 220; and a first insulating layer 240 formed on the charge storage layer 230. As an example, the semiconductor pattern SP may be formed by evaporation using a plasma enhanced CVD (Plasma enhanced CVD), a physical CVD (physical CVD) or an atomic layer deposition (ALD, Atomic Layer Deposition) technology.

[0041] like Figure 3 As shown, after forming the semiconductor pattern SP, a channel layer 250 covering the semiconductor pattern SP and the substrate 200 may be formed. The channel layer 250 may be a semiconductor material formed by one of atomic layer deposition (ALD) and chemical vapor deposition (CVD). As an example, the channel layer 250 may be a polycrystalline silicon film. According to an embodiment of the present invention, when evaporating, the channel layer 250 may be amorphous, but may be crystallized by an annealing process or the like. According to an embodiment of the present invention, the channel layer 250 may expose the substrate 200.

[0042] In the above embodiment, after forming the semiconductor pattern SP in the through hole H, the channel layer 250 is formed on the semiconductor pattern SP. However, in another embodiment of the present invention, the semiconductor pattern SP may not be formed in the through hole H but only in the channel layer 250 .

[0043] After forming the channel layer 250 , a trench pattern T may be formed inside the channel layer 250 by performing patterning.

[0044] Then, if Figure 4 As shown, as the high pressure surface treatment process is performed on the channel layer 250 , a protection layer 255 may be formed inside the trench pattern T of the channel layer 250 .

[0045] In one embodiment of the present invention, the high pressure surface treatment process performed on the channel layer 250 may include a high pressure nitridation (HPN) process or a high pressure fluorination (HPF) process.

[0046] In one embodiment of the present invention, the high pressure nitridation process may be performed in an inert atmosphere in a processing device (eg, a chamber or a furnace) injected with a nitrogen-containing reactive gas.

[0047] For example, the inert gas may be N 2 , Ar, or He, but the type of the inert gas is not limited thereto.

[0048] For example, the nitrogen-containing reactive gas may be NH 2 or NH 3 , but the type of the nitrogen-containing reactive gas is not limited thereto.

[0049] In one embodiment of the present invention, when performing the high pressure nitridation process, the concentration of the nitrogen-containing reactive gas in the processing device may be above 1%. For example, when performing the high pressure nitridation process, the concentration of the nitrogen-containing reactive gas in the processing device may be 1% to 100%.

[0050] In one embodiment of the present invention, when the high pressure nitridation process is performed, the internal pressure of the processing device may be maintained at 2 atmospheres to 100 atmospheres.

[0051] In one embodiment of the present invention, when the high pressure nitridation process is performed, the internal temperature of the processing device may be maintained at 200° C. to 1000° C.

[0052] In one embodiment of the present invention, the high pressure fluorination process may be performed in an inert atmosphere in a processing device injected with a fluorine-containing reactive gas.

[0053] For example, the inert gas may be N 2 , Ar, or He, but the type of the inert gas is not limited thereto.

[0054] For example, the fluorine-containing reactive gas may be CF4, C2F6, C3F8, NF3, SF6, WF6, or HF, but the type of the fluorine-containing reactive gas is not limited thereto.

[0055] In one embodiment of the present invention, when performing the high pressure fluorination process, the concentration of the fluorine-containing reactive gas in the processing device may be above 1%. For example, when performing the high pressure fluorination process, the concentration of the fluorine-containing reactive gas in the processing device may be 1% to 100%.

[0056] In one embodiment of the present invention, when the high pressure fluorination process is performed, the internal pressure of the processing device may be maintained at 2 atmospheres to 100 atmospheres.

[0057] In one embodiment of the present invention, when the high pressure fluorination process is performed, the internal temperature of the processing device may be maintained at 200° C. to 1000° C.

[0058] Then, if Figure 5 As shown, after the protection layer 255 is formed inside the channel pattern T of the channel layer 250 by performing a high pressure surface treatment process on the channel layer 250, an insulating layer forming process may be performed on the channel layer 250 to form a second insulating layer 260 inside the groove pattern T of the channel layer 250. As an example, the insulating layer forming process may be an insulating material (e.g., SiOx, SiNy, etc.) evaporation process or a channel layer 250 oxidation process, but the type of the insulating layer forming process is not limited thereto.

[0059] In the process of forming the second insulating layer 260, a part of the channel layer 250 will be consumed, that is, in the process of forming the second insulating layer 260, a consumption area 270 will be generated. According to one embodiment of the present invention, in the process of forming the second insulating layer 260, instead of directly forming the second insulating layer 260 on the channel layer 250, the second insulating layer 260 is formed on the protective layer 255. Therefore, in terms of thickness or volume, the consumption area 270 generated in the process of forming the second insulating layer 260 according to one embodiment of the present invention can be smaller than that based on Figure 2 A depletion region 170 resulting from a typical semiconductor manufacturing process is shown.

[0060] Furthermore, in the process of forming the second insulating layer 260, as the second insulating layer 260 is formed on the protective layer 255 instead of directly forming the second insulating layer 260 on the channel layer 250, compared with Figure 2 The conventional semiconductor manufacturing process shown can improve the conformality of the channel layer 250 .

[0061] As described above, after forming the protection layer 255 on the channel layer 250 , the second insulating layer 260 may be formed, so that the thickness of the channel layer 250 is maintained above a predetermined level, and the conformality of the channel layer 250 may be improved compared to the prior art. Thus, the electrical characteristics of the semiconductor device may be improved.

[0062] Figure 6The graphs respectively show the thickness of the channel layer of a semiconductor device prepared based on a common semiconductor device manufacturing method and the thickness of the channel layer of a semiconductor device prepared based on a semiconductor device manufacturing method according to an embodiment of the present invention.

[0063] exist Figure 6 In the figure, M1 represents the thickness 150 of the channel layer measured before the insulating layer forming process is performed on the channel layer based on the ordinary semiconductor device manufacturing method or the semiconductor device manufacturing method of one embodiment of the present invention. In addition, M2 represents the thickness 112 of the channel layer and the thickness 38 of the consumption area after the insulating layer forming process is directly performed on the channel layer based on the ordinary semiconductor device manufacturing method, and M3 represents the thickness 135 of the channel layer and the thickness 15 of the consumption area after the high-voltage surface treatment process and the insulating layer forming process are sequentially performed on the channel layer based on the semiconductor device manufacturing method of one embodiment of the present invention.

[0064] like Figure 6 As shown, if an insulating layer forming process is performed on the channel layer based on a common semiconductor device manufacturing method, the channel layer is over-consumed, resulting in a thickness 38 of the consumption region becoming thicker and a thickness 112 of the channel layer becoming thinner.

[0065] However, in the semiconductor device manufacturing method according to an embodiment of the present invention, after forming the protection layer on the channel layer, the insulating layer forming process is performed on the channel layer. Since the channel layer is not directly consumed, the thickness 15 of the consumed region becomes thinner and the thickness 135 of the channel layer becomes thicker compared to the semiconductor device manufactured based on the ordinary semiconductor device manufacturing method. As a result, the channel layer thickness at a predetermined level can be maintained, thereby improving the electrical characteristics of the semiconductor device.

[0066] Figure 7 The graphs respectively show the conformality of a channel layer of a semiconductor device manufactured based on a common semiconductor device manufacturing method and the conformality of a channel layer of a semiconductor device manufactured based on a semiconductor device manufacturing method according to an embodiment of the present invention.

[0067] exist Figure 7 In FIG. 1 , N1 represents the conformality 95 of the channel layer measured before the insulating layer forming process is performed on the channel layer based on a common semiconductor device manufacturing method or a semiconductor device manufacturing method according to an embodiment of the present invention.

[0068] Also, N2 represents the conformality 87 of the channel layer measured after directly performing an insulating layer forming step on the channel layer based on a general semiconductor device manufacturing method.

[0069] Furthermore, N3 represents the conformality 90 of the channel layer measured when the insulating layer forming step is performed after the high pressure surface treatment step is performed on the channel layer in a state where the internal pressure of the processing apparatus is maintained at 5 atmospheres according to the semiconductor device manufacturing method of one embodiment of the present invention.

[0070] Furthermore, N4 represents the conformality 93 of the channel layer measured when a high pressure surface treatment process is performed on the channel layer and then an insulating layer forming process is performed in a state where the internal pressure of the processing apparatus is maintained at 10 atmospheres according to the semiconductor device manufacturing method of one embodiment of the present invention.

[0071] Furthermore, N5 represents the conformality 95 of the channel layer measured when a high pressure surface treatment process is performed on the channel layer and then an insulating layer forming process is performed in a state where the internal pressure of the processing apparatus is maintained at 20 atmospheres according to the semiconductor device manufacturing method of one embodiment of the present invention.

[0072] like Figure 7 As shown, compared with the conformality 87 of the channel layer measured after the insulating layer forming process is directly performed on the channel layer based on the common semiconductor device manufacturing method, the conformality 90, 93, and 95 of the channel layer measured when the insulating layer forming process is performed after the high-voltage surface treatment process is performed on the channel layer based on the semiconductor device manufacturing method of an embodiment of the present invention are relatively high. That is, if the insulating layer forming process is performed after the high-voltage surface treatment process is performed on the channel layer, the conformality of the channel layer is improved compared with the case where the insulating layer forming process is directly performed on the channel layer. As a result, the electrical characteristics of the semiconductor device can be improved.

[0073] And, if Figure 7 As shown, when a high pressure surface treatment process is performed on a channel layer according to a semiconductor device manufacturing method according to an embodiment of the present invention, the conformality of the channel layer can be improved by increasing the internal gas pressure of the processing device.

[0074] As described above, although the present specification is described with reference to the illustrative drawings, the present invention is not limited to the embodiments and drawings disclosed in the present specification, and a person skilled in the art of the present invention can make various modifications. Moreover, in the process of describing the embodiments of the present invention, although the structural effects of the present invention are not clearly described, the effects that can be predicted by the corresponding structures should also be recognized.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The steps include: forming a thin film structure on a substrate; forming a through hole penetrating the thin film structure; forming a channel layer covering at least a portion of the through hole; performing a high pressure surface treatment process on the channel layer; and An insulating layer forming process is performed on the channel layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of performing the high-pressure surface treatment process includes the step of performing a high-pressure nitridation process or the step of performing a high-pressure fluoridation process.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The high pressure surface treatment process is performed in an inert atmosphere in a treatment apparatus into which a reactive gas containing nitrogen or fluorine is injected.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: When the high-pressure surface treatment step is performed, the concentration of the reactive gas in the treatment device is greater than 1%.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: When the above-mentioned high-pressure surface treatment process is performed, the internal pressure of the treatment device is maintained at 2 atmospheres to 100 atmospheres.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: When the above-mentioned high pressure surface treatment process is performed, the internal temperature of the treatment device is maintained at 200°C to 1000°C.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: forming a groove pattern inside the channel layer, By performing the insulating layer forming step on the channel layer, a second insulating layer is formed inside the groove pattern.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further includes forming a semiconductor pattern between the through hole and the channel layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor pattern includes: a barrier layer covering at least a portion of the through hole; a charge storage layer formed on the blocking layer; and The first insulating layer is formed on the charge storage layer.

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