Current Sampling Circuit and Current Sampling Method Based on Gallium Nitride Power Transistor

Abstract

The present application discloses a current sampling circuit and a current sampling method based on a gallium nitride power transistor, belonging to the field of circuit technologies. The temperature compensation module in the current sampling circuit can ensure that the conduction resistance ratio between the silicon sampling transistor and the upper transistor / lower transistor remains consistent within different temperature ranges; when the upper transistor conducts, the first temperature compensation module controls the first negative feedback module to generate a positive current or a negative current proportional to the sampling current, and the first current mirror module outputs the positive current or the negative current to the sampling module, and the sampling module calculates the sampling current of the upper transistor according to the positive current or the negative current; when the lower transistor conducts, the second temperature compensation module controls the second negative feedback module to generate a positive current or a negative current proportional to the sampling current, and the second current mirror module outputs the positive current or the negative current to the sampling module, and the sampling module calculates the sampling current of the lower transistor according to the positive current or the negative current. The present application can perform temperature compensation and can achieve bidirectional current sampling.

Description

Technical Field

[0001] This application relates to the field of circuit technologies, and particularly to a current sampling circuit and a current sampling method based on a gallium nitride power transistor. Background Art

[0002] Compared with a silicon (Si) power transistor, a gallium nitride (GaN) power transistor has a smaller parasitic capacitance and a lower on-resistance, and is widely used in high-voltage switching power supplies.

[0003] As Figure 1 shown, a high-voltage switching power supply includes gallium nitride power transistors M T and M B . When sampling the current of the high-voltage switching power supply, a silicon sampling transistor is usually used to sample the current of the gallium nitride power transistor. Since the sampling current is usually on the order of one-thousandth of the current of the gallium nitride power transistor, the loss of the silicon sampling transistor can be ignored. However, there is a problem of mismatch between the on-resistance of the silicon sampling transistor and the on-resistance of the gallium nitride power transistor at different temperatures, resulting in low sampling accuracy over the entire temperature range. Summary of the Invention

[0004] This application provides a current sampling circuit and a current sampling method based on a gallium nitride power transistor, which are used to solve the problem that the on-resistance of the silicon sampling transistor and the on-resistance of the gallium nitride power transistor are mismatched at different temperatures, resulting in low sampling accuracy over the entire temperature range. The technical solutions are as follows:

[0005] According to a first aspect of this application, a current sampling circuit based on a gallium nitride power transistor is provided. The current sampling circuit includes an upper transistor sampling circuit and a lower transistor sampling circuit. The upper transistor sampling circuit is used to sample the current of the upper transistor in a high-voltage switching power supply, and the lower transistor sampling circuit is used to sample the current of the lower transistor in the high-voltage switching power supply. The upper transistor and the lower transistor are gallium nitride power transistors;

[0006] The upper transistor sampling circuit includes a first temperature compensation module, a first negative feedback module, a first current mirror module, and a sampling module connected in sequence. The first temperature compensation module includes a first silicon sampling upper transistor and a first upper sampling transistor resistance compensation array connected together, and a first silicon sampling lower transistor and a first lower sampling transistor resistance compensation array connected together. The first upper sampling transistor resistance compensation array and the first lower sampling transistor resistance compensation array are resistance arrays with a negative temperature coefficient and / or a positive temperature coefficient, and the first upper sampling transistor resistance compensation array and the first lower sampling transistor resistance compensation array are respectively connected to the upper transistor to ensure that the on-resistance ratio between the first silicon sampling upper transistor and the upper transistor remains consistent within different temperature ranges, and the on-resistance ratio between the first silicon sampling lower transistor and the upper transistor remains consistent;

[0007] When the upper transistor is turned on, the first temperature compensation module is configured to cause, through the first negative feedback module, the first silicon sampling lower transistor and the first lower sampling transistor resistance compensation array to flow a forward current proportional to the sampling current of the upper transistor, or cause, through the first negative feedback module, the first silicon sampling upper transistor and the first upper sampling transistor resistance compensation array to flow a negative current proportional to the sampling current of the upper transistor; the first current mirror module is configured to mirror and output the forward current or the negative current to a sampling resistor in the sampling module; the sampling module is configured to calculate the sampling current of the upper transistor according to the forward current or the negative current;

[0008] The lower transistor sampling circuit includes a second temperature compensation module, a second negative feedback module, a second current mirror module, and a sampling module connected in sequence; the second temperature compensation module includes a second silicon sampling upper transistor and a second upper sampling transistor resistance compensation array connected together, and a second silicon sampling lower transistor and a second lower sampling transistor resistance compensation array connected together, where the second upper sampling transistor resistance compensation array and the second lower sampling transistor resistance compensation array are resistance arrays with negative temperature coefficient and / or positive temperature coefficient, and the second upper sampling transistor resistance compensation array and the second lower sampling transistor resistance compensation array are respectively connected to the lower transistor to ensure that in different temperature ranges, the on-resistance ratio of the second silicon sampling upper transistor to the lower transistor remains consistent, and the on-resistance ratio of the second silicon sampling lower transistor to the lower transistor remains consistent;

[0009] When the lower transistor is turned on, the second temperature compensation module is configured to cause, through the second negative feedback module, the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array to flow a forward current proportional to the sampling current of the lower transistor, or cause, through the second negative feedback module, the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array to flow a negative current proportional to the sampling current of the lower transistor; the second current mirror module is configured to mirror and output the forward current or the negative current to a sampling resistor in the sampling module; the sampling module is configured to calculate the sampling current of the lower transistor according to the forward current or the negative current.

[0010] In a possible implementation manner, the first temperature compensation module includes a first silicon sampling upper transistor, a first silicon sampling lower transistor, a first upper sampling transistor resistance compensation array, and a first lower sampling transistor resistance compensation array;

[0011] The source of the first silicon sampling upper transistor is connected to the first output terminal of the first negative feedback module as the first input terminal of the first temperature compensation module; the drain of the first silicon sampling upper transistor is connected to the first end of the first upper sampling transistor resistance compensation array; the second end of the first upper sampling transistor resistance compensation array is connected to the drain of the upper transistor as the first output terminal of the first temperature compensation module;

[0012] The drain of the first silicon sampling lower transistor is connected to the second output terminal of the first negative feedback module as the second input terminal of the first temperature compensation module; the source of the first silicon sampling lower transistor is connected to the first end of the first lower sampling transistor resistance compensation array; the second end of the first lower sampling transistor resistance compensation array is connected to the source of the upper transistor as the second output terminal of the first temperature compensation module;

[0013] The gates of the first silicon sampling upper transistor and the first silicon sampling lower transistor are respectively connected to the gate of the upper transistor.

[0014] In a possible implementation, the first negative feedback module includes a first high-bandwidth operational amplifier, a second high-bandwidth operational amplifier, a first power transistor, and a second power transistor;

[0015] The negative input terminal of the first high-bandwidth operational amplifier, the positive input terminal of the second high-bandwidth operational amplifier, and the drain of the second power transistor are connected and used as the first output terminal of the first negative feedback module;

[0016] The positive input terminal of the first high-bandwidth operational amplifier, the negative input terminal of the second high-bandwidth operational amplifier, and the drain of the first power transistor are connected and used as the second output terminal of the first negative feedback module;

[0017] The output terminal of the first high-bandwidth operational amplifier is connected to the gate of the first power transistor and used as the third output terminal of the first negative feedback module, and is connected to the first input terminal of the first current mirror module;

[0018] The output terminal of the second high-bandwidth operational amplifier is connected to the gate of the second power transistor and used as the fourth output terminal of the first negative feedback module, and is connected to the second input terminal of the first current mirror module;

[0019] The sources of the first power transistor and the second power transistor are connected to the bootstrap voltage as the input terminal of the first negative feedback module respectively.

[0020] In a possible implementation, the first current mirror module includes a third power transistor, a fourth power transistor, a first high-voltage transistor, a first low-voltage transistor, a second high-voltage transistor, and a second low-voltage transistor;

[0021] The gate of the third power transistor serves as the first input terminal of the first current mirror module; the gate of the fourth power transistor serves as the second input terminal of the first current mirror module;

[0022] The source of the third power transistor serves as the third input terminal of the first current mirror module and is connected to the bootstrap voltage; the source of the fourth power transistor serves as the fourth input terminal of the first current mirror module and is connected to the bootstrap voltage;

[0023] The drain of the third power transistor is connected to the source of the first high-voltage transistor; the drain of the first high-voltage transistor is respectively connected to the drain and gate of the first low-voltage transistor and then serves as the first output terminal of the first current mirror module, which is connected to the first input terminal of the sampling module; the source of the first low-voltage transistor is grounded; the gate of the first high-voltage transistor is connected to the source of the upper transistor;

[0024] The drain of the fourth power transistor is connected to the source of the second high-voltage transistor; the drain of the second high-voltage transistor is respectively connected to the drain and gate of the second low-voltage transistor and then serves as the second output terminal of the first current mirror module, which is connected to the second input terminal of the sampling module; the source of the second low-voltage transistor is grounded; the gate of the second high-voltage transistor is connected to the source of the upper transistor.

[0025] In a possible implementation, the second temperature compensation module includes a second silicon sampling upper transistor, a second silicon sampling lower transistor, a second lower sampling transistor resistor compensation array, and a second lower sampling transistor resistor compensation array;

[0026] The source of the second silicon sampling upper transistor serves as the first input terminal of the second temperature compensation module and is connected to the first output terminal of the second negative feedback module; the drain of the second silicon sampling upper transistor is connected to the first end of the second lower sampling transistor resistor compensation array; the second end of the second lower sampling transistor resistor compensation array serves as the first output terminal of the second temperature compensation module and is connected to the drain of the lower transistor;

[0027] The drain of the second silicon sampling lower transistor serves as the second input terminal of the second temperature compensation module and is connected to the second output terminal of the second negative feedback module; the source of the second silicon sampling lower transistor is connected to the first end of the second lower sampling transistor resistor compensation array; the second end of the second lower sampling transistor resistor compensation array serves as the second output terminal of the second temperature compensation module and is connected to the source of the lower transistor;

[0028] The gates of the second silicon sampling upper transistor and the second silicon sampling lower transistor are respectively connected to the gate of the lower transistor.

[0029] In a possible implementation, the second negative feedback module includes a third high-bandwidth operational amplifier, a fourth high-bandwidth operational amplifier, a fifth power transistor, and a sixth power transistor;

[0030] The negative input terminal of the third high-bandwidth operational amplifier, the positive input terminal of the fourth high-bandwidth operational amplifier, and the drain of the sixth power transistor are connected together and used as the first output terminal of the second negative feedback module;

[0031] The positive input terminal of the third high-bandwidth operational amplifier, the negative input terminal of the fourth high-bandwidth operational amplifier, and the drain of the fifth power transistor are connected together and used as the second output terminal of the second negative feedback module;

[0032] The output terminal of the third high-bandwidth operational amplifier is connected to the gate of the fifth power transistor and used as the third output terminal of the second negative feedback module, and is connected to the first input terminal of the second current mirror module;

[0033] The output terminal of the fourth high-bandwidth operational amplifier is connected to the gate of the sixth power transistor and used as the fourth output terminal of the second negative feedback module, and is connected to the second input terminal of the second current mirror module;

[0034] The sources of the fifth power transistor and the sixth power transistor are used as the input terminals of the second negative feedback module and are respectively connected to the bootstrap voltage.

[0035] In a possible implementation, the second current mirror module includes a seventh power transistor, an eighth power transistor, a third high-voltage transistor, a third low-voltage transistor, a fourth high-voltage transistor, and a fourth low-voltage transistor;

[0036] The gate of the seventh power transistor is used as the first input terminal of the second current mirror module; the gate of the eighth power transistor is used as the second input terminal of the second current mirror module;

[0037] The source of the seventh power transistor is used as the third input terminal of the second current mirror module and is connected to the bootstrap voltage; the source of the eighth power transistor is used as the fourth input terminal of the second current mirror module and is connected to the bootstrap voltage;

[0038] The drain of the seventh power transistor is connected to the source of the third high-voltage transistor; the drain of the third high-voltage transistor is connected to the drains and gates of the third low-voltage transistor together and used as the first output terminal of the second current mirror module, and is connected to the first input terminal of the sampling module; the source of the third low-voltage transistor is grounded; the gate of the third high-voltage transistor is connected to the drain of the lower transistor;

[0039] The drain of the eighth power transistor is connected to the source of the fourth high-voltage transistor; the drain of the fourth high-voltage transistor is connected to the drains and gates of the fourth low-voltage transistor together and used as the second output terminal of the second current mirror module, and is connected to the second input terminal of the sampling module; the source of the fourth low-voltage transistor is grounded; the gate of the fourth high-voltage transistor is connected to the drain of the lower transistor.

[0040] In a possible implementation, the sampling module includes a sample-and-hold circuit, a first current source, a second current source, a sampling resistor, and a reference power supply;

[0041] A first end of the sample-and-hold circuit serves as a first input end of the sampling module; a second end of the sample-and-hold circuit serves as a second input end of the sampling module; a third end of the sample-and-hold circuit is connected to a first end of the first current source; a fourth end of the sample-and-hold circuit is connected to a first end of the second current source;

[0042] A second end of the first current source is connected to an internal power supply voltage; a third end of the first current source is respectively connected to a second end of the second current source and a first end of the sampling resistor; a third end of the second current source is grounded;

[0043] A second end of the sampling resistor is connected to a positive electrode of the reference voltage; a negative electrode of the reference voltage is grounded.

[0044] In a possible implementation, when the sampling module includes a reference voltage, a voltage across the sampling resistor is equal to the reference voltage plus the sampling voltage, and the sampling voltage is equal to a product of the sampling current, a proportionality coefficient, and the sampling resistor.

[0045] According to a second aspect of the present application, there is provided a current sampling method for a current sampling circuit of a gallium nitride power transistor, which is used in the current sampling circuit of the gallium nitride power transistor as described above. The method includes:

[0046] When the upper transistor is turned on, the first negative feedback module is used to make a forward current proportional to the sampling current of the upper transistor flow through the first silicon sampling lower transistor and the first lower sampling transistor resistance compensation array, or the first negative feedback module is used to make a negative current proportional to the sampling current of the upper transistor flow through the first silicon sampling upper transistor and the first upper sampling transistor resistance compensation array; the first current mirror module mirrors and outputs the forward current or the negative current to the sampling resistor in the sampling module; the sampling module calculates the sampling current of the upper transistor according to the forward current or the negative current;

[0047] When the lower transistor is turned on, the second negative feedback module causes a positive current proportional to the sampling current of the lower transistor to flow through the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array, or the second negative feedback module causes a negative current proportional to the sampling current of the lower transistor to flow through the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array; the second current mirror module mirrors and outputs the positive current or the negative current to the sampling resistor in the sampling module; the sampling module calculates the sampling current of the lower transistor based on the positive current or the negative current.

[0048] The beneficial effects of the technical solution provided by this application at least include:

[0049] When using a silicon sampling transistor to sample the current of a gallium nitride power transistor, it is necessary to perform temperature compensation through a resistance compensation array to ensure that the on-resistance ratio of the silicon sampling transistor and the gallium nitride power transistor remains consistent within different temperature ranges, thereby improving the accuracy of current sampling.

[0050] When sampling the current of the upper transistor, the first negative feedback module can cause a positive current proportional to the sampling current of the upper transistor to flow through the first silicon sampling lower transistor and the first lower sampling transistor resistance compensation array, and calculate the sampling current of the upper transistor through the positive current; or, the first negative feedback module can cause a negative current proportional to the sampling current of the upper transistor to flow through the first silicon sampling upper transistor and the first upper sampling transistor resistance compensation array, and calculate the sampling current of the upper transistor through the negative current, thereby realizing the sampling of the bidirectional current of the upper transistor.

[0051] When sampling the current of the lower transistor, the second negative feedback module can cause a positive current proportional to the sampling current of the lower transistor to flow through the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array, and calculate the sampling current of the lower transistor through the positive current; or, the second negative feedback module can cause a negative current proportional to the sampling current of the lower transistor to flow through the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array, and calculate the sampling current of the lower transistor through the negative current, thereby realizing the sampling of the bidirectional current of the lower transistor. Description of the Drawings

[0052] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0053] Figure 1 It is a schematic structural diagram of a current sampling circuit based on a gallium nitride power transistor shown according to the related art;

[0054] Figure 2 It is a schematic structural diagram of a current sampling circuit based on a gallium nitride power transistor provided by an embodiment of the present application;

[0055] Figure 3 It is a schematic structural diagram of a resistor compensation array provided by an embodiment of the present application;

[0056] Figure 4 It is a schematic structural diagram of an upper transistor sampling circuit provided by an embodiment of the present application;

[0057] Figure 5 It is a schematic structural diagram of an upper transistor sampling circuit provided by an embodiment of the present application;

[0058] Figure 6 It is a schematic structural diagram of a lower transistor sampling circuit provided by an embodiment of the present application;

[0059] Figure 7 It is a schematic structural diagram of a lower transistor sampling circuit provided by an embodiment of the present application;

[0060] Figure 8 It is a schematic structural diagram of an upper and lower transistor sampling circuit provided by an embodiment of the present application;

[0061] Figure 9 It is a flowchart of a current sampling method based on a gallium nitride power transistor provided by an embodiment of the present application. Detailed implementation manners

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0063] As Figure 2 shown, an embodiment of the present application provides a current sampling circuit based on a gallium nitride power transistor. The current sampling circuit includes an upper transistor sampling circuit 210 and a lower transistor sampling circuit 220. The upper transistor sampling circuit 210 is used to sample the current of the upper transistor M T in the high-voltage switching power supply, and the lower transistor sampling circuit 220 is used to sample the current of the lower transistor M B in the high-voltage switching power supply.

[0064] In this embodiment, the upper transistor M T and the lower transistor M B are gallium nitride power transistors. Silicon sampling transistors are used in the sampling circuit. However, there is a problem of mismatch between the on-resistance of the silicon sampling transistor and the on-resistance of the gallium nitride power transistor at different temperatures. Therefore, temperature compensation is required to ensure that the ratio of the on-resistances of the silicon sampling transistor and the upper and lower transistors remains consistent within different temperature ranges.

[0065] Specifically, a resistor compensation array can be used to match the on-resistances of the silicon sampling tube and the gallium nitride power tube. The resistor compensation array is composed of resistors with positive temperature coefficients and resistors with negative temperature coefficients connected in series. As Figure 3 shown, R PT1 , R PT2 , R PT3 , R PT4 and R PT5 represent resistors with positive temperature coefficients, and R NT1 , R NT2 , R NT3 , R NT4 and R NT5 represent resistors with negative temperature coefficients. Of course, in actual use, the number of resistors can be set according to actual requirements, which is not limited here.

[0066] When the resistor compensation matrix is used for the first time, it needs to be calibrated. Specifically, when the temperature curve slope of the on-resistance of the silicon sampling tube is greater than the temperature curve slope of the on-resistance of the gallium nitride power tube, we will burn out the fuse of the resistor with a negative temperature coefficient so that the resistor is connected to the sampling circuit. Similarly, when the temperature curve slope of the on-resistance of the silicon sampling tube is less than the temperature curve slope of the on-resistance of the gallium nitride power tube, we will burn out the fuse of the resistor with a positive temperature coefficient so that the resistor is connected to the sampling circuit. After calibration, the resistors connected to the sampling circuit in the resistor compensation matrix are fixed, and the resistor compensation matrix does not need to be adjusted when the sampling circuit is used subsequently.

[0067] As Figure 4 and Figure 5 shown, in the calibrated sampling circuit, the upper tube sampling circuit 210 includes a first temperature compensation module 211, a first negative feedback module 212, a first current mirror module 213, and a sampling module 214 connected in sequence; the first temperature compensation module 211 includes a connected first silicon sampling upper tube M SH1 and a first upper sampling tube resistor compensation array, and a connected first silicon sampling lower tube M SH2 and a first lower sampling tube resistor compensation array. The first upper sampling tube resistor compensation array and the first lower sampling tube resistor compensation array are resistor arrays with negative temperature coefficients and / or positive temperature coefficients, and the first upper sampling tube resistor compensation array and the first lower sampling tube resistor compensation array are respectively connected to the upper tube M T to ensure that in different temperature ranges, the on-resistance ratio of the first silicon sampling upper tube M SH1 and the upper tube M T remains consistent, and the on-resistance ratio of the first silicon sampling lower tube M SH2 and the upper tube M T remains consistent.

[0068] Upper tube MT When conducting, when the current flows from V IN to V SW (the direction of the current I MT is positive), the first temperature compensation module 211 is used to control V in the first negative feedback module 212 A =V B such that the first silicon sampling lower transistor M SH2 and the first lower sampling transistor resistance compensation array flow through a forward current I proportional to the sampling current I T of the upper transistor M MT , or, when the current flows from V SHP to V SW (the direction of the current I IN is negative), by controlling V in the first negative feedback module 212 MT =V A such that the first silicon sampling upper transistor M B and the first upper sampling transistor resistance compensation array flow through a negative current I proportional to the sampling current I SH1 of the upper transistor M T ; the first current mirror module 213 is used to mirror and output the forward current I MT or the negative current I SHN to the sampling resistor R in the sampling module 214 SHP ; the sampling module 214 is used to calculate the sampling current I of the upper transistor M SHN according to the forward current I SNS or the negative current I SHP ; SHN . T MT .

[0069] As shown in Figure 6 and Figure 7 , in the calibrated sampling circuit, the lower transistor sampling circuit 220 includes a second temperature compensation module 221, a second negative feedback module 222, a second current mirror module 223, and a sampling module 214 connected in sequence; the second temperature compensation module 221 includes a second silicon sampling upper transistor M SH3 and a second upper sampling transistor resistance compensation array, and, a second silicon sampling lower transistor M SH4 and a second lower sampling transistor resistance compensation array connected, the second upper sampling transistor resistance compensation array and the second lower sampling transistor resistance compensation array are negative temperature coefficient and / or positive temperature coefficient resistance arrays, and the second upper sampling transistor resistance compensation array and the second lower sampling transistor resistance compensation array are respectively connected to the lower transistor M B to ensure that in different temperature ranges, the on-resistance ratio of the second silicon sampling upper transistor M SH3 and the lower transistor M B remains consistent, and the on-resistance ratio of the second silicon sampling lower transistor M SH4 and the lower transistor MB The on-resistance ratios remain consistent.

[0070] Lower transistor M B When it is turned on, when the current flows from V SW to ground (the direction of the current I MB is positive), the second temperature compensation module 221 is used to control V in the second negative feedback module 222 A =V B so that the second silicon sampling lower transistor M SH4 and the second lower sampling transistor resistance compensation array flow through a forward current I proportional to the sampling current I B of the lower transistor M MB ; or, when the current flows from ground to V SHP (the direction of the current I SW is negative), by controlling V in the second negative feedback module 222 MB =V A =V B so that the second silicon sampling upper transistor M SH3 and the second upper sampling transistor resistance compensation array flow through a negative current I proportional to the sampling current I B of the lower transistor M MB ; the second current mirror module 223 is used to mirror and output the forward current I SHN or the negative current I SHP to the sampling resistor R in the sampling module 214 SHN ; the sampling module 214 is used to calculate the sampling current I SNS of the lower transistor M SHP based on the forward current I SHN or the negative current I B . MB .

[0071] Figure 8 Fig. shows the complete current sampling circuit including the upper transistor sampling circuit 210 and the lower transistor sampling circuit 220.

[0072] The structures of the upper transistor sampling circuit 210 and the lower transistor sampling circuit 220 will be described separately below.

[0073] (1) First temperature compensation module 211

[0074] (1) The first temperature compensation module 211

[0075] The first temperature compensation module 211 includes the first silicon sampling upper transistor M SH1 , the first silicon sampling lower transistor M SH2 , the first upper sampling transistor resistance compensation array and the first lower sampling transistor resistance compensation array;

[0076] The first silicon sampling upper transistor M SH1The source of is connected to the first input terminal of the first temperature compensation module 211 and the first output terminal of the first negative feedback module 212; the drain of the first silicon sampling upper transistor M SH1 is connected to the first end of the first upper sampling transistor resistance compensation array; the second end of the first upper sampling transistor resistance compensation array serves as the first output terminal of the first temperature compensation module 211 and is connected to the drain of the upper transistor M T ;

[0077] The drain of the first silicon sampling lower transistor M SH2 is connected to the second input terminal of the first temperature compensation module 211 and the second output terminal of the first negative feedback module 212; the source of the first silicon sampling lower transistor M SH2 is connected to the first end of the first lower sampling transistor resistance compensation array; the second end of the first lower sampling transistor resistance compensation array serves as the second output terminal of the first temperature compensation module 211 and is connected to the source of the upper transistor M T ;

[0078] The gates of the first silicon sampling upper transistor M SH1 and the first silicon sampling lower transistor M SH2 are respectively connected to the gate TG of the upper transistor M T .

[0079] (2) The first negative feedback module 212

[0080] The first negative feedback module 212 includes a first high - bandwidth operational amplifier Positive HB AMP1, a second high - bandwidth operational amplifier Negative HB AMP1, a first power transistor M SM1 and a second power transistor M SM3 ;

[0081] The negative input terminal of the first high - bandwidth operational amplifier Positive HB AMP1, the positive input terminal of the second high - bandwidth operational amplifier Negative HB AMP1, and the drain of the second power transistor M SM3 are connected and serve as the first output terminal of the first negative feedback module 212;

[0082] The positive input terminal of the first high - bandwidth operational amplifier Positive HB AMP1, the negative input terminal of the second high - bandwidth operational amplifier Negative HB AMP1, and the drain of the first power transistor M SM1 are connected and serve as the second output terminal of the first negative feedback module 212;

[0083] The output terminal of the first high - bandwidth operational amplifier Positive HB AMP1 is connected to the gate of the first power transistor M SM1 and serves as the third output terminal of the first negative feedback module 212, and is connected to the first input terminal of the first current mirror module 213;

[0084] The output terminal of the second high-bandwidth operational amplifier Negative HB AMP1 is connected to the gate of the second power transistor M SM3 and serves as the fourth output terminal of the first negative feedback module 212, and is connected to the second input terminal of the first current mirror module 213;

[0085] The source electrodes of the first power transistor M SM1 and the second power transistor M SM3 serve as the input terminals of the first negative feedback module 212 and are respectively connected to the bootstrap voltage V BST connected.

[0086] (3) The first current mirror module 213

[0087] The first current mirror module 213 includes a third power transistor M SM2 , a fourth power transistor M SM4 , a first high-voltage transistor M HV1 , a first low-voltage transistor M LV1 , a second high-voltage transistor M HV2 and a second low-voltage transistor M LV2 ;

[0088] The gate of the third power transistor M SM2 serves as the first input terminal of the first current mirror module 213; the gate of the fourth power transistor M SM4 serves as the second input terminal of the first current mirror module 213;

[0089] The source electrode of the third power transistor M SM2 serves as the third input terminal of the first current mirror module 213 and is connected to the bootstrap voltage V BST connected; the source electrode of the fourth power transistor M SM4 serves as the fourth input terminal of the first current mirror module 213 and is connected to the bootstrap voltage V BST connected;

[0090] The drain of the third power transistor M SM2 is connected to the source electrode of the first high-voltage transistor M HV1 ; the drain of the first high-voltage transistor M HV1 is respectively connected to the drain and gate of the first low-voltage transistor M LV1 and serves as the first output terminal of the first current mirror module 213, and is connected to the first input terminal of the sampling module 214; the source electrode of the first low-voltage transistor M LV1 is grounded; the gate of the first high-voltage transistor M HV1 is connected to the source electrode of the upper transistor M T ;

[0091] The drain of the fourth power transistor M SM4 is connected to the source electrode of the second high-voltage transistor M HV2 ; the drain of the second high-voltage transistor M HV2 is respectively connected to the second low-voltage transistor MLV2 After the drain and gate are connected, it serves as the second output terminal of the first current mirror module 213 and is connected to the second input terminal of the sampling module 214; the source of the second low-voltage transistor M LV2 is grounded; the gate of the second high-voltage transistor M HV2 is connected to the source of the upper transistor M T .

[0092] (4) Sampling module 214

[0093] The sampling module 214 includes a sample and hold circuit, a first current source I1, a second current source I2, a sampling resistor R SNS and a reference power supply V REF ;

[0094] The first end of the sample and hold circuit serves as the first input terminal of the sampling module 214; the second end of the sample and hold circuit serves as the second input terminal of the sampling module 214; the third end of the sample and hold circuit is connected to the first end of the first current source I1; the fourth end of the sample and hold circuit is connected to the first end of the second current source I2;

[0095] The second end of the first current source I1 is connected to the internal power supply voltage V CC ; the third end of the first current source I1 is respectively connected to the second end of the second current source I2 and the first end of the sampling resistor R SNS ; the third end of the second current source I2 is grounded;

[0096] The second end of the sampling resistor R SNS is connected to the positive pole of the reference voltage V REF ; the negative pole of the reference voltage V REF is grounded.

[0097] When the current flows from V IN to V SW (the direction of the current I MT is positive), the first silicon sampling upper transistor M SH1 , the first silicon sampling lower transistor M SH2 , the first upper sampling transistor resistor compensation array and the first lower sampling transistor resistor compensation array in the first temperature compensation module 211, the first high-bandwidth op-amp Positive HB AMP1 and the first power transistor M SM1 in the first negative feedback module 212, the third power transistor M SM2 , the first high-voltage transistor M HV1 and the first low-voltage transistor M LV1 in the first current mirror module 213, and the sample and hold circuit, the first current source I1, the sampling resistor R SNS and the reference power supply V REF in the sampling module 214 are connected to the upper transistor sampling circuit 210, that is, Figure 4The black components are connected to the upper transistor sampling circuit 210, and the gray components are not connected to the upper transistor sampling circuit 210.

[0098] When the current flows from V SW to V IN (the direction of the current I MT is negative), in the first temperature compensation module 211, the first silicon sampling upper transistor M SH1 , the first silicon sampling lower transistor M SH2 , the first upper sampling transistor resistance compensation array and the first lower sampling transistor resistance compensation array, in the first negative feedback module 212, the second high bandwidth operational amplifier Negative HB AMP1 and the second power transistor M SM3 , in the first current mirror module 213, the fourth power transistor M SM4 , the second high voltage transistor M HV2 and the second low voltage transistor M LV2 , the sample and hold circuit, the second current source I2, the sampling resistor R SNS and the reference power supply V REF in the sampling module 214 are connected to the upper transistor sampling circuit 210, that is, Figure 5 the black components in

[0099] When the sampling module 214 includes the reference voltage V REF , the voltage V SNS across the sampling resistor R ISNS is equal to the reference voltage V REF plus the sampling voltage, and the sampling voltage is equal to the product of the sampling current I L , the proportionality coefficient K m and the sampling resistor R SNS . That is, V ISNS = V REF + I L ×K m ×R SNS , where V REF represents the bias voltage, I L represents the sampling current of the upper transistor M T , K m represents the internal conversion coefficient, and R SNS represents the resistance value of the sampling resistor.

[0100] (2) Lower Transistor Sampling Circuit 220

[0101] (1) Second Temperature Compensation Module 221

[0102] The second temperature compensation module 221 includes the second silicon sampling upper transistor M SH3 , the second silicon sampling lower transistor M SH4, the second downsampling tube resistance compensation array and the second downsampling tube resistance compensation array;

[0103] The source electrode of the second silicon sampling upper tube M SH3 is connected as the first input terminal of the second temperature compensation module 221 to the first output terminal of the second negative feedback module 222; The second silicon sampling upper tube M SH3 The drain electrode of is connected to the first end of the second downsampling tube resistance compensation array; The second end of the second downsampling tube resistance compensation array is used as the first output terminal of the second temperature compensation module 221 and is connected to the drain electrode of the lower tube M B ;

[0104] The drain electrode of the second silicon sampling lower tube M SH4 is connected as the second input terminal of the second temperature compensation module 221 to the second output terminal of the second negative feedback module 222; The second silicon sampling lower tube M SH4 The source electrode of is connected to the first end of the second downsampling tube resistance compensation array; The second end of the second downsampling tube resistance compensation array is used as the second output terminal of the second temperature compensation module 221 and is connected to the source electrode of the lower tube M B ;

[0105] The second silicon sampling upper tube M SH3 and the second silicon sampling lower tube M SH4 The gate electrodes of are respectively connected to the gate electrode of the lower tube M B ;

[0106] (2) The second negative feedback module 222

[0107] The second negative feedback module 222 includes a third high - bandwidth operational amplifier Positive HB AMP2, a fourth high - bandwidth operational amplifier Negative HB AMP2, a fifth power tube M SM5 and a sixth power tube M SM7 ;

[0108] The negative input terminal of the third high - bandwidth operational amplifier Positive HB AMP2, the positive input terminal of the fourth high - bandwidth operational amplifier Negative HB AMP2, and the drain electrode of the sixth power tube M SM7 are connected and used as the first output terminal of the second negative feedback module 222;

[0109] The positive input terminal of the third high - bandwidth operational amplifier Positive HB AMP2, the negative input terminal of the fourth high - bandwidth operational amplifier Negative HB AMP2, and the drain electrode of the fifth power tube M SM5 are connected and used as the second output terminal of the second negative feedback module 222;

[0110] The output terminal of the third high - bandwidth operational amplifier Positive HB AMP2 is connected to the fifth power tube M SM5After being connected to the gate, it serves as the third output terminal of the second negative feedback module 222 and is connected to the first input terminal of the second current mirror module 223;

[0111] The output terminal of the fourth high-bandwidth operational amplifier Negative HB AMP2 is connected to the gate of the sixth power transistor M SM7 After being connected to the gate, it serves as the fourth output terminal of the second negative feedback module 222 and is connected to the second input terminal of the second current mirror module 223;

[0112] The fifth power transistor M SM5 and the sixth power transistor M SM7 The sources of are used as the input terminal of the second negative feedback module 222 and are respectively connected to the bootstrap voltage V BST connected.

[0113] (3) The second current mirror module 223

[0114] The second current mirror module 223 includes the seventh power transistor M SM6 , the eighth power transistor M SM8 , the third high-voltage transistor M HV3 , the third low-voltage transistor M LV3 , the fourth high-voltage transistor M HV4 and the fourth low-voltage transistor M LV4 ;

[0115] The gate of the seventh power transistor M SM6 serves as the first input terminal of the second current mirror module 223; the gate of the eighth power transistor M SM8 serves as the second input terminal of the second current mirror module 223;

[0116] The source of the seventh power transistor M SM6 serves as the third input terminal of the second current mirror module 223 and is connected to the bootstrap voltage V BST connected; the source of the eighth power transistor M SM8 serves as the fourth input terminal of the second current mirror module 223 and is connected to the bootstrap voltage V BST connected;

[0117] The drain of the seventh power transistor M SM6 is connected to the source of the third high-voltage transistor M HV3 ; the drain of the third high-voltage transistor M HV3 is respectively connected to the drain and gate of the third low-voltage transistor M LV3 and then serves as the first output terminal of the second current mirror module 223 and is connected to the first input terminal of the sampling module 214; the source of the third low-voltage transistor M LV3 is grounded; the gate of the third high-voltage transistor M HV3 is connected to the drain of the lower transistor M B ;

[0118] The eighth power transistor MSM8 The drain of which is connected to the source of the fourth high-voltage transistor M HV4 ; the drain of the fourth high-voltage transistor M HV4 is respectively connected to the drain and gate of the fourth low-voltage transistor M LV4 , and after being connected, they serve as the second output terminal of the second current mirror module 223 and are connected to the second input terminal of the sampling module 214; the source of the fourth low-voltage transistor M LV4 is grounded; the gate of the fourth high-voltage transistor M HV4 is connected to the drain of the lower transistor M B .

[0119] (4) Sampling module 214

[0120] The sampling module 214 is as described above and will not be elaborated here.

[0121] When the current flows from V SW to the ground (the direction of the current I MB is positive), the second silicon sampling upper transistor M SH3 , the second silicon sampling lower transistor M SH4 , the second lower sampling tube resistance compensation array and the second lower sampling tube resistance compensation array in the second temperature compensation module 221, the third high-bandwidth operational amplifier Positive HB AMP2 and the fifth power transistor M SM5 in the second negative feedback module 222, the seventh power transistor M SM6 , the third high-voltage transistor M HV3 and the third low-voltage transistor M LV3 in the second current mirror module 223, the sample-and-hold circuit, the first current source I1, the sampling resistor R SNS and the reference power supply V REF in the sampling module 214 are connected to the lower transistor sampling circuit 220, that is Figure 6 the black components in are connected to the lower transistor sampling circuit 220, and the gray components are not connected to the lower transistor sampling circuit 220.

[0122] When the current flows from the ground to V SW (the direction of the current I MB is negative), the second silicon sampling upper transistor M SH3 , the second silicon sampling lower transistor M SH4 , the second lower sampling tube resistance compensation array and the second lower sampling tube resistance compensation array in the second temperature compensation module 221, the fourth high-bandwidth operational amplifier Negative HB AMP2 and the sixth power transistor M SM7 in the second negative feedback module 222, the eighth power transistor M SM8 , the fourth high-voltage transistor M HV4 and the fourth low-voltage transistor M LV4, the sample-and-hold circuit in the sampling module 214, the second current source I2, the sampling resistor R SNS and the reference power supply V REF are connected to the lower transistor sampling circuit 220, that is Figure 7 the black components in are connected to the lower transistor sampling circuit 220, and the gray components are not connected to the lower transistor sampling circuit 220.

[0123] When the sampling module 214 includes the reference voltage V REF , the voltage V SNS across the sampling resistor R ISNS is equal to the reference voltage V REF plus the sampling voltage, and the sampling voltage is equal to the product of the sampling current I L , the proportionality coefficient K m and the sampling resistor R SNS . That is, V ISNS = V REF + I L × K m × R SNS , where V REF represents the bias voltage, I L represents the sampling current of the upper transistor M T , K m represents the internal conversion coefficient, and R SNS represents the resistance value of the sampling resistor.

[0124] In summary, for the current sampling circuit based on the gallium nitride power transistor provided in the embodiments of the present application, when using a silicon sampling transistor to sample the current of the gallium nitride power transistor, it is necessary to perform temperature compensation through a resistor compensation array to ensure that the ratio of the on-resistances of the silicon sampling transistor and the gallium nitride power transistor remains consistent within different temperature ranges, thereby improving the accuracy of current sampling.

[0125] When sampling the current of the upper transistor, the first negative feedback module can be used to make the first silicon sampling lower transistor and the first lower sampling transistor resistor compensation array flow through a positive current proportional to the sampling current of the upper transistor, and calculate the sampling current of the upper transistor through the positive current; or, the first negative feedback module can be used to make the first silicon sampling upper transistor and the first upper sampling transistor resistor compensation array flow through a negative current proportional to the sampling current of the upper transistor, and calculate the sampling current of the upper transistor through the negative current, thereby realizing the sampling of the bidirectional current of the upper transistor.

[0126] When sampling the current of the lower transistor, the second negative feedback module can be used to make the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array flow through a positive current proportional to the sampling current of the lower transistor, and calculate the sampling current of the lower transistor through the positive current; alternatively, the second negative feedback module can be used to make the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array flow through a negative current proportional to the sampling current of the lower transistor, and calculate the sampling current of the lower transistor through the negative current, so as to realize the sampling of the bidirectional current of the lower transistor.

[0127] As Figure 9 shown, this embodiment provides a current sampling method applied to the current sampling circuit based on the gallium nitride power transistor described above. The current sampling method includes:

[0128] Step 901, when the upper transistor is conducting, the first negative feedback module is used to make the first silicon sampling lower transistor and the first lower sampling transistor resistance compensation array flow through a positive current proportional to the sampling current of the upper transistor, or the first negative feedback module is used to make the first silicon sampling upper transistor and the first upper sampling transistor resistance compensation array flow through a negative current proportional to the sampling current of the upper transistor; the first current mirror module mirrors and outputs the positive current or negative current to the sampling resistor in the sampling module; the sampling module calculates the sampling current of the upper transistor according to the positive current or negative current.

[0129] When the current flows from V IN to V SW (the direction of the current I MT is positive), V A = V B in the first negative feedback module, resulting in the positive current I SHP being proportional to the current I T of the upper transistor M MT . Then, the positive current I SHP is sent by the first current mirror module to the sampling module, generating a voltage drop across the sampling resistor R SNS , and the voltage V REF provides a bias, generating a voltage V ISNS at the output node.

[0130] When the current flows from V SW to V IN (the direction of the current I MT is negative), V A = V B in the first negative feedback module, resulting in the negative current I SHN being proportional to the current I T of the upper transistor M MT . Then, the negative current I SHN is sent by the first current mirror module to the sampling module, generating a voltage drop across the sampling resistor R SNS , and the voltage VREF Provide a bias to generate a voltage V at the output node ISNS .

[0131] V ISNS = V REF + I L × K m × R SNS , where V REF represents the bias voltage, I L represents the sampling current of the upper transistor M T , K m represents the internal conversion coefficient, and R SNS represents the resistance value of the sampling resistor.

[0132] Step 902, when the lower transistor conducts, the second negative feedback module causes the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array to flow a positive current proportional to the sampling current of the lower transistor, or the second negative feedback module causes the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array to flow a negative current proportional to the sampling current of the lower transistor; the second current mirror module mirrors the positive current or the negative current to the sampling resistor in the sampling module; the sampling module calculates the sampling current of the lower transistor according to the positive current or the negative current.

[0133] When the current flows from V SW to ground (the direction of the current I MB is positive), V A = V B in the second negative feedback module, resulting in the positive current I SHP being proportional to the current I B of the lower transistor M MB . Then, the positive current I SHP is sent by the second current mirror module to the sampling module, generating a voltage drop across the sampling resistor R SNS . The voltage V REF provides a bias to generate a voltage V ISNS at the output node.

[0134] When the current flows from ground to V SW (the direction of the current I MB is negative), V A = V B in the second negative feedback module, resulting in the negative current I SHN being proportional to the current I B of the lower transistor M MB . Then, the negative current I SHN is sent by the second current mirror module to the sampling module, generating a voltage drop across the sampling resistor R SNS . The voltage V REF provides a bias to generate a voltage V ISNS。

[0135] V ISNS = V REF + I L × K m × R SNS wherein, V REF represents the bias voltage, I L represents the sampling current of the upper transistor M T , K m represents the internal conversion coefficient, and R SNS represents the resistance value of the sampling resistor.

[0136] In summary, for the current sampling method provided by the embodiments of the present application, when using a silicon sampling transistor to sample the current of a gallium nitride power transistor, temperature compensation needs to be performed through a resistor compensation array to ensure that the on-resistance ratio between the silicon sampling transistor and the gallium nitride power transistor remains consistent within different temperature ranges, thereby improving the accuracy of current sampling.

[0137] When sampling the current of the upper transistor, the first negative feedback module can be used to make a positive current proportional to the sampling current of the upper transistor flow through the first silicon sampling lower transistor and the first lower sampling transistor resistor compensation array, and calculate the sampling current of the upper transistor through the positive current; or, the first negative feedback module can be used to make a negative current proportional to the sampling current of the upper transistor flow through the first silicon sampling upper transistor and the first upper sampling transistor resistor compensation array, and calculate the sampling current of the upper transistor through the negative current, thereby realizing the sampling of the bidirectional current of the upper transistor.

[0138] When sampling the current of the lower transistor, the second negative feedback module can be used to make a positive current proportional to the sampling current of the lower transistor flow through the second silicon sampling lower transistor and the second lower sampling transistor resistor compensation array, and calculate the sampling current of the lower transistor through the positive current; or, the second negative feedback module can be used to make a negative current proportional to the sampling current of the lower transistor flow through the second silicon sampling upper transistor and the second upper sampling transistor resistor compensation array, and calculate the sampling current of the lower transistor through the negative current, thereby realizing the sampling of the bidirectional current of the lower transistor.

[0139] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0140] The above description is not intended to limit the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A current sampling circuit based on a gallium nitride power transistor, characterized in that, The current sampling circuit includes an upper transistor sampling circuit and a lower transistor sampling circuit. The upper transistor sampling circuit is used to sample the current of the upper transistor in the high-voltage switching power supply, and the lower transistor sampling circuit is used to sample the current of the lower transistor in the high-voltage switching power supply. The upper transistor and the lower transistor are gallium nitride power transistors; The upper transistor sampling circuit includes a first temperature compensation module, a first negative feedback module, a first current mirror module, and a sampling module connected in sequence. The first temperature compensation module includes a first silicon sampling upper transistor and a first upper sampling transistor resistance compensation array connected together, and a first silicon sampling lower transistor and a first lower sampling transistor resistance compensation array connected together. The first upper sampling transistor resistance compensation array and the first lower sampling transistor resistance compensation array are resistance arrays with negative temperature coefficients and / or positive temperature coefficients, and the first upper sampling transistor resistance compensation array and the first lower sampling transistor resistance compensation array are respectively connected to the upper transistor to ensure that the conduction resistance ratio of the first silicon sampling upper transistor to the upper transistor remains consistent, and the conduction resistance ratio of the first silicon sampling lower transistor to the upper transistor remains consistent within different temperature ranges; When the upper transistor is conducting, the first temperature compensation module is used to cause the first silicon sampling lower transistor and the first lower sampling transistor resistance compensation array to flow through a forward current proportional to the sampling current of the upper transistor through the first negative feedback module, or cause the first silicon sampling upper transistor and the first upper sampling transistor resistance compensation array to flow through a negative current proportional to the sampling current of the upper transistor through the first negative feedback module. The first current mirror module is used to mirror the forward current or the negative current to the sampling resistor in the sampling module. The sampling module is used to calculate the sampling current of the upper transistor based on the forward current or the negative current; The lower transistor sampling circuit includes a second temperature compensation module, a second negative feedback module, a second current mirror module, and a sampling module connected in sequence. The second temperature compensation module includes a second silicon sampling upper transistor and a second upper sampling transistor resistance compensation array connected together, and a second silicon sampling lower transistor and a second lower sampling transistor resistance compensation array connected together. The second upper sampling transistor resistance compensation array and the second lower sampling transistor resistance compensation array are resistance arrays with negative temperature coefficients and / or positive temperature coefficients, and the second upper sampling transistor resistance compensation array and the second lower sampling transistor resistance compensation array are respectively connected to the lower transistor to ensure that the conduction resistance ratio of the second silicon sampling upper transistor to the lower transistor remains consistent, and the conduction resistance ratio of the second silicon sampling lower transistor to the lower transistor remains consistent within different temperature ranges; When the lower transistor is turned on, the second temperature compensation module is configured to, through the second negative feedback module, cause a forward current proportional to the sampling current of the lower transistor to flow through the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array, or, through the second negative feedback module, cause a negative current proportional to the sampling current of the lower transistor to flow through the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array; the second current mirror module is configured to mirror and output the forward current or the negative current to a sampling resistor in the sampling module; the sampling module is configured to calculate the sampling current of the lower transistor based on the forward current or the negative current.

2. The current sampling circuit based on a gallium nitride power transistor according to claim 1, characterized in that The first temperature compensation module includes a first silicon sampling upper transistor, a first silicon sampling lower transistor, a first upper sampling transistor resistance compensation array, and a first lower sampling transistor resistance compensation array; The source of the first silicon sampling upper transistor is connected to the first output terminal of the first negative feedback module as the first input terminal of the first temperature compensation module; the drain of the first silicon sampling upper transistor is connected to the first end of the first upper sampling transistor resistance compensation array; the second end of the first upper sampling transistor resistance compensation array is connected to the drain of the upper transistor as the first output terminal of the first temperature compensation module; The drain of the first silicon sampling lower transistor is connected to the second output terminal of the first negative feedback module as the second input terminal of the first temperature compensation module; the source of the first silicon sampling lower transistor is connected to the first end of the first lower sampling transistor resistance compensation array; the second end of the first lower sampling transistor resistance compensation array is connected to the source of the upper transistor as the second output terminal of the first temperature compensation module; The gates of the first silicon sampling upper transistor and the first silicon sampling lower transistor are respectively connected to the gate of the upper transistor.

3. The current sampling circuit based on a gallium nitride power transistor according to claim 1, wherein, The first negative feedback module includes a first high-bandwidth operational amplifier, a second high-bandwidth operational amplifier, a first power transistor, and a second power transistor; The negative input terminal of the first high-bandwidth operational amplifier, the positive input terminal of the second high-bandwidth operational amplifier, and the drain of the second power transistor are connected and used as the first output terminal of the first negative feedback module; The positive input terminal of the first high-bandwidth operational amplifier, the negative input terminal of the second high-bandwidth operational amplifier, and the drain of the first power transistor are connected and used as the second output terminal of the first negative feedback module; The output terminal of the first high-bandwidth operational amplifier is connected to the gate of the first power transistor and used as the third output terminal of the first negative feedback module, and is connected to the first input terminal of the first current mirror module; The output terminal of the second high-bandwidth operational amplifier is connected to the gate of the second power transistor and used as the fourth output terminal of the first negative feedback module, and is connected to the second input terminal of the first current mirror module; The sources of the first power transistor and the second power transistor are connected to the bootstrap voltage as the input terminal of the first negative feedback module respectively.

4. The current sampling circuit based on a gallium nitride power transistor according to claim 1, characterized in that The first current mirror module includes a third power transistor, a fourth power transistor, a first high-voltage transistor, a first low-voltage transistor, a second high-voltage transistor, and a second low-voltage transistor; The gate of the third power transistor serves as the first input terminal of the first current mirror module; the gate of the fourth power transistor serves as the second input terminal of the first current mirror module; The source of the third power transistor serves as the third input terminal of the first current mirror module and is connected to the bootstrap voltage; the source of the fourth power transistor serves as the fourth input terminal of the first current mirror module and is connected to the bootstrap voltage; The drain of the third power transistor is connected to the source of the first high-voltage transistor; the drain of the first high-voltage transistor is respectively connected to the drain and gate of the first low-voltage transistor and then serves as the first output terminal of the first current mirror module, which is connected to the first input terminal of the sampling module; the source of the first low-voltage transistor is grounded; The gate of the first high-voltage transistor is connected to the source of the upper transistor; The drain of the fourth power transistor is connected to the source of the second high-voltage transistor; the drain of the second high-voltage transistor is respectively connected to the drain and gate of the second low-voltage transistor and then serves as the second output terminal of the first current mirror module, which is connected to the second input terminal of the sampling module; the source of the second low-voltage transistor is grounded; the gate of the second high-voltage transistor is connected to the source of the upper transistor.

5. The current sampling circuit based on a gallium nitride power transistor according to claim 1, characterized in that The second temperature compensation module includes a second silicon sampling upper transistor, a second silicon sampling lower transistor, a second lower sampling transistor resistor compensation array, and a second lower sampling transistor resistor compensation array; The source of the second silicon sampling upper transistor serves as the first input terminal of the second temperature compensation module and is connected to the first output terminal of the second negative feedback module; the drain of the second silicon sampling upper transistor is connected to the first end of the second lower sampling transistor resistor compensation array; the second end of the second lower sampling transistor resistor compensation array serves as the first output terminal of the second temperature compensation module and is connected to the drain of the lower transistor; The drain of the second silicon sampling lower transistor serves as the second input terminal of the second temperature compensation module and is connected to the second output terminal of the second negative feedback module; the source of the second silicon sampling lower transistor is connected to the first end of the second lower sampling transistor resistor compensation array; the second end of the second lower sampling transistor resistor compensation array serves as the second output terminal of the second temperature compensation module and is connected to the source of the lower transistor; The gates of the second silicon sampling upper transistor and the second silicon sampling lower transistor are respectively connected to the gate of the lower transistor.

6. The current sampling circuit based on a gallium nitride power transistor according to claim 1, characterized in that, The second negative feedback module includes a third high-bandwidth operational amplifier, a fourth high-bandwidth operational amplifier, a fifth power transistor, and a sixth power transistor; The negative input terminal of the third high-bandwidth operational amplifier, the positive input terminal of the fourth high-bandwidth operational amplifier, and the drain of the sixth power transistor are connected and then serve as the first output terminal of the second negative feedback module; The positive input terminal of the third high-bandwidth operational amplifier, the negative input terminal of the fourth high-bandwidth operational amplifier, and the drain of the fifth power transistor are connected and then serve as the second output terminal of the second negative feedback module; The output terminal of the third high-bandwidth operational amplifier is connected to the gate of the fifth power transistor and then serves as the third output terminal of the second negative feedback module, which is connected to the first input terminal of the second current mirror module; The output terminal of the fourth high-bandwidth operational amplifier is connected to the gate of the sixth power transistor and then serves as the fourth output terminal of the second negative feedback module, and is connected to the second input terminal of the second current mirror module; The sources of the fifth power transistor and the sixth power transistor serve as the input terminals of the second negative feedback module and are respectively connected to the bootstrap voltage.

7. The current sampling circuit based on a gallium nitride power transistor according to claim 1, wherein The second current mirror module includes a seventh power transistor, an eighth power transistor, a third high-voltage transistor, a third low-voltage transistor, a fourth high-voltage transistor, and a fourth low-voltage transistor; The gate of the seventh power transistor serves as the first input terminal of the second current mirror module; the gate of the eighth power transistor serves as the second input terminal of the second current mirror module; The source of the seventh power transistor serves as the third input terminal of the second current mirror module and is connected to the bootstrap voltage; the source of the eighth power transistor serves as the fourth input terminal of the second current mirror module and is connected to the bootstrap voltage; The drain of the seventh power transistor is connected to the source of the third high-voltage transistor; the drain of the third high-voltage transistor is respectively connected to the drain and the gate of the third low-voltage transistor and then serves as the first output terminal of the second current mirror module, and is connected to the first input terminal of the sampling module; the source of the third low-voltage transistor is grounded; the gate of the third high-voltage transistor is connected to the drain of the lower transistor; The drain of the eighth power transistor is connected to the source of the fourth high-voltage transistor; the drain of the fourth high-voltage transistor is respectively connected to the drain and the gate of the fourth low-voltage transistor and then serves as the second output terminal of the second current mirror module, and is connected to the second input terminal of the sampling module; the source of the fourth low-voltage transistor is grounded; The gate of the fourth high-voltage transistor is connected to the drain of the lower transistor.

8. The current sampling circuit based on a gallium nitride power transistor according to claim 1, characterized in that The sampling module includes a sample and hold circuit, a first current source, a second current source, a sampling resistor, and a reference voltage; The first terminal of the sample and hold circuit serves as the first input terminal of the sampling module; the second terminal of the sample and hold circuit serves as the second input terminal of the sampling module; the third terminal of the sample and hold circuit is connected to the first terminal of the first current source; the fourth terminal of the sample and hold circuit is connected to the first terminal of the second current source; The second terminal of the first current source is connected to the internal power supply voltage; the third terminal of the first current source is respectively connected to the second terminal of the second current source and the first terminal of the sampling resistor; the third terminal of the second current source is grounded; The second terminal of the sampling resistor is connected to the positive pole of the reference voltage; the negative pole of the reference voltage is grounded.

9. The current sampling circuit based on a gallium nitride power transistor according to any one of claims 1 to 8, characterized in that When the sampling module includes a reference voltage, the voltage across the sampling resistor is equal to the sum of the reference voltage and the sampling voltage, and the sampling voltage is equal to the product of the sampling current, the proportionality coefficient, and the sampling resistor.

10. A current sampling method for a current sampling circuit based on a gallium nitride power transistor, characterized in that, In the current sampling circuit based on gallium nitride power transistors as described in any one of claims 1 to 9, the method includes: When the upper transistor is turned on, the first negative feedback module causes the first silicon sampling lower transistor and the first lower sampling transistor resistance compensation array to flow a positive current proportional to the sampling current of the upper transistor, or the first negative feedback module causes the first silicon sampling upper transistor and the first upper sampling transistor resistance compensation array to flow a negative current proportional to the sampling current of the upper transistor; the first current mirror module mirrors and outputs the positive current or the negative current to the sampling resistor in the sampling module; the sampling module calculates the sampling current of the upper transistor according to the positive current or the negative current. When the lower transistor is turned on, the second negative feedback module causes the second silicon sampling lower transistor and the second lower sampling transistor resistance compensation array to flow a positive current proportional to the sampling current of the lower transistor, or the second negative feedback module causes the second silicon sampling upper transistor and the second upper sampling transistor resistance compensation array to flow a negative current proportional to the sampling current of the lower transistor; the second current mirror module mirrors and outputs the positive current or the negative current to the sampling resistor in the sampling module; the sampling module calculates the sampling current of the lower transistor according to the positive current or the negative current.

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