Method for determining etch profile of layer of wafer for simulation system

Abstract

A method for determining an etch profile is described. The method includes determining an initial masking layer profile. Load information is determined. The load information indicates a dependency of an etch rate for the mask layer profile on the number and pattern of material being etched. Flux information is determined. The flux information indicates a dependency of the etch rate on an intensity and a spread angle of radiation incident on a profile of the mask layer. And determining redeposition information. The redeposition information indicates a dependency of the etch rate on an amount of material removed from and redeposited back onto the masking layer profile. An output etch profile of the layer of the wafer is determined based on the load information, the flux information, and / or the redeposition information.

Description

[0001] This application is a divisional application of the patent application with application number 201980049948.7, whose entry date into the Chinese national phase is January 26, 2021 and whose invention name is “Method for determining the etching profile of a layer of a wafer for a simulation system” (international application date is July 19, 2019, and international application number is PCT / EP2019 / 069460), whose applicant is “ASML Netherlands B.V.”

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. application 62 / 703,529, filed on July 26, 2018, and the entire contents of the U.S. application are incorporated herein by reference. Technical Field

[0004] The present disclosure generally relates to mask making and patterning processes. More specifically, the disclosure relates to methods and apparatus for determining an etch profile of a layer of a wafer for a simulation system. Background Art

[0005] Lithographic projection apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In such cases, a patterning device (e.g., a mask) may contain or provide a pattern corresponding to a single layer of the IC (a "design layout"), and this pattern may be transferred to a target portion (e.g., comprising one or more dies) on a substrate (e.g., a silicon wafer) that has been coated with a layer of radiation-sensitive material (a "resist"), such as by irradiating the target portion through the pattern on the patterning device. Typically, a single substrate comprises a plurality of adjacent target portions to which the pattern is transferred successively, one at a time, by the lithographic projection apparatus. In this type of lithographic projection apparatus, the pattern on the entire patterning device is transferred to one target portion at a time; such apparatus is often referred to as a stepper. In an alternative apparatus, often referred to as a stepper-scan apparatus, the projection beam is scanned over the patterning device in a given reference direction (the "scanning" direction) while the substrate is synchronously moved parallel or antiparallel to this reference direction. Different portions of the pattern on the patterning device are transferred stepwise to one target portion. Typically, because the lithographic projection apparatus will have a reduction ratio M (e.g. 4), the speed F at which the substrate is moved will be 1 / M times the speed at which the projection beam scans the patterning device. More information on lithographic devices as described herein can be gleaned, for example, from US 6,046,792, which is incorporated herein by reference.

[0006] Before the pattern is transferred from the pattern forming device to the substrate, the substrate may undergo various processes, such as primer, resist coating, and soft baking. After exposure, the substrate may undergo other processes ("post-exposure processes"), such as post-exposure baking (PEB), development, hard baking, and measurement / inspection of the transferred pattern. This array of processes is used as the basis for making a single layer of a device (e.g., IC). The substrate may then undergo various processes such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all of which are intended to refine the single layer of the device. If several layers are required in the device, the entire process or its variant is repeated for each layer. Eventually, there will be a device in each target portion on the substrate. These devices are then separated from each other by techniques such as cutting or sawing, whereby individual devices can be mounted on a carrier, connected to pins, etc.

[0007] Therefore, manufacturing devices such as semiconductor devices generally involves using multiple manufacturing processes to process a substrate (e.g., a semiconductor wafer) to form various features and multiple layers of the device. Such layers and features are generally manufactured and processed using, for example, deposition, photolithography, etching, chemical mechanical polishing, and ion implantation. Multiple devices can be made on multiple dies on a substrate, and the devices are subsequently separated into individual devices. Such a device manufacturing process can be considered a patterning process. The patterning process involves a patterning step, such as optical and / or nanoimprint lithography that uses a pattern forming device in a lithographic device to transfer a pattern on the pattern forming device to a substrate, and the patterning process generally but optionally involves one or more related pattern processing steps, such as resist development by a developing device, baking the substrate using a baking tool, etching using a pattern using an etching device, etc.

[0008] As mentioned, photolithography is a central step in the fabrication of devices such as ICs, where patterns formed on a substrate define the functional elements of the device, such as microprocessors, memory chips, etc. Similar photolithography techniques are also used to form flat panel displays, microelectromechanical systems (MEMS), and other devices.

[0009] As semiconductor manufacturing processes continue to advance, the size of functional elements has been continuously reduced over the decades, while the number of functional elements, such as transistors, per device has been steadily increasing, following a trend generally referred to as "Moore's Law." In the current state of the art, the layers of a device are fabricated using a lithographic projection apparatus that projects a design layout onto a substrate using illumination from a deep ultraviolet illumination source, thereby producing individual functional elements with dimensions well below 100 nm (i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source)).

[0010] This process of printing features with dimensions smaller than the classical resolution limit of the lithographic projection apparatus is generally referred to as low-k1 lithography, according to the resolution formula CD = k1×λ / NA, where λ is the wavelength of the radiation employed (currently 248 nm or 193 nm in most cases), NA is the numerical aperture of the projection optics in the lithographic projection apparatus, CD is the "critical dimension" (generally the minimum feature size printed), and k1 is an empirical resolution factor. In general, the smaller k1 is, the more difficult it becomes to reproduce a pattern on a substrate that resembles the shape and dimensions planned by the designer in order to achieve specific electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps are applied to the lithographic projection apparatus, the design layout, or the patterning device. These steps include, for example, but are not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase-shifted patterning devices, optical proximity correction (OPC, sometimes also called "optical and process correction") in the design layout, or other methods generally defined as "resolution enhancement techniques" (RET). The term "projection optics" as used herein should be broadly interpreted to cover various types of optical systems, including, for example, refractive optics, reflective optics, apertures, and reflective-refractive optics. The term "projection optics" may also include components that operate according to any of these design types for guiding, shaping or controlling a projection radiation beam, either collectively or individually. The term "projection optics" may include any optical component in a lithographic projection apparatus, regardless of where the optical component is located on the optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, adjusting and / or projecting the radiation from a source before it passes through a pattern forming device, and / or optical components for shaping, adjusting and / or projecting the radiation after it passes through a pattern forming device. Projection optics generally do not include a source and a pattern forming device. Summary of the invention

[0011] According to an embodiment, the present invention provides a method for determining an etching profile of a layer of a wafer for a simulation system. The method includes: determining a starting shielding layer profile of the layer of the wafer. The method includes: determining load information of the shielding layer profile based at least in part on the shielding layer profile. The load information indicates the dependence of an etching rate for the shielding layer profile on the amount and pattern of material being etched. The method includes: determining flux information of the shielding layer profile based at least in part on the shielding layer profile. The flux information indicates the dependence of the etching rate for the shielding layer profile on the intensity and spread angle of radiation incident on the shielding layer profile. The method includes: determining redeposition information of the shielding layer profile based at least in part on the shielding layer profile. The redeposition information indicates the dependence of the etching rate for the shielding layer profile on the amount of material removed from the shielding layer profile and redeposited back on the shielding layer profile. The method includes: determining an output etching profile of the layer of the wafer based on the load information, the flux information and / or the redeposition information of the shielding layer profile.

[0012] In an embodiment, the method further comprises determining depth information based on the output etch profile for use during overlay determination.

[0013] In an embodiment, determining the load information, determining the flux information, determining the redeposition information and / or determining the output etch profile are performed iteratively until the depth information corresponds to a depth of an image of a corresponding layer of a physical wafer.

[0014] In an embodiment, the method further comprises generating an electronic depiction of the layer of the wafer based on the depth information to facilitate visual comparison between the electronic depiction and the image of the corresponding layer of the physical wafer.

[0015] In an embodiment, the method further comprises generating an electronic depiction of the layer of the wafer based on the depth information to facilitate size measurement of the electronic depiction for comparison with sizes obtained from the image of the corresponding layer of the physical wafer.

[0016] In an embodiment, the method further comprises: calibrating the operating parameters of the method based on information from a metrology system of the corresponding layer of the physical wafer and / or the simulated wafer. For example, calibration may involve tuning the parameters by minimizing the difference between the output (measurement result) of the metrology system on the physical wafer and the output of the simulated metrology output on the simulated wafer. The metrology system may be, for example, a SEM (explained in more detail below) or a scatterometry system (optical tool).

[0017] In an embodiment, the method further comprises: calibrating operating parameters of the method based on information from the metrology system of the corresponding layer of the simulated wafer, and the calibration further comprises adjusting wafer simulation parameters of the simulated wafer. In other words, the calibration may involve further tuning the parameters of the model that determines the shielding layer profile. For example, the shielding layer may be a resist layer, and the system that determines the shielding layer may be a lithography model, and the parameters are the parameters for the lithography model (explained in more detail below).

[0018] In an embodiment, determining the masking layer profile, determining the loading information, determining the flux information, determining the redeposition information and / or determining the output etch profile is performed for a region of interest of the layer of the wafer.

[0019] In an embodiment, the masking layer profile of the layer of the wafer comprises a patterned profile.

[0020] In an embodiment, the masking layer profile of the layer of the wafer comprises an after-development inspection (ADI) dimension.

[0021] In an embodiment, determining the shielding layer profile of the layer of the wafer comprises one or more of the following operations: obtaining a dimension of the shielding layer profile, designing a dimension of the shielding layer profile, or measuring a dimension of the shielding layer profile.

[0022] In an embodiment, the method further comprises: simulating a trimming operation on the shielding layer profile according to a trimming option. Simulating the trimming operation on the shielding layer profile may comprise modifying a size of the shielding layer profile.

[0023] In an embodiment, simulating the trimming operation on the masking layer profile includes adjusting a mask critical dimension (CD) offset.

[0024] In an embodiment, determining the loading information of the masking layer profile comprises adjusting one or more of: an etch rate constant, a short range loading factor, or a long range loading factor.

[0025] In an embodiment, determining the flux information of the obscuration layer profile comprises adjusting one or more of: ionic intensity, neutral intensity or spread angle of the incident radiation.

[0026] In an embodiment, determining the redeposition information of the obscuring layer profile comprises adjusting a redeposition rate of the obscuring layer profile.

[0027] In an embodiment, determining the load information includes determining the dependence of the etching rate at individual locations across the shielding layer profile on the amount and pattern of etched material at the individual locations; determining the flux information includes determining the dependence of the etching rate at individual locations across the shielding layer profile on the intensity and spread angle of radiation incident on the shielding layer profile at the individual locations; and determining the redeposition information includes determining the dependence of the etching rate at individual locations across the shielding layer profile on the amount of material removed from the shielding layer profile at the individual locations and redeposited back onto the shielding layer profile at the individual locations.

[0028] In an embodiment, determining the dependence of the etch rate at the individual locations across the masking layer profile comprises determining individual load factors for the individual locations.

[0029] In an embodiment, the individual load factors are determined based on Boolean functions of the mask pattern at the individual locations.

[0030] In an embodiment, the flux information is determined based on one or more bias constants, one or more fitting constants, a short-range loading factor, and a long-range loading factor corresponding to the individual sites.

[0031] In an embodiment, the redeposition information is determined based on one or more bias constants, long range fit factors and long range loading factors corresponding to individual sites.

[0032] According to another embodiment, a computer program product is provided. The computer program product includes a non-transitory computer-readable medium having instructions recorded thereon, and the instructions implement the method described above when executed by a computer.

[0033] According to another embodiment, a method for generating an etch model application for a metrology target design is provided. The method includes: calibrating the etch model using experimental cross-sectional profile information from a layer of a physical wafer generated based on the etch model. The method includes: predicting an etch depth profile of a layer of the modeled wafer based on the calibrated etch model. The method includes: using the predicted etch depth profile in a rigorously coupled wave analysis (RCWA) to enhance the metrology target design.

[0034] In an embodiment, predicting the etch depth profile of the layer of the modeled wafer based on the calibrated etch model includes: determining (i) a starting resist profile of the layer of the wafer and (ii) a resist trimming etch profile; determining a trimmed resist profile by simulating a trimming operation on the starting resist profile according to the resist trimming etch profile, and at least partially based on the trimmed resist profile: determining load information for the trimmed resist profile, the load information indicating a dependency of an etch rate of the trimmed resist profile on an amount and pattern of material being etched; and / or determining a trimmed resist profile. Flux information of the trimmed resist profile, the flux information indicating the dependence of the etch rate of the trimmed resist profile on the intensity and spread angle of radiation incident on the trimmed resist profile; and / or redeposition information of the trimmed resist profile, the redeposition information indicating the dependence of the etch rate of the trimmed resist profile on the amount of material removed from the trimmed resist profile and redeposited back onto the trimmed resist profile; and determining an output etch depth profile of the layer of the wafer based on the load information, the flux information and / or the redeposition information of the trimmed resist profile.

[0035] In an embodiment, enhancing the metrology target design includes adjusting one or more dimensions and / or patterns of the metrology target design.

[0036] In an embodiment, the experimental cross-sectional profile information comprises a visual or dimensional comparison between an electronic image of the layer of the physical wafer and a corresponding electronic depiction of the layer generated using the model.

[0037] According to another embodiment, a computer program product is provided. The computer program product includes a non-transitory computer-readable medium having instructions recorded thereon, and the instructions, when executed by a computer, implement the method described immediately above.

[0038] According to another embodiment, a method for calibrating an etch model application of a dual-size etch model for an optical proximity correction (OPC) application is provided. The method includes: calibrating the etch model using any combination of cross-sectional profiles, SEM, and scatter measurements (e.g., using optical tools) from a layer of a simulated wafer generated based on the etch process. The method includes: predicting the etch bias of multiple patterns in the layer of the modeled wafer based on the calibrated etch model. The method includes: using the predicted etch bias to correct a photomask (e.g., an OPC application), verify the post-etch process window (OPC verification or lithography manufacturability check (LMC)), or co-optimize the lithography source and photomask (e.g., using a source mask optimization (SMO) application).

[0039] According to another embodiment, a computer program product is provided. The computer program product includes a non-transitory computer-readable medium having instructions recorded thereon, and the instructions, when executed by a computer, implement the method described immediately above.

[0040] According to another embodiment, a method is provided for calibrating an etch model application for predicting etch fingerprints across a wafer as an input to a wafer inspection or patterning control operation. The method includes calibrating the etch model with parameters describing the variation across the wafer of the etch process, using any combination of cross-sectional profiles, SEM and scatter measurements of layers across the wafer from a simulated wafer generated based on the etch process. The method includes predicting the etch bias of multiple patterns of the layer of the modeled wafer based on the calibrated etch model. The method includes using the predicted etch bias fingerprint as a defect prediction for an inspection system (e.g., a guided wafer defect inspection application, such as a pattern fidelity metrology (PFM) application) or an input to a wafer manufacturing process control system (e.g., a pattern fidelity control (PFC) system) to improve patterning performance across the wafer (e.g., using a wafer manufacturing process control application).

[0041] According to another embodiment, a computer program product is provided. The computer program product includes a non-transitory computer-readable medium having instructions recorded thereon, and the instructions, when executed by a computer, implement the method described immediately above. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above aspects and other aspects and features will become apparent to those of ordinary skill in the art upon reviewing the following description of specific embodiments in conjunction with the accompanying drawings, in which:

[0043] Figure 1 A lithographic apparatus according to an embodiment is schematically depicted.

[0044] Figure 2 Embodiments of a lithography cell or cluster according to embodiments are schematically depicted.

[0045] Figure 3 Example inspection equipment and metrology techniques according to embodiments are schematically depicted.

[0046] Figure 4 An example inspection device according to an embodiment is schematically depicted.

[0047] Figure 5 FIG. 2 illustrates the relationship between an illumination spot and a measurement target of an inspection device according to an embodiment.

[0048] Figure 6A process of deriving a plurality of variables of interest based on measurement data according to an embodiment is schematically depicted.

[0049] Fig. 7A is a flow chart illustrating the various stages of a “design for controls” process flow according to an embodiment.

[0050] Figure 7B is a block diagram illustrating various stages for visualization according to an embodiment.

[0051] Figure 7C is a flow chart showing how the Design for Control process determines a measurement target design that is robust to process disturbances.

[0052] Figure 8a A method for determining an etch profile of a layer of a wafer for a simulation system according to an embodiment is illustrated.

[0053] Figure 8b A similar method for determining an etch profile of a layer of a wafer without trim-related operations is illustrated for a simulation system according to an embodiment.

[0054] Figure 8c is a diagram of an alternative method of calibration using a combination of overlay and alignment systems.

[0055] Fig. 9 Illustrated are aspects of determining loading information for a region of interest of a layer of a wafer according to an embodiment.

[0056] Fig.10 Two illustrations are provided related to determining flux information according to an embodiment.

[0057] Fig.11 Illustrated are electronic traces of two different depth profiles and corresponding scanning electron microscope (SEM) images of a physical wafer generated using the systems and methods described herein, according to an embodiment.

[0058] Fig.12 is a block diagram of an example computer system according to an embodiment.

[0059] Fig.13 is similar to the embodiment Figure 1 Schematic diagram of a lithography projection apparatus.

[0060] Fig.14 According to the embodiment Fig.13 A more detailed view of the devices in the

[0061] Fig.15 According to the embodiment Fig.13 and Fig.14 A more detailed view of the source collector module of the device SO. DETAILED DESCRIPTION

[0062] The description herein generally relates to mask manufacturing and patterning processes. More specifically, the description relates to an apparatus or method for determining an etch profile of a layer of a wafer for a simulation system. As just one example, these simulation systems can use the determined etch profile during alignment measurement target design or in other operations. As described in more detail below, overlap is an indication of the relative displacement between the current layer and the previous layer of the wafer. Overlap is typically determined based on the optical response of the measurement marks included in the scribe line. The measurement marks and optical responses are typically modeled using software tools such as ASML Design 4 Control (D4C) and YieldStar before physically manufacturing the wafer to facilitate optimization of wafer manufacturing options and measurement mark design (e.g., to reduce overlap and / or for other purposes).

[0063] The geometric model is used for the current overlap and measurement mark design for the patterning process definition (e.g., to model or otherwise determine the etching profile). For example, D4C or other similar tools require an etching profile (among many other process-related inputs) to construct a "stack" that models the actual wafer to feed back into the rigorous coupled wave analysis (RCWA) for accurate simulation. However, the geometric model is overly simplified (e.g., the model uses a constant etching depth, sidewall angle, binary etchable or non-etchable description of the material in the stack, etc.). Etching effects on the wafer such as micro-loading effects, tortuosity, etc. are not well described by the geometric model, which reduces the simulation accuracy and generally results in poor correlation between simulated overlap measurements and actual overlap measurements. YieldStar (e.g.) or other scanner measurement mark signals are sensitive to the modeled post-etching profile (especially the depth of such a profile). The etching profile difference between the modeled profile and the actual profile is usually caused by the geometric model being unable to accurately consider local pattern features (such as density and resist profile) and global effects (such as chemical and physical inhomogeneities).

[0064] For example, in some layers of the stack, the metrology marks are segmented to enhance process uniformity. However, the YieldStar overlay marks may have a major pitch of about 500-800 nm, and other scanner alignment marks may require a pitch of about 1.6 μm to produce a diffraction signal to determine the overlay or alignment position. Due to both process design and metrology constraints, the pattern density can vary significantly in the metrology mark area. For example, etch microloading effects are often observed in the metrology mark area.

[0065] Using the systems and methods described below, local loading effects are modeled using visibility angle, pattern density, and other parameters. Thus, a more accurate simulated etch profile can be fed into the D4C software (or other similar tools) which can help more accurately simulate the response of the YieldStar signal or other scanner measurement mark signal to achieve more accurate predictions of overlay or other parameters.

[0066] The semi-empirical model of the present system and method (in contrast to previous geometric models) uses multiple parameters to represent plasma physics and material behavior, and reconstructs the post-etch profile by capturing local etch load effects, which are caused by pattern size and density. In the present system and method, global load effects are introduced by adding electric field distribution and other perturbations to simulate chemical and physical inhomogeneities. In addition, the model of the present system and method can be calibrated based on cross-sectional secondary electron microscopy (SEM) images to ensure that the modeling process steps described herein accurately reflect the specific etching process.

[0067] The following paragraphs describe several components of the system and / or related systems and methods for determining the etch profile of a layer of a wafer for a simulation system. As described above, these simulation systems can use the determined etch profile, for example, during alignment measurement target design or during other operations.

[0068] Although specific reference may be made herein to the manufacture of integrated circuits (ICs), it should be understood that the description herein has many other possible applications. For example, the description may be used to manufacture integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, etc. Those skilled in the art will appreciate that in the context of such alternative applications, any use of the terms "reticle", "wafer" or "die" herein should be considered interchangeable with the more general terms "mask", "substrate" and "target portion", respectively.

[0069] Figure 1 An embodiment of a lithographic apparatus LA is schematically depicted. The apparatus comprises:

[0070] - an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. UV radiation, DUV radiation or EUV radiation);

[0071] - a support structure (eg mask table) MT configured to support a patterning device (eg mask) MA and connected to a first positioner PM configured to accurately position the patterning device according to certain parameters;

[0072] - a substrate table (e.g. wafer stage) WT (e.g. WTa, WTb or both) configured to hold a substrate (e.g. a resist coated wafer) W and coupled to a second positioner PW configured to accurately position the substrate according to certain parameters; and

[0073] - a projection system (e.g. a refractive projection lens system) PS configured to project a pattern imparted to the radiation beam B by the patterning device MA onto a target portion C (e.g. comprising one or more dies and often referred to as a field) of the substrate W. The projection system is supported on a reference frame (RF).

[0074] As depicted here, the device is of the transmissive type (for example employing a transmissive mask). Alternatively, the device may be of the reflective type (for example employing a programmable mirror array of the type mentioned above, or employing a reflective mask).

[0075] The illuminator IL receives a radiation beam from a radiation source SO. For example, when the source is an excimer laser, the source and the lithographic apparatus may be separate entities. In such a case, the source is not considered to form part of the lithographic apparatus, and the radiation beam is transferred from the source SO to the illuminator IL by means of a beam delivery system BD comprising, for example, suitable directional mirrors and / or a beam expander. In other cases, for example, when the source is a mercury lamp, the source may be an integral part of the apparatus. The source SO and the illuminator IL, together with the beam delivery system BD where appropriate, may be referred to as a radiation system.

[0076] The illuminator IL may modify the intensity distribution of the beam. The illuminator may be arranged to limit the radial extent of the radiation beam so that the intensity distribution within an annular region in a pupil plane of the illuminator IL is non-zero. Additionally or alternatively, the illuminator IL may be operable to limit the distribution of the beam in the pupil plane so that the intensity distribution in a plurality of equally spaced segments in the pupil plane is non-zero. The intensity distribution of the radiation beam in the pupil plane of the illuminator IL may be referred to as an illumination pattern.

[0077] The illuminator IL may comprise an adjuster AM configured to adjust the (angular / spatial) intensity distribution of the beam. Typically, at least the outer radial extent and / or the inner radial extent (typically referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. The illuminator IL may be operable to vary the angular distribution of the beam. For example, the illuminator may be operable to change the number and angular extent of the segments in the pupil plane in which the intensity distribution is non-zero. By adjusting the intensity distribution of the beam in the pupil plane of the illuminator, different illumination modes may be achieved. For example, by limiting the radial and angular extent of the intensity distribution in the pupil plane of the illuminator IL, the intensity distribution may have a multipolar distribution, such as (for example) a dipole, quadrupole or hexapole distribution. The desired illumination mode may be obtained, for example, by inserting an optical device providing said illumination mode into the illuminator IL or by using a spatial light modulator.

[0078] The illuminator IL may be operable to change the polarization of the beam and may be operable to adjust the polarization using the adjuster AM. The polarization state of the radiation beam across the pupil plane of the illuminator IL may be referred to as a polarization mode. Using different polarization modes may achieve greater contrast in the image formed on the substrate W. The radiation beam may be unpolarized. Alternatively, the illuminator may be arranged so that the radiation beam is linearly polarized. The polarization direction of the radiation beam may vary across the pupil plane of the illuminator IL. The polarization direction of the radiation may be different in different regions in the pupil plane of the illuminator IL. The polarization state of the radiation may be selected depending on the illumination mode. For a multipolar illumination mode, the polarization of each pole of the radiation beam may be substantially perpendicular to the position vector of the pole in the pupil plane of the illuminator IL. For example, for a dipole illumination mode, the radiation may be linearly polarized in a direction substantially perpendicular to a line of two opposing segments that bisect a dipole. The radiation beam may be polarized in one of two different orthogonal directions that may be referred to as an X polarization state and a Y polarization state. For a quadrupole illumination mode, the radiation in the segment of each pole may be linearly polarized in a direction substantially perpendicular to a line that bisects the segment. This polarization mode may be referred to as XY polarization. Similarly, for a hexapole illumination mode, the radiation in the segments of each pole may be linearly polarized in a direction substantially perpendicular to a line bisecting the segment. This polarization mode may be referred to as TE polarization.

[0079] In addition, the illuminator IL typically includes various other components, such as an integrator IN and a condenser CO. The illumination system may include various types of optical components for directing, shaping or controlling the radiation, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof.

[0080] The illuminator thus provides a conditioned radiation beam B having a desired uniformity and intensity distribution in cross-section.

[0081] The support structure MT supports the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions (such as whether the patterning device is maintained in a vacuum environment). The support structure can use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device. The support structure can be, for example, a frame or table that can be fixed or movable as required. The support structure can ensure that the patterning device is in a desired position, for example relative to a projection system. Any use of the term "reticle" or "mask" herein can be considered synonymous with the more general term "patterning device".

[0082] The term "patterning device" as used herein should be broadly interpreted as referring to any device that can be used to impart a pattern in a target portion of a substrate. In an embodiment, the patterning device is any device that can be used to impart a pattern to a radiation beam in its cross-section so as to produce a pattern in the target portion of the substrate. It should be noted that, for example, if the pattern imparted to the radiation beam includes phase-shifting features or so-called assist features, the pattern may not exactly correspond to the desired pattern in the target portion of the substrate. Typically, the pattern imparted to the radiation beam will correspond to a specific functional layer in a device (such as an integrated circuit) produced in the target portion of the device.

[0083] The patterning device may be transmissive or reflective. Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography and include mask types such as binary, alternating phase shift, and attenuated phase shift, as well as various hybrid mask types. An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which can be individually tilted so as to reflect an incident radiation beam in different directions. The tilted mirrors impart a pattern to the radiation beam reflected by the mirror matrix.

[0084] The term "projection system" as used herein should be broadly interpreted to cover any type of projection system suitable for the exposure radiation used or for other factors such as the use of immersion liquid or the use of a vacuum, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof. Any use of the term "projection lens" herein may be considered synonymous with the more general term "projection system".

[0085] The projection system PS has an optical transfer function that may be non-uniform and may affect the pattern imaged on the substrate W. For unpolarized radiation, these effects can be very well described by two scalar maps that describe the transmission (apodization) and relative phase (aberration) of the radiation exiting the projection system PS as a function of its position in the pupil plane. These scalar maps, which may be referred to as transmission maps and relative phase maps, can be expressed as linear combinations of a complete set of basis functions. A particularly suitable set is the Zernike polynomials, which form a set of orthogonal polynomials defined on the unit circle. The determination of each scalar map may involve determining the coefficients in such an expansion. Because the Zernike polynomials are orthogonal on the unit circle, the Zernike coefficients may be determined by calculating the inner product of the measured scalar map with each Zernike polynomial in turn and dividing such inner product by the square of the norm of the Zernike polynomial.

[0086] The transmission map and the relative phase map are field and system dependent. That is, typically each projection system PS will have a different Zernike expansion for each field point (i.e. for each spatial location in the image plane of the projection system PS). The relative phase of the projection system PS in its pupil plane can be determined by projecting radiation, for example from a point source in the object plane of the projection system PS (i.e. the plane of the patterning device MA) and using a shearing interferometer to measure the wavefront (i.e. the locus of points with the same phase) through the projection system PS. The shearing interferometer is a common path interferometer and therefore, advantageously, no secondary reference beam is required to measure the wavefront. The shearing interferometer may comprise a diffraction grating, e.g. a two-dimensional grid, in the image plane of the projection system (i.e. the substrate table WT) and a detector arranged to detect an interference pattern in a plane conjugate to the pupil plane of the projection system PS. The interference pattern is related to the derivative of the phase of the radiation with respect to the coordinate in the pupil plane in the shear direction. The detector may comprise an array of sensing elements, such as (for example) a charge coupled device (CCD).

[0087] The projection system PS of the lithographic apparatus may not produce visible fringes, therefore, phase stepping techniques (such as (for example) moving a diffraction grating) may be used to enhance the accuracy of the determination of the wavefront. Stepping may be performed in the plane of the diffraction grating and in a direction perpendicular to the scanning direction of the measurement. The stepping range may be one grating period and at least three (uniformly distributed) phase steps may be used. Thus, for example, three scanning measurements may be performed in the y direction, each for a different position in the x direction. Such stepping of the diffraction grating effectively transforms phase changes into intensity changes, allowing the phase information to be determined. The grating may be stepped in a direction perpendicular to the diffraction grating (z direction) to calibrate the detector.

[0088] The diffraction grating may be scanned continuously in two perpendicular directions, which may coincide with the axes (x and y) of the coordinate system of the projection system PS or may be at an angle, such as 45 degrees, to these axes. The scanning may be performed over an integer number of grating periods, such as one grating period. The scanning averages the phase changes in one direction, thereby allowing the phase changes in the other direction to be reconstructed. This allows the wavefront to be determined from two directions.

[0089] The transmission (apodization) of the projection system PS in its pupil plane may be determined by projecting radiation, for example, from a point source in the object plane of the projection system PS (i.e. the plane of the patterning device MA) through the projection system PS and using a detector to measure the intensity of the radiation in a plane conjugate to the pupil plane of the projection system PS. The same detector may be used as that used to measure the wavefront to determine the aberrations.

[0090] The projection system PS may include a plurality of optical (e.g., lens) elements and may also include an adjustment mechanism AM configured to adjust one or more of the optical elements to correct aberrations (phase changes in the pupil plane across the entire field). To achieve this, the adjustment mechanism may be operable to manipulate one or more optical (e.g., lens) elements within the projection system PS in one or more different ways. The projection system may have a coordinate system in which the optical axis of the projection system extends in the z direction. The adjustment mechanism may be operable to perform any combination of the following operations: displacing one or more optical elements; tilting one or more optical elements; and / or deforming one or more optical elements. The displacement of the optical element may be performed in any direction (x, y, z, or a combination thereof). The tilting of the optical element is typically performed outside a plane perpendicular to the optical axis by rotating around an axis in the x and / or y direction, but for non-rotationally symmetric aspheric optical elements, rotation around the z axis may be used. The deformation of the optical element may include low-frequency shapes (e.g., astigmatism) and / or high-frequency shapes (e.g., free-form aspheric surfaces). Deformation of the optical element may be performed, for example, by using one or more actuators to apply forces to one or more sides of the optical element and / or by using one or more heating elements to heat one or more selected regions of the optical element. Typically, it is not possible to adjust the projection system PS to correct for apodization (variations in transmission across the pupil plane). When designing a patterning device (e.g., mask) MA for the lithographic apparatus LA, a transmission map of the projection system PS may be used. Using computational lithography techniques, the patterning device MA may be designed to at least partially correct for apodization.

[0091] The lithographic apparatus may be of a type having two (dual stage) or more tables (e.g. two or more substrate tables WTa, WTb, two or more patterning device tables, substrate table WTa and table WTb below the projection system without a dedicated substrate for, e.g., facilitating measurement and / or cleaning, etc.). In these "multi-stage" machines, the extra tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposure. For example, alignment measurements using alignment sensor AS and / or level (height, inclination, etc.) measurements using level sensor LS may be performed.

[0092] The lithographic apparatus may also be of a type in which at least a portion of the substrate may be covered by a liquid having a relatively high refractive index, such as water, to fill the space between the projection system and the substrate. Immersion liquid may also be applied to other spaces in the lithographic apparatus, such as the space between the patterning device and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of a projection system. The term "immersion" as used herein does not mean that structures such as the substrate must be immersed in the liquid, but only that the liquid is located between the projection system and the substrate during exposure.

[0093] In operation of the lithographic apparatus, a radiation beam is provided and conditioned by an illumination system IL. The radiation beam B is incident on a patterning device (e.g. a mask) MA held on a support structure (e.g. a mask table) MT and is patterned by the patterning device. Having traversed the patterning device MA, the radiation beam B passes through a projection system PS which focuses the beam onto a target portion C of the substrate W. With the aid of a second positioner PW and a position sensor IF (e.g. an interferometric device, a linear encoder, a 2D encoder or a capacitive sensor), the substrate table WT can be accurately moved, for example, so that different target portions C are positioned in the path of the radiation beam B. Similarly, the first positioner PM and a further position sensor ( Figure 1The support structure MT is provided with a plurality of actuators (not explicitly depicted in the figure) to accurately position the pattern forming device MA relative to the path of the radiation beam B. Typically, movement of the support structure MT can be achieved with the help of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) forming part of the first positioner PM. Similarly, movement of the substrate table WT can be achieved using a long-stroke module and a short-stroke module forming part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the support structure MT may be connected only to the short-stroke actuator, or may be fixed. The pattern forming device MA and the substrate W may be aligned using pattern forming device alignment marks M1, M2 and substrate alignment marks P1, P2. Although the substrate alignment marks as shown occupy dedicated target portions, the substrate alignment marks may be located in the space between the target portions (these substrate alignment marks are called scribe alignment marks). Similarly, in the case where more than one die is arranged on the pattern forming device MA, the pattern forming device alignment marks may be located between the dies.

[0094] The depicted device can be used in at least one of the following modes:

[0095] 1. In step mode, the support structure MT and substrate table WT are held substantially stationary while the entire pattern imparted to the radiation beam is projected at one time onto a target portion C (i.e. a single static exposure). Subsequently, the substrate table WT is shifted in the X and / or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure.

[0096] 2. In scan mode, the support structure MT and substrate table WT are scanned synchronously while projecting a pattern imparted to the radiation beam onto a target portion C (i.e. a single dynamic exposure). The speed and direction of the substrate table WT relative to the support structure MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width of the target portion in a single dynamic exposure (in the non-scanning direction), while the length of the scanning movement determines the height of the target portion (in the scanning direction).

[0097] 3. In another mode, the support structure MT is held substantially stationary, thereby holding the programmable patterning device, and the substrate table WT is moved or scanned, while a pattern imparted to the radiation beam is projected onto a target portion C. In such a mode, a pulsed radiation source is typically employed, and the programmable patterning device is updated as required after each movement of the substrate table WT or between successive radiation pulses during a scan. This mode of operation may be readily applicable to maskless lithography utilizing a programmable patterning device, such as a programmable mirror array of the type mentioned above.

[0098] Combinations and / or variations of the above-described modes of use or entirely different modes of use may also be employed.

[0099] Although specific reference may be made herein to the use of lithographic apparatus in IC manufacturing, it should be understood that the lithographic apparatus described herein may have other applications, such as manufacturing integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal displays (LCDs), thin film magnetic heads, etc. Those skilled in the art will appreciate that in the context of these alternative applications, any use of the term "wafer" or "die" herein may be considered synonymous with the more general term "substrate" or "target portion", respectively. The substrates referred to herein may be processed in, for example, a coating and developing system (a tool that typically applies a resist layer to a substrate and develops the exposed resist) or a measurement or inspection tool before or after exposure. Where applicable, the disclosure herein may be applied to these and other substrate processing tools. In addition, the substrate may be processed more than once, for example to produce a multi-layer IC, so that the term substrate used herein may also refer to a substrate that already contains multiple processed layers.

[0100] As used herein, the terms "radiation" and "beam" encompass all types of electromagnetic radiation, including ultraviolet (UV) or deep ultraviolet (DUV) radiation (e.g., having a wavelength of 365, 248, 193, 157 or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 5-20 nm), as well as particle beams (such as ion beams or electron beams).

[0101] Individual patterns on or provided by a pattern forming device may have different process windows, i.e., the space of process variables within which a pattern within specification will be produced. Examples of pattern specifications for potential systematic defects include checking for necking, line pullback, line thinning, CD, edge placement, overlay, resist top loss, resist undercut, and / or bridging. The process window of a pattern on a pattern forming device or a region thereof may be obtained by merging the process windows of each individual pattern (e.g., overlapping the process windows). The boundaries of the process windows of a group of patterns include the boundaries of the process windows of some of the individual patterns. In other words, these individual patterns limit the process windows of the group of patterns. These patterns may be referred to as "hot spots" or "process window limiting patterns (PWLPs)", which are used interchangeably herein. It is possible and economical to focus on hot spots when controlling a portion of a patterning process. When the hot spots are not defective, it is most likely that the other patterns are defective.

[0102] like Figure 2As shown in Figure 1, the lithography equipment LA can form part of a lithography unit LC (sometimes also referred to as a lithography cell or cluster), which also includes equipment for performing pre-exposure and post-exposure processes on a substrate. Conventionally, these equipment include one or more spin coaters SC for depositing one or more resist layers, one or more developers DE for developing the exposed resist, one or more chill plates CH and / or one or more baking plates BK. The substrate conveyor or robot RO picks up one or more substrates from the input / output ports I / O1, I / O2, moves the substrates between different process equipment and transfers the substrates to the feed station LB of the lithography equipment. These equipment, which are generally referred to as coating and developing systems, are under the control of a coating and developing system control unit TCU, which is itself controlled by a management control system SCS, which also controls the lithography equipment via a lithography control unit LACU. Therefore, different equipment can be operated to maximize production volume and processing efficiency.

[0103] In order to correctly and consistently expose a substrate exposed by a lithography apparatus, and / or in order to monitor a part of a patterning process (e.g. a device manufacturing process) comprising at least one pattern transfer step (e.g. an optical lithography step), it is necessary to inspect the substrate or other object to measure or determine one or more properties, such as alignment, overlay (which may be, for example, between structures in superimposed layers or between structures in the same layer that have been provided to said layer respectively by, for example, a double patterning process), line thickness, critical dimension (CD), focus offset, material properties, etc. Therefore, a manufacturing facility in which a lithocell LC is located typically also comprises a metrology system MET, which measures some or all of the substrates W that have been processed in the lithocell or other objects in the lithocell. The metrology system MET may be part of the lithocell LC, for example, it may be part of the lithography apparatus LA (such as an alignment sensor AS).

[0104] The one or more measured parameters may include, for example, overlap between successive layers formed in or on a patterned substrate, for example, critical dimensions (CD) of features formed in or on a patterned substrate (e.g., critical line width), focus or focus error of an optical lithography step, dose or dose error of an optical lithography step, optical aberration of an optical lithography step, etc. Such measurements may be performed on a target on the product substrate itself and / or on a dedicated metrology target disposed on the substrate. The measurements may be performed after resist development but before etching, or may be performed after etching.

[0105] There are various techniques for measuring the structures formed in the patterning process, including the use of scanning electron microscopes, image-based measurement tools and / or various special tools. As discussed above, a fast and non-invasive form of a special measurement tool is a measurement tool in which a radiation beam is directed to a target on the surface of a substrate and the properties of the scattered beam (diffraction beam / reflection beam) are measured. By evaluating one or more properties of the radiation scattered by the substrate, one or more properties of the substrate can be determined. This can be referred to as diffraction-based measurement. One such application of this diffraction-based measurement is in the measurement of feature asymmetry within a target. The measurement of this feature asymmetry can be used as a measure of overlap, for example, but other applications are also known. For example, asymmetry can be measured by comparing relative portions of the diffraction spectrum (for example, comparing the -1 order with the +1 order in the diffraction spectrum of a periodic grating). This measurement can be accomplished in the manner described above, and as described in, for example, U.S. Patent Application Publication US 2006-066855, which is incorporated herein by reference in its entirety. Another application of diffraction-based metrology is in the measurement of feature width (CD) within a target. These techniques can use the apparatus and methods described below.

[0106] Thus, in a device fabrication process (e.g., a patterning process or a lithography process), a substrate or other object may be subjected to various types of measurements during or after the process. The measurements may determine whether a particular substrate is defective, may establish adjustments to the process and equipment used in the process (e.g., aligning two layers on a substrate or aligning a pattern forming device to a substrate), may measure the performance of the process and equipment, or may be used for other purposes. Examples of measurements include optical imaging (e.g., optical microscopy), non-imaging optical measurements (e.g., diffraction-based measurements, such as ASML YieldStar metrology tools, ASML SMASH metrology systems), mechanical measurements (e.g., profile probing using a stylus, atomic force microscopy (AFM)), and / or non-optical imaging (e.g., scanning electron microscopy (SEM)). The SMASH (Smart Alignment Sensor Hybrid) system, as described in U.S. Pat. No. 6,961,116, which is incorporated herein by reference in its entirety, employs a self-referencing interferometer that produces two superimposed and relatively rotated images of an alignment mark, detects intensity in a pupil plane where Fourier transforms of the images are interfered, and extracts position information from the phase difference between the diffraction orders of the two images, which manifests itself as intensity variations in the interference orders.

[0107] The measurement results may be provided directly or indirectly to the supervisory control system SCS. If an error is detected, the exposure of subsequent substrates (especially if the inspection can be completed quickly and quickly enough that one or more other substrates of the batch remain to be exposed) and / or the subsequent exposure of the exposed substrate may be adjusted. In addition, the exposed substrate may be stripped and reworked to improve the yield, or discarded, thereby avoiding further processing of substrates known to be defective. In the case where only some target portions of the substrate are defective, further exposure may be performed only on those target portions that meet the specifications.

[0108] Within the metrology system MET, the metrology equipment is used to determine one or more properties of a substrate, and in particular, to determine how one or more properties of different substrates vary or how different layers of the same substrate vary from layer to layer. As mentioned above, the metrology equipment may be integrated into the lithographic apparatus LA or the lithography cell LC, or may be a separate device.

[0109] In order to achieve the measurement, one or more targets may be provided on the substrate. In an embodiment, the target is specially designed and may include a periodic structure. In an embodiment, the target is a part of a device pattern, for example, a periodic structure of the device pattern. In an embodiment, the device pattern is a periodic structure of a memory device (e.g., a bipolar transistor (BPT), a bit line contact (BLC), etc.).

[0110] In an embodiment, the target on the substrate may include one or more 1-D periodic structures (e.g., gratings) that are printed such that after development, the periodic structural features are formed by solid resist lines. In an embodiment, the target may include one or more 2-D periodic structures (e.g., gratings) that are printed such that after development, the one or more periodic structures are formed by solid resist posts or vias in the resist. The bars, posts or vias may alternatively be etched into the substrate (e.g., etched into one or more layers on the substrate).

[0111] In an embodiment, one of the parameters of interest in the patterning process is overlap. Overlap can be measured using dark field scattering measurements, in which the zeroth order of diffraction (corresponding to specular reflection) is blocked and only higher orders are processed. Examples of dark field measurements can be found in PCT patent application publications WO 2009 / 078708 and WO 2009 / 106279, which are incorporated herein by reference in their entirety. Further advances in the technology have been described in U.S. patent application publications US2011-0027704, US2011-0043791, and US2012-0242970, which are incorporated herein by reference in their entirety. Overlap based on diffraction detection using dark field detection of diffraction orders enables overlap measurement of smaller targets. These targets can be smaller than the irradiation spot and can be surrounded by device product structures on the substrate. In an embodiment, multiple targets can be measured in one radiation capture.

[0112] Figure 3 An example inspection apparatus (e.g., a scatterometer) is depicted. The inspection apparatus comprises a broadband (white light) radiation projector 2 that projects radiation onto a substrate W. The redirected radiation is passed to a spectrometer detector 4, which measures a spectrum 10 (intensity as a function of wavelength) of the specularly reflected radiation, as for example in Figure 3 Based on this data, the processor PU can be used, for example, by rigorous coupled wave analysis and nonlinear regression or by comparing with Figure 3 The structure or profile of the detected spectrum is reconstructed by comparing it to the simulated spectral library shown at the lower right. Typically, for the reconstruction, the general form of the structure is well known, and some variables are assumed based on knowledge of the process by which the structure was made, leaving only a few variables of the structure to be determined from the measured data. Such an inspection device can be configured as a normal incidence inspection device or an oblique incidence inspection device.

[0113] exist Figure 4 Another inspection device that can be used is shown in . In such an arrangement, radiation emitted by a radiation source 2 is collimated using a lens system 12 and transmitted through an interference filter 13 and a polarizer 17, reflected by a partially reflective surface 16 and focused into a spot S on a substrate W via an objective lens 15, which has a high numerical aperture (NA), desirably at least 0.9 or at least 0.95. Immersion inspection devices (using a relatively high refractive index fluid, such as water) can even have a numerical aperture of more than 1.

[0114] As in the lithographic apparatus LA, one or more substrate tables may be provided to hold a substrate W during measurement operations. The substrate table may be similar in form to Figure 1The substrate table WT of the inspection device is similar or identical. In the example where the inspection device is integrated with the lithographic device, the substrate table can even be the same substrate table. A coarse positioner and a fine positioner can be provided to a second positioner PW, which is configured to accurately position the substrate relative to the measuring optical system. Various sensors and actuators are provided, for example, to obtain the position of an object of interest and bring the object of interest into position under the objective lens 15. Typically, many measurements will be made on targets at different locations across the substrate W. The substrate support can be moved in the X and Y directions to obtain different targets, and the substrate support can be moved in the Z direction to obtain the desired location of the target relative to the focus of the optical system. For example, in practice, when the optical system can remain essentially stationary (usually in the X and Y directions, but possibly also in the Z direction) and only the substrate moves, it is appropriate to consider and describe the operation as if the objective lens is brought into a different location relative to the substrate. Assuming the relative position of the substrate to the optical system is correct, it does not matter in principle which of the substrate and the optical system moves in the real world, or both move, or a combination in which part of the optical system moves (e.g. in Z and / or tilt direction) while the rest of the optical system is stationary and the substrate moves (e.g. in X and Y direction, but optionally also in Z and / or tilt direction).

[0115] The radiation redirected by the substrate W is then passed through the partially reflective surface 16 to the detector 18 so that the spectrum can be detected. The detector 18 can be located at the back-projection focal plane 11 (i.e., at the focal length of the lens system 15), or the plane 11 can be re-imaged onto the detector 18 with auxiliary optics (not shown). The detector can be a two-dimensional detector so that a two-dimensional angular scattering spectrum of the substrate target 30 can be measured. The detector 18 can be, for example, a CCD or CMOS sensor array, and can use, for example, an integration time of 40 milliseconds per frame.

[0116] The reference beam can be used, for example, to measure the intensity of incident radiation. To make such a measurement, when the radiation beam is incident on partially reflective surface 16, a portion of the radiation beam is transmitted through partially reflective surface 16 as a reference beam toward reference mirror 14. The reference beam is then projected onto a different portion of the same detector 18 or alternatively onto a different detector (not shown).

[0117] One or more interference filters 13 may be used to select wavelengths of interest in the range of, for example, 405-790 nm or even lower, such as 200-300 nm. The interference filters may be tunable, rather than comprising a collection of different filters. Gratings may be used instead of interference filters. An aperture stop or spatial light modulator (not shown) may be provided in the illumination path to control the range of angles of incidence of the radiation on the target.

[0118] The detector 18 can measure the intensity of the redirected radiation at a single wavelength (or a narrow wavelength range), the intensity of the redirected radiation at multiple wavelengths respectively, or the intensity of the redirected radiation integrated over a wavelength range. In addition, the detector can measure the intensity of the transverse magnetic polarized radiation and the transverse electric polarized radiation respectively and / or the phase difference between the transverse magnetic polarized radiation and the transverse electric polarized radiation.

[0119] The target 30 on the substrate W can be a 1-D grating, which is printed so that after development, the bars are formed by solid resist lines. The target 30 can be a 2-D grating, which is printed so that after development, the grating is formed by solid resist guide posts or through holes in the resist. The bars, guide posts or through holes can be etched into or onto the substrate (for example, etched into one or more layers on the substrate). The pattern (for example, the pattern of bars, guide posts or through holes) is sensitive to process changes during the patterning process (for example, optical aberrations, focus changes, dose changes, etc. in the lithographic projection equipment (specifically, the projection system PS)) and will be manifested as changes in the printed grating. Therefore, the measured data of the printed grating is used to reconstruct the grating. One or more parameters of a 1-D grating (such as line width and / or shape) or one or more parameters of a 2-D grating (such as guide post or via width or length or shape) can be input into a reconstruction process performed by processor PU based on knowledge of the printing steps and / or other inspection processes.

[0120] In addition to the measurement of parameters by reconstruction, angle-resolved scatterometry is also suitable for the measurement of asymmetry of features in products and / or resist patterns. A particular application of asymmetry measurement is for overlay measurements, where the target 30 comprises a set of periodic features superimposed on another set of periodic features. Figure 3 or Figure 4 The concept of asymmetry measurement of an instrument is described, for example, in U.S. Patent Application Publication US2006-066855, which is incorporated herein in its entirety. In short, while the positions of the diffraction orders in the diffraction spectrum of a target are determined only by the periodicity of the target, the asymmetry in the diffraction spectrum indicates the asymmetry in the individual features that make up the target. Figure 4 In an instrument where the detector 18 may be an image sensor, such asymmetry in the diffraction orders appears directly as an asymmetry in the pupil image recorded by the detector 18. Such asymmetry may be measured by digital image processing in the unit PU and may be calibrated against known overlap values.

[0121] Figure 5 A plan view of a typical target 30 is shown and Figure 4In order to obtain a diffraction spectrum that does not interfere with surrounding structures, in an embodiment, the target 30 is a periodic structure (e.g., a grating) that is larger than the width (e.g., diameter) of the illumination spot S. The width of the spot S may be smaller than the width and length of the target. In other words, the target is "underfilled" by the illumination, and the diffraction signal is substantially free of any signal from product features, etc., external to the target itself. Irradiation arrangements 2, 12, 13, 17 ( Figure 4 ) may be configured to provide illumination of uniform intensity across the back focal plane of the objective 15. Alternatively, illumination may be limited to on-axis or off-axis directions, for example by including apertures in the illumination path.

[0122] Figure 6 An example process for determining values ​​of one or more variables of interest for a target pattern 30 based on measurement data obtained using metrology is schematically depicted. Radiation detected by detector 18 provides a measured radiation distribution 608 for target 30. For a given target 30, a radiation distribution 612 may be calculated / simulated from a parameterized model 606 using, for example, a numerical Maxwell solver 610. Parameterized model 606 shows example layers of various materials that make up the target and are associated with the target. Parameterized model 606 may include one or more of the variables for features and layers of the portion of the target under consideration, which may be varied and derived. Figure 6 As shown in , one or more of the variables may include the thickness t of one or more layers, the width w (e.g., CD) of one or more features, the height h of one or more features, and / or the sidewall angle α of one or more features. Although not shown, one or more of the variables may also include, but are not limited to: the refractive index (e.g., real or complex refractive index, refractive index tensor, etc.) of one or more layers, the extinction coefficient of one or more layers, the absorptivity of one or more layers, the resist loss during development, the footing of one or more features, and / or the line edge roughness of one or more features. The initial value of the variable may be the value expected for the measured target. The measured radiation distribution 608 is then compared to the calculated radiation distribution 612 at 612 to determine the difference between the two. If there is a difference, the value of one or more of the variables of the parameterized model 606 may be changed, and a new calculated radiation distribution 612 may be calculated and compared to the measured radiation distribution 608 until there is a sufficient match between the measured radiation distribution 608 and the calculated radiation distribution 612. At this point, the values ​​of the variables of the parameterized model 606 provide a good or optimal match to the geometry of the actual target 30. In an embodiment, a sufficient match exists when the difference between the measured radiation distribution 608 and the calculated radiation distribution 612 is within a tolerance threshold.

[0123] Fig. 7A A flow chart listing the main stages of the "Design for Control" (D4C) method is shown. In stage 710, the material to be used in the lithography process is selected. The material can be selected from a material library that interfaces with D4C via an appropriate GUI. In stage 720, the lithography process is defined by entering each of the process steps and creating a computer simulation model for the entire process sequence. In stage 730, the metrology target is defined, that is, the dimensions and other characteristics of the various features included in the target are input into the D4C process. For example, if a grating is included in the structure, the number of grating elements, the width of a single grating element, the spacing between two grating elements, etc. must be defined. In stage 740, a 3D geometry is generated. This step also takes into account whether there is any information related to the multi-layer target design, such as the relative displacement between different layers. This feature enables a multi-layer target design. In stage 750, the final geometry of the designed target is observed. As will be explained in more detail below, not only the final design is observed, but also as the designer applies the various steps of the lithography process, the designer can visualize how the 3D geometry is formed and how it changes due to process-induced effects. For example, the 3D geometry after resist patterning is different from the 3D geometry after resist removal and etching.

[0124] An important aspect of the present invention is to enable the target designer to observe the stages of the method to facilitate his perception and control during modeling and simulation. Different observation tools called "viewers" are built into the D4C software. For example, Figure 7B , the designer can view material curves 760 (and can also obtain run time estimation curves) depending on the defined lithography process and targets. Once the lithography model is generated, the designer can view the model parameters through the model viewer tool 775. The design layout viewer tool 780 can be used to view the design layout (e.g., a visual presentation of the GDS file). The resist profile viewer tool 785 can be used to view the pattern profiles in the resist. The geometry viewer tool 790 can be used to view the 3D structure on the substrate. The pupil viewer tool 795 can be used to view the simulated response to the measurement tool. Those skilled in the art will understand that these viewing tools can be used to enhance the designer's understanding during design and simulation. In some embodiments of the D4C software, one or more of these tools may not be present, and in some other embodiments, additional viewing tools may be present.

[0125] Figure 7CA flow chart illustrating how the D4C process improves efficiency in the overall simulation process by reducing the number of metrology targets selected for actual simulation of a lithography process. As mentioned previously, D4C enables designers to design thousands or even millions of designs. Not all of these designs may be robust with respect to changes in process steps. In order to select a subset of target designs that can withstand process changes, the lithography operator may intentionally perturb one or more steps of the defined lithography process, as shown in block 752. The introduction of the perturbation changes the entire process sequence relative to how the entire process sequence was originally defined. Therefore, the process sequence after applying the perturbation (block 754) also changes the 3D geometry of the design target. The lithography operator selects only the perturbations that show non-zero changes in the initial design target and generates a subset of the selected process perturbations (block 756). This subset of process perturbations is then used to simulate the lithography process (block 758).

[0126] The use of a lithography process (or, generally, a patterning process) to manufacture or fabricate a substrate typically involves process variations. Process variations are non-uniform across the substrate. For example, during a deposition process, the film tends to be thicker at the center of the substrate and thinner near the edge. These systematic variations are typically reflected in the measurement data as a "fingerprint," which is a characteristic of the substrate based on known process conditions. In other words, there is a stack on the substrate with spatial variations as a function of the substrate coordinates. The stack includes multiple layers formed on the substrate during the patterning process to form a selected pattern (e.g., a design pattern) on the substrate. Each layer of the stack can be associated with thickness, material properties and characteristics, and related parameters of the patterning process (e.g., CD, pitch, overlap, etc.).

[0127] Figure 8a A method 800a for determining an etch profile of a layer of a wafer for a simulation system or for other purposes is illustrated according to an embodiment of the present disclosure. Figure 8bThe diagram shows a similar method for determining the etching profile of a layer of a wafer for a simulation system but without the need for trimming related operations. Methods 800a and 800b are described below in the context of measuring mark alignment, but this is not intended to be limiting. In some embodiments, the resist profile generated from process 800a or 800b can be used as an input for a downstream design-for-control application for control, such as to determine optimal overlap marks and / or alignment marks. Methods 800a and 800b can generally be applied to multiple different processes where etching profile determination is useful. The simulation system for determining the etching profile can be configured to simulate the response of the measurement or inspection system to the etching profile, or other simulation functions. For example, the determined etching profile / simulation system can be used to calibrate the OPC model measured by an optical system or SEM, which can be used to simulate cross-wafer fingerprints from a measurement system or for other purposes. According to embodiments of the present disclosure, methods 800a and 800b are enhanced (relative to prior art systems) etching profile determination methods that advantageously promote more accurate and realistic modeling and / or determination of etching profiles. For example, although other purposes are covered, this more accurate modeling and / or determination of the etching profile can advantageously enhance the determination of the relative displacement between the current layer and the previous layer of the wafer (overlap). As described above, the overlap is generally determined based on the optical response of the measurement mark included in the scribing. In some embodiments, methods 800a and 800b produce more accurate (relative to the prior art system) measurement target models, which in turn promotes more accurate (relative to the prior art system) determination of overlap or other parameters in the design process for control. According to embodiments of the present disclosure, in 800a and 800b, local load effects are modeled using visibility angle, pattern density, and other parameters. This semi-empirical model (in contrast to the previous geometric model) uses multiple parameters to represent plasma physics and material behavior, and reconstructs the post-etching profile by capturing local etching load effects, which are caused by pattern size and density and other factors. Global load effects are introduced by adding electric field distribution and other perturbations to simulate chemical and physical inhomogeneities. Additionally, models of the present apparatus and methods can be calibrated through cross-sectional secondary electron microscopy (SEM) images to accurately describe a specific etching process.

[0128] Methods 800a and 800b include determining 802 a starting masking layer profile for a layer of a wafer. Method 800a includes determining 804 a resist trim etch profile and determining 806 a trim masking layer profile (these operations are not included in method 800b). Methods 800a and 800b include determining 808 load information, determining 810 flux information, determining redeposition information 812, determining 814 an output etch profile for a layer of a wafer, and determining 816 depth information based on the output etch profile for use by a simulation system (e.g., during metrology target design and / or other operations). Determining 814 an output etch profile for a layer of a wafer is based on the load information, flux information, redeposition information, and / or other information as described herein. In an embodiment, determining 802 a starting masking layer profile, determining or otherwise simulating 804, 806 trimming operations, determining 808 load information, determining 810 flux information, determining 812 redeposition information, and / or determining 814 an output etch profile are performed for a region of interest of a layer of a wafer. In an embodiment, determining 818 load information, determining flux information, determining redeposition information, and / or determining an output etch profile are iteratively performed until the depth information corresponds to the depth of the image of the corresponding layer of the physical wafer. Each of these operations is discussed in turn below.

[0129] It should be noted that Figure 8a The order, arrangement, inputs, and outputs of operations 802-818 shown in and / or 8b and discussed below are not intended to be limiting. Figure 8a The illustration shows determining 802 a starting mask layer profile, which is used as an input to determining 804 a resist trim etch profile and determining 806 a trim mask layer profile. Figure 8b These operations are not included at all. As another example, in Figure 8a In the example, determining 804 a resist trim etch recipe may include receiving a resist trim etch recipe or information related to a resist trim etch recipe from an external source that is not part of the system of the present invention via user input or selection of recipe parameters through a user interface or through other operations. In this example, the starting mask layer profile may be modified using the received resist trim etch recipe to produce a trimmed mask layer profile. As another example, Figure 8a The trimmed shadow layer profile (and Figure 8b In an embodiment, these three operations may be performed in parallel (or in other arrangements) and (in Figure 8a Middle) The trimmed mask outline (and if Figure 8bIn this example, the output from all three operations can flow directly into the contour determination 814 step. Figure 8a and Figure 8b There are numerous other examples of various orders, arrangements, inputs, and outputs of the determinations illustrated in .

[0130] like Figure 8a and Figure 8b 8, methods 800a and 800b include determining 802 a starting shielding layer profile for a layer of a wafer. The starting shielding layer profile may be and / or include a resist profile such as a photolithography photoresist profile, a general shielding layer such as a hard mask, or other shielding layer profile. Typically, the starting shielding layer profile may be any pattern design used as an input to methods 800a and 800b. The pattern design may indicate which portions of the wafer will be etched and which portions of the wafer will not be etched. The pattern design may indicate the size, material properties, and other properties of these etched and non-etched areas.

[0131] In some embodiments, the starting masking layer profile (eg, resist profile) can be derived directly from the geometry and dimensions of the corresponding pattern target design without involving lithography or patterning process simulation.

[0132] In an embodiment, the starting masking layer profile of a layer of a wafer comprises a profile after patterning. In an embodiment, the starting masking layer profile of a layer of a wafer comprises a dimension of an after-development inspection (ADI). ADI is typically performed after photoresist exposure and development. The ADI profile advantageously contains additional information resulting from the effects of the patterning process, such as corner rounding, random roughness, compared to the corresponding target design. Therefore, using ADI as an input in a simulation flow can lead to more accurate and realistic predictions.

[0133] In an embodiment, determining a starting shielding layer profile of a layer of a wafer comprises one or more of: obtaining dimensions or other characteristics of the starting shielding layer profile, designing dimensions or other characteristics of the starting shielding layer profile, or measuring dimensions or other characteristics of the starting shielding layer profile.

[0134] For example, obtaining the dimensions or other features of the starting shielding layer profile may include: accessing such information electronically via a database of one or more external computing systems; accessing such information in a local electronic storage device; receiving or accessing such information via network communication; receiving such information from a non-transitory storage medium and / or other electronic storage device source via upload, download or other electronic archive transfer; or obtaining such information by other methods. As another example, the designed dimensions and / or other features of the starting shielding layer profile may be input or selected by a user or through communication with a user via a user interface associated with a design software (e.g., D4C) or other source. As a third example, the dimensions or other features of the starting shielding layer profile may be measured as part of methods 800a and 800b. For example, these measurements may be made on an immediately preceding layer of a solid body or a modeled wafer that has undergone a manufacturing process. In some embodiments, the starting shielding layer profile may also be created based on assumptions made by a designer, system or other source.

[0135] In some embodiments, the starting masking layer profile may be an after-development inspection (ADI) profile generated by modeling a patterning process.

[0136] In one example, the source model represents the optical characteristics of the illumination of the pattern forming device (including the radiation intensity distribution, bandwidth and / or phase distribution). The source model can represent the following optical characteristics of the illumination, including but not limited to the numerical aperture setting, the illumination sigma (σ) setting, and any specific illumination shape (e.g., off-axis radiation shape, such as toroidal, quadrupole, dipole, etc.), where sigma is the outer radius range of the illuminator.

[0137] The projection optics model represents the optical properties of the projection optics (including changes to the radiation intensity distribution and / or phase distribution caused by the projection optics). The projection optics model may represent the optical properties of the projection optics, including aberrations, deformations, one or more refractive indices, one or more physical sizes, one or more physical dimensions, etc.

[0138] The patterning device / design layout model module captures how design features are arranged in the pattern of the patterning device and may include a representation of detailed physical properties of the patterning device, as described, for example, in U.S. Pat. No. 7,587,704, the entire contents of which are incorporated by reference. In an embodiment, the patterning device / design layout model module represents the optical properties (including the changes to the radiation intensity distribution and / or phase distribution by a given design layout) of a design layout (e.g., a device design layout corresponding to features of an integrated circuit, memory, electronic device, etc.), which is a representation of the arrangement of features located on or formed by the patterning device. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus (including at least the illumination and projection optics). The purpose of the simulation is often to accurately predict, for example, edge placement and CD, which can then be compared with the device design. The device design is typically defined as a pre-OPC patterning device layout and will be provided in a standardized digital file format (such as GDSII or OASIS).

[0139] An aerial image can be simulated based on the source model, the projection optics model and the patterning device / design layout model. The aerial image (AI) is the radiation intensity distribution at substrate level. The optical properties of the lithographic projection apparatus (e.g., the properties of the illumination, the patterning device and the projection optics) determine the aerial image.

[0140] A resist layer on a substrate is exposed by the aerial image, and the aerial image is transferred to the resist layer as a potential "resist image" (RI) therein. The resist image (RI) can be defined as the spatial distribution of the solubility of the resist in the resist layer. The resist image can be simulated from the aerial image using a resist model. The resist model can be used to calculate the resist image based on the aerial image, an example of which can be found in U.S. Patent Application Publication No. US 2009-0157360, the entire contents of which are hereby incorporated by reference. The resist model typically describes the effects of chemical processes occurring during resist exposure, post-exposure baking (PEB), and development to predict (for example) the contours of resist features formed on the substrate, and therefore it typically only relates to such properties of the resist layer (for example, the effects of chemical processes occurring during exposure, post-exposure baking, and development). In an embodiment, the optical properties of the resist layer - for example, refractive index, film thickness, propagation and polarization effects - may be captured as part of the projection optics model.

[0141] Thus, in general, the connection between the optics and the resist model is the simulated spatial image intensity within the resist layer, which results from the projection of the radiation onto the substrate, refraction at the resist interface and multiple reflections in the resist film stack. The radiation intensity distribution (spatial image intensity) is converted into a potential "resist image" due to absorption of the incident energy, which is further modified by diffusion processes and various loading effects. Efficient simulation methods that are fast enough for full-chip applications approximate the true 3-dimensional intensity distribution in the resist stack via a 2-dimensional spatial (and resist) image.

[0142] In an embodiment, the resist image may be used as an input to a post-pattern transfer process model module. The post-pattern transfer process model defines the performance of one or more post-resist development processes (eg, etching, developing, etc.).

[0143] Simulation of the patterning process can, for example, predict the profile, CD, edge placement (e.g., edge placement error) in the resist and / or etched image, etc. Thus, the goal of the simulation is to accurately predict, for example, edge placement, and / or spatial image intensity slope, and / or CD, etc., of the printed pattern.

[0144] Thus, the model formula describes most, if not all, of the known physics and chemistry of the overlapping processes, and each of the model parameters is expected to correspond to a different physical or chemical effect. The model formula thus sets an upper bound on how well the model can be used to simulate the entire manufacturing process.

[0145] In some embodiments, a resist image generated according to the above patterned modeling can be used as a starting outline 802. In one embodiment, the patterning process simulates a resist image of the feature. The contour line setting of the feature is extracted from the generated resist image. The contour line setting is then reconstructed into a 3-dimensional contour and used as a starting masking layer contour.

[0146] For example, then, Figure 8a and Figure 8b The model / method shown in may include calibrating the starting obscuration layer profile to an accurate shape using data from cross-sectional profile images and / or scatterometry measurements.

[0147] In some embodiments, the trimming process may simulate the etching process and thereby introduce micro-scale modifications to the starting masking layer profile (e.g., ADI resist image), such as CD shift, roughness tuning, or other random effects. Method 800a includes determining 804 a resist trim etch profile. The resist trim etch profile may specify various trim etch parameters or trim criteria. The trim etch parameters or trim criteria may include trim time, target size, etching gas, etching gas ratio, etching rate (lateral and vertical), etching gas pressure, bias power, source power, temperature, and other parameters. In an embodiment, for example, determining the resist trim etch profile may include: electronically accessing such profile information via a database of one or more external computing systems; accessing such information in a local electronic storage device; receiving or accessing such information via network communication; receiving such information from a non-transitory storage medium and / or other electronic storage device source via upload, download, or other electronic file transfer; or obtaining such information by other methods. In an embodiment, the trim etch parameters or trim criteria may be input or selected by a user or by communication with a user, via a user interface communication associated with design software (e.g., D4C) or other source. In some embodiments, "trim" may be a general description of modification of a critical dimension (CD) that is different from the ADI dimension as printed. In some embodiments, the trim operation may involve another modeling cycle, such as from 804 to 814.

[0148] The method 800a includes determining 806 a trimmed shielding layer profile by simulating a trim operation on a starting shielding layer profile according to a resist trim etch profile. In an embodiment, simulating the trim operation on the starting shielding layer profile includes modifying a size or other characteristic of the starting shielding layer profile based on a size and / or other characteristic of the starting shielding layer profile, a trim etch parameter or a trim criterion in an etch trim profile, or other information. In an embodiment, simulating the trim operation on the starting shielding layer profile includes adjusting a mask critical dimension (CD) offset 820. In an embodiment, adjusting the mask critical dimension offset 820 includes manually tuning the mask critical dimension offset 820 (e.g., by a user via a user interface and associated software tools), calibrating the mask critical dimension offset 820 based on an image or measurement of a physical wafer, or other adjustments. In an embodiment, after adjusting the mask critical dimension offset 820, the process of simulating the trim operation on the starting shielding layer profile according to the resist trim etch profile may be repeated. For example, this process may be repeated iteratively until one or more trimmed occlusion layer profile criteria (eg, size, surface properties, etc.) are met.

[0149] Methods 800a and 800b include determining 808 load information for a shielding layer profile based at least in part on the trimmed shielding layer profile (800a) or the starting shielding layer profile (800b). The load information indicates the dependency of the etch rate for the shielding layer profile on the amount and pattern of the etched material, which portions of the pattern are covered or uncovered, the surrounding environment, or other factors. In an embodiment, determining the load information for the shielding layer profile includes adjusting one or more parameters of an etch rate constant 822, a short-range load factor 824, a long-range load factor 826, or other adjustable parameters. In an embodiment, adjusting the etch rate constant 822, the short-range load factor 824, the long-range load factor 826, or other adjustable parameters includes: manually tuning the etch rate constant 822, the short-range load factor 824, the long-range load factor 826, etc. (e.g., by a user via a user interface and associated software tools), calibrating the etch rate constant 822, the short-range load factor 824, the long-range load factor 826, etc. based on images or measurements of a physical wafer, or other adjustments. In an embodiment, after adjusting the etch rate constant 822, the short-range load factor 824, the long-range load factor 826, etc., the process of determining 808 load information may be repeated.

[0150] In an embodiment, determining 808 the load information includes determining the dependency of the etch rate at individual locations across the shielding layer profile. These determinations can be made based on the amount and pattern of material being etched at the individual locations, which parts of the pattern are covered or uncovered, the surrounding environment, or other factors. In an embodiment, determining the dependency of the etch rate at individual locations across the shielding layer profile includes determining individual load factors for the individual locations.

[0151] By way of non-limiting example, Fig. 9 900 of determining the aspect of the load information of the region of interest of the masking layer profile. In some embodiments, the load operation can be applied to the masking layer profile which can be a simulated or measured ADI, or a simulated or measured resist image, and the ADI or resist image can have been through a trimming process. In some other embodiments, the load operation can be applied to the masking layer profile which includes only geometric and dimensional information derived from the target design and not generated from a patterning process or a patterning process simulation. In an embodiment, Fig. 9 The following discussion may describe a pattern density model for the systems and methods of the present invention. The pattern density model may detect or otherwise model the surrounding mask pattern of individual sample points in a region of interest. Fig. 9 , the region of interest 900 includes a trench region 902 and a mask region 904 (this is not intended to be limiting). In an embodiment, determining 808 ( Figure 8a and Figure 8b) The load information includes determining the dependency of the etch rate at individual XY locations across the region 900. In an embodiment, determining the dependency of the etch rate at the individual XY locations includes determining individual load factors at the individual locations. In an embodiment, the individual load factors are determined based on a Boolean function of the mask pattern at the individual locations or other information. For example, the individual load factors p for the individual XY locations can be determined based on Equation 1.

[0152] P(x,y,r) = b(x,y,r)×M (x,y)(1)

[0153] Where x and y indicate the coordinates of the evaluation point within the region of interest 900, r is a range factor, M (x, y) indicates the overall mask pattern (e.g., the pattern of the trench region 902 and the mask region 904) or ADI pattern (e.g., the resist image pattern generated from 802 and / or 804, as described above) within the region of interest 900, and b(x, y, r) is a combination of a Boolean function and a Gaussian distribution function of the mask pattern. In this example, p(x, y, r) is a separate XY location or region for which a separate load factor p is determined, and is determined by Fig. 9 In this example, the Boolean function in b(x, y, r) is 0 in the trench region 902 and 1 in the mask region 904. After combining with the Gaussian function, the Boolean function will be a value between 0 and 1.

[0154] Back to Figure 8a and Figure 8b , methods 800a and 800b include determining 810 flux information for a shielding layer profile based at least in part on a trimmed shielding layer profile (800a) or a starting shielding layer profile (800b). The flux information indicates a dependency of an etch rate for the shielding layer profile on an intensity and a spread angle or other information of radiation incident on the shielding layer profile. In an embodiment, determining the flux information for the shielding layer profile includes adjusting one or more of an ion intensity 830, a neutral intensity 832, a spread angle 834, or other characteristics of the incident radiation. In an embodiment, adjusting the ion intensity 830, the neutral intensity 832, the spread angle 834, or other characteristics of the incident radiation includes: manually tuning the ion intensity 830, the neutral intensity 832, the spread angle 834, or other characteristics of the incident radiation (e.g., by a user via a user interface and associated software tools), calibrating the ion intensity 830, the neutral intensity 832, the spread angle 834, or other characteristics of the incident radiation based on images or measurements of a physical wafer, or other adjustments. In an embodiment, the process of determining 810 flux information may be repeated after adjusting the ion intensity 830, neutral intensity 832, spread angle 834, or other characteristics of the incident radiation.

[0155] In an embodiment, the flux information is determined based on one or more bias constants, one or more fitting constants, short-range loading factors, and long-range loading factors corresponding to individual sites. For example, the neutral intensity 832 can be described by Equation 2 shown below.

[0156] f neutral = c o +(c 1 ×p 1 )+(c 2 ×p 2 ) (2)

[0157] In Equation 2, c o is the bias constant, c 1 and c 2 are the short-range and long-range fitting factors, and p 1 and p 2 are the short-range and long-range load factors. For example, ionic strength 830 can be described by similar equations. One or more bias constants, one or more fit factors, short-range load factors, and long-range load factors can be determined when manufacturing the system of the present invention, obtained from an electronic storage device or other source by the system of the present invention, input, selected, or adjusted by a user via a user interface associated with the system described herein, or determined in other ways.

[0158] In an embodiment, determining 810 flux information includes determining the dependence of the etch rate at individual locations across the shielding layer profile on the intensity, spread angle, or other characteristics of the radiation incident on the shielding layer profile at the individual locations. In an embodiment, this can be a visibility etching model or part thereof of the present system and method. For example, for an area of ​​interest (e.g., Fig. 9 For individual etchable points in the region 900 (shown in FIG. 1 ), the visibility etching model can use the collection angle relative to a predefined incident (ionic and neutral) radiation angle to determine the etching rate (e.g., an etching rate vector). In the present system and method, the etching rate is not assumed as in the prior art system. Determining 810 flux information (e.g., a visibility etching model) can include: modeling the movement of etchable points in the region of interest toward the incident radiation; determining an etching ratio based on the ionic and neutral distribution within a small time segment; repeating these operations at individual etchable points; and iterating according to Equation 3 shown below.

[0159] (3)

[0160] The F(x) term comes from Equation 2 above. Θ represents the angle of incidence.

[0161] By way of non-limiting example, Fig.10 Provide and determine (for example, from Figure 8a and Figure 8b 810). Diagram 1010 shows radiation 1025, 1026 incident on mask material 1030 and etch material 1040. As etchable points 1050, 1060 in the region of interest are modeled to move relative to the incident radiation 1025, 1026, the interaction of the incident radiation 1025, 1026 with the mask material 1030 and etch material 1040 changes. For example, in diagram 1010, the angle α of the incident radiation 1025 is different compared to the incident radiation 1026. As another example, radiation 1025 is cut off or blocked by mask material 1030, while radiation 1026 is not cut off or blocked by mask material 1030. Diagram 1020 shows how the inventive system or method better accounts for these interactions relative to prior art systems or methods. For example, in a "before" image 1070 corresponding to how the prior art system models radiation incident on the mask material 1030 and the etch material 1040 shown in diagram 1010, the flux intensity 1072 is not affected in the x-direction 1074 or in the y-direction 1076, even though the mask material 1030 may block or at least affect the incident radiation. In an "after" image 1080 corresponding to how the inventive system and method models radiation incident on the mask material 1030 and the etch material 1040 shown in diagram 1010, the flux intensity 1072 is truncated in the x-direction 1074 in region 1075 and in the y-direction 1076 in region 1077. The inventive system and method is configured such that this truncation occurs because the model is able to take into account that the mask material 1030 blocks or at least affects the incident radiation.

[0162] Back to Figure 8a and Figure 8b , methods 800a and 800b include determining, based at least in part on a trimmed shading layer profile ( Figure 8a ) or the starting mask outline ( Figure 8b) to determine 812 redeposition information for the shielding layer profile. The redeposition information indicates a dependency of an etch rate for the shielding layer profile on an amount of material removed from the shielding layer profile and redeposited back onto the shielding layer profile. In an embodiment, determining the redeposition information for the shielding layer profile includes adjusting a redeposition rate 840 for the shielding layer profile. In an embodiment, adjusting the redeposition rate 840 includes manually tuning the redeposition rate 840 (e.g., by a user via a user interface and associated software tools), calibrating the redeposition rate 840 based on an image or measurement of a physical wafer, or other adjustments. In an embodiment, after adjusting the redeposition rate 840, the process of determining 812 redeposition information may be repeated. In an embodiment, determining the redeposition information includes determining a dependency of an etch rate at separate locations across the shielding layer profile on an amount of material removed from the shielding layer profile at the separate locations and redeposited back onto the shielding layer profile at the separate locations.

[0163] In an embodiment, the redeposition information is determined based on one or more bias constants, a long-range fit factor, and a long-range load factor corresponding to individual sites. For example, the redeposition rate 840 may be described by Equation 4 shown below.

[0164] F redep = c 3 + c 4 ×p 3 (4)

[0165] In Equation 4, c 3 and c 4 is a constant and a short-range fitting factor, and p 3 is the short range load factor. One or more fit factors and different range load factors may be determined when manufacturing the system of the present invention, obtained by the system of the present invention from an electronic storage device or other source, input, selected or adjusted by a user via a user interface associated with the system described herein, or otherwise determined.

[0166] Methods 800a and 800b include determining 814 an output etch profile of a layer of a wafer. The output etch profile of the layer of the wafer is determined based on load information, flux information, redeposition information, or other information of the (trimmed or initial) shielding layer profile. In an embodiment, for example, determining 814 the output etch profile can be performed using a method similar or identical to the method for determining the output etch profile using D4C described herein. However, as described above, the present system and method use load information, flux information, and redeposition information to determine the output etch profile, rather than using a simplified geometric model of the prior art.

[0167] In an embodiment, methods 800a and 800b include determining 816 depth information based on the output etch profile for use by a simulation system (e.g., during overlay determination in a metrology target design and / or during other operations). In an embodiment, for example, determining 816 the depth information can be determined using a method similar to or the same as the method described herein for determining depth information using D4C.

[0168] In an embodiment, one or more (parametric) operations of methods 800a and 800b can be calibrated by fitting the simulated depth profile to the corresponding cross section of a physical wafer using a scanning electron microscope (SEM) or other tool. In the SEM, a primary electron beam is emitted from an electron source and converged by a condenser lens, and then passes through a beam deflector, an ExB deflector, and an objective lens to irradiate a substrate on a substrate stage at a focal point. When the substrate is irradiated with an electron beam, secondary electrons are generated from the substrate. The secondary electrons are deflected by the ExB deflector and detected by a secondary electron detector. A two-dimensional electron beam image can be obtained by detecting the electrons generated from the sample synchronously with the following operations: for example, two-dimensional scanning of the electron beam by a beam deflector or repeated scanning of the electron beam in the X or Y direction by a beam deflector, and continuous movement of the substrate in the other direction of the X or Y direction by the substrate stage. The signal detected by the secondary electron detector is converted into a digital signal by an analog / digital (A / D) converter, and the digital signal is sent to an image processing system. In an embodiment, the image processing system may have a memory for storing all or part of the digital images for processing by the processing unit. The processing unit (e.g., a specially designed hardware or a combination of hardware and software or a computer-readable medium including software) is configured to convert or process the digital image into a data set representing the digital image. In an embodiment, the processing unit is configured or programmed so as to perform the method described herein. In addition, the image processing system may have a storage medium configured to store the digital image and the corresponding data set in a reference database. A display device may be connected to the image processing system so that an operator can perform the necessary operations of the equipment by means of a graphical user interface.

[0169] In an embodiment, methods 800a and 800b further include generating an electronic depiction (e.g., a model, an electronic image, etc.) of a layer of a wafer based on the depth information to facilitate visual comparison between the electronic depiction and an image of a corresponding layer of a physical wafer. The electronic depiction may be an image (e.g., a SEM image), a model, and / or other electronic depiction. The electronic depiction may be a cross-sectional image, a non-cross-sectional image, a number or code representing a layer (e.g., not an image at all), or other information forming an electronic depiction. In an embodiment, the method further includes generating an electronic depiction of a layer of a wafer based on the depth information to facilitate dimensional measurement of the electronic depiction for comparison with dimensions obtained from an image of a corresponding layer of a physical wafer. In an embodiment, one or more (parametric) operations of methods 800a and 800b may be calibrated based on information from any metrology system (e.g., a scatterometer, etc.). In an embodiment, the system of the present invention may include an independent calibration system and a metrology system including an etching model (e.g., methods 800a and / or 800b). In an embodiment, a mask layer may be measured or simulated (e.g., a lithography simulator may generate a profile output). The calibration may include calibration of parameters in the mask layer model (eg, parameters affecting the resist profile of the lithography model).

[0170] As described above, one or more operations of methods 800a and 800b can be calibrated by fitting a simulated depth profile (e.g., electronic depiction) to a corresponding cross section of a physical or modeled wafer. Calibration can include adjusting one or more parameters described above (e.g., mask critical dimension offset 820, etching rate constant 822, short-range factor 824, long-range factor 826, ion intensity 830, neutral intensity 832, spread angle 834, redeposition rate 840, or other parameters) based on the similarity or difference between the simulated depth profile (or other electronic depiction) and the corresponding cross section of the physical wafer. The calibrated method (e.g., model) can be used to predict (as just one example, to measure the target design) etch profile, which can be fed to a simulation system such as a design for control (or other similar design software) to predict overlay (e.g., by Yieldstar (described above)) or other alignment signal performance. In some embodiments, the prediction can then be used to generate a better overlay or alignment mark design in the design for control. In an embodiment, determining load information, determining flux information, determining redeposition information, determining output etch profile, and / or calibration are iteratively performed 818 until the depth information corresponds to the depth of the image and / or other electronic depiction (e.g., model) of the corresponding layer of the physical wafer.

[0171] Figure 8cFIGURE 1 is a diagram of an alternative method for calibration using a combination of an overlay and alignment system. For example, the overlay and alignment system can be replaced with an optical critical dimension (OCD) system (e.g., another scatterometry system) or a SEM or electron beam system. The different measurement systems can also be a combination system (e.g., calibration based on cross-sectional data, OCD data, and / or SEM data). Figure 8c 8, model parameters 850, alignment mark design 852, and overlay target design 854 are fed into an etch model 856. The etch model 856 outputs a wafer alignment simulation 858 and a wafer overlay simulation 860. These are used in combination with overlay measurement 862 data (based on overlay target design 854) and alignment measurement 864 data (based on alignment mark design 852) for model parameter calibration 866. The calibrated model parameters 850 are fed back into the model 856.

[0172] Fig.11 The electronic depictions 1100 and 1102 of two different depth profiles produced using the methods 800a or 800b described above are shown. Fig.11 1102 reflects the variation in depth 1108 of each recess 1112 across the planar dimension 1110 of the modeled wafer 1113. A bow 1120 at the bottom edge of a depth profile 1122 modeled using the systems or methods described herein and shown in the electronic depiction 1102 is reflected.

[0173] Fig.12 1 is a block diagram illustrating a computer system 100 that may assist in implementing the methods, processes, or systems disclosed herein. The computer system 100 includes a bus 102 or other communication mechanism for communicating information, and a processor 104 (or multiple processors 104 and 105) coupled to the bus 102 for processing information. The computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 102 for storing information and instructions to be executed by the processor 104. The main memory 106 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 104. The computer system 100 also includes a read-only memory (ROM) 108 or other static storage device coupled to the bus 102 for storing static information and instructions for the processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to the bus 102 for storing information and instructions.

[0174] The computer system 100 can be coupled to a display 112, such as a cathode ray tube (CRT) or a flat panel display or a touch panel display, via the bus 102 for displaying information to a computer user. An input device 114 including alphanumeric keys and other keys is coupled to the bus 102 for communicating information and command selections to the processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball, or cursor direction keys, for communicating directional information and command selections to the processor 104 and for controlling cursor movement on the display 112. Such an input device typically has two degrees of freedom on two axes, a first axis (e.g., x) and a second axis (e.g., y), allowing the device to indicate a position in a plane. A touch panel (screen) display can also be used as an input device.

[0175] According to one embodiment, portions of one or more methods described herein may be performed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. These instructions may be read into main memory 106 from another computer-readable medium, such as storage device 110. Execution of the sequence of instructions contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be used to execute the sequence of instructions contained in main memory 106. In alternative embodiments, hard-wired circuits may be used instead of or in combination with software instructions. Therefore, the description herein is not limited to any specific combination of hardware circuitry and software.

[0176] As used herein, the term "computer-readable medium" refers to any medium that participates in providing instructions to the processor 104 for execution. Such media can be in many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical disks or magnetic disks, such as storage devices 110. Volatile media include volatile memories, such as main memory 106. Transmission media include coaxial cables, copper wires, and optical fibers, which include wires containing bus 102. Transmission media can also be in the form of sound waves or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, floppy disks, floppy disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, DVDs, any other optical media, punch cards, paper tapes, any other physical media with hole patterns, RAMs, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cartridges, carriers as described below, or any other media that can be read by a computer.

[0177] Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may be initially carried on a disk of a remote computer. The remote computer may load the instructions into its volatile memory and send the instructions via a telephone line using a modem. A modem local to computer system 100 may receive data on the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector coupled to bus 102 may receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries the data to main memory 106, from which processor 104 retrieves and executes instructions. The instructions received by main memory 106 may optionally be stored on storage device 110 before or after being executed by processor 104.

[0178] The computer system 100 may also include a communication interface 118 coupled to the bus 102. The communication interface 118 provides bidirectional data communication coupled to a network link 120, which is connected to a local area network 122. For example, the communication interface 118 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, the communication interface 118 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link may also be implemented. In any such implementation, the communication interface 118 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0179] The network link 120 typically provides data communications to other data devices through one or more networks. For example, the network link 120 may provide a connection to a host computer 124 or to data equipment operated by an Internet Service Provider (ISP) 126 through a local area network 122. The ISP 126, in turn, provides data communication services through a global packet data communication network, now commonly referred to as the "Internet" 128. Both the local area network 122 and the Internet 128 use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on the network link 120 and through the communication interface 118 are exemplary carrier wave forms of conveying information, which carry the digital data to and from the computer system 100.

[0180] The computer system 100 can send messages and receive data including program code through the network, network link 120 and communication interface 118. In the Internet example, the server 130 can transmit the requested code for the application program through the Internet 128, ISP 126, local area network 122 and communication interface 118. For example, one such downloaded application program can provide all or part of the methods described herein. The received code can be executed by the processor 104 when it is received, and / or stored in the storage device 110 or other non-volatile storage device for later execution. In this way, the computer system 100 can obtain application code in the form of a carrier wave.

[0181] Fig.13 An exemplary lithographic projection apparatus incorporating the techniques described herein that may be utilized is schematically depicted. The apparatus comprises:

[0182] - an illumination system IL for conditioning the radiation beam B. In this particular case, the illumination system also comprises a radiation source SO;

[0183] a first object table (eg patterning device table) MT having a patterning device holder for holding a patterning device MA (eg a reticle) and connected to a first positioner for accurately positioning the patterning device relative to the item PS;

[0184] a second object table (substrate table) WT having a substrate holder for holding a substrate W (e.g. a silicon wafer coated with resist) and connected to a second positioner for accurately positioning the substrate relative to the object PS;

[0185] - a projection system ("lens") PS (eg, a refractive, reflective or catadioptric optical system) to image the illuminated portion of the patterning device MA onto a target portion C of the substrate W (eg, comprising one or more dies).

[0186] As depicted herein, the device is of the transmissive type (i.e., has a transmissive patterning device). However, in general, for example, the device may also be of the reflective type (have a reflective patterning device). The device may employ a different kind of patterning device than a classical mask; examples include a programmable mirror array or an LCD matrix.

[0187] A source SO (e.g. a mercury lamp or an excimer laser, a laser produced plasma (LPP) EUV source) generates a radiation beam. This beam is fed into an illumination system (illuminator) IL, for example directly or after having traversed a conditioning device such as a beam expander Ex. The illuminator IL may include an adjustment device AD ​​for setting the outer radial extent and / or the inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, the illuminator typically includes various other components, such as an integrator IN and a condenser CO. In this way, the beam B impinging on the patterning device MA has a desired uniformity and intensity distribution in its cross section.

[0188] about Fig.13 It should be noted that the source SO can be within the housing of the lithographic projection apparatus (this is often the case when the source SO is, for example, a mercury lamp), but it can also be remote from the lithographic projection apparatus, the radiation beam it generates being directed into the apparatus (for example, with the aid of suitable directional mirrors); this latter case is often the case when the source SO is an excimer laser (for example, based on the action of a KrF, ArF or F2 laser).

[0189] The beam PB then intercepts the patterning device MA held on the patterning device table MT. Having traversed the patterning device MA, the beam B passes through a lens PL which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning device (and the interferometric measurement device IF), the substrate table WT can be accurately moved, for example in order to position different target portions C in the path of the beam PB. Similarly, the first positioning device can be used to accurately position the patterning device MA relative to the path of the beam B, for example after mechanical retrieval of the patterning device MA from a patterning device library or during scanning. Typically, movement of the object table MT, WT will be achieved with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) which are not explicitly depicted. However, in the case of a stepper (as opposed to a step-and-scan tool), the patterning device table MT may be connected to a short-stroke actuator only, or may be fixed.

[0190] The depicted tools can be used in two different modes:

[0191] - in step mode, the patterning device table MT is kept substantially stationary and the entire patterning device image is projected at once (i.e. a single "flash") onto a target portion C. The substrate table WT is subsequently shifted in the x and / or y direction so that a different target portion C can be illuminated by the beam PB;

[0192] - In scan mode, essentially the same situation applies, except that a given target portion C is not exposed in a single "flash". Alternatively, the patterning device table MT can be moved in a given direction (the so-called "scanning direction", e.g. the y-direction) at a speed v, so as to scan the projection beam B over the patterning device image; while the substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mv, where M is the magnification of the lens PL (typically M=1 / 4 or 1 / 5). In this way, a relatively large target portion C can be exposed without having to compromise resolution.

[0193] Fig.14 The apparatus 1000 is shown in more detail and includes a source collector module SO, an illumination system IL, and a projection system PS. The source collector module SO is constructed and arranged so that a vacuum environment can be maintained in an enclosure 220 of the source collector module SO. An EUV radiation emitting plasma 210 can be formed by a discharge-generated plasma source. EUV radiation can be generated by a gas or vapor (e.g., Xe gas, Li vapor, or Sn vapor), wherein a very hot plasma 210 is generated to emit radiation in the EUV range of the electromagnetic spectrum. For example, the very hot plasma 210 is generated by a discharge that generates an at least partially ionized plasma. For efficient generation of radiation, a partial pressure of, for example, 10 Pa of Xe, Li, Sn vapor, or any other suitable gas or vapor may be required. In an embodiment, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0194] The radiation emitted by the hot plasma 210 is transferred from the source chamber 211 to the collector chamber 212 via an optional gas barrier or contaminant trap 230 (also referred to as a contaminant barrier or foil trap in some cases) positioned in or behind an opening in the source chamber 211. The contaminant trap 230 may include a channel structure. The contaminant trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. As is known in the art, the contaminant trap or contaminant barrier 230 further indicated herein includes at least a channel structure.

[0195] The collector chamber 211 may include a radiation collector CO which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation traversing the collector CO may be reflected from the grating spectral filter 240 to be focused into a virtual source point IF along the optical axis indicated by the dotted line "O". The virtual source point IF is often referred to as an intermediate focus, and the source collector module is arranged so that the intermediate focus IF is located at or near an opening 221 in the enclosure structure 220. The virtual source point IF is an image of the radiation emitting plasma 210.

[0196] The radiation then traverses an illumination system IL which may include a faceted field mirror arrangement 22 and a faceted pupil mirror arrangement 24 which are arranged to provide a desired angular distribution of the radiation beam 21 at the patterning device MA and a desired uniformity of radiation intensity at the patterning device MA. After reflection of the radiation beam 21 at the patterning device MA held by the support structure MT, a patterned beam 26 is formed and the patterned beam 26 is imaged by the projection system PS via reflective elements 28, 30 onto a substrate W held by a substrate table WT.

[0197] In general, more elements than shown may be present in the illumination optics unit IL and the projection system PS. Depending on the type of lithographic apparatus, a grating spectral filter 240 may optionally be present. In addition, more mirrors may be present than shown in the figures, for example, more than 200 mirrors may be present in the projection system PS. Fig.14 The reflective elements shown in FIG. 1 may have 1 to 6 additional reflective elements more than the reflective elements shown in FIG.

[0198] Will be like Fig.14 The collector optics CO illustrated in FIG. 1 is depicted as a nested collector with grazing incidence reflectors 253, 254 and 255, merely as an example of a collector (or collector mirror). The grazing incidence reflectors 253, 254 and 255 are arranged axially symmetrically around the optical axis O, and this type of collector optics CO can be used in combination with a discharge produced plasma source, generally referred to as a DPP source.

[0199] Alternatively, the source collector module SO may be as follows Fig.15 . The laser LA is arranged to deposit laser energy into a fuel such as xenon (Xe), tin (Sn) or lithium (Li), thereby producing a highly ionized plasma 210 with an electron temperature of several 10 eV. The high-energy radiation produced during the deexcitation and recombination of these ions is emitted from the plasma, collected by the near normal incidence collector optics CO, and focused onto an opening 221 in the enclosure structure 220.

[0200] The following aspects may be used to further describe the embodiments:

[0201] 1. A method for determining an etch profile of a layer of a wafer for a simulation system, the method comprising:

[0202] determining a shadow layer profile of a layer of the wafer, wherein the initial shadow layer profile is a profile inspected after development;

[0203] Based at least in part on the occlusion layer profile:

[0204] determining loading information for the masking layer profile, the loading information indicating a dependency of an etch rate for the masking layer profile on an amount and pattern of material being etched; and / or

[0205] determining flux information for the shielding layer profile, the flux information indicating a dependence of the etch rate for the shielding layer profile on the intensity and spread angle of radiation incident on the shielding layer profile; and / or

[0206] determining redeposition information for the shielding layer profile, the redeposition information indicating a dependence of the etch rate for the shielding layer profile on an amount of material removed from the shielding layer profile and redeposited back onto the shielding layer profile; and

[0207] Based on the loading information, the flux information and / or the redeposition information of the masking layer profile, an output etch profile for the layer of the wafer is determined.

[0208] 2. The method of clause 1, further comprising: determining depth information based on the output etch profile for use during overlay determination.

[0209] 3. The method according to aspect 2, wherein determining the load information, determining the flux information, determining the redeposition information and / or determining the output etch profile are performed iteratively until the depth information corresponds to the depth of the image of the corresponding layer of the physical wafer.

[0210] 4. The method of clause 3, further comprising: generating an electronic depiction of the layer of the wafer based on the depth information to facilitate visual comparison between the electronic depiction and the image of the corresponding layer of the physical wafer.

[0211] 5. The method of clause 3, further comprising: generating an electronic depiction of the layer of the wafer based on the depth information to facilitate dimensional measurement of the electronic depiction for comparison with dimensions obtained from the image of the corresponding layer of the physical wafer.

[0212] 6. The method of clause 1, further comprising: calibrating operating parameters of the method based on information from a metrology system for corresponding layers of the physical wafer and / or the simulated wafer.

[0213] 7. The method of clause 6, comprising: calibrating operating parameters of the method based on information from the metrology system for the corresponding layer of the simulated wafer, wherein the calibration further comprises adjusting wafer simulation parameters of the simulated wafer.

[0214] 8. A method according to any one of aspects 1 to 7, wherein determining the masking layer profile, determining the load information, determining the flux information, determining the redeposition information and / or determining the output etching profile are performed for a region of interest of the layer of the wafer.

[0215] 9. The method of any one of clauses 1 to 8, wherein the masking layer profile of the layer of the wafer comprises a patterned profile.

[0216] 10. The method according to any one of aspects 1 to 9, wherein the post-development inspection profile is obtained by measurement or patterning process simulation.

[0217] 11. A method according to any one of aspects 1 to 10, wherein determining the shielding layer profile of the layer of the wafer comprises one or more of the following operations: obtaining a size of the shielding layer profile, designing a size of the shielding layer profile, or measuring a size of the shielding layer profile.

[0218] 12. The method according to any one of aspects 1 to 11, further comprising: simulating a trimming operation on the shielding layer profile according to a trimming option, wherein simulating the trimming operation on the shielding layer profile comprises modifying a size of the shielding layer profile.

[0219] 13. The method of clause 12, wherein simulating the trimming operation on the masking layer profile comprises adjusting a mask critical dimension (CD) offset.

[0220] 14. The method of any one of clauses 1 to 13, wherein determining the loading information of the masking layer profile comprises one or more of the following operations: adjusting an etch rate constant, a short-range loading factor, or a long-range loading factor.

[0221] 15. The method of any one of aspects 1 to 14, wherein determining the flux information of the obscuration layer profile comprises adjusting one or more of: ionic intensity, neutral intensity, or spread angle of the incident radiation.

[0222] 16. The method according to any one of aspects 1 to 15, wherein determining the redeposition information of the obscuring layer profile comprises adjusting a redeposition rate of the obscuring layer profile.

[0223] 17. The method according to any one of aspects 1 to 16, wherein:

[0224] Determining the loading information includes determining a dependency of the etch rate at individual locations across the masking layer profile based on an amount and pattern of material being etched at the individual locations;

[0225] Determining the flux information includes determining a dependency of the etch rate at the individual locations across a shielding layer profile based on an intensity and a spread angle of radiation incident on the shielding layer profile at the individual locations; and

[0226] Determining the redeposition information includes determining a dependency of the etch rate at the individual locations across the masking layer profile based on an amount of material removed from the masking layer profile at the individual locations and redeposited back onto the masking layer profile at the individual locations.

[0227] 18. The method of clause 17, wherein determining the dependence of the etch rate at the individual locations across the masking layer profile comprises determining individual load factors for the individual locations.

[0228] 19. The method of clause 18, wherein the individual load factors are determined based on Boolean functions of the mask pattern at the individual locations.

[0229] 20. The method of aspect 17, wherein the flux information is determined based on one or more bias constants, one or more fitting constants, a short-range loading factor, and a long-range loading factor corresponding to individual sites.

[0230] 21. The method of clause 17, wherein the redeposition information is determined based on one or more bias constants, long-range fit factors, and long-range loading factors corresponding to individual sites.

[0231] 22. A method according to aspects 1 to 17, wherein the post-development inspection profile is obtained from a resist image.

[0232] 23. The method according to clauses 1 to 17 and 22, wherein the contour of the post-development inspection is constructed based on contour lines extracted from the resist image.

[0233] 24. The method of clauses 1 to 10 and 23, further comprising: constructing a device stack by using the output etch profile; feeding the constructed stack to a metrology simulation process to predict a metrology signal.

[0234] 25. The method according to clauses 1 to 10 and 22 to 24, further comprising: determining a design of overlay and / or alignment marks based on the predicted metrology signals.

[0235] 26. A computer program product comprising a non-transitory computer readable medium having recorded thereon instructions, the instructions when executed by a computer implementing the method according to any one of aspects 1 to 25.

[0236] 27. A method for generating an etch model application for a metrology target design, the method comprising:

[0237] calibrating the etch model using experimental cross-sectional profile information from layers of a physical wafer generated based on the etch model;

[0238] predicting an etch depth profile of a layer of the modeled wafer based on the calibrated etch model; and

[0239] The predicted etch depth profile is used in rigorous coupled wave analysis (RCWA) to enhance the metrology target design.

[0240] 28. The method of clause 24, wherein predicting an etch depth profile of a layer of the modeled wafer based on the calibrated etch model comprises:

[0241] determining (i) a starting resist profile for said layer of said wafer and (ii) a resist trim etch profile;

[0242] determining a trimmed resist profile by simulating a trimming operation on the initial resist profile according to the resist trimming etch profile,

[0243] Based at least in part on the trimmed resist profile:

[0244] determining loading information for the trimmed resist profile, the loading information indicating a dependency of an etch rate of the trimmed resist profile on an amount and pattern of material being etched; and / or

[0245] determining flux information for the trimmed resist profile, the flux information indicating a dependence of the etch rate of the trimmed resist profile on the intensity and spread angle of radiation incident on the trimmed resist profile; and / or

[0246] determining redeposition information for the trimmed resist profile, the redeposition information indicating a dependence of the etch rate of the trimmed resist profile on an amount of material removed from the trimmed resist profile and redeposited back onto the trimmed resist profile; and

[0247] An output etch depth profile for the layer of the wafer is determined based on the loading information, the flux information and / or the redeposition information of the trimmed resist profile.

[0248] 29. The method of any of clauses 27 to 28, wherein enhancing the metrology target design comprises adjusting one or more dimensions and / or patterns of the metrology target design.

[0249] 30. The method of any one of aspects 27 to 29, wherein the experimental cross-sectional profile information comprises a visual or dimensional comparison between an electronic image of the layer of the physical wafer and a corresponding electronic depiction of the layer generated using the model.

[0250] 31. A computer program product comprising a non-transitory computer readable medium having recorded thereon instructions, the instructions when executed by a computer implementing the method according to any one of aspects 27 to 30.

[0251] 32. A method for calibrating an etch pattern application of a dual-size etch pattern for an optical proximity effect correction application, the method comprising:

[0252] calibrating the etch model using any combination of cross-sectional profiles of layers from simulated wafers produced based on the corresponding etch process, scanning electron microscopy, and scatterometry measurements;

[0253] predicting etch biases for a plurality of patterns in a layer of the modeled wafer based on the calibrated etch model; and

[0254] Use the predicted etch bias to calibrate photomasks, verify post-etch process windows, or co-optimize lithography sources and photomasks.

[0255] 33. A computer program product comprising a non-transitory computer readable medium having recorded thereon instructions, the instructions when executed by a computer implementing the method of clause 32.

[0256] 34. A method for calibrating an etch model application for predicting etch fingerprints across a wafer as input to a wafer inspection or patterning control operation, the method comprising:

[0257] calibrating the etch model using any combination of cross-wafer cross-sectional profiles of layers from simulated wafers generated based on the etch process, scanning electron microscopy, and scatterometry measurements with parameters describing cross-wafer variations of the corresponding etch process;

[0258] predicting etch biases for a plurality of patterns of a layer of the modeled wafer based on the calibrated etch model; and

[0259] Using the predicted etch bias as defect prediction for an inspection system or as input to a pattern fidelity control system improves patterning performance across the wafer.

[0260] 35. A computer program product comprising a non-transitory computer readable medium having recorded thereon instructions, the instructions when executed by a computer implementing the method of clause 30.

[0261] 36. A method according to aspects 1 to 25, wherein the post-development inspection profile includes three-dimensional information and random information about the features.

[0262] The concepts disclosed herein can simulate or model any general imaging system for imaging sub-wavelength features, and can be particularly applicable to emerging imaging technologies that can produce shorter and shorter wavelengths. Emerging technologies already in use include extreme ultraviolet (EUV), DUV lithography that can produce 193 nm wavelengths by using ArF lasers and even 157 nm wavelengths by using fluorine lasers. In addition, EUV lithography can produce wavelengths in the range of 20-5 nm by using a synchrotron or by firing high-energy electrons at a material (solid or plasma) to produce photons in this range.

[0263] Although the concepts disclosed herein may be used for imaging on substrates such as silicon wafers, it should be understood that the disclosed concepts may be used with any type of lithography imaging system, for example, a lithography imaging system for imaging on substrates other than silicon wafers.

[0264] The above description is intended to be illustrative rather than limiting. Accordingly, those skilled in the art will appreciate that modifications may be made as described without departing from the scope of the claims set forth hereinafter.

Claims

1. A method for determining an etch profile of a layer of a wafer for a simulation system, the method comprising: determining a shadow layer profile of a layer of the wafer, wherein the initial shadow layer profile is a profile inspected after development; Based at least in part on the occlusion layer profile: determining loading information for the masking layer profile, the loading information indicating a dependency of an etch rate for the masking layer profile on an amount and pattern of material being etched; and / or determining flux information for the shielding layer profile, the flux information indicating a dependence of the etch rate for the shielding layer profile on an intensity and a spread angle of radiation incident on the shielding layer profile; and / or determining redeposition information for the shielding layer profile, the redeposition information indicating a dependence of the etch rate for the shielding layer profile on an amount of material removed from the shielding layer profile and redeposited back onto the shielding layer profile; and Based on the loading information, the flux information and / or the redeposition information of the masking layer profile, an output etch profile for the layer of the wafer is determined.

2. The method according to claim 1, comprising: Operating parameters of the method are calibrated based on information from a metrology system for a corresponding layer of a simulated wafer, wherein the calibration further comprises adjusting wafer simulation parameters of the simulated wafer.

3. The method according to any one of claims 1 to 2, wherein: Determining the shielding layer profile of the layer of the wafer includes one or more of the following operations: obtaining dimensions of the shielding layer profile, designing dimensions of the shielding layer profile, or measuring dimensions of the shielding layer profile.

4. The method according to any one of claims 1 to 2, wherein: Determining the loading information includes determining a dependency of the etch rate at individual locations across the masking layer profile based on an amount and pattern of material being etched at the individual locations; Determining the flux information includes determining a dependency of the etch rate at the individual locations across the shielding layer profile based on an intensity and a spread angle of radiation incident on the shielding layer profile at the individual locations; as well as Determining the redeposition information includes determining a dependency of the etch rate at the individual locations across the masking layer profile based on an amount of material removed from the masking layer profile at the individual locations and redeposited back onto the masking layer profile at the individual locations.

5. The method according to claim 4, wherein: Determining the dependence of the etch rate at the individual locations across the masking layer profile includes determining individual load factors for the individual locations.

6. The method according to claim 5, wherein: The individual load factors are determined based on Boolean functions of the mask pattern at the individual locations.

7. The method according to claim 4, wherein: The flux information is determined based on one or more bias constants, one or more fitting constants, a short-range loading factor, and a long-range loading factor corresponding to the individual sites.

8. The method according to claim 4, wherein: The redeposition information is determined based on one or more bias constants, long-range fit factors, and long-range loading factors corresponding to individual sites.

9. The method according to any one of claims 1 to 2 and 5 to 8, wherein: The post-development inspected profile includes three-dimensional information and random information about the features.

10. A computer program product, comprising a non-transitory computer-readable medium having recorded thereon instructions, the instructions implementing the method according to any one of claims 1 to 9 when executed by a computer.

11. A method for generating an etch model application for a metrology target design, the method comprising: calibrating the etch model using experimental cross-sectional profile information from layers of a physical wafer generated based on the etch model; predicting an etch depth profile of a layer of the modeled wafer based on the calibrated etch model; as well as The predicted etch depth profile is used in rigorous coupled wave analysis (RCWA) to enhance the metrology target design.

12. The method according to claim 11, wherein: Predicting an etch depth profile of a layer of a modeled wafer based on a calibrated etch model includes: determining (i) a starting resist profile for said layer of said wafer and (ii) a resist trim etch profile; determining a trimmed resist profile by simulating a trimming operation on the initial resist profile according to the resist trimming etch profile, Based at least in part on the trimmed resist profile: determining loading information for the trimmed resist profile, the loading information indicating a dependency of an etch rate of the trimmed resist profile on an amount and pattern of material being etched; and / or determining flux information for the trimmed resist profile, the flux information indicating a dependence of the etch rate of the trimmed resist profile on the intensity and spread angle of radiation incident on the trimmed resist profile; and / or determining redeposition information for the trimmed resist profile, the redeposition information indicating a dependence of the etch rate of the trimmed resist profile on an amount of material removed from the trimmed resist profile and redeposited back onto the trimmed resist profile; and An output etch depth profile for the layer of the wafer is determined based on the loading information, the flux information and / or the redeposition information of the trimmed resist profile.

13. The method according to any one of claims 11 to 12, wherein: Enhancing the metrology target design includes adjusting one or more dimensions and / or patterns of the metrology target design.

14. The method according to any one of claims 11 to 12, wherein: The experimental cross-sectional profile information includes a visual or dimensional comparison between an electronic image of the layer of the physical wafer and a corresponding electronic depiction of the layer generated using the model.

15. A computer program product comprising a non-transitory computer-readable medium having recorded thereon instructions, the instructions implementing the method according to any one of claims 11 to 14 when executed by a computer.

16. A method for calibrating an etch pattern application of a dual-size etch pattern for an optical proximity effect correction application, the method comprising: calibrating the etch model using any combination of cross-sectional profiles of layers from simulated wafers produced based on the corresponding etch process, scanning electron microscopy, and scatterometry measurements; predicting etch biases for a plurality of patterns in a layer of the modeled wafer based on the calibrated etch model; as well as Use the predicted etch bias to calibrate photomasks, verify post-etch process windows, or co-optimize lithography sources and photomasks.

17. A computer program product comprising a non-transitory computer-readable medium having recorded thereon instructions, the instructions implementing the method according to claim 16 when executed by a computer.

18. A method for calibrating an etch model application for predicting etch fingerprints across a wafer as input to a wafer inspection or patterning control operation, the method comprising: calibrating the etch model using any combination of cross-wafer cross-sectional profiles of layers from simulated wafers generated based on the etch process, scanning electron microscopy, and scatterometry measurements with parameters describing cross-wafer variations of the corresponding etch process; predicting etch biases for a plurality of patterns of a layer of the modeled wafer based on the calibrated etch model; as well as Using the predicted etch bias as defect prediction for an inspection system or as input to a pattern fidelity control system improves patterning performance across the wafer.

19. A computer program product comprising a non-transitory computer-readable medium having recorded thereon instructions, the instructions implementing the method according to claim 18 when executed by a computer.

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