Power management circuit based on flip voltage follower

Abstract

The invention discloses a power supply management circuit based on a flip voltage follower, which comprises a voltage stabilizing circuit and a biasing circuit, can provide stable voltage with high-speed transient response characteristic, is used for supplying power to a core of a FLASH memory, and is characterized in that a common-gate amplifier is added on the basis of a traditional flip voltage follower structure; a resistive load is used for replacing a current source load, so that the current driving capability and the current discharging capability of an output node are improved on the premise of not influencing the loop gain, and the slew rate is increased; the bias circuit is characterized in that a transient enhancement adjusting module is added, when the output voltage fluctuates and is coupled to the bias voltage, the bias voltage can be rapidly adjusted and stabilized, and the transient response capability of the output voltage is further improved. According to the invention, stable voltage with a high-speed transient response characteristic can be provided when the memory is subjected to read-write operation, and the read-write stability of the memory is improved.

Description

Technical Field

[0001] The invention relates to a power management circuit based on a flip voltage follower, belonging to the technical field of analog power supply. Background Art

[0002] In general voltage stabilization circuits, low dropout linear regulator (LDO) structures are often used. They have the advantages of simple circuit structure, low load regulation rate and linear regulation rate, and are suitable for scenarios with small load fluctuations and low requirements for large signal response time. However, in certain specific applications, such as when the FLASH memory is read and written, the load current fluctuates greatly, and the reading time is usually in the order of nanoseconds. A voltage stabilization circuit with high-speed transient response characteristics is required to provide a stable voltage for the FLASH. The traditional LDO structure is limited by power supply voltage and power, and cannot meet the requirements of high slew rate. At the same time, the traditional flip voltage follower has the characteristics of strong current driving capability, high conversion rate, and large slew rate, but poor current discharge capability.

[0003] Therefore, it is necessary to design a voltage-stabilizing circuit with strong load capacity, high-speed transient response characteristics and high stability. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a power management circuit based on a flip voltage follower, including a bias circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is based on the flip voltage follower and improves the loop gain and reduces the load response time through design optimization, while improving the current driving and current discharge capabilities. The bias circuit adopts transient enhancement regulation technology to realize the bias voltage auxiliary regulation function, further improve the transient response characteristics of the overall circuit, and ensure the rapid response and stability of the circuit output voltage.

[0005] The technical solution of the present invention is: a power management circuit based on a flip voltage follower, including: a bias circuit and a voltage stabilizing circuit, specifically:

[0006] The bias circuit is used to generate a bias voltage and provide it to the voltage stabilizing circuit, so that the voltage stabilizing circuit operates at a suitable DC operating point;

[0007] The voltage stabilizing circuit is a flip voltage follower structure, which relies on a feedback loop to output a stable voltage and serves as a power supply module to provide a stable voltage to an external circuit.

[0008] Preferably, the bias circuit includes: a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3 and a fourth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3, resistors R1, R2, R3 and R4, an error amplifier G1, and a current source;

[0009] Among them, the source of the first NMOS tube N1 is grounded; the drain of the first NMOS tube N1, the gate of the second NMOS tube N2, and the gate of the third NMOS tube N3 are connected together, and the connection node is recorded as the first output node, outputting the first bias voltage V1, and connected to the external power supply VDD through the current source; the gate of the first NMOS tube N1 and the source of the second NMOS tube N2 are grounded through the resistor R1; the drain of the second NMOS tube, the drain of the first PMOS tube P1, the gate of the first PMOS tube P1, and the gate of the second PMOS tube P2 are connected together, and the connection node is recorded as the second output node, outputting the second bias voltage V2; the source of the first PMOS tube P1, the source of the second PMOS tube P2, and the source of the third PMOS tube P3 are connected to the external power supply VDD; the drain of the second PMOS tube P2, the drain of the third NMOS tube N3, and the gate of the third PMOS tube P3 are connected together, and the connection node is recorded as the first node; the source of the third NMOS tube N3 and the drain of the fourth PMOS tube P4 are grounded through the resistor R2; the drain of the third PMOS tube P3 and the source of the fourth PMOS tube P4 are grounded after passing through the resistor R3 and the resistor R4 in sequence; the connection point of the resistor R3 and the resistor R4 is recorded as the second node, the second node is connected to the negative input terminal of the error amplifier G1, the reference voltage Vref is connected to the positive input terminal of the error amplifier G1, the output terminal of the error amplifier and the gate of the fourth PMOS tube P4 are connected together, and the connection node is recorded as the third output node, and the third bias voltage V3 is output.

[0010] Preferably, the voltage stabilizing circuit includes: a fifth PMOS tube P5 and a sixth PMOS tube P6, a fourth NMOS tube N4 and a fifth NMOS tube N5, resistors R5 and R6, and a capacitor C1;

[0011] Among them, the gate of the fourth NMOS tube N4 is connected to the first output node to obtain the first bias voltage V1; the source of the fourth NMOS tube N4 and the source of the fifth NMOS tube N5 are both grounded through the resistor R6; the drain of the fourth NMOS tube N4, the drain of the fifth PMOS tube P5, and the gate of the sixth PMOS tube P6 are connected to a common node, which is recorded as the third node. The third node is connected to the capacitor C1 and the resistor R5 in sequence and then connected to the voltage regulation output node; the gate of the fifth PMOS tube P5 is connected to the second output node to obtain the second bias voltage V2; the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are both connected to the external power supply VDD; the gate of the fifth NMOS tube N5 is connected to the third output node to obtain the third bias voltage V3; the drain of the fifth NMOS tube N5 and the drain of the sixth PMOS tube P6 are respectively connected to the voltage regulation output node to generate the final regulated output voltage Vout, that is, the stable output voltage.

[0012] Preferably, the bias circuit can be divided into a feedback loop and a transient enhancement regulation module:

[0013] The feedback loop includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a resistor R1 and a current source;

[0014] The transient enhancement regulation module includes: a second PMOS transistor P2, a third NMOS transistor N3, a resistor R2, a third PMOS transistor P3, a fourth PMOS transistor P4, a resistor R3, a resistor R4 and an error amplifier G1.

[0015] Preferably, the feedback loop generates a first bias voltage V1 and a second bias voltage V2, and the values ​​of the first bias voltage and the second bias voltage V2 are controlled by setting the current source, the size of the MOS tube and the resistance value.

[0016] Preferably, the transient enhancement regulation module generates a third bias voltage V3, whose value is controlled by setting the error amplifier G1 and the reference voltage Vref in the transient enhancement regulation module, wherein the reference voltage Vref determines the DC operating point of the error amplifier G1, and further determines the third bias voltage V3.

[0017] Preferably, the fifth PMOS tube P5 and the fourth NMOS tube N4 in the voltage stabilizing circuit constitute a common-gate amplifier, the sixth PMOS tube P6, the fifth NMOS tube N5 and the resistor R6 constitute a flip voltage follower, and the two parts are combined into a negative feedback closed loop; when the final regulated output voltage Vout fluctuates, the negative feedback closed loop can quickly adjust it and output a stable bias voltage.

[0018] Preferably, when the final regulated output voltage Vout increases, the source voltage of the fourth NMOS tube N4 increases accordingly, resulting in an increase in the drain voltage of the fourth NMOS tube N4, thereby increasing the gate voltage of the sixth PMOS tube P6, and reducing the saturation current provided by the sixth PMOS tube P6. The voltage regulation output node also discharges through the load resistor R6, thereby increasing the voltage drop speed of Vout and ultimately reducing Vout.

[0019] Preferably, when the final regulated output voltage Vout decreases, the source voltage of the fourth NMOS tube N4 decreases accordingly, resulting in a decrease in the drain voltage of the fourth NMOS tube N4, thereby reducing the gate voltage of the sixth PMOS tube P6, increasing the saturation current provided by the sixth PMOS tube P6, and charging the voltage regulation output node through the sixth PMOS tube P6;

[0020] The sixth PMOS tube P6 is a large-size power tube, and its width-to-length ratio is 5000-6000.

[0021] Preferably, all MOS tubes used in the circuit are enhancement type MOS tubes.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] (1) The present invention designs a voltage stabilizing circuit based on a flip voltage follower and its bias circuit, and replaces the traditional current source load of the flip voltage follower with a resistor load R6, thereby improving the current discharge capability of the output node. Because if a current source load is used, the pull-down current is constant, and the discharge current is limited by the current source, resulting in slow discharge, which affects the transient response time. After using the resistor load R6, the discharge current is determined by the output voltage and the resistor R6, which can increase and maintain a relatively large current discharge speed within a certain range, thereby improving the transient response capability.

[0024] (2) After the present invention uses resistor R6 to replace the current source load, the current discharge speed problem is solved, but the loop gain of the flip voltage follower is reduced, which in turn affects the load regulation rate and linear regulation rate of the loop. In order to compensate for the loop gain, a first-stage common-gate amplifier is added to increase the loop gain and reduce the output impedance.

[0025] (3) The sixth PMOS transistor P6 in the voltage stabilizing circuit is a power transistor with a relatively large size, so the parasitic capacitance from the output node to the gate of the sixth PMOS transistor P6 is relatively large; the fifth NMOS transistor N5 is an input transistor of the flip voltage follower, and its size is relatively small compared to the power transistor, so the parasitic capacitance from the output node to the gate of the fifth NMOS transistor N5 is relatively small. When the output voltage Vout changes due to the influence of the load, it will be coupled to the gate of the fifth NMOS transistor N5 through the parasitic capacitance, causing the bias voltage V3 to change, affecting the DC operating point of the loop, and causing the output voltage Vout to deviate significantly. In order to solve this problem, the present invention adds a transient enhancement regulation module to the bias circuit, and uses the transient enhancement regulation module to maintain the stability of the V3 voltage to ensure that the voltage stabilizing circuit operates under the correct DC conditions, and further improves the transient regulation ability and stability of the voltage stabilizing module.

[0026] (4) The bias circuit with transient enhancement regulation module and the improved flip voltage follower voltage regulator circuit work together to achieve the voltage regulator circuit with strong load capacity, high-speed transient response characteristics and high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural diagram of a bias circuit with a transient enhancement regulation module of the present invention;

[0028] Figure 2 This is a structural diagram of the improved flip voltage follower voltage stabilizing circuit of the present invention. DETAILED DESCRIPTION

[0029] The present invention provides a power management circuit based on a flip voltage follower, comprising: a bias circuit and a voltage stabilizing circuit; specifically:

[0030] The bias voltage generating circuit generates three bias voltages V1, V2 and V3, wherein the bias voltages V1 and V2 are generated by a feedback loop composed of the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the resistor R1 and the current source, and the bias voltage V3 is generated by the transient enhancement regulation module. When the voltage V3 fluctuates, the gate voltage of the fourth PMOS tube P4 changes accordingly, causing the source voltage of the fourth PMOS tube P4 to change. After the voltage is divided by the resistors R3 and R4, the second node voltage changes, and the second node is connected to the negative input terminal of the error amplifier G1, thereby changing the bias voltage V3, and realizing rapid adjustment and control of the bias voltage V3. Output stable bias voltage; the voltage stabilizing circuit consists of two parts, the fifth PMOS tube P5 and the fourth NMOS tube N4 constitute a common-gate amplifier, the sixth PMOS tube P6, the fifth NMOS tube N5 and the resistor R6 constitute a flip voltage follower, and the two parts are combined into a negative feedback closed loop. When the output voltage Vout fluctuates, the source voltage of the fourth NMOS tube N4 changes accordingly (the input end of the common-gate amplifier), causing the drain voltage of the fourth NMOS tube N4 to change (the output end of the common-gate amplifier), thereby affecting the gate voltage of the sixth PMOS tube P6, and finally adjusting the output voltage Vout, realizing rapid adjustment of the output voltage Vout and outputting a stable bias voltage.

[0031] Specific:

[0032] The bias circuit includes: a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3 and a fourth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3, resistors R1, R2, R3 and R4, an error amplifier G1, and a current source;

[0033] Among them, the source of the first NMOS tube N1 is grounded; the drain of the first NMOS tube N1, the gate of the second NMOS tube N2, and the gate of the third NMOS tube N3 are connected together, and the connection node is denoted as the first output node, outputting the first bias voltage V1, and connected to the external power supply VDD through the current source; the gate of the first NMOS tube N1 and the source of the second NMOS tube N2 are connected to the ground through the resistor R1; the drain of the second NMOS tube, the drain of the first PMOS tube P1, the gate of the first PMOS tube P1, and the gate of the second PMOS tube P2 are connected together, and the connection node is denoted as the second output node, outputting the second bias voltage V2; the source of the first PMOS tube P1, the source of the second PMOS tube P2, and the source of the third PMOS tube P3 are connected connected to an external power supply VDD; the drain of the second PMOS tube P2, the drain of the third NMOS tube N3, and the gate of the third PMOS tube P3 are connected together, and the connection node is recorded as the first node; the source of the third NMOS tube N3 and the drain of the fourth PMOS tube P4 are connected to the ground through the resistor R2; the drain of the third PMOS tube P3 and the source of the fourth PMOS tube P4 are connected to the ground through the resistors R3 and R4 in sequence; the connection point of the resistor R3 and the resistor R4 is recorded as the second node, the second node is connected to the negative input terminal of the error amplifier G1, the reference voltage Vref is connected to the positive input terminal of the error amplifier G1, the output terminal of the error amplifier and the gate of the fourth PMOS tube P4 are connected together, and the connection node is recorded as the third output node, and the third bias voltage V3 is output.

[0034] The error amplifier G1 is used to quickly adjust the voltage fluctuation of the output node V3 to improve the transient response characteristics and stability of the output bias voltage.

[0035] The voltage stabilizing circuit includes: a fifth PMOS tube P5 and a sixth PMOS tube P6, a fourth NMOS tube N4 and a fifth NMOS tube N5, resistors R5 and R6, and a capacitor C1;

[0036] Among them, the gate of the fourth NMOS tube N4 is connected to the first output node to obtain the first bias voltage V1; the source of the fourth NMOS tube N4 and the source of the fifth NMOS tube N5 are connected to the ground through the resistor R6; the drain of the fourth NMOS tube N4, the drain of the fifth PMOS tube P5, and the gate of the sixth PMOS tube P6 are connected to a common node, which is recorded as the third node. The third node is connected to the capacitor C1 and the resistor R5 in series and then connected to the voltage regulation output node; the gate of the fifth PMOS tube P5 is connected to the second output node to obtain the second bias voltage V2; the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are both connected to the external power supply VDD; the gate of the fifth NMOS tube N5 is connected to the third output node to obtain the third bias voltage V3; the drain of the fifth NMOS tube N5 and the drain of the sixth PMOS tube P6 are respectively connected to the voltage regulation output node to generate the final regulated output voltage Vout, that is, the stable output voltage.

[0037] The three output node voltages of the bias circuit are all adjusted to a normal working state through self-feedback, and their values ​​are controlled by setting the current source, MOS tube size and resistance value.

[0038] The three input voltages of the voltage regulator circuit are all provided by the three output node voltages generated by the bias voltage. The output node voltage is adjusted to a normal working state through its own feedback, and its value is controlled by setting the bias voltage and the size of the MOS tube.

[0039] The structure diagram of a bias circuit with a transient enhancement adjustment module of the present invention is shown in FIG. Figure 1 As shown, it includes a feedback loop composed of a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a resistor R1 and a current source, and a transient enhancement regulation module.

[0040] The working principle is as follows:

[0041] The bias voltages V1 and V2 are generated by a feedback loop, and their values ​​are controlled by setting the current source, the size of the MOS tube and the resistance value; specifically: after the current of the branch where the current source is located is determined, the gate-source voltage Vgs1 of the first NMOS tube N1 can be determined by adjusting the size of the first NMOS tube N1; after Vgs1 is determined, the current of the branch where the second NMOS tube N2 is located is determined by adjusting the resistance value of the resistor R1; after the branch current is determined, the gate-source voltage Vgs2 of the second NMOS tube N2 is determined by adjusting the size of the second NMOS tube N2; the first bias voltage V1 is the sum of the gate-source voltage Vgs1 of the first NMOS tube N1 and the gate-source voltage Vgs2 of the second NMOS tube N2, and the first bias voltage V1 is determined; the first PMOS tube P1 is a diode connection mode, and is in the same branch with the second NMOS tube N2, and the current of this branch has been determined, and the second bias voltage V2 can be determined by adjusting the size of the first PMOS tube P1.

[0042] The bias voltage V3 is generated by the transient enhancement regulation module, and the reference voltage Vref and the error amplifier G1 determine the bias voltage V3. When the final regulated output voltage Vout is affected by the load and voltage fluctuation occurs, this voltage fluctuation will be coupled to the bias voltage V3 through the gate capacitance of the fifth NMOS tube N5, causing voltage fluctuation in the bias voltage V3. When the voltage of V3 increases, the gate voltage of the fourth PMOS tube P4 increases, causing the conduction capability of the fourth PMOS tube P4 to deteriorate, the current through it decreases, and then the saturation current of the third PMOS tube P3 gradually flows to the R3 and R4 branches, causing the voltage of the second node to increase, the voltage of the negative input terminal of the error amplifier G1 to increase, and the output voltage of the error amplifier G1 to decrease, which eventually causes the voltage of V3 to decrease, forming a feedback loop; when the voltage of V3 decreases, the gate voltage of the fourth PMOS tube P4 decreases, causing the conduction capability of the fourth PMOS tube P4 to increase, the current through it increases, and then the saturation current of the third PMOS tube P3 gradually flows to the fourth PMOS tube P4 branch, the current of the R3 and R4 branches gradually decreases, causing the voltage of the second node to decrease, the voltage of the negative input terminal of the error amplifier G1 to decrease, and the output voltage of the error amplifier G1 to increase, which eventually causes the voltage of V3 to increase. In this loop, the third PMOS tube P3 and the fourth PMOS tube P4 are larger in size to provide a larger slew rate to ensure that the large signal transient response time of V3 is small enough. The width-to-length ratio of the third PMOS transistor P3 and the fourth PMOS transistor P4 is 600-700.

[0043] like Figure 2 As shown, it is a structural diagram of an improved flip voltage follower voltage stabilizing circuit of the present invention, including a common gate amplifier composed of a fifth PMOS tube P5 and a fourth NMOS tube N4, and a flip voltage follower composed of a sixth PMOS tube P6, a fifth NMOS tube N5 and a resistor R6, and the two parts are combined into a negative feedback closed loop.

[0044] The working principle is as follows:

[0045] When the final regulated output voltage Vout increases, the source voltage of the fourth NMOS tube N4 increases accordingly (common-gate amplifier input end), causing the drain voltage of the fourth NMOS tube N4 to increase (common-gate amplifier output end), thereby increasing the gate voltage of the sixth PMOS tube P6, and reducing the saturation current provided by the sixth PMOS tube P6. The voltage regulation output node also discharges through the load resistor R6, thereby increasing the voltage drop speed of Vout, and finally reducing the output voltage Vout.

[0046] When the final regulated output voltage Vout decreases, the source voltage of the fourth NMOS tube N4 decreases accordingly (common-gate amplifier input end), resulting in a decrease in the drain voltage of the fourth NMOS tube N4 (common-gate amplifier output end), thereby reducing the gate voltage of the sixth PMOS tube P6, and increasing the saturation current provided by the sixth PMOS tube P6. The voltage regulated output node is charged through the sixth PMOS tube P6. This PMOS tube is a large-size power tube with a width-to-length ratio of 5000 to 6000, which further increases the voltage charging speed of the output node, and finally increases the output voltage Vout.

[0047] The MOS tubes used in the present invention are all enhancement type MOS tubes.

[0048] The present invention can provide a stable voltage with high-speed transient response characteristics for powering the FLASH memory core. The voltage stabilization circuit is characterized by adding a common-gate amplifier on the basis of a traditional flip voltage follower structure, and by using a resistive load instead of a current source load, the current driving capability and current discharge capability of the output node are improved without affecting the loop gain, so as to increase the slew rate; the bias circuit is characterized by adding a transient enhancement adjustment module, and when the output voltage fluctuates and couples to the bias voltage, the bias voltage can be quickly adjusted and stabilized, further improving the transient response capability of the output voltage. The present invention can ensure that when the memory performs read and write operations, a stable voltage with high-speed transient response characteristics is provided, thereby improving the read and write stability of the memory.

[0049] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. A power management circuit based on a flip voltage follower, characterized in that include: Bias circuit, voltage regulator circuit, specifically: The bias circuit is used to generate a bias voltage and provide it to the voltage stabilizing circuit, so that the voltage stabilizing circuit operates at a suitable DC operating point; The voltage stabilizing circuit is a flip voltage follower structure, which relies on a feedback loop to output a stable voltage and serves as a power supply module to provide a stable voltage to an external circuit.

2. The power management circuit based on a flip voltage follower according to claim 1, characterized in that: The bias circuit includes: a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3 and a fourth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3, resistors R1, R2, R3 and R4, an error amplifier G1, and a current source; Among them, the source of the first NMOS tube N1 is grounded; the drain of the first NMOS tube N1, the gate of the second NMOS tube N2, and the gate of the third NMOS tube N3 are connected together, and the connection node is recorded as the first output node, outputting the first bias voltage V1, and connected to the external power supply VDD through the current source; the gate of the first NMOS tube N1 and the source of the second NMOS tube N2 are grounded through the resistor R1; the drain of the second NMOS tube, the drain of the first PMOS tube P1, the gate of the first PMOS tube P1, and the gate of the second PMOS tube P2 are connected together, and the connection node is recorded as the second output node, outputting the second bias voltage V2; the source of the first PMOS tube P1, the source of the second PMOS tube P2, and the source of the third PMOS tube P3 are connected to the external power supply VDD; the drain of the second PMOS tube P2, the drain of the third NMOS tube N3, and the gate of the third PMOS tube P3 are connected together, and the connection node is recorded as the first node; the source of the third NMOS tube N3 and the drain of the fourth PMOS tube P4 are grounded through the resistor R2; the drain of the third PMOS tube P3 and the source of the fourth PMOS tube P4 are grounded after passing through the resistor R3 and the resistor R4 in sequence; the connection point of the resistor R3 and the resistor R4 is recorded as the second node, the second node is connected to the negative input terminal of the error amplifier G1, the reference voltage Vref is connected to the positive input terminal of the error amplifier G1, the output terminal of the error amplifier and the gate of the fourth PMOS tube P4 are connected together, and the connection node is recorded as the third output node, and the third bias voltage V3 is output.

3. The power management circuit based on a flip voltage follower according to claim 2, characterized in that: The voltage stabilizing circuit includes: a fifth PMOS transistor P5 and a sixth PMOS transistor P6, a fourth NMOS transistor N4 and a fifth NMOS transistor N5, resistors R5 and R6, and a capacitor C1; Among them, the gate of the fourth NMOS tube N4 is connected to the first output node to obtain the first bias voltage V1; the source of the fourth NMOS tube N4 and the source of the fifth NMOS tube N5 are both grounded through the resistor R6; the drain of the fourth NMOS tube N4, the drain of the fifth PMOS tube P5, and the gate of the sixth PMOS tube P6 are connected to a common node, which is recorded as the third node. The third node is connected to the capacitor C1 and the resistor R5 in sequence and then connected to the voltage regulation output node; the gate of the fifth PMOS tube P5 is connected to the second output node to obtain the second bias voltage V2; the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are both connected to the external power supply VDD; the gate of the fifth NMOS tube N5 is connected to the third output node to obtain the third bias voltage V3; the drain of the fifth NMOS tube N5 and the drain of the sixth PMOS tube P6 are respectively connected to the voltage regulation output node to generate the final regulated output voltage Vout, that is, the stable output voltage.

4. The power management circuit based on a flip voltage follower according to claim 2, characterized in that: The bias circuit can be divided into a feedback loop and a transient enhancement regulation module: The feedback loop includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a resistor R1 and a current source; The transient enhancement regulation module includes: a second PMOS transistor P2, a third NMOS transistor N3, a resistor R2, a third PMOS transistor P3, a fourth PMOS transistor P4, a resistor R3, a resistor R4 and an error amplifier G1.

5. The power management circuit based on a flip voltage follower according to claim 4, characterized in that: The feedback loop generates a first bias voltage V1 and a second bias voltage V2, the values ​​of which are controlled by setting the current source, the size of the MOS tube and the resistance value.

6. The power management circuit based on a flip voltage follower according to claim 4, characterized in that: The transient enhancement regulation module generates a third bias voltage V3, whose value is controlled by setting the error amplifier G1 and the reference voltage Vref in the transient enhancement regulation module, wherein the reference voltage Vref determines the DC operating point of the error amplifier G1, and further determines the third bias voltage V3.

7. The power management circuit based on a flip voltage follower according to claim 1, characterized in that: The fifth PMOS tube P5 and the fourth NMOS tube N4 in the voltage stabilizing circuit form a common-gate amplifier, the sixth PMOS tube P6, the fifth NMOS tube N5 and the resistor R6 form a flip voltage follower, and the two parts are combined into a negative feedback closed loop; when the final regulated output voltage Vout fluctuates, the negative feedback closed loop can quickly adjust it and output a stable bias voltage.

8. The power management circuit based on a flip voltage follower according to claim 7, characterized in that: When the final regulated output voltage Vout increases, the source voltage of the fourth NMOS tube N4 increases accordingly, resulting in an increase in the drain voltage of the fourth NMOS tube N4, thereby increasing the gate voltage of the sixth PMOS tube P6, and reducing the saturation current provided by the sixth PMOS tube P6. The voltage regulation output node also discharges through the load resistor R6, thereby increasing the voltage drop speed of Vout and finally reducing Vout.

9. The power management circuit based on a flip voltage follower according to claim 7, characterized in that: When the final regulated output voltage Vout decreases, the source voltage of the fourth NMOS tube N4 decreases accordingly, causing the drain voltage of the fourth NMOS tube N4 to decrease, thereby reducing the gate voltage of the sixth PMOS tube P6, increasing the saturation current provided by the sixth PMOS tube P6, and charging the voltage regulation output node through the sixth PMOS tube P6; The sixth PMOS tube P6 is a large-size power tube, and its width-to-length ratio is 5000-6000.

10. The power management circuit based on a flip voltage follower according to claim 1, characterized in that: All MOS tubes used in the circuit are enhancement type MOS tubes.

Images