Abnormality positioning method, device, equipment, readable storage medium and program product

Abstract

The application provides an abnormality positioning method, device, equipment, readable storage medium and program product, which are applied to the technical field of computers, and the method comprises the following steps: in the case that a transaction execution exception exists in a multi-chip system, acquiring information records of at least one processing unit in each chip; each processing unit is used for receiving and sending information to execute the transaction; the information received by each processing unit from other processing units and the information sent by each processing unit to other processing units are stored in the respective information records; and based on the information records of the at least one processing unit in each chip, an abnormal processing unit causing the transaction execution exception is determined. The application can improve the accuracy of abnormality positioning.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an anomaly location method, apparatus, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] Large-scale integrated circuits are typically complex systems composed of interconnected chips. Transaction processing in complex systems involves information exchange between multiple chips. When an exception occurs during transaction execution, it is necessary to identify the location of the exception in order to optimize and debug it.

[0003] Currently, embedded logic analyzers are used to capture logic state signals and then analyze the cause of the problem.

[0004] However, with current solutions, embedded logic analyzers are difficult to deploy fully in complex systems, and they cannot accurately locate anomalies, resulting in insufficient accuracy in anomaly localization. Summary of the Invention

[0005] This application provides an anomaly location method, apparatus, electronic device, computer-readable storage medium, and computer program product to solve the problem of insufficient accuracy in anomaly location in the prior art.

[0006] In a first aspect, embodiments of this application provide an anomaly localization method, the method comprising:

[0007] In the event of a transaction execution exception in a multi-chip system, the information records of at least one processing unit in each chip are obtained; each processing unit is used to receive and send information to execute the transaction; the information received by each processing unit from other processing units and the information sent to other processing units are stored in its respective information record;

[0008] Based on the information records of at least one processing unit in each chip, the exception handling unit that caused the transaction execution error is determined.

[0009] Secondly, embodiments of this application provide an anomaly location device, the device comprising:

[0010] The information recording module is used to obtain the information records of at least one processing unit in each chip in the event of a transaction execution exception in a multi-chip system; each processing unit is used to receive and send information to execute the transaction; the information received by each processing unit from other processing units and the information sent to other processing units are stored in its respective information record.

[0011] An exception determination module is used to determine the exception handling unit that caused the transaction execution exception based on the information records of at least one processing unit in each chip.

[0012] Thirdly, embodiments of this application provide an electronic device, including: a processor, a communication interface, a memory, and a communication bus; wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0013] Memory, used to store computer programs;

[0014] When a processor executes a program stored in memory, it implements the steps in the exception location method described in the first aspect above.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the anomaly localization method described in the first aspect.

[0016] Fifthly, embodiments of this application provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps in the anomaly localization method described in the first aspect.

[0017] Compared with prior art, this application has the following advantages:

[0018] In this embodiment, when a transaction execution exception occurs in a multi-chip system, information records of at least one processing unit in each chip are obtained. Each processing unit is used to receive and send information to execute transactions. Information received by each processing unit from other processing units and information sent to other processing units are stored in its respective information record. Based on the information records of at least one processing unit, the exception handling unit that caused the transaction execution exception is determined. This allows for a complete record of the information interaction process of each processing unit, and thus, based on the information records of each processing unit, the exception handling unit that caused the transaction execution exception can be determined, improving the accuracy of exception localization.

[0019] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0021] Figure 1 A flowchart illustrating the steps of an anomaly localization method provided in an embodiment of this application;

[0022] Figure 2 A schematic diagram of the internal structure of the chip provided in the embodiments of this application;

[0023] Figure 3 This is a schematic diagram of a multi-chip interconnect structure provided in an embodiment of this application;

[0024] Figure 4 A schematic diagram illustrating the internal chip interactions provided in an embodiment of this application;

[0025] Figure 5 A step diagram illustrating another anomaly localization method provided in this application embodiment;

[0026] Figure 6 A schematic diagram of an anomaly location device provided in an embodiment of this application;

[0027] Figure 7 A block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0028] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0029] With the development of large-scale integrated circuit technology, the logic scale of chips continues to increase, which brings challenges to the prototype verification of field programmable gate arrays (FPGAs). FPGA prototype verification is characterized by long preparation time, high verification efficiency, and slow problem analysis and localization. Efficiently analyzing and localizing abnormal problems in the prototype verification process has become an important factor affecting the progress of chip development.

[0030] For complex, large-scale interconnect chip systems, the use of embedded logic analyzers has limitations. First, in multi-chip scenarios, embedded logic analyzers need to be deployed on each chip separately, which is inconvenient and has low accuracy. Second, FPGA bit stream updates and iterations are slow, and a modification and resynthesis usually takes seven or eight hours. If the accuracy of anomaly localization is not high, it will take a long time to complete the analysis of the problem. Using existing technical solutions to analyze and locate a problem greatly reduces the efficiency of prototype verification.

[0031] Figure 1 This is a flowchart illustrating the steps of an anomaly localization method provided in an embodiment of this application. The method includes:

[0032] Step 101: In the event of a transaction execution exception in a multi-chip system, obtain the information records of at least one processing unit in each chip; each processing unit is used to receive and send information to execute the transaction; the information received by each processing unit from other processing units and the information sent to other processing units are stored in its respective information record.

[0033] In the embodiments of this application, the executing entity of the method steps can be a functional module in a multi-chip complex system, and the transaction can be related to computation, data storage, control, and management. The execution of the transaction requires interaction between various chips in the complex system, and each chip also includes multiple processing units, such as client agent units and host agent units, for transaction proxying.

[0034] Figure 2 This is a schematic diagram of the internal structure of the chip provided in the embodiments of this application; Figure 2 It includes multiple first interface modules 201, a message distribution module 202, multiple protocol processing modules 203, a switching interconnection module 204, and multiple second interface modules 205. The first interface modules 201 and the second interface modules 205 are used to connect different objects.

[0035] Figure 3 This is a schematic diagram of the multi-chip interconnect structure provided in the embodiments of this application; Figure 3 It includes multiple interconnect chips 301, each of which can communicate with other interconnect chips 301.

[0036] Each processing unit in the chip can receive and send information, allowing it to send information to and receive information from other processing units. Information received from and sent by each processing unit to other processing units is stored in its own information record. In case of an exception, at least one processing unit's information record is retrieved. It is understood that the storage of information records can be performed by each processing unit individually, or by other functional modules; no restriction is placed here.

[0037] Figure 4 This is a schematic diagram of the internal chip interaction provided in the embodiments of this application;

[0038] Step 401: The first processing unit sends first information to the second processing unit;

[0039] Step 402: The second processing unit sends the second information to the third processing unit;

[0040] Step 403: The third processing unit sends third information to the second processing unit;

[0041] Step 404: The second processing unit sends the fourth information to the first processing unit;

[0042] Understandable Figure 4 The information interaction process shown is only illustrative and is used to illustrate the information sending and receiving process between processing units.

[0043] Step 102: Based on the information records of at least one processing unit in each chip, determine the exception handling unit that caused the transaction execution error.

[0044] In this embodiment, it is possible to check whether there is missing information in the information records of each processing unit. For example, if processing unit A sends information to processing unit B, and processing unit A's information record contains a related information sending record, but processing unit B's information record does not contain a related information receiving record, then processing unit B can be identified as the exception handling unit that caused the transaction execution error. Alternatively, each processing unit can have its own information verification data. By comparing the processing unit's information record with the information verification data, anomaly localization can be performed when discrepancies exist. There are no specific limitations on how to determine the exception handling unit based on information records.

[0045] In summary, in this embodiment, when a transaction execution exception occurs in a multi-chip system, the information records of at least one processing unit in each chip are obtained. Each processing unit is used to receive and send information to execute transactions. Information received by each processing unit from other processing units and information sent to other processing units are stored in its respective information record. Based on the information records of at least one processing unit, the exception handling unit causing the transaction execution exception is determined. This allows for a complete record of the information interaction process of each processing unit, and thus, based on the information records of each processing unit, the exception handling unit causing the transaction execution exception can be determined, improving the accuracy of exception localization.

[0046] Figure 5 This is a flowchart illustrating another anomaly localization method provided in this application.

[0047] Step 501: In the event of a transaction execution exception in the multi-chip system, obtain the information record of at least one processing unit in each chip; each processing unit is used to receive and send information to execute the transaction; the information received by each processing unit from other processing units and the information sent to other processing units are stored in its respective information record.

[0048] Step 502: Based on the information records of at least one processing unit in each chip, determine the exception handling unit that caused the transaction execution error.

[0049] For details of steps 501-502, please refer to the above. Figure 1 The details of the embodiments will not be repeated here.

[0050] Optionally, there are multiple transactions; the step of determining the exception handling unit that caused the transaction execution error based on the information records of at least one processing unit in each chip includes:

[0051] In the event of multiple transactions encountering exceptions, the time of exception for each transaction should be determined.

[0052] Based on the time points of multiple abnormal times, the multiple transactions are sorted to determine the transaction sequence;

[0053] Based on the information records of at least one processing unit in each chip, the exception handling unit corresponding to each transaction in the transaction sequence is determined one by one.

[0054] In this embodiment of the application, there may be multiple transactions to be executed, and each transaction may encounter an exception. In the event that multiple transactions encounter exceptions, the exception time of each transaction is determined.

[0055] Based on the specific time points of multiple abnormal events, multiple transactions are sorted, for example, by time points from morning to evening, in order to determine the transaction sequence.

[0056] Then, based on the order of the transaction sequence, the exception handling unit corresponding to each transaction is determined one by one.

[0057] The embodiments of this application determine the exception time for each transaction when multiple transactions encounter exceptions; sort the multiple transactions according to the time points of the multiple exception times to determine a transaction sequence; and determine the exception handling unit corresponding to each transaction in the transaction sequence based on the information records of at least one processing unit. This enables the orderly processing of multiple abnormal transactions based on the time of exception occurrence, and the determination of exception handling units one by one, thus improving the orderliness of exception handling.

[0058] Optionally, there are multiple transactions; the step of determining the exception handling unit that caused the transaction execution error based on the information records of at least one processing unit in each chip includes:

[0059] In the event of multiple transactions encountering exceptions, determine the exception type for each transaction.

[0060] Based on the number of transactions for each exception type, multiple transactions are sorted to determine the transaction sequence;

[0061] Based on the information records of at least one processing unit in each chip, the exception handling unit corresponding to each transaction in the transaction sequence is determined one by one.

[0062] In this embodiment of the application, when multiple transactions encounter anomalies, the anomaly type for each transaction is determined. The anomaly type can indicate the reason for the transaction anomaly, such as a chip malfunction, a complex system composed of chips crashing, or an abnormal restart.

[0063] Based on the number of transactions for each exception type, multiple transactions are sorted. For example, transactions corresponding to the exception type with the most transactions can be arranged first, and transactions corresponding to the exception type with the fewest transactions can be arranged last, in order to determine the transaction sequence.

[0064] Then, based on the information records of at least one processing unit, the exception handling unit corresponding to each transaction in the transaction sequence is determined one by one.

[0065] In embodiments of this application, when multiple transactions experience anomalies, the anomaly type of each transaction is determined; the multiple transactions are sorted according to the number of transactions of each anomaly type to determine a transaction sequence; and based on the information records of at least one processing unit, the anomaly handling unit corresponding to each transaction in the transaction sequence is determined one by one. Classifying and sorting transactions according to anomaly type improves the efficiency and orderliness of determining anomaly handling units.

[0066] Optionally, the method further includes:

[0067] Step 503: Determine the preset execution operation corresponding to each processing unit, and determine the target processing unit that has completed the preset execution operation in at least one processing unit;

[0068] Step 504: Delete the information record of the target processing unit.

[0069] In this embodiment, the information record can be stored in the FPGA's memory, such as random access memory (RAM) or other read / write memory. Since the memory provides limited storage capacity, information records that meet the criteria can be deleted.

[0070] During transaction processing, the preset operations that each processing unit needs to perform are different, meaning that the information to be received and sent is inconsistent. Therefore, once the processing unit has completed its corresponding preset operations, the information record of that processing unit can be deleted.

[0071] In embodiments of this application, information records of the processing unit are deleted after the processing unit has completed a corresponding preset execution operation. This allows for the appropriate deletion of information records in the memory, reducing storage pressure.

[0072] Optionally, step 503, which involves determining the preset execution operation corresponding to each processing unit and identifying the target processing unit that has completed the preset execution operation in at least one processing unit, includes:

[0073] Sub-step 5031: For each processing unit, obtain the operation configuration of the processing unit; the operation configuration represents the preset execution operation of the processing unit when executing the transaction;

[0074] Sub-step 5032: Based on the information record of the processing unit, determine the operation that the processing unit has performed;

[0075] Sub-step 5033: If the executed operation conforms to the preset execution operation, determine the processing unit as the target processing unit.

[0076] In this embodiment, an operation configuration corresponding to each processing unit can be obtained. The operation configuration represents the preset execution operation of the processing unit when executing a transaction. It is understood that the preset execution operation of the same processing unit may be different in different transaction executions.

[0077] Since the information record of the processing unit contains both received and sent information, the information record also records the specific information receiving and sending operations that the processing unit has performed, i.e., the operations that have been performed.

[0078] The system can compare the executed operations with the preset execution operations. If the executed operations match the preset execution operations, the current processing unit is determined as the target processing unit, and the information record of the target processing unit can be deleted.

[0079] Optionally, there are multiple transactions; the method further includes:

[0080] In a series of transactions, identify the target transaction that has been completed.

[0081] The target information corresponding to the target transaction in the information record of at least one processing unit is determined, and the target information is deleted.

[0082] In this embodiment, there can be multiple transactions, and the execution of these transactions can be sequential; some transactions can be completed first, while others can be completed later. Once a transaction is completed, it indicates that no execution exception occurred, and therefore the information records for that part of the transaction can be deleted.

[0083] Since each processing unit's information record contains information received and sent by that unit, a single processing unit can involve information records from multiple transactions. Therefore, within multiple transactions, it is possible to identify the target transaction that has been completed, determine the target information of that target transaction in the information record of at least one processing unit, and then delete that target information.

[0084] In embodiments of this application, by identifying a completed target transaction among multiple transactions, determining the target information of the target transaction in the information record of the at least one processing unit, and deleting the target information, it is possible to delete the information records of some transactions after they have been executed without any abnormalities in a multi-transaction execution scenario, thereby reducing data storage pressure.

[0085] Optionally, there are multiple transactions; the method further includes:

[0086] A target communication protocol is determined between the at least one processing unit, and a transaction count parameter of the target communication protocol is determined; the transaction count parameter represents the maximum number of transactions that the target communication protocol can handle.

[0087] Based on the transaction quantity parameter, determine the corresponding number of storage areas;

[0088] Establish a one-to-one correspondence between transactions and storage areas; different storage areas are used to store information records of different transactions.

[0089] In this embodiment of the application, at least one processing unit is adjusted based on a specific communication protocol. Each communication protocol can handle a different number of transactions. Therefore, it is necessary to determine the transaction quantity parameter of the target communication protocol according to the current target communication protocol, so as to obtain the maximum number of transactions that the target communication protocol can handle.

[0090] Based on the maximum number of transactions indicated by the transaction count parameter, the preset storage area can be divided into a number of storage areas corresponding to the maximum number of transactions. Furthermore, a one-to-one correspondence is established between transactions and storage areas, ensuring that information records from different transactions are stored in their respective storage areas.

[0091] In implementing embodiments of this application, a target communication protocol is determined between the at least one processing unit, and a transaction quantity parameter of the target communication protocol is determined. Based on the transaction quantity parameter, a corresponding number of storage areas are determined, establishing a one-to-one correspondence between transactions and storage areas. This enables information records for different transactions to be stored in different areas, avoiding data chaos and providing data orderliness and clarity.

[0092] Optionally, the method further includes:

[0093] Construct information processing description data; the information processing description data is used to represent the information receiving status and information sending status of the processing unit.

[0094] When the processing unit receives information sent by other processing units, the first flag bit corresponding to the processing unit in the information processing description data is set to a preset value;

[0095] When the processing unit sends information to other processing units, the second flag bit corresponding to the processing unit in the information processing description data is set to a preset value.

[0096] In this embodiment, information processing description data can also be constructed, which is used to represent the information receiving status and information sending status of the processing unit. There can be a one-to-one correspondence between the information processing description data and transactions, and each piece of information processing description data can represent the status of receiving and sending information by the relevant processing unit during the execution of a specific transaction.

[0097] When a processing unit receives information from other processing units, it sets the first flag bit corresponding to the processing unit in the information processing description data to a preset value, such as one. When a processing unit sends information to other processing units, it sets the second flag bit corresponding to the processing unit in the information processing description data to a preset value. The specific value of the preset value is not limited here and can be adjusted flexibly.

[0098] In embodiments of this application, information processing description data is constructed. When a processing unit receives information sent by other processing units, a first flag bit corresponding to the processing unit in the information processing description data is set to a preset value. When a processing unit sends information to other processing units, a second flag bit corresponding to the processing unit in the information processing description data is set to a preset value. This allows for a direct and intuitive view of the specific status of transaction processing and the status of each processing unit through the information processing description data, improving the intuitiveness of information interaction and providing a clear understanding of the intermediate states of the information interaction process.

[0099] Optionally, the method further includes:

[0100] If there is information to be stored, determine the target transaction and its target storage area corresponding to the information to be stored; the information to be stored is received information or sent information.

[0101] If the target storage area is full, delete the oldest historical information stored in the target storage area and store the information to be stored in the target storage area.

[0102] In this embodiment of the application, when the processing unit receives or sends information, it is considered that there is information to be stored. The target transaction corresponding to the information to be stored can be determined, and the target storage area corresponding to the target transaction can be determined according to the one-to-one correspondence between the transaction and the storage area.

[0103] If the target storage area is full, new information cannot be stored directly. Instead, the oldest historical information stored in the target storage area can be deleted, and the information to be stored can be stored in the target storage area. Since the oldest historical information stored in the target storage area is most likely not used for anomaly location, it can be deleted first to provide storage space for the information to be stored.

[0104] Optionally, the method further includes:

[0105] If there is information to be stored, determine the target transaction and its target storage area corresponding to the information to be stored;

[0106] If the target storage area is full, determine the data size of the information to be stored;

[0107] Based on the data size of the information to be stored, delete at least one historical piece of information with the earliest storage time in the target storage area; the data size of the at least one historical piece of information is greater than or equal to the data size of the information to be stored.

[0108] The information to be stored is stored in the target storage area.

[0109] In this embodiment of the application, similarly, when there is information to be stored, the target transaction corresponding to the information to be stored and its target storage area are determined.

[0110] If the target storage area is full, determine the size of the information to be stored to clarify the required storage space. Then, based on the size of the information to be stored, select at least one historical record from the target storage area that has the oldest storage time. The size of this historical record can be greater than or equal to the size of the information to be stored. Delete this historical record to make room for the information to be stored.

[0111] In implementing embodiments of this application, by selecting at least one historical information with the earliest storage time in the target storage area based on the data size of the information to be stored, the data size of the at least one historical information can be greater than or equal to the data size of the information to be stored, thereby minimizing the impact on existing stored information records and storing the information to be stored.

[0112] Optionally, the method further includes:

[0113] Receive a stop recording command and, in response to the stop recording command, stop storing received and transmitted information.

[0114] In this embodiment, since storing information occupies RAM resources, it can be enabled and turned on only during FPGA prototype verification and turned off when the application specific integrated circuit (ASIC) is fabricated. By receiving a stop recording command, the storage of received and sent information can be stopped in response to the stop recording command, thereby saving RAM resources and reducing chip area.

[0115] Optionally, the method further includes:

[0116] Receive read / write access requests sent by the monitoring and management system; the read / write access requests carry identification information, which is used to indicate the target transaction or target processing unit;

[0117] In response to the read / write access request, the information record indicated by the identification information is sent to the monitoring and management system; the monitoring and management system is used to perform anomaly analysis based on the information record.

[0118] In the embodiments of this application, a complex system consisting of a chip including a processing unit may experience a fault. In the event of a fault, the system can receive read / write access requests sent by the monitoring and management system. In response to the read / write access requests, the system can send information records to the monitoring and management system, and the monitoring and management system can perform system fault analysis based on the information records.

[0119] Information records will not be reset or reset in the event of system crash or abnormal restart. They will only be reset during the chip's power-on process. Information records of system anomalies can be saved intact and accessed by reading and writing through an independent monitoring and management system. Transaction information records can be captured for the analysis and localization of faults.

[0120] Optionally, the step of determining the exception handling unit that caused the transaction execution exception based on the information records of at least one processing unit in each chip includes:

[0121] For each processing unit, obtain the operation configuration of the processing unit; the operation configuration represents the preset execution operation of the processing unit when executing the transaction.

[0122] Based on the information recorded by the processing unit, determine the operations that the processing unit has performed;

[0123] The executed operation is compared with the preset execution operation. If there is a difference between the executed operation and the preset execution operation, the processing unit corresponding to the difference is determined to be an exception handling unit.

[0124] In this embodiment of the application, similarly, for each processing unit, the operation configuration of the processing unit can be obtained. The operation configuration represents the preset execution operations of the processing unit when executing a transaction. Based on the information record of the processing unit, the executed operations of the processing unit are determined, which will not be elaborated here.

[0125] The executed operation is compared with the preset execution operation. If there is a difference between the executed operation and the preset execution operation, the corresponding exception handling unit is determined.

[0126] For example, the executed operation could be that the first processing unit receives and sends information, and the second processing unit sends information. The preset execution operation could be that the first processing unit receives and sends information, and the second processing unit receives and sends information. In this case, it can be determined that there is a difference between the executed operation of the second processing unit and the preset execution operation, and the second processing unit is an exception handling unit.

[0127] Optionally, the step of sorting multiple transactions according to the number of transactions for each exception type to determine the transaction sequence includes:

[0128] Determine the number of transactions corresponding to each exception type;

[0129] Based on the number of transactions, the transactions corresponding to each exception type are arranged in descending order to determine the transaction sequence.

[0130] In this embodiment of the application, the number of transactions corresponding to each exception type is determined, and the transactions corresponding to each exception type are arranged in descending order to determine the transaction sequence. Transactions of exception types that occur more frequently can be arranged first.

[0131] In embodiments of this application, the number of transactions corresponding to each exception type is determined; based on the number of transactions, the transactions corresponding to each exception type are arranged sequentially in descending order to determine the transaction sequence. This allows for sorting according to the frequency of exception types, improving the intuitiveness of exception types.

[0132] Optionally, there are multiple transactions; the step of determining the exception handling unit that caused the transaction execution error based on the information records of at least one processing unit in each chip includes:

[0133] In the event of multiple transactions encountering exceptions, determine the exception type for each transaction.

[0134] Multiple transactions are sorted according to the preset priority of each exception type to determine the transaction sequence;

[0135] Based on the information records of at least one processing unit in each chip, the exception handling unit corresponding to each transaction in the transaction sequence is determined one by one.

[0136] In this embodiment, when multiple transactions encounter anomalies, the anomaly type of each transaction is determined, and the multiple transactions are sorted according to the preset priority of each anomaly type to determine the transaction sequence. It is understood that if multiple transactions have the same anomaly type, their positions in the transaction sequence can be adjacent, and the positions of multiple transactions with the same anomaly type in the transaction sequence can change.

[0137] The preset priorities for different anomaly types can be flexibly adjusted. Different priorities can be set according to the severity or urgency of the anomaly type, without specific restrictions here.

[0138] In embodiments of this application, when multiple transactions experience anomalies, the exception type of each transaction is determined; the multiple transactions are sorted according to a preset priority for each exception type to determine a transaction sequence; and based on the information records of at least one processing unit in each chip, the exception handling unit corresponding to each transaction in the transaction sequence is determined one by one. This allows for the sorting of transactions of different exception types based on preset priorities, enabling flexible adjustment of the transaction sequence based on priorities and improving the flexibility of sequence determination.

[0139] Optionally, there are multiple transactions; the step of determining the exception handling unit that caused the transaction execution error based on the information records of at least one processing unit in each chip includes:

[0140] Based on the information records of the at least one processing unit, at least one exception handling unit is determined for each transaction;

[0141] The at least one exception handling unit is classified to obtain at least one exception unit set; each exception unit set includes at least one exception handling unit of the same type;

[0142] Based on the number of exception handling units in each exception unit set, the at least one exception handling unit is sorted to obtain an exception handling unit sequence.

[0143] In this embodiment of the application, when there are multiple transactions, there may be multiple abnormal transactions, and each abnormal transaction may have one or more exception handling units during execution. Therefore, at least one exception handling unit corresponding to each transaction can be determined based on the information recorded by at least one handling unit.

[0144] The exception handling units of multiple abnormal transactions are summarized and classified, with at least one set of exception units. Each set of exception units includes at least one exception handling unit of the same type. For example, exception unit set 1 includes 3 exception handling units A, which can indicate that the handling unit A is abnormal in the execution of 3 transactions.

[0145] Based on the number of exception handling units in each exception unit set, at least one exception handling unit is sorted. The number of exception handling units can represent the number of exceptions or frequency of that unit. Therefore, at least one exception handling unit is sorted according to the number of units in each set. For example, if exception unit set 1 has 3 exception handling units A and exception unit set 2 has 2 exception handling units B, then the 3 exception handling units A can be ranked first.

[0146] In embodiments of this application, based on information records from at least one processing unit, at least one exception handling unit is determined for each transaction; the at least one exception handling unit is classified to obtain at least one set of exception units; and the at least one exception handling unit is sorted according to the number of exception handling units in each set to obtain an exception handling unit sequence. This approach highlights processing units with higher exception counts or frequencies, improving the intuitiveness of the exception handling units.

[0147] In summary, in this embodiment of the application, when a transaction execution exception occurs in a multi-chip system, the information records of at least one processing unit in each chip are obtained. Each processing unit is used to receive and send information to execute the transaction. Information received by each processing unit from other processing units and information sent to other processing units are stored in its respective information record. Based on the information records of at least one processing unit, the exception handling unit causing the transaction execution exception is determined. This allows for a complete record of the information interaction process of each processing unit, and thus, based on the information records of each processing unit, the exception handling unit causing the transaction execution exception can be determined, improving the accuracy of exception localization.

[0148] The anomaly localization method and mechanism based on information recording proposed in this application captures first-hand information about anomalies during the protocol processing, similar to the collection of simulation anomaly results, and can quickly analyze the cause and precise location of the problem.

[0149] Figure 6 This is a schematic diagram of an anomaly location device provided in an embodiment of this application. The device includes:

[0150] The information recording module 601 is used to obtain the information records of at least one processing unit in each chip in the event of a transaction execution exception in a multi-chip system; each processing unit is used to receive and send information to execute the transaction; the information received by each processing unit from other processing units and the information sent to other processing units are stored in its respective information record.

[0151] The exception determination module 602 is used to determine the exception handling unit that caused the transaction execution exception based on the information records of at least one processing unit in each chip.

[0152] Optionally, there are multiple transactions; the exception determination module includes:

[0153] The exception time submodule is used to determine the exception time of each transaction when multiple transactions encounter exceptions.

[0154] The time sorting submodule is used to sort the multiple transactions according to the time points of multiple abnormal times in order to determine the transaction sequence;

[0155] The time processing submodule is used to determine the exception handling unit corresponding to each transaction in the transaction sequence based on the information records of at least one processing unit in each chip.

[0156] Optionally, there are multiple transactions; the exception determination module includes:

[0157] The first exception type submodule is used to determine the exception type of each transaction when multiple transactions encounter exceptions.

[0158] The quantity sorting submodule is used to sort multiple transactions based on the number of transactions for each exception type to determine the transaction sequence;

[0159] The quantity processing submodule is used to determine the exception handling unit corresponding to each transaction in the transaction sequence based on the information records of at least one processing unit in each chip.

[0160] Optionally, the device also includes:

[0161] The completed unit determination module is used to determine the preset execution operation corresponding to each processing unit, and to determine the target processing unit that has completed the preset execution operation in at least one processing unit;

[0162] The unit deletion module has been completed, which is used to delete the information records of the target processing unit.

[0163] Optionally, the completed cell determination module includes:

[0164] The first configuration submodule is used to obtain the operation configuration of each processing unit; the operation configuration represents the preset execution operation of the processing unit when executing the transaction;

[0165] The first executed operation submodule is used to determine the executed operation of the processing unit based on the information record of the processing unit;

[0166] The operation conformance submodule is used to determine the processing unit as the target processing unit when the executed operation conforms to the preset execution operation.

[0167] Optionally, there are multiple transactions; the apparatus further includes:

[0168] The completed transaction determination module is used to determine the target transaction that has been completed among multiple transactions;

[0169] The completed transaction information module is used to determine the target information corresponding to the target transaction in the information record of at least one processing unit, and delete the target information.

[0170] Optionally, there are multiple transactions; the apparatus further includes:

[0171] The protocol transaction quantity module is used to determine the target communication protocol between the at least one processing unit and to determine the transaction quantity parameter of the target communication protocol; the transaction quantity parameter represents the maximum number of transactions that the target communication protocol can handle.

[0172] The storage area partitioning module is used to determine a corresponding number of storage areas based on the transaction quantity parameter;

[0173] The transaction area correspondence module is used to establish a one-to-one correspondence between transactions and storage areas; different storage areas are used to store information records of different transactions.

[0174] Optionally, the device also includes:

[0175] The description module is used to construct information processing description data; the information processing description data is used to represent the information receiving status and information sending status of the processing unit.

[0176] The receiving status module is used to set the first flag bit corresponding to the processing unit in the information processing description data to a preset value when the processing unit receives information sent by other processing units.

[0177] The sending status module is used to set the second flag bit corresponding to the processing unit in the information processing description data to a preset value when the processing unit sends information to other processing units.

[0178] Optionally, the method further includes:

[0179] The first storage module is used to determine the target transaction and its target storage area corresponding to the storage information when storage information exists; the storage information is received information or sent information.

[0180] The history deletion module is used to delete the oldest historical information stored in the target storage area when the target storage area is full, and to store the information to be stored in the target storage area.

[0181] Optionally, the device also includes:

[0182] The second storage module is used to determine the target transaction and its target storage area corresponding to the information to be stored when there is information to be stored.

[0183] A data size module is used to determine the data size of the information to be stored when the target storage area is full;

[0184] The size deletion module is used to delete at least one historical piece of information with the earliest storage time in the target storage area based on the data size of the information to be stored; the data size of the at least one historical piece of information is greater than or equal to the data size of the information to be stored;

[0185] Update the storage module to store the information to be stored in the target storage area.

[0186] Optionally, the method further includes:

[0187] Receive a stop recording command and, in response to the stop recording command, stop storing received and transmitted information.

[0188] Optionally, the device also includes:

[0189] The monitoring and management module is used to receive read and write access requests sent by the monitoring and management system; the read and write access requests carry identification information, which is used to indicate the target transaction or target processing unit;

[0190] The data monitoring module is used to send the information record indicated by the identification information to the monitoring and management system in response to the read / write access request; the monitoring and management system is used to perform anomaly analysis based on the information record.

[0191] Optional, the exception determination module includes:

[0192] The second configuration submodule is used to obtain the operation configuration of each processing unit; the operation configuration represents the preset execution operation of the processing unit when executing the transaction;

[0193] The second executed operation submodule is used to determine the executed operation of the processing unit based on the information record of the processing unit;

[0194] The comparison difference submodule is used to compare the executed operation with the preset execution operation, and if there is a difference between the executed operation and the preset execution operation, determine the processing unit corresponding to the difference as an exception handling unit.

[0195] Optional, quantity sorting submodule, including:

[0196] The transaction count unit is used to determine the number of transactions corresponding to each exception type.

[0197] The descending sorting unit is used to arrange the transactions corresponding to each exception type in descending order based on the number of transactions, so as to determine the transaction sequence.

[0198] Optionally, there are multiple transactions; the exception determination module includes:

[0199] The second exception type submodule is used to determine the exception type of each transaction when multiple transactions encounter exceptions.

[0200] The type priority submodule is used to sort multiple transactions according to the preset priority of each exception type in order to determine the transaction sequence;

[0201] The priority processing submodule is used to determine the exception handling unit corresponding to each transaction in the transaction sequence based on the information records of at least one processing unit in each chip.

[0202] Optionally, there are multiple transactions; the exception determination module includes:

[0203] Each exception submodule is used to determine at least one exception handling unit corresponding to each transaction based on the information records of the at least one processing unit;

[0204] An exception unit classification submodule is used to classify the at least one exception handling unit to obtain at least one exception unit set; each exception unit set includes at least one exception handling unit of the same type;

[0205] The exception unit sequence submodule is used to sort the at least one exception processing unit according to the number of exception processing units in each exception unit set to obtain an exception processing unit sequence.

[0206] In summary, in this embodiment of the application, when a transaction execution exception occurs in a multi-chip system, the information records of at least one processing unit in each chip are obtained. Each processing unit is used to receive and send information to execute the transaction. Information received by each processing unit from other processing units and information sent to other processing units are stored in its respective information record. Based on the information records of at least one processing unit, the exception handling unit causing the transaction execution exception is determined. This allows for a complete record of the information interaction process of each processing unit, and thus, based on the information records of each processing unit, the exception handling unit causing the transaction execution exception can be determined, improving the accuracy of exception localization.

[0207] This application also provides an electronic device, such as... Figure 7 As shown, it includes a processor 1701, a communication interface 1702, a memory 1703, and a communication bus 1704, wherein the processor 1701, the communication interface 1702, and the memory 1703 communicate with each other through the communication bus 1704.

[0208] Memory 1703 is used to store computer programs.

[0209] When processor 1701 executes a program stored in memory 1703, it performs the following steps: in the event of a transaction execution exception in a multi-chip system, it acquires the information records of at least one processing unit in each chip; each processing unit is used to receive and send information to execute the transaction; information received by each processing unit from other processing units and information sent to other processing units are stored in its respective information records; based on the information records of at least one processing unit in each chip, it determines the exception handling unit that caused the transaction execution exception.

[0210] The processor 1701 can also perform other steps in the above-mentioned anomaly location method, which will not be elaborated here.

[0211] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into area buses, data buses, control buses, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0212] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0213] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0214] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0215] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform the anomaly location method described in the above embodiments.

[0216] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the anomaly location method described in the above embodiments.

[0217] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0218] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0219] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0220] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A method of anomaly localization, the method comprising: The method comprises: In the case of transaction execution exception in a multi-chip system, obtaining the respective information records of at least one processing unit in each chip; each processing unit is used to receive and send information to execute the transaction; the information received by each processing unit from other processing units and the information sent to other processing units are stored in the respective information records; Based on the respective information records of at least one processing unit in each chip, determining the abnormal processing unit that causes the transaction execution exception; The step of determining the abnormal processing unit that causes the transaction execution exception based on the respective information records of at least one processing unit in each chip comprises: For each processing unit, obtaining the operation configuration of the processing unit; the operation configuration represents the preset execution operation of the processing unit when executing the transaction; According to the information record of the processing unit, determining the executed operation of the processing unit; Comparing the executed operation with the preset execution operation, in the case of difference between the executed operation and the preset execution operation, determining the processing unit corresponding to the difference as the abnormal processing unit.

2. The method of claim 1, wherein, The transaction has multiple; the step of determining the abnormal processing unit that causes the transaction execution exception based on the respective information records of at least one processing unit in each chip comprises: In the case of multiple transaction exceptions, determining the respective exception time of each transaction; According to the time points of multiple exception times, sorting the multiple transactions to determine the transaction sequence; Based on the respective information records of at least one processing unit in each chip, determining the abnormal processing unit corresponding to each transaction in the transaction sequence one by one.

3. The method of claim 1, wherein, The transaction has multiple; the step of determining the abnormal processing unit that causes the transaction execution exception based on the respective information records of at least one processing unit in each chip comprises: In the case of multiple transaction exceptions, determining the respective exception type of each transaction; According to the number of transactions of each exception type, sorting the multiple transactions to determine the transaction sequence; Based on the respective information records of at least one processing unit in each chip, determining the abnormal processing unit corresponding to each transaction in the transaction sequence one by one.

4. The method of claim 1, wherein, The method further comprises: Determining the preset execution operation corresponding to each processing unit, and determining the target processing unit in which the preset execution operation has been completed in at least one processing unit; Deleting the information record of the target processing unit.

5. The method of claim 4, wherein, The step of determining the preset execution operation corresponding to each processing unit, and determining the target processing unit in which the preset execution operation has been completed in at least one processing unit comprises: For each processing unit, obtaining the operation configuration of the processing unit; the operation configuration represents the preset execution operation of the processing unit when executing the transaction; According to the information record of the processing unit, determining the executed operation of the processing unit; In the case that the executed operation conforms to the preset execution operation, determining the processing unit as the target processing unit.

6. The method of claim 1, wherein, The transaction has multiple; the method further comprises: In the multiple transactions, determining the target transaction that has been executed and completed; determining a target information corresponding to the target transaction in an information record of the at least one processing unit, and deleting the target information.

7. The method of claim 1, wherein, The transactions have a plurality of transactions; the method further comprises: determining a target communication protocol between the at least one processing unit, and determining a transaction number parameter of the target communication protocol; the transaction number parameter represents a maximum number of transactions that can be processed by the target communication protocol; determining a corresponding number of storage areas according to the transaction number parameter; establishing a one-to-one correspondence between the transactions and the storage areas; different storage areas are used to store information records of different transactions.

8. The method of claim 1, wherein, The method further comprises: constructing information processing description data; the information processing description data is used to represent an information receiving state and an information sending state of a processing unit; in a case where the processing unit receives information sent by another processing unit, setting a first flag corresponding to the processing unit in the information processing description data to a preset value; in a case where the processing unit sends information to another processing unit, setting a second flag corresponding to the processing unit in the information processing description data to a preset value.

9. The method of claim 7, wherein, The method further comprises: in a case where there is to-be-stored information, determining a target transaction corresponding to the to-be-stored information and a target storage area thereof; the to-be-stored information is received information or sent information; in a case where the target storage area is full, deleting historical information stored earliest in the target storage area, and storing the to-be-stored information into the target storage area.

10. The method of claim 7, wherein, The method further comprises: in a case where there is to-be-stored information, determining a target transaction corresponding to the to-be-stored information and a target storage area thereof; in a case where the target storage area is full, determining a data size of the to-be-stored information; according to the data size of the to-be-stored information, deleting at least one historical information stored earliest in the target storage area; the data size of the at least one historical information is greater than or equal to the data size of the to-be-stored information; storing the to-be-stored information into the target storage area.

11. The method of claim 1, wherein, The method further comprises: receiving a stop recording instruction, and stopping storage of received information and sent information in response to the stop recording instruction.

12. The method of claim 1, wherein, The method further comprises: receiving a read-write access request sent by a monitoring management system; the read-write access request carries identification information, and the identification information is used to indicate a target transaction or a target processing unit; in response to the read-write access request, sending information records indicated by the identification information to the monitoring management system; the monitoring management system is used to perform abnormality analysis based on the information records.

13. The method of claim 3, wherein, The step of sorting a plurality of transactions according to a number of transactions of each abnormal type to determine a transaction sequence comprises: determining a number of transactions corresponding to each abnormal type; based on the number of transactions, arranging transactions corresponding to each abnormal type in turn in a descending order to determine a transaction sequence.

14. The method of claim 1, wherein, The transactions have a plurality of transactions; the step of determining an abnormal processing unit causing an abnormal execution of the transactions based on information records of the at least one processing unit in each chip comprises: In the case of multiple transaction exceptions, determine the respective exception type of each transaction; According to the preset priority of each exception type, sort the multiple transactions to determine the transaction sequence; Based on the respective information record of at least one processing unit in each chip, determine the corresponding exception processing unit of each transaction in the transaction sequence.

15. The method of claim 1, wherein, The transaction has multiple; The step of determining the exception processing unit causing the transaction execution exception based on the information record of at least one processing unit in each chip comprises: Based on the information record of the at least one processing unit, determine at least one exception processing unit corresponding to each transaction; Classify the at least one exception processing unit to obtain at least one exception unit set; Each exception unit set includes at least one exception processing unit of the same type; According to the number of exception processing units in each exception unit set, sort the at least one exception processing unit to obtain an exception processing unit sequence.

16. An anomaly locating device, characterized by The device comprises: An information record module for obtaining the respective information record of at least one processing unit in each chip in the case of transaction execution exception in a multi-chip system; Each processing unit is used to receive and send information to execute the transaction; The information received by each processing unit from other processing units and the information sent to other processing units are stored in the respective information record; An exception determination module for determining the exception processing unit causing the transaction execution exception based on the respective information record of at least one processing unit in each chip; The exception determination module comprises: A second configuration submodule for obtaining the operation configuration of each processing unit; The operation configuration represents the preset execution operation of the processing unit when executing the transaction; A second executed operation submodule for determining the executed operation of the processing unit according to the information record of the processing unit; A comparison difference submodule for comparing the executed operation and the preset execution operation, and determining the processing unit corresponding to the difference as the exception processing unit in the case of difference between the executed operation and the preset execution operation.

17. An electronic device, comprising: It comprises: A memory for saving a computer program; A processor for executing the computer program to implement the exception positioning method of any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, For storing computer programs / instructions; Wherein the computer programs / instructions are executed by the processor to implement the exception positioning method of any one of claims 1 to 15.

19. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to implement the exception positioning method of any one of claims 1 to 15.

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