Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a wafer to be processed; carrying out light doping ion implantation on the to-be-processed wafer in an ion implantation chamber, and forming a light doping region in the to-be-processed wafer; after the lightly doped drain ion implantation process is carried out, transferring the wafer to be processed into a transfer chamber from an ion implantation chamber; and after the to-be-processed wafer is transferred to the transfer chamber, first protective gas is introduced into the transfer chamber until the air pressure in the transfer chamber is greater than the atmospheric pressure, the transfer chamber is opened, and the to-be-processed wafer is moved out, so that the probability that a photoresist layer reacts with acid to form a condensation defect is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, even a tiny defect can have a great impact on the device. Take static random-access memory (SRAM) as an example, most of them are volatile static memories composed of complementary metal oxide semiconductors (CMOS). Since CMOS is easily affected by defects in the manufacturing process, CMOS memory may fail, affecting the chip yield.

[0003] Specifically, in the current semiconductor manufacturing process, a major cause of abnormal quality of memory chips is related to the condensation defect generated on the surface of the wafer after the lightly doped drain (LDD) process. This defect cannot be removed with conventional cleaning solutions, resulting in the condensation defect being buried in the subsequent process of forming an inter-level dielectric (ILD) layer, affecting the contact resistance of the subsequent metal connections and devices, and further affecting the storage performance of the chip in this area.

[0004] Therefore, the existing semiconductor manufacturing process needs to be further improved to reduce the generation of condensation defects and thus improve device performance. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a wafer to be processed; lightly doping the wafer to be processed by injecting ions in an ion implantation chamber to form a lightly doped region in the wafer to be processed; after performing the lightly doped drain ion implantation process, transferring the wafer to be processed from the ion implantation chamber to a transfer chamber; after the wafer to be processed is transferred to the transfer chamber, introducing a first protective gas into the transfer chamber until the gas pressure in the transfer chamber is greater than the atmospheric pressure, and then opening the transfer chamber and removing the wafer to be processed.

[0007] Optionally, the first protective gas includes one or more of nitrogen, argon and an inert gas.

[0008] Optionally, the method for forming the lightly doped region includes a first ion implantation process and a second ion implantation process after the first ion implantation process, and the implanted ions in the second ion implantation process do not contain fluorine ions.

[0009] Optionally, the process parameters of the first ion implantation process include: the implanted ions include BF2 + The implantation energy range is 6KeV and the implantation dose range is 2×10 15 atom / cm 2 .

[0010] Optionally, the process parameters of the second ion implantation process include: the implanted ions include N-type conductive ions, the implantation energy ranges from 5 KeV to 60 KeV, and the implantation dose ranges from 1×10 12 atom / cm 2 Up to 1×10 14 atom / cm 2 .

[0011] Optionally, the method for forming the lightly doped region further includes a third ion implantation process, and the third ion implantation process is performed before the first ion implantation process.

[0012] Optionally, the process parameters of the third ion implantation process include: the implanted ions include carbon ions, the implantation energy is less than or equal to 10 KeV, and the implantation dose range is 1×10 13 atom / cm 2 Up to 5×10 15 atom / cm 2 .

[0013] Optionally, before the transfer chamber is opened, the difference between the air pressure in the transfer chamber and the atmospheric pressure ranges from 20 torr to 200 torr.

[0014] Optionally, the wafer to be processed includes a substrate, a gate layer and a photoresist layer located on the substrate, the substrate includes a first region and a second region located on both sides of the first region, the gate layer is located on the first region, and the photoresist layer exposes the second region; the method for forming the lightly doped region also includes: using the photoresist layer as a mask to inject ions into the second region.

[0015] Optionally, after removing the wafer to be processed, the method further includes: moving the wafer to be processed into a transmission box; transferring the wafer to be processed to an etching chamber through the transmission box, and etching the wafer to be processed to remove the photoresist layer.

[0016] Optionally, the transport box has a sealable box cavity; the method of moving the wafer to be processed into the transport box includes: moving the wafer to be processed into the sealed box cavity.

[0017] Optionally, the method of transferring the wafer to be processed to the etching chamber also includes: using a vacuum device and a ventilation device to place the wafer to be processed in the box cavity in an atmosphere of a second protective gas, the vacuum device being used to extract the gas in the box cavity, and the ventilation device being used to introduce the second protective gas into the box cavity.

[0018] Optionally, the second protective gas includes one or more of nitrogen, argon and air; the humidity range of the second protective gas is less than or equal to 5%; the purity range of the nitrogen is greater than 99.999%.

[0019] Optionally, the method further includes monitoring the control time of the wafer to be processed from being moved out of the transfer chamber to entering the etching chamber, and when the control time exceeds a preset time, stopping the continued operation of the wafer to be processed.

[0020] Optionally, after removing the photoresist layer, the method further includes: detecting condensation defects on the surface of the wafer to be processed; and performing subsequent processes when the number of the condensation defects ranges from 0 to 10.

[0021] Optionally, both the ion implantation chamber and the transfer chamber are closed chambers, and a sealed transmission channel is provided between the ion implantation chamber and the transfer chamber, and the wafer to be processed is transferred to the transfer chamber through the sealed transmission channel.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first protective gas is introduced into the transfer chamber until the air pressure in the transfer chamber is greater than the atmospheric pressure, and then the transfer chamber is opened and the wafer to be processed is removed. Since the air pressure in the transfer chamber is greater than the external atmospheric pressure, at the moment the transfer chamber is opened, air convection can hinder the entry of water vapor in the external environment, thereby reducing the probability of water vapor being adsorbed on the surface of the wafer to be processed, thereby reducing the probability of acid being formed due to chemical reaction between water vapor and fluoride ions on the surface of the wafer to be processed, and further reducing the probability of condensation defects formed by the reaction of the photoresist layer with the acid, thereby improving the performance of the formed device in the semiconductor process.

[0024] Furthermore, the method for forming the lightly doped region includes a first ion implantation process and a second ion implantation process after the first ion implantation process, and the implanted ions in the second ion implantation process do not contain fluorine ions. The heat generated in the second ion implantation process plays a role of self-annealing, which can make the fluorine ions remaining on the surface of the wafer to be processed in the first ion implantation process form more stable fluorides, inhibit the precipitation of fluorine ions on the surface of the wafer to be processed, thereby reducing the probability of fluorine ions reacting with water vapor to produce acid, and further reducing the probability of the photoresist layer reacting with acid to form condensation defects.

[0025] Furthermore, the method for forming the lightly doped region further comprises a third ion implantation process, which is performed before the first ion implantation process. The carbon ions implanted in the third ion implantation process are BF2 + The binding effect is beneficial to inhibit the diffusion of fluoride ions to the surface of the wafer to be processed, thereby reducing the probability of fluoride ions reacting with water vapor to produce acid, and further reducing the probability of condensation defects formed by the reaction of the photoresist layer with acid. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of a possible chemical reaction mechanism in a semiconductor structure formation method;

[0027] Figure 2 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0028] Figures 3 to 5 is a structural schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of a device in a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] As described in the background art, the existing semiconductor manufacturing process needs to be further improved. Now, a method for forming a semiconductor structure is described and analyzed.

[0032] In a PMOS device LDD process, a photoresist pattern is first formed on the wafer surface, and the photoresist is retained in the area where LDD is not required. Then, ion implantation is performed using the photoresist as a mask to improve the hot carrier injection effect. Since the LDD process requires low implantation energy and a shallow implantation depth of doped ions (approximately less than 10 nanometers), BF2 with a relatively large molecular weight is often used to achieve this purpose. +Doping ions are implanted. However, the doping ions are easy to precipitate fluorine ions on the surface of the wafer and combine with silicon. In the environment of production workshop humidity ~45%, hydrofluoric acid (HF) is easy to be generated on the surface of the wafer, that is, an acidic environment is formed on the surface of the wafer. The above acidic environment will cause condensation defects at the edge of the photoresist. For specific reasons, please refer to Figure 1 .

[0033] Figure 1 It is a schematic diagram of the possible chemical reaction mechanism in the method of forming a semiconductor structure.

[0034] Please refer to Figure 1 In the schematic diagram of the chemical reaction mechanism, the decomposition of the ester bond (-COO-) in the photoresist requires an acidic environment. Specifically, the photoresist and hydrofluoric acid react to generate tert-butyl alcohol ((CH3)3COH) (as shown by the dotted line in the figure). Since the freezing point of tert-butyl alcohol is 25°C (while the ambient temperature is about 22°C), tert-butyl alcohol is easily condensed, forming condensation defects.

[0035] In order to reduce the generation of the condensation defects, the purpose of controlling the condensation defects is usually achieved by controlling the Q-time (referring to the waiting time between the end of the LDD process and the start of the photoresist removal process). However, the effect of reducing the condensation defects by controlling the Q-time is still poor.

[0036] In order to solve the above problems, in a method for forming a semiconductor structure provided by the present invention, a first protective gas is introduced into the transfer chamber until the air pressure in the transfer chamber is greater than the atmospheric pressure, and then the transfer chamber is opened and the wafer to be processed is removed. Since the air pressure in the transfer chamber is greater than the external atmospheric pressure, at the moment the transfer chamber is opened, air convection can hinder the entry of water vapor in the external environment, thereby reducing the probability of water vapor being adsorbed on the surface of the wafer to be processed, thereby reducing the probability of acid being formed due to chemical reaction between water vapor and fluoride ions on the surface of the wafer to be processed, and further reducing the probability of condensation defects formed by the reaction of the photoresist layer with the acid, thereby improving the performance of the formed device in the semiconductor process.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 2 It is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 2 , the method for forming the semiconductor structure comprises the following process:

[0040] S101, providing a wafer to be processed;

[0041] S102, lightly doping the wafer to be processed by ion implantation in an ion implantation chamber to form a lightly doped region in the wafer to be processed;

[0042] S103, after performing the lightly doped drain ion implantation process, transferring the wafer to be processed from the ion implantation chamber to a transfer chamber;

[0043] S104, after the wafer to be processed is transferred to the transfer chamber, a first protective gas is introduced into the transfer chamber until the gas pressure in the transfer chamber is greater than the atmospheric pressure, and then the transfer chamber is opened and the wafer to be processed is removed.

[0044] The following is a detailed description with reference to the accompanying drawings.

[0045] Figures 3 to 5 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Please continue to refer to Figure 2 , and refer to Figure 3 , providing a wafer 20 to be processed.

[0047] In this embodiment, the processed chip 20 includes a substrate 201, a gate layer 202 and a photoresist layer 203 located on the substrate 201, the substrate 201 includes a first region I and a second region II located on both sides of the first region I, the gate layer 202 is located on the first region I, and the photoresist layer 203 exposes the second region II.

[0048] In this embodiment, the photoresist layer 203 is located on the top surface of the gate layer 202. In another embodiment, the photoresist layer exposes the gate layer.

[0049] The second region II is used to define the positions of the source / drain doped regions and the lightly doped regions to be formed subsequently.

[0050] In this embodiment, the substrate 201 has a well region 204 located in the first region I and the second region II. The well region 204 has N-type conductive ions. The well region 204 is used to form a PMOS device.

[0051] Figure 6 It is a schematic diagram of a device in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0052] Please continue to refer to Figure 2 , and refer to Figure 4 and Figure 6 , ions are lightly doped into the wafer 20 to be processed in the ion implantation chamber A to form a lightly doped region 205 in the wafer 20 to be processed.

[0053] In this embodiment, the method for forming the lightly doped region 205 further includes: using the photoresist layer 203 as a mask to implant ions into the second region II.

[0054] In this embodiment, the method for forming the lightly doped region 205 includes a first ion implantation process and a second ion implantation process after the first ion implantation process, and the implanted ions in the second ion implantation process do not contain fluorine ions. The first ion implantation process is used to improve the hot carrier injection effect, and the second ion implantation process is used to suppress the precipitation of fluorine ions generated in the first ion implantation process.

[0055] In this embodiment, the process parameters of the first ion implantation process include: the implanted ions include BF2 + The implantation energy range is 6KeV and the implantation dose range is 2×10 15 atom / cm 2 .

[0056] In this embodiment, the process parameters of the second ion implantation process include: the implanted ions include N-type conductive ions, the implantation energy ranges from 5KeV to 60KeV, and the implantation dose ranges from 1×10 12 atom / cm 2 Up to 1×10 14 atom / cm 2 In this embodiment, the N-type conductive ions are In + The implantation energy range is 45KeV and the implantation dose range is 5×10 13 atom / cm 2 .

[0057] Here, the heat generated in the second ion implantation process plays a role of self-annealing, which can make the fluorine ions remaining on the surface of the wafer 20 to be processed in the first ion implantation process form more stable fluorides, inhibit the precipitation of fluorine ions on the surface of the wafer 20 to be processed, thereby reducing the probability of fluorine ions reacting with water vapor to produce acid, and further reducing the probability of the photoresist layer 203 reacting with acid to form condensation defects.

[0058] In this embodiment, the method for forming the lightly doped region 205 further includes a third ion implantation process, and the third ion implantation process is performed before the first ion implantation process.

[0059] In this embodiment, the process parameters of the third ion implantation process include: the implanted ions include carbon ions, the implantation energy is less than or equal to 10 KeV, and the implantation dose range is 1×10 13 atom / cm 2 Up to 5×10 15 atom / cm2 In this embodiment, the implantation energy is 6KeV and the implantation dose is 6×10 14 atom / cm 2 Among them, carbon ions react with BF2 + The binding effect is beneficial to inhibit the diffusion of fluorine ions to the surface of the wafer 20 to be processed, thereby reducing the probability of fluorine ions reacting with water vapor to produce acid, and further reducing the probability of the photoresist layer 203 reacting with acid to form condensation defects.

[0060] Please continue to refer to Figure 2 and Figure 6 After the lightly doped drain ion implantation process is performed, the wafer 20 to be processed is transferred from the ion implantation chamber A to the transfer chamber B.

[0061] In this embodiment, the ion implantation chamber A and the transfer chamber B are both closed chambers, and there is a closed transmission channel C between the ion implantation chamber A and the transfer chamber B. The processed wafer 20 is transferred to the transfer chamber B through the closed transmission channel C.

[0062] Please continue to refer to Figure 2 and Figure 6 After the wafer 20 to be processed is transferred to the transfer chamber B, a first protective gas is introduced into the transfer chamber B until the gas pressure in the transfer chamber B is greater than the atmospheric pressure, and then the transfer chamber B is opened and the wafer 20 to be processed is removed.

[0063] Specifically, the transfer chamber B has a valve b0 that can be connected to the outside. The valve b0 is opened to move the wafer 20 to be processed out.

[0064] Here, the first protective gas is introduced into the transfer chamber B until the air pressure in the transfer chamber B is greater than the atmospheric pressure, and then the transfer chamber B is opened and the wafer to be processed 20 is removed. Since the air pressure in the transfer chamber B is greater than the external atmospheric pressure, at the moment the transfer chamber B is opened, the convection of air can hinder the entry of water vapor from the external environment, thereby reducing the probability of water vapor being adsorbed on the surface of the wafer to be processed 20, thereby reducing the probability of acid being formed due to chemical reaction between water vapor and fluoride ions on the surface of the wafer to be processed 20, and further reducing the probability of condensation defects formed by the reaction of the photoresist layer 203 with the acid, thereby improving the performance of the formed device in the semiconductor process.

[0065] The first protective gas includes one or more of nitrogen, argon and an inert gas. The inert gas may be xenon or helium. In this embodiment, the first protective gas is nitrogen.

[0066] In this embodiment, before opening the transfer chamber, the difference between the air pressure in the transfer chamber B and the atmospheric pressure is in the range of 20 torr to 200 torr. The purpose of selecting the range is to prevent the entry of water vapor from the external environment and to reduce the difficulty in opening the transfer chamber B due to the large difference.

[0067] In this embodiment, after removing the wafer 20 to be processed, please refer to Figure 5 .

[0068] Please refer to Figure 5 , and continue to refer to Figure 6 , move the wafer 20 to be processed into a transmission box D; through the transmission box D, transfer the wafer 20 to be processed to an etching chamber E, and perform an etching process on the wafer 20 to be processed to remove the photoresist layer 203.

[0069] In this embodiment, the transmission box D has a sealable box cavity (not shown in the figure); the method of moving the wafer 20 to be processed into the transmission box D includes: moving the wafer 20 to be processed into the sealed box cavity.

[0070] In this embodiment, the method of transferring the wafer to be processed 20 to the etching chamber E also includes: using a vacuum device (not shown in the figure) and a ventilation device (not shown in the figure) to place the wafer to be processed 20 in the box cavity in an atmosphere of a second protective gas, the vacuum device being used to extract the gas in the box cavity, and the ventilation device being used to introduce the second protective gas into the box cavity.

[0071] The second protective gas includes one or more of nitrogen, argon and air. In this embodiment, the second protective gas is nitrogen. The second protective gas is used to reduce the probability of contact between the surface of the wafer 20 to be processed and water vapor, and based on the above reasons, the probability of condensation defects is reduced.

[0072] In this embodiment, the purity range of the nitrogen is greater than 99.999%.

[0073] In this embodiment, the humidity range of the second protective gas is less than or equal to 5%.

[0074] In this embodiment, the method further includes monitoring the control time of the processed wafer 20 moving out of the transfer chamber B and entering the etching chamber E. When the control time exceeds the preset time, the continued operation of the processed wafer 20 is stopped.

[0075] Monitoring by card control time is helpful to reduce the probability of the wafer to be processed 20 contacting with water vapor, and also helps to reduce the probability of condensation defects.

[0076] In this embodiment, after removing the photoresist layer 203, the condensation defects on the surface of the wafer 20 to be processed are also detected; when the number of the condensation defects ranges from 0 to 10, the subsequent process is performed.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing wafers to be processed; Injecting ions lightly into the wafer to be processed in an ion implantation chamber to form a lightly doped region in the wafer to be processed; After the lightly doped drain ion implantation process is performed, the wafer to be processed is transferred from the ion implantation chamber to a transfer chamber; After the wafer to be processed is transferred to the transfer chamber, a first protective gas is introduced into the transfer chamber until the gas pressure in the transfer chamber is greater than the atmospheric pressure, and then the transfer chamber is opened and the wafer to be processed is removed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first protective gas includes one or more of nitrogen, argon and an inert gas.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the lightly doped region includes a first ion implantation process and a second ion implantation process after the first ion implantation process, and the implanted ions in the second ion implantation process do not contain fluorine ions.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process parameters of the first ion implantation process include: the implanted ions include BF2 + The implantation energy range is 6KeV and the implantation dose range is 2×10 15 atom / cm 2 .

5. The method for forming a semiconductor structure according to claim 3, wherein: The process parameters of the second ion implantation process include: the implanted ions include N-type conductive ions, the implantation energy ranges from 5KeV to 60KeV, and the implantation dose ranges from 1×10 12 atom / cm 2 Up to 1×10 14 atom / cm 2 .

6. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the lightly doped region further includes a third ion implantation process, and the third ion implantation process is performed before the first ion implantation process.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process parameters of the third ion implantation process include: the implanted ions include carbon ions, the implantation energy is less than or equal to 10 KeV, and the implantation dose range is 1×10 13 atom / cm 2 Up to 5×10 15 atom / cm 2 .

8. The method for forming a semiconductor structure according to claim 1, wherein: Before the transfer chamber is opened, the difference between the air pressure in the transfer chamber and the atmospheric pressure ranges from 20 torr to 200 torr.

9. The method for forming a semiconductor structure according to claim 1, wherein: The wafer to be processed includes a substrate, a gate layer and a photoresist layer located on the substrate, the substrate includes a first region and second regions located on both sides of the first region, the gate layer is located on the first region, and the photoresist layer exposes the second region; the method for forming the lightly doped region also includes: using the photoresist layer as a mask to inject ions into the second region.

10. The method for forming a semiconductor structure according to claim 9, wherein: After the wafer to be processed is removed, the method further includes: moving the wafer to be processed into a transmission box; transferring the wafer to be processed to an etching chamber through the transmission box, and performing etching on the wafer to be processed to remove the photoresist layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The transmission box has a sealable box cavity; the method for moving the wafer to be processed into the transmission box comprises: moving the wafer to be processed into the sealed box cavity.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method of transferring the wafer to be processed to the etching chamber also includes: using a vacuum device and a ventilation device to place the wafer to be processed in the box cavity in an atmosphere of a second protective gas, wherein the vacuum device is used to extract the gas in the box cavity, and the ventilation device is used to introduce the second protective gas into the box cavity.

13. The method for forming a semiconductor structure according to claim 12, wherein: The second protective gas includes one or more of nitrogen, argon and air; the humidity range of the second protective gas is less than or equal to 5%; the purity range of the nitrogen is greater than 99.999%.

14. The method for forming a semiconductor structure according to claim 10, wherein: The method further includes monitoring the control time of the wafer to be processed from being moved out of the transfer chamber to entering the etching chamber, and when the control time exceeds a preset time, stopping the continued operation of the wafer to be processed.

15. The method for forming a semiconductor structure according to claim 10, wherein: After removing the photoresist layer, the method further includes: detecting condensation defects on the surface of the wafer to be processed; and performing subsequent processes when the number of the condensation defects ranges from 0 to 10.

16. The method for forming a semiconductor structure according to claim 1, wherein: The ion implantation chamber and the transfer chamber are both closed chambers, and a sealed transmission channel is provided between the ion implantation chamber and the transfer chamber, and the wafer to be processed is transferred to the transfer chamber through the sealed transmission channel.

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