Asynchronous SAR analog-to-digital converter

Abstract

The invention discloses an asynchronous SAR analog-to-digital converter which comprises a comparator, an asynchronous clock generation module, a successive approximation module and a perturbation injection module. The comparator accesses a sampling signal and outputs a differential comparison result; the successive approximation module obtains the quantization result of the current bit according to the difference comparison result; the asynchronous clock generation module outputs an asynchronous clock to the comparator so as to control the comparator to execute a comparison process of a current bit through an effective pulse of the current bit of the asynchronous clock; adjacent effective pulses of the asynchronous clock are spaced by a first time delay; the perturbation injection module generates a perturbation signal according to the asynchronous clock and outputs the perturbation signal to the comparator so as to force the comparator to output a differential comparison result of a current bit after the comparator enters a metastable state; the effective pulse of the current bit of the disturbance signal is generated after the second time delay at the starting moment of the effective pulse of the current bit of the asynchronous clock. According to the technical scheme provided by the invention, the metastable state rate of the SAR analog-to-digital converter can be reduced, and data conversion errors are avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converters, and in particular to an asynchronous SAR analog-to-digital converter. Background Art

[0002] With the rapid development of process technology, successive approximation register analog-to-digital converter (SAR ADC) has received more and more attention. In high-speed applications, asynchronous clock SAR ADC is generally used. Since SAR ADC digital quantization is successive, the comparison time left for the comparator is very short, and the comparator is easily in a metastable state, resulting in errors in SAR ADC conversion data.

[0003] Specifically, the SAR ADC will perform multiple comparator comparison processes after each sampling, and each comparison requires a clock to control. The asynchronous clock does not rely on the system clock, but generates the next comparator clock after a certain delay (such as Tr) after each comparison. Comparator metastable occurs when the comparator input voltage is too small. At this time, the comparator output will not be able to get the correct output for a long time, and further cause the asynchronous clock to be unable to generate the next clock for a long time, causing the quantization process to freeze or even terminate, causing the ADC to work abnormally. Summary of the invention

[0004] The embodiment of the present invention provides an asynchronous SAR analog-to-digital converter to reduce the metastable rate of the SAR analog-to-digital converter and avoid errors in data conversion by the SAR analog-to-digital converter.

[0005] The embodiment of the present invention provides an asynchronous SAR analog-to-digital converter, including: a comparator, an asynchronous clock generation module, a successive approximation module and a perturbation injection module;

[0006] The input end of the comparator is used to access the positive terminal voltage and the negative terminal voltage of the sampling signal; the output end of the comparator outputs the differential comparison result; the successive approximation module is connected to the output end of the comparator, and is used to obtain and store the quantization result of the current bit according to the differential comparison result;

[0007] The asynchronous clock generating module is connected to the comparator, and is used to output an asynchronous clock to the comparator, so as to control the comparator to perform a comparison process of the current bit through a valid pulse of the current bit of the asynchronous clock; adjacent valid pulses of the asynchronous clock are separated by a first delay;

[0008] The perturbation injection module is connected to the asynchronous clock generation module and the comparator respectively, and is used to generate a disturbance signal according to the asynchronous clock and output it to the comparator, so that after the comparator enters a metastable state, the effective pulse of the disturbance signal forces the comparator to output a differential comparison result of the current bit; wherein the effective pulse of the current bit of the disturbance signal is generated after a second delay from the start time of the effective pulse of the current bit of the asynchronous clock.

[0009] In the present invention, the asynchronous SAR analog-to-digital converter converts the sampling signal into a multi-bit differential comparison result through a comparator, and the successive approximation module obtains the quantization results of each bit according to the differential comparison result in turn. In the comparison process of the comparator, the asynchronous clock generation module controls the comparator to perform the comparison process of the current bit through the effective pulse of the asynchronous clock, and controls the comparator to perform the next comparison process after the first time delay of the current bit comparison process. The perturbation injection module forms an effective pulse of the disturbance signal after the second time delay at the start of the comparison of the comparator. If the comparator has completed the comparison process of the current bit, the effective pulse of the perturbation signal will not affect the work of the comparator. If the comparator is in a metastable state, the effective pulse of the perturbation signal can force the comparator to output the differential comparison result immediately, end the metastable process, and there will be no interruption of the quantization process, and there will be no major mistakes in the interruption of the asynchronous SAR analog-to-digital converter to convert data. And there will be no interruption of the quantization process, so there is no need to find the digital bit where the metastable state appears in time, so there will be no introduction of the interruption position judgment circuit, and there will be no risk of misjudgment. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural schematic diagram of an asynchronous SAR analog-to-digital converter in the prior art;

[0011] Figure 2 for Figure 1 The comparator clock timing diagram of the asynchronous SAR analog-to-digital converter that has metastable state;

[0012] Figure 3 A schematic diagram of the structure of a SAR analog-to-digital converter provided by an embodiment of the present invention;

[0013] Figure 4 for Figure 3 The comparator clock timing diagram of the asynchronous SAR analog-to-digital converter that has metastable state;

[0014] Figure 5 A schematic diagram of the structure of another SAR analog-to-digital converter provided by an embodiment of the present invention;

[0015] Figure 6 for Figure 5 The comparator clock timing diagram of the asynchronous SAR analog-to-digital converter that has metastable state;

[0016] Figure 7 A schematic structural diagram of an asynchronous SAR analog-to-digital converter according to a comparative example provided by an embodiment of the present invention;

[0017] Figure 8 for Figure 7 The comparator clock timing diagram of the asynchronous SAR analog-to-digital converter that has metastable state;

[0018] Fig. 9 for Figure 7 Comparator clock timing diagram of an asynchronous SAR analog-to-digital converter that experiences metastable state due to latch metastable state. DETAILED DESCRIPTION

[0019] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0020] like Figure 1 As shown, Figure 1 It is a schematic diagram of the structure of an asynchronous SAR analog-to-digital converter in the prior art. The asynchronous SAR analog-to-digital converter is mainly composed of a digital-to-analog converter 11', a comparator 12', a comparison completion detection circuit 13', a successive approximation logic 14' and an asynchronous clock generation circuit 15'. After each sampling is completed, each sampling cycle T1' requires multiple comparator comparisons, and each comparator result is stored in a corresponding position (such as a register) to complete a quantization. For example, the sampling signal is converted by the asynchronous SAR analog-to-digital converter to form a 4-digit digital signal. Each comparator comparison requires clock control. For example Figure 2 As shown, Figure 2 for Figure 1 The comparator clock timing diagram of the asynchronous SAR analog-to-digital converter in the metastable state. In a general synchronous clock system, the comparator clock is generated by the system clock, while in an asynchronous clock system, the comparator clock clkc' is valid (such as pulled high) after a fixed delay (such as Tr') after each comparator comparison is completed, and is reset (such as pulled low) after the comparison is completed, so it does not rely on the system clock. Since the comparator comparison speed is negatively correlated with the comparator input voltage, the comparator clock cycle in the synchronous clock system needs to meet the maximum comparator comparison time, that is, the comparison time corresponding to the minimum input voltage that needs to be distinguished; while in the asynchronous clock system, each comparison time is determined by the size of each input voltage, so it can save extra time overhead, which is beneficial to speed up the working speed of the SAR ADC. For example, Figure 2As shown, in one sampling cycle T1', the asynchronous clock system sequentially completes four comparison processes S1', S2', S3', and S4', and the interval between two adjacent comparison processes is a time period Tr', which effectively speeds up the working speed of the SAR ADC.

[0021] However, due to the working characteristics of the asynchronous clock, if the comparator input voltage is too small (for example, much smaller than the minimum voltage required to be distinguished) during a comparison process, the comparator will need much longer than expected time to get the comparison result. We call this situation metastable. Figure 2 As shown in the figure, in the second sampling cycle T1', after the asynchronous clock system completes the first comparison process S1', the second comparison process S2' takes too long because the comparator input voltage is too small in the second comparison process S2'. When the metastable state occurs, the quantization time of the current sampling will be seriously extended, or even quantization termination will occur, resulting in the failure to complete the current quantization before the next sampling starts, causing the quantization result to be wrong.

[0022] like Figure 2 As shown, a 4-bit SAR ADC is taken as an example. It can be seen that in the first sampling cycle T1', since the input voltage is different each time the comparator works, the effective time of each comparator clock is different (the duration of S2' and S3' is different), and each comparator clock is generated through Tr' after the previous comparison is completed, and finally 4 comparisons are completed before the effective pulse T2' of the next sampling clock arrives, so the first sampling completes the normal quantization. In the second sampling cycle T1', the first comparator comparison S1' is completed in a limited time (sampling cycle T1'), but a metastable state occurs when the second comparator compares S2', which takes up a very long comparison time, resulting in the inability to perform the third and fourth comparisons before the effective pulse of the next sampling clock arrives, resulting in an error in the quantization result.

[0023] In order to effectively avoid the influence of metastable state on data conversion, an embodiment of the present invention provides a SAR analog-to-digital converter, such as Figure 3 As shown, Figure 3 A schematic diagram of the structure of a SAR analog-to-digital converter provided by an embodiment of the present invention includes: a comparator 12, an asynchronous clock generation module 15, a successive approximation module 14 and a perturbation injection module 16;

[0024] The input end of the comparator 12 is used to connect the positive terminal voltage and the negative terminal voltage of the sampling signal; the output end of the comparator 12 outputs the differential comparison result; the successive approximation module 14 is connected to the output end of the comparator 12, and is used to obtain and store the quantization result Dout of the current bit according to the differential comparison result;

[0025] The asynchronous clock generating module 15 is connected to the comparator 12, and is used to output the asynchronous clock clkc to the comparator 12, so as to control the comparator 12 to perform the comparison process of the current bit through the valid pulse of the current bit of the asynchronous clock clkc; the adjacent valid pulses of the asynchronous clock clkc are separated by a first delay Tr;

[0026] The perturbation injection module 16 is respectively connected to the asynchronous clock generation module 15 and the comparator 12, and is used to generate a disturbance signal preamp_rd according to the asynchronous clock clkc and output it to the comparator 12, so that the effective pulse of the disturbance signal preamp_rd forces the comparator 12 to output the differential comparison result of the current bit after the comparator 12 enters the metastable state; wherein the effective pulse of the current bit of the disturbance signal preamp_rd is generated after the second delay Tmeta at the starting time of the effective pulse of the current bit of the asynchronous clock clkc.

[0027] Optionally, the asynchronous clock generating module 15 can also be used to control the effective pulse of the current bit of the asynchronous clock clkc to reset after the comparator 12 completes the comparison process. Then, the end time of the current bit comparison process of the comparator 12 is the end time of the effective pulse of the current bit of the asynchronous clock clkc.

[0028] In the embodiment of the present invention, the asynchronous SAR analog-to-digital converter converts the sampling signal into a multi-bit differential comparison result through a comparator, and the successive approximation module obtains the quantization result of each bit according to the differential comparison result in turn. In the comparison process of the comparator, the asynchronous clock generation module controls the comparator to perform the comparison process of the current bit through the effective pulse of the asynchronous clock, and controls the comparator to perform the next comparison process after the first delay of the current bit comparison process. The perturbation injection module forms an effective pulse of the disturbance signal after the second delay at the start of the comparison of the comparator. If the comparator has completed the comparison process of the current bit, the effective pulse of the perturbation signal will not affect the operation of the comparator. If the comparator is in a metastable state, the effective pulse of the perturbation signal can force the comparator to output the differential comparison result immediately, end the metastable process, and there will be no interruption of the quantization process, and there will be no major mistakes in the asynchronous SAR analog-to-digital converter converting data interruption. And there will be no interruption of the quantization process, so there is no need to find the digital bit where the metastable state appears in time, so there will be no introduction of the interrupt position judgment circuit, and there will be no risk of misjudgment.

[0029] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The input end of the comparator 12 includes a positive input end and a reverse input end, which are respectively connected to the positive terminal voltage and the negative terminal voltage of the sampling signal. The comparator 12 can output a differential comparison result including a positive signal and a negative signal. The successive approximation module 14 quantizes the differential comparison result to form a quantization result Dout. The SAR analog-to-digital converter is used to sample and quantize the analog signal to form a digital signal including multiple digital bits. In each sampling process (each sampling corresponds to a sampling period T1, the comparator 12 needs to undergo multiple comparisons to form multiple differential comparison results. Each differential comparison result corresponds to a quantization result, that is, a numerical bit. The asynchronous clock generation module 15 can generate an asynchronous clock clkc, and the comparison process of the current bit of the comparator 12 is controlled by the valid pulse of the current bit of the asynchronous clock clkc. The valid pulse starts from the starting time (if the high level is valid, it is the rising edge), and the comparator 12 starts to execute the comparison process of the current bit. When the comparator 12 completes the comparison process of the current bit, the asynchronous clock generation module 15 ends the current bit valid pulse (if the high level is valid, it is the falling edge). After that, the asynchronous clock generation module 15 intervals the first delay T r, output the valid pulse corresponding to the next digital bit to control the comparator 12 to start the comparison process of the next bit. It should be noted that the first comparison clock (valid pulse) of the comparator 12 is determined by the delay of the valid pulse T2 of the sampling clock, and the subsequent comparison clocks are generated by the asynchronous clock generation module 15. For example, after the first comparison is completed, the output result of the comparator 12 is valid, and then this valid indication signal is input to the asynchronous clock generation module 15, and the asynchronous clock generation module 15 generates a second comparison clock. Due to the delay of digital logic and the establishment time of the switch capacitor array, the asynchronous clock generation module 15 outputs the comparison clock to the comparator 12 after a certain delay Tr after receiving the valid indication signal, and the cycle continues until the last bit of the sampling point is converted.

[0031] The perturbation injection module 16 generates a perturbation signal preamp_rd according to the asynchronous clock clkc generated by the asynchronous clock generation module 15, and outputs the perturbation signal preamp_rd to the comparator 12 at a second delay Tmeta after the comparison process starts. Figure 4 As shown, Figure 4 for Figure 3 The clock timing diagram of the comparator of the asynchronous SAR analog-to-digital converter in the metastable state. Generally speaking, the disturbance signal preamp_rd is small. If the comparator 12 does not enter the metastable state at this time, such as Figure 4 In the comparison process S1, S3 and S4, the differential comparison result of the comparator will not change due to the disturbance signal preamp_rd. If the comparator enters the metastable state at this time, such as Figure 4In the comparison process S2 in the example, the disturbance signal preamp_rd can force the comparator 12 to output the differential comparison result, and after obtaining the differential comparison result, the asynchronous clock can still generate the next valid pulse and continue to complete the entire quantization process without interrupting the working state. The influence of the metastable state on the SAR analog-to-digital converter is effectively eliminated, and the big mistake of the asynchronous SAR analog-to-digital converter converting data interruption is avoided. In addition, even if the moment when the disturbance signal preamp_rd is injected coincides with the moment when the comparator completes the comparison process, by controlling the time of the second delay Tmeta, it can be ensured that the input of the comparator 12 is much smaller than the minimum voltage required to be distinguished at this time. Therefore, even if the disturbance signal preamp_rd causes an erroneous flip, the final error will still be within a least significant bit (LSB), which is still acceptable.

[0032] Continue to refer Figure 3 Optionally, when no metastable state occurs, the valid pulse of the current bit of the disturbance signal preamp_rd does not cause the comparator to output the differential comparison result of the current bit; when a metastable state occurs, the valid pulse of the current bit of the disturbance signal preamp_rd forces the comparator to output the differential comparison result of the current bit before the valid pulse of the next bit of the asynchronous clock clkc. That is, the end time of the valid pulse of the disturbance signal preamp_rd is earlier than the start time of the valid pulse of the next bit of the asynchronous clock clkc. Therefore, the size of the disturbance signal preamp_rd is selected, and will not cause the comparator to flip when no metastable state occurs, and can ensure that the comparator flips quickly when a metastable state occurs. In this embodiment, the disturbance signal preamp_rd can force the comparator to quickly output the differential comparison result after entering the metastable state, eliminate the interference of the metastable state, and does not affect the next bit comparison process of the comparator.

[0033] Continue to refer Figure 3, Optionally, the comparator 12 may include: an amplifier 121 and a latch 122; the input end of the amplifier 121 is used to access the positive terminal voltage and the negative terminal voltage of the sampling signal; the amplifier 121 is used to output the differential comparison result to the input end of the latch 122 according to the sampling signal; the latch 122 is used to keep the differential comparison result for a comparison cycle and output it to the successive approximation module 14; the asynchronous clock generation module 15 is used to output the asynchronous clock clkc to the latch 122; the perturbation injection module 16 is used to send the perturbation signal preamp_rd to the amplifier 121 or the latch 122. In a real circuit, the comparator 12 can be composed of an amplifier 121 and a latch 122, wherein the amplifier 121 is responsible for amplifying the comparator input to a size that can trigger the latch 122 to latch, and when the latch 122 completes the latching, the comparator completes a comparison process. When the input of the latch 122 is extremely small, the latch 122 cannot trigger the latching, and the comparator enters a metastable state. The latch 122 receives the asynchronous clock clkc. In the metastable state, the perturbation injection module 16 is used to send a perturbation signal preamp_rd to the amplifier 121 or the latch 122, forcing the amplifier 121 or the latch 122 to output a differential comparison result, and can maintain the differential comparison result for a comparison cycle and output it to the successive approximation module 14. It should be noted that in practical applications, the amplifier 121 is not a necessary component of the comparator 12, and the comparator 12 can also be composed of other devices. This embodiment is only explained by taking the above-mentioned composition as a specific example, and does not constitute a limitation on the specific structure of the comparator 12.

[0034] like Figure 3 As shown, optionally, the perturbation injection module 16 may include: a delay circuit 162 and a perturbation generating circuit 161; the delay circuit 162 is used to delay the asynchronous clock clkc by a second delay Tmeta and send it to the perturbation generating circuit 161; the perturbation generating circuit 161 is used to generate a perturbation signal preamp_rd according to the asynchronous clock clkc after the second delay Tmeta. The delay circuit 162 is used to generate the second delay Tmeta, and the perturbation generating circuit 161 is used to inject the perturbation signal preamp_rd after the second delay Tmeta. There are many ways to provide perturbation in this embodiment, including but not limited to using capacitors or switches to provide asymmetric voltage mutations to the differential inputs of the latch 122.

[0035] Figure 5A structural diagram of another SAR analog-to-digital converter provided in an embodiment of the present invention, optionally, a perturbation injection module 16 may include: a reset circuit 17; the reset circuit 17 is connected to the asynchronous clock generation module 15 and the comparator 12 respectively; the reset circuit 17 is used to generate a reset signal preamp_rstn of the comparator 12 according to the asynchronous clock clkc; the effective pulse of the reset signal preamp_rstn is generated by delaying the second delay Tmeta at the start time of the effective pulse of the asynchronous clock clkc; the reset signal preamp_rstn is multiplexed as the perturbation signal preamp_rd. It should be noted that the reset circuit 17 is only an optional module provided in this embodiment, and not all embodiments require the setting of the reset circuit 17. This embodiment only further expands the structure of the SAR analog-to-digital converter in an exemplary manner, but does not serve as a limitation on the SAR analog-to-digital converter.

[0036] Optionally, the end time of the valid pulse of the current bit of the disturbance signal preamp_rd is before the start time of the valid pulse of the next bit of the asynchronous clock clkc. Exemplarily, the effective level of the asynchronous clock clkc is a high level; the effective level of the reset signal preamp_rstn is a low level; then the rising edge of the valid pulse of the current bit of the disturbance signal preamp_rd is before the rising edge of the valid pulse of the next bit of the asynchronous clock clkc. The start time of the valid pulse of the current bit of the reset signal preamp_rstn differs from the start time of the valid pulse of the current bit of the asynchronous clock clkc by a second delay Tmeta.

[0037] Figure 6 for Figure 5 In this embodiment, the perturbation injection module 16 sends a perturbation signal preamp_rd to the amplifier 121 as an example. In this embodiment, the reset operation of the amplifier (preamp) 121 can be used to achieve the perturbation of the latch 122. The specific timing is as follows Figure 6 As shown, a reset signal (such as preamp_rstn, for example, low valid) of the amplifier 121 is generated, the rising edge of preamp_rstn is consistent with the rising edge of clkc (the valid pulse of the next bit), or the rising edge of preamp_rstn is before the rising edge of clkc (the valid pulse of the next bit), and the falling edge of preamp_rstn is generated after a certain delay (such as the second delay Tmeta) from the rising edge of clkc (the valid pulse of the current bit), and the length of the second delay Tmeta should ensure that the comparator can compare the minimum voltage value that needs to be distinguished.

[0038] Normally, the amplifier 121 should be reset after the comparison is completed, such as Figure 6 As shown in the 1st, 3rd, and 4th comparisons in . When a comparison time exceeds Tmeta, such as Figure 6 In the second comparison, the preamp will be reset in advance. Ideally, during the preamp reset process, the output voltage of the preamp is pulled to near the differential mode of 0, but due to the influence of switch mismatch, preamp mismatch, latch mismatch, etc., this process will introduce a non-zero voltage change at the latch input, thus deviating from the current input voltage that triggers the metastable state and forcing the latch to trigger the latch, completing this comparison after a limited comparison time. It is worth noting that this limited comparison time will be much shorter than the comparison time required in the metastable state.

[0039] In the asynchronous clock, clkc always generates the next comparison start signal after a fixed delay Tr after the previous comparison, and this implementation scheme forces the latch to be latched after the metastable state occurs, pulling down clkc so that the asynchronous clock generation circuit can continue to work, so it will not affect the entire asynchronous timing cycle generation process, and the impact on the system structure is minimal. The only thing to note is that the delays need to be arranged reasonably to ensure that the preamp is fully reset before the next clkc arrives in all cases.

[0040] Optionally, the asynchronous SAR analog-to-digital converter may also include: a digital-to-analog converter 11; the digital-to-analog converter 11 is connected to the successive approximation module 14, and is used to obtain a sampling clock signal; the digital-to-analog converter 11 is connected to the comparator 12, and is used to output a sampling signal to the comparator 12 in a sampling cycle; the comparator 12 is used to complete the comparison process of multiple digital bits in sequence in a sampling cycle.

[0041] Optionally, the asynchronous SAR analog-to-digital converter may also include: a comparison completion detection circuit 13; the comparison completion detection circuit 13 is connected to the output end of the comparator 12, and is used to output a valid indication signal comp_ready to the asynchronous clock generation module 15 when the differential comparison result is detected to be valid; the asynchronous clock generation module 15 is used to output a valid pulse to the comparator 12 after a first delay Tr.

[0042] This embodiment finds an asynchronous SAR analog-to-digital converter for eliminating metastable states from the prior art, which has a comparative significance with the embodiment of the present invention. This embodiment can be called a comparative example. Figure 7 As shown, Figure 7A schematic diagram of the structure of an asynchronous SAR analog-to-digital converter of a comparative example provided by an embodiment of the present invention. In the prior art, the solution to the metastable state of the asynchronous SAR ADC can be called a "metastable-then-set" type, that is, by monitoring the working state of the comparator, and generating a metastable flag signal (such as MD) when the metastable state is detected, and terminating the operation of the comparator, retaining the existing comparator output and storing it in a register, and assigning a specific code word (such as 100...00 or 011...11) to the register of the remaining unobtained comparator output through the digital output correction module 16', at this time, the maximum output error is 1 least significant bit (LSB), which is an acceptable error range, so the metastable rate can be effectively reduced. Figure 8 for Figure 7 The comparator clock timing diagram of the asynchronous SAR analog-to-digital converter in the metastable state. Figure 8 As shown, it can be seen that compared with Figure 1 The structure of the traditional asynchronous SAR analog-to-digital converter in FIG. 1 has a metastable monitoring module 17' and a digital codeword correction module 16'. The metastable monitoring module 17' is composed of a comparison time monitoring circuit 171' and a latch 172'. When the comparison time of this comparison exceeds a preset value (such as Tmeta), Figure 8 In the second comparison process S2, the comparison time monitoring circuit 171' outputs Tm is valid, and latches the generated MD signal through the latch 172', terminating the further operation of the comparator, and combines the output comparison result with a specific code word (such as 100...00 or 011...11) through the digital output correction module 16' to generate an output result Dout with an error range not exceeding 1LSB, effectively reducing the metastable rate.

[0043] The problem with the prior art is that it requires an additional metastable monitoring module 17' and a digital output correction module 16', which increases the circuit overhead. More importantly, since the metastable monitoring module 17' requires the participation of a latch structure in order to generate the MD flag, and the latch structure itself may also encounter a metastable state, which may cause the flag to be generated at a time that is inconsistent with expectations. At the same time, since the "Metastable-then-set" technology will interrupt the normal quantization process of the ADC, if the metastable state of the latch 172' causes the generation of the MD flag to appear after the current bit codeword is latched, the next bit comparison process will be terminated prematurely, and the subsequent digital correction will introduce serious output errors.

[0044] Fig. 9 for Figure 7 Comparator clock timing diagram of an asynchronous SAR analog-to-digital converter that experiences metastable state due to latch metastable state. Fig. 9The timing when the latch metastable state causes an erroneous metastable state judgment, wherein the second bit comparison duration is only slightly longer than Tmeta, and Tm is only valid when the comparison time exceeds Tmeta and before the current bit comparison is completed, resulting in the Tm signal to produce an extremely narrow pulse width. Since the latch 172' has requirements for the effective duration of the input signal Tm, it may cause the latch 172' to enter a metastable state, and the MD signal output by the latch 172' is only partially established and not fully effective, and the MD signal may be established in the next bit. If the MD signal is established in the next bit, such as when the third bit is compared, it will cause the ADC to have an erroneous quantization interrupt at the third bit and assign values ​​to the remaining codewords instead of the second bit. Since the third bit does not have a metastable state, forcing the remaining codewords to be assigned will result in a huge error.

[0045] It can be seen from the above comparative scheme that the "Metastable-then-set" type asynchronous SAR analog-to-digital converter obtains the metastable state in time by monitoring the metastable state, and stops the quantization process at this moment, which not only causes the next comparison process to be terminated in advance, but also the subsequent digital correction will introduce serious output errors. The above comparative scheme has a large error, while the scheme of the embodiment of the present invention does not involve the monitoring of the metastable state, but is only achieved by introducing a perturbation through a fixed delay. Therefore, it does not involve triggering the metastable state of the relevant metastable monitoring module, and achieves stable metastable elimination. The present embodiment avoids the use of a metastable monitoring module, thereby avoiding the occurrence of relevant determination circuits, such as the metastable state of the metastable monitoring module, from the root, and realizes a stable and reliable scheme for reducing the metastable rate. Moreover, compared with the comparative example, the present embodiment introduces fewer new modules and has a lower manufacturing cost.

[0046] In summary, the core idea of ​​the embodiment of the present invention is to inject a perturbation into the comparator after waiting for a constant time delay (such as Tmeta) after the comparator starts comparison. If the comparator has completed the comparison, the perturbation will not affect the comparison result; if the comparator is in a metastable state, the perturbation can force the comparator to obtain a comparison result, thereby eliminating the influence of the metastable state of the comparator on the asynchronous clock SAR ADC, reducing the metastable rate of the SAR analog-to-digital converter, and avoiding errors in the conversion data of the SAR analog-to-digital converter.

[0047] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An asynchronous SAR analog-to-digital converter, characterized in that: include: Comparator, asynchronous clock generation module, successive approximation module and perturbation injection module; The input end of the comparator is used to access the positive terminal voltage and the negative terminal voltage of the sampling signal; the output end of the comparator outputs the differential comparison result; the successive approximation module is connected to the output end of the comparator, and is used to obtain and store the quantization result of the current bit according to the differential comparison result; The asynchronous clock generating module is connected to the comparator, and is used to output an asynchronous clock to the comparator, so as to control the comparator to perform a comparison process of the current bit through a valid pulse of the current bit of the asynchronous clock; adjacent valid pulses of the asynchronous clock are separated by a first delay; The perturbation injection module is connected to the asynchronous clock generation module and the comparator respectively, and is used to generate a disturbance signal according to the asynchronous clock and output it to the comparator, so that after the comparator enters a metastable state, the effective pulse of the disturbance signal forces the comparator to output a differential comparison result of the current bit; wherein the effective pulse of the current bit of the disturbance signal is generated after a second delay from the start time of the effective pulse of the current bit of the asynchronous clock.

2. The asynchronous SAR analog-to-digital converter according to claim 1, characterized in that: When the metastable state does not occur, the effective pulse of the current bit of the disturbance signal does not cause the differential comparison result of the current bit output by the comparator to change; When a metastable state occurs, a valid pulse of a current bit of the disturbance signal forces the comparator to output a differential comparison result of the current bit before a valid pulse of a next bit of the asynchronous clock.

3. The asynchronous SAR analog-to-digital converter according to claim 1, characterized in that: The comparator comprises: an amplifier and a latch; The input end of the amplifier is used to access the positive terminal voltage and the negative terminal voltage of the sampling signal; the amplifier is used to output the differential comparison result to the input end of the latch according to the sampling signal; the latch is used to keep the differential comparison result for a comparison cycle and output it to the successive approximation module; The asynchronous clock generating module is used for outputting the asynchronous clock to the latch; the perturbation injection module is used for sending the perturbation signal to the amplifier or the latch.

4. The asynchronous SAR analog-to-digital converter according to claim 1, characterized in that: The perturbation injection module includes: a delay circuit and a perturbation generation circuit; The delay circuit is used for delaying the asynchronous clock by the second time delay and sending it to the perturbation generating circuit; the perturbation generating circuit is used for generating the perturbation signal according to the asynchronous clock after being delayed by the second time delay.

5. The asynchronous SAR analog-to-digital converter according to claim 1, characterized in that: The perturbation injection module comprises: a reset circuit; The reset circuit is connected to the asynchronous clock generating module and the comparator respectively; The reset circuit is used to generate a reset signal of the comparator according to the asynchronous clock; the effective pulse of the reset signal is delayed by the second delay at the starting time of the effective pulse of the asynchronous clock; and the reset signal is multiplexed as the disturbance signal.

6. The asynchronous SAR analog-to-digital converter according to claim 5, characterized in that: The end time of the valid pulse of the current bit of the disturbance signal is before the start time of the valid pulse of the next bit of the asynchronous clock.

7. The asynchronous SAR analog-to-digital converter according to claim 1, characterized in that: Also includes: Digital to analog converters; The digital-to-analog converter is connected to the successive approximation module to obtain a sampling clock signal; the digital-to-analog converter is connected to the comparator to output a sampling signal to the comparator in a sampling cycle; The comparator is used to sequentially complete the comparison process of multiple digital bits in one sampling cycle.

8. The asynchronous SAR analog-to-digital converter according to claim 2, characterized in that: Also includes: Comparison completion detection circuit; The comparison completion detection circuit is connected to the output end of the comparator, and is used to output a valid indication signal to the asynchronous clock generation module when detecting that the differential comparison result is valid; The asynchronous clock generating module is used for outputting a valid pulse to the comparator after the first time delay.

9. The asynchronous SAR analog-to-digital converter according to claim 1, characterized in that: The asynchronous clock generating module is further used to control the valid pulse of the current bit of the asynchronous clock to be reset after the comparator completes the comparison process.

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