Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes a plurality of processes. An oxide layer is formed on the isolation trench on the substrate. A liner layer is formed on the oxide layer. And oxidizing the lining layer. After the liner layer is oxidized, an implant region is formed on the substrate. Forming a character line structure on the substrate, wherein the character line structure crosses the oxide layer and the lining layer; therefore, the designed pattern is prevented from being damaged, and the process can be saved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] In the process of manufacturing a memory device (e.g., a DRAM device), an active area may be defined on a substrate by a hard mask. An oxide material and a liner may be filled in a plurality of isolation trenches defined on the substrate. However, due to the difference in etching rates between the oxide material and the liner, unexpected bumps may appear on the mask layer formed on the oxide material and the liner, and these unexpected bumps may affect the designed pattern.

[0003] Therefore, how to reduce the generation of unexpected bumps is one of the problems that technicians in the field want to solve. Summary of the invention

[0004] One aspect of the present invention relates to a method of forming a semiconductor structure.

[0005] According to one or more embodiments of the present invention, a method for forming a semiconductor structure includes multiple processes. An oxide layer is formed in an isolation trench on a substrate. A liner is formed on the oxide layer. The liner is oxidized. After the liner is oxidized, an implantation region is formed on the substrate. A word line structure is formed on the substrate, wherein the word line structure crosses the oxide layer and the liner.

[0006] In one or more embodiments of the present invention, the liner is oxidized to have an unoxidized liner portion and an oxidized liner portion above the unoxidized liner portion. The oxidized liner portion extends to the isolation trench.

[0007] In one or more embodiments of the present invention, the method of forming a semiconductor structure further includes forming a semiconductor layer on a substrate and in an isolation trench, wherein the liner is oxidized to have an unoxidized liner portion and an oxidized liner portion above the unoxidized liner portion, and the bottom surface of the oxidized liner portion is lower than the top surface of the semiconductor layer.

[0008] In one or more embodiments of the present invention, the method of forming a semiconductor structure further includes forming a sacrificial oxide layer on the oxide layer and the liner after the liner is oxidized, wherein the implantation region is formed by an implantation process through the sacrificial oxide layer.

[0009] In one or more embodiments of the present invention, the method for forming a semiconductor structure further includes a plurality of processes. A hard mask is formed on the oxide layer and the liner. The hard mask is patterned so that the oxide layer and the oxide liner portion of the liner are exposed. A word line trench is etched across the oxide layer and the liner based on the hard mask, wherein a word line structure is formed in the word line trench.

[0010] In some embodiments, the word line trench is etched so that the oxide liner portion of the liner is cut into a first portion and a second portion separated from each other.

[0011] In one or more embodiments of the present invention, before the liner is oxidized, the liner is an oxygen-free layer.

[0012] One aspect of the present invention relates to a method of forming a semiconductor structure.

[0013] According to one or more embodiments of the present invention, a method for forming a semiconductor structure includes multiple processes. An isolation trench is formed on a substrate. A first oxide layer is formed on the isolation trench. A liner is formed on the first oxide layer. A second oxide layer is formed on the liner. The second oxide layer is polished so that the first oxide layer and the liner are exposed. The liner is oxidized. An implantation region is formed on the substrate. A word line structure is formed on the substrate across the isolation trench.

[0014] In one or more embodiments of the present invention, the liner is oxidized to have an unoxidized liner portion and an oxidized liner portion over the unoxidized liner portion, the oxidized liner portion extending to the isolation trench.

[0015] In some embodiments, after the word line structure is formed, the second oxide layer remains between oxide liner portions of the liner of one of the isolation trenches in the peripheral region outside the word line structure.

[0016] In one or more embodiments of the present invention, the method of forming a semiconductor structure further includes forming a sacrificial oxide layer on the first oxide layer, the liner layer and the second oxide layer after the liner layer is oxidized, wherein the implantation region is formed by an implantation process through the sacrificial oxide layer.

[0017] In one or more embodiments of the present invention, the method for forming a semiconductor structure further includes a plurality of processes. A hard mask is formed on the first oxide layer and the liner. The hard mask is patterned so that the oxide liner portion of the first oxide layer and the liner is exposed. A word line trench is etched across the oxide layer and the liner based on the hard mask, wherein the word line structure is formed in the word line trench.

[0018] In one or more embodiments of the present invention, before the liner is oxidized, the liner is an oxygen-free layer.

[0019] One aspect of the present invention relates to a semiconductor structure.

[0020] According to one or more embodiments of the present invention, a semiconductor structure includes a first isolation region and a word line structure. The first isolation region is located on a substrate. The first isolation region includes a first oxide layer and a first liner on the first oxide layer. The first liner has a first unoxidized liner portion and a first oxidized liner portion located above the first unoxidized liner portion. The word line structure crosses the first isolation region. The first portion and the second portion of the first unoxidized liner portion are separated from each other by the word line structure.

[0021] In one or more embodiments of the present invention, the semiconductor structure further includes a second isolation region. The second isolation region is located on the substrate. The second isolation region includes a second liner having a second oxide liner portion. The first portion and the second portion of the second oxide liner portion are separated from each other by a word line structure.

[0022] In some embodiments, the semiconductor structure further includes an active implantation region, wherein the active implantation region is located between a first oxide liner portion of the first liner layer and a second oxide liner portion of the second liner layer.

[0023] In one or more embodiments of the present invention, the semiconductor structure further includes a second isolation region. The second isolation region is located on the substrate. The second isolation region includes a second oxide layer, a second liner on the second oxide layer, and a third oxide layer on the second liner. The second liner has a second unoxidized liner portion and a second oxidized liner portion on the second unoxidized liner portion. The second oxidized liner portion is located between the second oxide layer and the third oxide layer.

[0024] In some embodiments, the second isolation region is outside the word line structure.

[0025] In one or more embodiments of the present invention, the material of the first oxide liner portion is different from the material of the first oxide layer.

[0026] In one or more embodiments of the present invention, the semiconductor structure further comprises a semiconductor layer. The semiconductor layer is located on the substrate. The bottom surface of the first oxide liner portion is lower than the top surface of the semiconductor layer.

[0027] In summary, in one or more embodiments of the present invention, an oxidation process can be performed on the liner in the isolation structure. In this way, since the etching selectivity between the oxidized liner and the oxide layer is reduced, the design pattern of the memory device is prevented from being damaged by bumps that are not expected to be generated due to the etching selectivity between the liner and the oxide layer, and the additional planarization process performed on the mask layer on the isolation structure for removing the bumps that are not expected to be generated is omitted.

[0028] The above description is only used to illustrate the problems to be solved by the present invention, the technical means to solve the problems, and the effects produced, etc. The specific details of the present invention will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The advantages and advantages of the present invention should be better understood by referring to the following embodiments and the accompanying drawings. The description of these drawings is only an example of the embodiments, and therefore should not be considered to limit the individual embodiments or the scope of the invention claims.

[0030] Figure 1 A schematic cross-sectional view of forming an anti-reflection layer on a hard mask on a substrate according to one or more embodiments of the present invention is shown;

[0031] Figure 2 A schematic cross-sectional view of a patterned hard mask and etching a substrate based on the patterned hard mask is shown according to one or more embodiments of the present invention;

[0032] Figure 3 A schematic cross-sectional view showing the removal of a hard mask and an anti-reflective layer according to one or more embodiments of the present invention;

[0033] Figure 4 A schematic cross-sectional view of forming a semiconductor layer on a top surface of a substrate and in an isolation trench according to one or more embodiments of the present invention is shown;

[0034] Figure 5 A schematic cross-sectional view of forming a first oxide layer on a semiconductor layer according to one or more embodiments of the present invention is shown;

[0035] Figure 6 A schematic cross-sectional view of forming a liner on a first oxide layer according to one or more embodiments of the present invention is shown;

[0036] Figure 7 A schematic cross-sectional view of forming a second oxide layer on a liner according to one or more embodiments of the present invention is shown;

[0037] Figure 8 A schematic cross-sectional view of polishing a second oxide layer according to one or more embodiments of the present invention is shown;

[0038] Fig. 9 A schematic cross-sectional view of etching a first oxide layer, a liner layer, and a second oxide layer is shown according to one or more embodiments of the present invention;

[0039] Fig.10 A schematic cross-sectional view of an oxide liner is shown according to one or more embodiments of the present invention;

[0040] Fig.11 A schematic cross-sectional view of forming a sacrificial oxide layer on a first oxide layer, a liner layer, and a second oxide layer according to one or more embodiments of the present invention is shown;

[0041] Fig.12 A schematic cross-sectional view of forming an implantation region on a substrate according to one or more embodiments of the present invention is shown;

[0042] Fig.13 A schematic cross-sectional view of removing a sacrificial oxide layer according to one or more embodiments of the present invention is shown;

[0043] Fig.14 A schematic cross-sectional view of forming a mask layer on a first oxide layer, a liner layer, and a second oxide layer according to one or more embodiments of the present invention is shown;

[0044] Fig.15 A schematic top view of a patterned mask layer is shown according to one or more embodiments of the present invention; and

[0045] FIG. 16A to FIG. 16E Schematic top views and cross-sectional views of semiconductor structures are shown in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION

[0046] The following examples are described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention, and the description of the structural operation is not intended to limit the order of its execution. Any device with equal functions produced by the re-combination of components is within the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in their original size. For ease of understanding, the same or similar components in the following description will be indicated by the same symbols.

[0047] In addition, the terms used throughout the specification and claims generally have the ordinary meaning of each term used in this field, in the content disclosed herein, and in the specific content, unless otherwise noted. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the present invention.

[0048] Herein, the terms “first”, “second”, etc. are only used to distinguish elements or operating methods with the same technical terms, and are not intended to indicate an order or to limit the present invention.

[0049] In addition, the words "include", "including", "provide" and similar terms are open-ended limitations in this article, meaning including but not limited to.

[0050] Further, in this article, unless the text specifically limits the article, "a", "an" and "the" may refer to a single one or more. It will be further understood that "comprising", "including", "having" and similar words used in this article indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude the described or additional one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0051] In a memory device, an active area can be defined by forming a plurality of isolation structures. In some embodiments, the isolation structure may include a plurality of oxide layer liners. For example, the material of the plurality of oxide layers may include silicon oxide, and the material of the liner may include silicon nitride. In the manufacturing process of a semiconductor device, since the oxide layer and the liner of the isolation structure are formed of different materials with different etching rates, after the oxide layer and the liner are etched, the residual heights of the oxide layer and the liner will be different. Subsequently, when a mask layer is formed on the isolation structure of the oxide layer and the liner to form a word line structure of a memory device, a plurality of unexpected bumps will be formed on the mask layer due to the different residual heights between the oxide layer and the liner. The bumps on the mask layer will affect the design pattern of the memory device. In some embodiments, an additional planarization process needs to be performed on the mask layer with bumps to remove the unexpected bumps and avoid damage to the design pattern.

[0052] In one or more embodiments of the present invention, an oxidation process can be performed on the liner in the isolation structure. The oxidized portion of the liner can have a similar etching rate as the oxide layer. After performing an etching process for forming the isolation structure of the liner and the oxide layer in the formed isolation trench, the oxide layer and the liner can have similar residual heights. Therefore, after a mask layer is subsequently formed on the isolation structure, little or no accidental bumps are formed on the mask layer. In this way, damage to the design pattern of the memory device can be avoided, and an additional planarization process performed on the mask layer on the isolation structure can be saved.

[0053] Please refer to Figures 1 to 16E , to illustrate the formation according to one or more embodiments of the present invention, wherein the formed semiconductor structure can be used as a memory device.

[0054] Figure 1 A schematic cross-sectional view of forming an anti-reflection layer 210 on a hard mask 220 on a substrate 110 is shown according to one or more embodiments of the present invention. In one or more embodiments of the present invention, the substrate 110 may be a semiconductor substrate, such as a silicon substrate. The anti-reflection layer 210 may be a silicon oxide layer formed by a thermal process. The hard mask 220 may be a tetraethoxysilane (TEOS) layer deposited on the anti-reflection layer 210.

[0055] Figure 2 According to one or more embodiments of the present invention, a schematic cross-sectional view of a patterned hard mask 220 and etching of a substrate 110 based on the patterned hard mask 220 is depicted. In one or more embodiments of the present invention, a photoresist layer may be formed on the hard mask 220 and developed into a photoresist layer having a design pattern. Subsequently, the hard mask 220 may etch the developed photoresist layer, thereby transferring the design pattern on the developed photoresist layer to the hard mask 220. After the hard mask 220 is patterned, the substrate 110 is etched according to the patterned hard mask 220. A plurality of isolation trenches 115 and isolation trenches 120 are formed on the substrate 110, and the isolation trenches 115 and isolation trenches 120 are recessed from the upper surface of the substrate 110. In some embodiments, the isolation trenches 115 and isolation trenches 120 in the substrate 110 may be formed by a dry etching process. The isolation trenches 115 and isolation trenches 120 may be used to accommodate isolation structures formed subsequently.

[0056] like Figure 2 As shown, the design pattern of the hard mask 220 can further define the device area DA and the peripheral area PA outside the device area DA. The isolation trench 115 in the device area DA can be used to define the active area of ​​the word line structure in the memory device. A plurality of peripheral circuits connected to the components (such as the word line structure) can be formed in the peripheral area PA. The isolation trench 120 can be used to isolate the peripheral circuits in the peripheral area PA. In some embodiments, as Figure 2 As shown, the width of each isolation trench 115 is smaller than the width of the isolation trench 120. The density of the isolation trenches 115 in the device area DA may be greater than the density of the isolation trenches 120 in the peripheral area PA.

[0057] Figure 3 A schematic cross-sectional view of removing the hard mask 220 and the anti-reflection layer 210 is shown according to one or more embodiments of the present invention. After the isolation trenches 115 and 120 are formed, the hard mask 220 and the anti-reflection layer 210 will be removed. In some embodiments, the hard mask 220 of TEOS and the anti-reflection layer 210 of silicon oxide can be removed by a dry etch post-clean process and a wet chemical removal process.

[0058] Figure 4A schematic cross-sectional view of forming a semiconductor layer 125 on the top surface of the substrate 110 and in the isolation trench 115 is shown according to one or more embodiments of the present invention. In some embodiments, the formation of the semiconductor layer 125 can be used to expand the area of ​​the active region in the device area DA. The material of the semiconductor layer 125 can be the same as that of the substrate 110. In this embodiment, the substrate 110 is a silicon substrate, and the semiconductor layer 125 is a silicon thin film deposited on the substrate 110.

[0059] The formed semiconductor layer 125 can be regarded as an extension of the substrate 110 . After the semiconductor layer 125 is formed, the isolation trench 115 and the isolation trench 120 can be redefined as trenches extending downward from the top surface of the semiconductor layer 125 to the substrate 110 .

[0060] Figure 5 According to one or more embodiments of the present invention, a schematic cross-sectional view of forming a first oxide layer 130 on a semiconductor layer 125 is shown. In this embodiment, the first oxide layer 130 is a silicon oxide layer. In one or more embodiments of the present invention, the first oxide layer 130 of the silicon oxide layer can be formed by depositing a silicon layer on the semiconductor layer 125 and then oxidizing the silicon layer.

[0061] like Figure 5 As shown, due to the loading effect of the first oxide layer 130, the top surface of the first oxide layer 130 adjacent to the isolation trench 120 in the peripheral area PA is higher than the top surface of the first oxide layer 130 adjacent to the isolation trench 115 in the device area DA. Since the width of each isolation trench 115 is smaller than the width of the isolation trench 120, and the density of the isolation trenches 115 in the device area DA is greater than the density of the isolation trenches 120 in the peripheral area PA, the deposition amount of the first oxide layer 130 in the device area DA is less than the deposition amount of the first oxide layer 130 in the peripheral area PA.

[0062] Figure 6 A schematic cross-sectional view of forming a liner 135 on the first oxide layer 130 is shown according to one or more embodiments of the present invention. In this embodiment, the liner 135 may be a silicon nitride layer conformally deposited on the silicon oxide first oxide layer 130. In some embodiments, the liner 135 may be an oxygen-free layer covering the first oxide layer 130.

[0063] exist Figure 6 , in the device area DA, the isolation trench 115 is filled with the first oxide layer 130 and the liner 135 , and because the width of the isolation trench 120 is greater than the width of each isolation trench 115 , the isolation trench 120 in the peripheral area PA is not filled with the first oxide layer 130 and the liner 135 .

[0064] Figure 7A schematic cross-sectional view of forming a second oxide layer 140 on the liner 135 is shown according to one or more embodiments of the present invention. In this embodiment, the second oxide layer 140 may be silicon oxide conformally deposited on the silicon nitride liner 135. Figure 7 In the embodiment, the isolation trench 120 in the peripheral area PA is filled with the first oxide layer 130, the liner 135 and the second oxide layer 140 after the second oxide layer 140 is formed. The second oxide layer 140 has a groove recessed from the top surface of the second oxide layer 140 and aligned with the isolation trench 120.

[0065] Figure 8 A schematic cross-sectional view of polishing the second oxide layer 140 is shown according to one or more embodiments of the present invention. In this embodiment, after the second oxide layer 140 of silicon oxide is formed, a chemical mechanical polishing (CMP) process is performed on the second oxide layer 140. According to the difference in polishing rate between the second oxide layer 140 and the liner layer 135, the CMP process on the second oxide layer 140 may stop at the top surface of the nitrided silicon liner layer 135.

[0066] Fig. 9 According to one or more embodiments of the present invention, a schematic cross-sectional view of etching the first oxide layer 130, the liner 135, and the second oxide layer 140 is shown. In this embodiment, the first oxide layer 130 and the second oxide layer 140 are silicon nitride, the liner 135 is silicon nitride, and an etching process having a low etching selectivity with respect to silicon oxide and silicon nitride is performed on the first oxide layer 130, the liner 135, and the second oxide layer 140.

[0067] like Fig. 9 As shown, after the etching process is completed, the first oxide layer 130 and the liner 135 are exposed. The second oxide layer 140 in the device area DA is removed, and the second oxide layer 140 remains in the isolation trench 120 in the peripheral area PA. The horizontal portion of the liner 135 extending on the first oxide layer 130 is removed. The remaining liner 135 has a plurality of liner portions extending from the upper surface of the first oxide layer 130 to the isolation trench 115 in the device area DA or the isolation trench 120 in the peripheral area PA. The liner 135 remaining in the isolation trench 120 is located between the first oxide layer 130 and the second oxide layer 140.

[0068] Fig.10A schematic cross-sectional view of an oxidation liner 135 is depicted according to one or more embodiments of the present invention. In one or more embodiments of the present invention, the liner 135 may be oxidized by a low temperature plasma oxidation process. For example, the low temperature plasma oxidation process for oxidizing the liner 135 may be an oxygen plasma oxidation process at a low process temperature. In this embodiment, the exposed top portion of the silicon nitride liner 135 is oxidized and converted into an oxidation liner portion 137 of silicon oxynitride, and the bottom portion of the liner 135 remains and may be regarded as an unoxidized liner portion 136. It should be noted that since the first oxide layer 130 and the second oxide layer 140 are oxides, the oxidation process of the liner 135 can be performed without changing the composition of the first oxide layer 130 and the second oxide layer 140.

[0069] In one or more embodiments of the present invention, the first oxide layer 130, the second oxide layer 140 and the oxide liner portion 137 of the oxide liner 135 may be oxides with similar etching rates. Due to the presence of the oxide liner portion 137, the etching selectivity of the liner 135, the first oxide layer 130 and the second oxide layer 140 may be reduced.

[0070] In this embodiment, the oxidized liner portion 137 of silicon oxynitride covers the unoxidized liner portion 136 of silicon nitride. Once the oxidized liner portion 137 to be etched is completely removed, the unoxidized liner portion 136 will be exposed, wherein the etching rate of the unoxidized liner portion 136 is different from that of the first oxide layer 130 and the second oxide layer 140. Therefore, the oxidized liner portion 137 can be designed to have a sufficient length for etching. Fig.10 As shown, the length of the oxidation liner portion 137 extends into the isolation trench 115 and the isolation trench 120. In some embodiments, the length of the oxidation liner portion 137 can be controlled by adjusting the plasma conditions of the plasma oxidation process, and the oxidation liner portion 137 can have a longer length extending into the isolation trench 115 and the isolation trench 120. Fig.10 As shown, a height 137B of a bottom surface of the oxide liner portion 137 is lower than a height 125T of a top surface of the semiconductor layer 125 .

[0071] In one or more embodiments of the present invention, the process temperature of the plasma oxidation process for oxidizing the liner 135 can be controlled to avoid excessive damage to the first oxide layer 130, the liner 135, and the second oxide layer 140 and to avoid heating the substrate 110. Fig. 9 and Fig.10As shown, after the liner 135 is subjected to the low temperature plasma oxidation process, the first oxide layer 130, the liner 135 and the upper portion of the second oxide layer 140 may be removed by plasma. In some embodiments, the low temperature plasma oxidation process for oxidizing the liner 135 may be performed at a process temperature in the range of 25°C to 250°C.

[0072] like Fig.10 As shown, the oxide liner portion 137 in the device area DA is located between portions of the first oxide layer 130. The oxide liner portion 137 in the peripheral area PA is located between the first oxide layer 130 and the second oxide layer 140.

[0073] Fig.11 According to one or more embodiments of the present invention, a schematic cross-sectional view of forming a sacrificial oxide layer 145 on the first oxide layer 130, the liner 135 (including the unoxidized liner portion 136 and the oxidized liner portion 137), and the second oxide layer 140 is shown. In this embodiment, the sacrificial oxide layer 145 may be a silicon oxide layer formed on the first oxide layer 130, the liner 135, and the second oxide layer 140 by a deposition process.

[0074] Fig.12 A schematic cross-sectional view of forming an implantation region 111 on a substrate 110 is shown according to one or more embodiments of the present invention. Fig.12 As shown, an implantation process IM is performed on the substrate 110 and the semiconductor layer 125 through the sacrificial oxide layer 145 and the first oxide layer 130 to form an implantation region 111 between the isolation trenches 115. In the device area DA, the first oxide layer 130 and the liner 135 form an isolation structure in the isolation trench 115, and the implantation region 111 in the device area DA can be defined as one of the active regions between the isolation structures in the isolation trench 115. In some embodiments, the implantation region 111 can be regarded as a semiconductor well having a semiconductor type (such as p-type or n-type). In some embodiments, the implantation region 111 can be formed by multiple cycles of an implantation process of the sacrificial oxide layer 145 and a cleaning process.

[0075] Fig.13 A schematic cross-sectional view of removing the sacrificial oxide layer 145 is shown according to one or more embodiments of the present invention. After the implantation region 111 is formed, the sacrificial oxide layer 145 may be removed by an etching process. In this embodiment, since the first oxide layer 130, the second oxide layer 140, the sacrificial oxide layer 145, and the oxidized liner portion 137 of the liner 135 are all oxides, the etching selectivity of the etching process of the sacrificial oxide layer 145 may be reduced for the first oxide layer 130, the second oxide layer 140, the sacrificial oxide layer 145, and the oxidized liner portion 137 of the liner 135. Fig.13As shown, after the sacrificial oxide layer 145 is removed, the top surface of the oxide liner portion 137 of the liner 135 , the top surface of the first oxide layer 130 , and the top surface of the second oxide layer 140 may be coplanar.

[0076] Fig.14 A schematic cross-sectional view of forming a mask layer 150 on the first oxide layer 130, the oxide liner portion of the liner 135, and the second oxide layer 140 is shown according to one or more embodiments of the present invention. In this embodiment, the mask layer 150 may be a silicon nitride layer formed by a deposition process. The mask layer 150 may be used to form a word line structure in the device area DA.

[0077] Fig.15 A schematic top view of a patterned mask layer 150 is shown in accordance with one or more embodiments of the present invention. Fig.15 A schematic top view of the device area DA is shown. Fig.15 In the embodiment, the mask layer 150 is patterned and has an opening 151, exposing the semiconductor layer 125 on the substrate 110 and the isolation structure in the isolation trench 115. The isolation structure in the isolation trench 115 includes a first oxide layer 130 and an oxide liner 135. Fig.15 As shown, the oxide liner portion 137 of the oxide liner 135 is exposed from the opening 151 of the mask layer 150. In one embodiment, the opening 151 is outside the peripheral area PA and is not related to the peripheral area PA, and the word line structure is not formed in the peripheral area PA.

[0078] FIG. 16A to FIG. 16E A schematic top view and cross-sectional view of a semiconductor structure are shown according to one or more embodiments of the present invention, wherein Fig.16A A schematic top view is shown. Fig. 16B For the sake of clarity, the relative Fig.16A A schematic top view of the mask layer 150 having a height higher than the top surface of the semiconductor layer 125 is omitted.

[0079] In the device area DA, after the mask layer 150 is patterned, the substrate 110, the semiconductor layer 125, and the isolation structure (including the first oxide layer 130 and the liner 135 in the isolation trench 115) are etched to form a word line trench 165 spanning the first oxide layer 130 and the liner 135 in the isolation trench 115. Subsequently, a word line structure 160 is formed in the word line trench 165. The word line structure 160 includes a dielectric layer 161 in the word line trench 165 and a conductive layer 162 on the dielectric layer 161. After the word line structure 160 is formed, a semiconductor structure is formed, wherein the semiconductor structure includes the isolation structure formed by the first oxide layer 130 and the liner 135 in the isolation trench 115 and the word line structure 160 in the word line trench 165.

[0080] After the word line structure 160 is formed, the mask layer 150 remaining on the semiconductor layer 125 may be used as a mask layer for forming a bit line or a dielectric layer covering the semiconductor layer 125 .

[0081] like Fig. 16B and Fig.16E As shown, each oxide liner portion 137 of the oxide liner 135 is cut into two separated oxide liner portions 1371 and 1372 . Fig.16E A schematic cross-sectional view along two separate oxide liner portions 1371 and 1372 is shown.

[0082] Fig. 16C A schematic cross-sectional view of two adjacent isolation structures along the isolation trench 115 is shown, wherein an oxidized liner portion 137 of the liner 135 remains in the formed semiconductor structure.

[0083] Fig.16D is a schematic cross-sectional view of the word line structure 160 and the implantation region 111. Fig.16D In the embodiment, the implantation region 111 is cut into two separate implantation regions 1111 and 1112. In some embodiments, the implantation regions 1111 and 1112 can be used as source / drain regions, the dielectric layer 161 and the conductive layer 162 of the word line structure 160 form a gate structure, and the source / drain regions of the implantation regions 1111 and 1112 and the gate structure of the dielectric layer 161 and the conductive layer 162 form a transistor in the device area DA. In one or more embodiments of the present invention, a larger number of implantation regions 111 and word line structures 160 can be formed in the device area DA to form a transistor array for a memory device.

[0084] In summary, in one or more embodiments of the present invention, an oxidation process may be performed on the liner in the isolation structure. The oxidized portion of the liner and the oxide layer may have similar etching rates. Therefore, after a mask layer is subsequently formed on the isolation structure, little or no unexpected bumps are formed on the mask layer. After an etching process is performed on the oxide layer and the oxide liner, the oxide layer and the liner may have similar residual heights. In this way, the design pattern of the memory device may not be damaged, and an additional planarization process on the mask layer on the isolation structure may be omitted.

[0085] Although the present invention has been disclosed as above in the form of implementation modes, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

[0086] It is obvious to those skilled in the art that various modifications and changes may be made to the structure of the embodiments of the present invention without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present invention is intended to cover modifications and changes of the present invention as long as they fall within the scope of the attached protection.

[0087]

Explanation of symbols

[0088] 110:Substrate

[0089] 111,1111,1112: injection area

[0090] 115: Isolation groove

[0091] 120: Isolation groove

[0092] 125: Semiconductor layer

[0093] 125T:Height

[0094] 130: First oxide layer

[0095] 135: Lining

[0096] 136: Unoxidized liner portion

[0097] 137,1371,1372: Oxidation liner part

[0098] 137B: Height

[0099] 140: Second oxide layer

[0100] 145: Sacrificial oxide layer

[0101] 150: Mask layer

[0102] 151: Opening

[0103] 160: Character line structure

[0104] 161: Dielectric layer

[0105] 162: Conductive layer

[0106] 165: Character line groove

[0107] 210: Anti-reflection layer

[0108] 220: Hard Mask

[0109] DA: Installation Area

[0110] IM: Injection process

[0111] PA: Peripheral area.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming an oxide layer in the isolation trench on the substrate; forming a liner on the oxide layer; oxidizing the liner; After oxidizing the liner, forming an implantation region on the substrate; as well as A word line structure is formed on the substrate, wherein the word line structure crosses the oxide layer and the liner.

2. The method according to claim 1, characterized in that The liner is oxidized to have a non-oxidized liner portion and an oxidized liner portion over the non-oxidized liner portion, the oxidized liner portion extending to the isolation trench.

3. The method according to claim 1, characterized in that Further including: A semiconductor layer is formed on the substrate and in the isolation trench, wherein the liner is oxidized to have an unoxidized liner portion and an oxidized liner portion above the unoxidized liner portion, and a bottom surface of the oxidized liner portion is lower than a top surface of the semiconductor layer.

4. The method according to claim 1, characterized in that: Further including: After the liner is oxidized, a sacrificial oxide layer is formed on the oxide layer and the liner, wherein the implantation region is formed by an implantation process through the sacrificial oxide layer.

5. The method according to claim 1, characterized in that Further including: forming a hard mask on the oxide layer and the liner; Patterning the hard mask so that the oxide layer and the oxide liner portion of the liner are exposed; as well as A word line trench crossing the oxide layer and the liner is etched based on the hard mask, wherein the word line structure is formed in the word line trench.

6. The method according to claim 5, characterized in that The word line trench is etched so that the oxide liner portion of the liner is cut into a first portion and a second portion separated from each other.

7. The method according to claim 1, characterized in that Before the lining layer is oxidized, the lining layer is an oxygen-free layer.

8. A method for forming a semiconductor structure, characterized in that: include: forming a plurality of isolation trenches on the substrate; forming a first oxide layer on the plurality of isolation trenches; forming a liner on the first oxide layer; forming a second oxide layer on the liner; polishing the second oxide layer so that the first oxide layer and the liner are exposed; oxidizing the liner; forming an implantation region on the substrate; as well as A word line structure is formed on the substrate and spans across the plurality of isolation trenches.

9. The method according to claim 8, characterized in that The liner is oxidized to have a plurality of unoxidized liner portions and a plurality of oxidized liner portions over the plurality of unoxidized liner portions, the plurality of oxidized liner portions extending to the plurality of isolation trenches.

10. The method according to claim 9, characterized in that After the word line structure is formed, the second oxide layer is retained between the plurality of oxide liner portions of the liner of one of the plurality of isolation trenches in a peripheral region outside the word line structure.

11. The method according to claim 8, characterized in that Further including: After the liner is oxidized, a sacrificial oxide layer is formed on the first oxide layer, the liner and the second oxide layer, wherein the implantation region is formed by an implantation process through the sacrificial oxide layer.

12. The method according to claim 8, characterized in that Further including: forming a hard mask on the first oxide layer and the liner; patterning the hard mask so that the first oxide layer and a plurality of oxide liner portions of the liner are exposed; as well as A word line trench crossing the oxide layer and the liner is etched based on the hard mask, wherein the word line structure is formed in the word line trench.

13. The method according to claim 8, characterized in that Before the lining layer is oxidized, the lining layer is an oxygen-free layer.

14. A semiconductor structure, characterized in that: include: A first isolation region is located on the substrate, wherein the first isolation region includes a first oxide layer and a first liner on the first oxide layer, and the first liner has a first unoxidized liner portion and a first oxidized liner portion located on the first unoxidized liner portion; as well as A word line structure crosses the first isolation region, wherein a first portion and a second portion of the first unoxidized liner portion are separated from each other by the word line structure.

15. The semiconductor structure according to claim 14, characterized in that: Further including: A second isolation region is located on the substrate, wherein the second isolation region includes a second liner having a second oxide liner portion, and a first portion and a second portion of the second oxide liner portion are separated from each other by the word line structure.

16. The semiconductor structure according to claim 15, characterized in that Further including: The active injection region is located between the first oxide liner portion of the first liner and the second oxide liner portion of the second liner.

17. The semiconductor structure according to claim 14, characterized in that Further including: A second isolation region is located on the substrate, wherein the second isolation region includes a second oxide layer, a second liner on the second oxide layer, and a third oxide layer on the second liner, the second liner has a second unoxidized liner portion and a second oxidized liner portion on the second unoxidized liner portion, and the second oxidized liner portion is located between the second oxide layer and the third oxide layer.

18. The semiconductor structure according to claim 17, characterized in that: The second isolation region is outside the word line structure.

19. The semiconductor structure according to claim 14, characterized in that The material of the first oxide liner portion is different from the material of the first oxide layer.

20. The semiconductor structure according to claim 14, wherein: Further including: The semiconductor layer is located on the substrate, wherein the bottom surface of the first oxide liner portion is lower than the top surface of the semiconductor layer.

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